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[libata] PCI ID table cleanup in various drivers
[deliverable/linux.git] / drivers / ata / pata_cmd64x.c
1 /*
2 * pata_cmd64x.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based upon
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
8 *
9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10 * Note, this driver is not used at all on other systems because
11 * there the "BIOS" has done all of the following already.
12 * Due to massive hardware bugs, UltraDMA is only supported
13 * on the 646U2 and not on the 646U.
14 *
15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
16 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
17 *
18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
19 *
20 * TODO
21 * Testing work
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <scsi/scsi_host.h>
31 #include <linux/libata.h>
32
33 #define DRV_NAME "pata_cmd64x"
34 #define DRV_VERSION "0.2.1"
35
36 /*
37 * CMD64x specific registers definition.
38 */
39
40 enum {
41 CFR = 0x50,
42 CFR_INTR_CH0 = 0x02,
43 CNTRL = 0x51,
44 CNTRL_DIS_RA0 = 0x40,
45 CNTRL_DIS_RA1 = 0x80,
46 CNTRL_ENA_2ND = 0x08,
47 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
56 ARTTIM2 = 0x57,
57 ARTTIM3 = 0x57,
58 DRWTIM23 = 0x58,
59 DRWTIM2 = 0x58,
60 BRST = 0x59,
61 DRWTIM3 = 0x5b,
62 BMIDECR0 = 0x70,
63 MRDMODE = 0x71,
64 MRDMODE_INTR_CH0 = 0x04,
65 MRDMODE_INTR_CH1 = 0x08,
66 MRDMODE_BLK_CH0 = 0x10,
67 MRDMODE_BLK_CH1 = 0x20,
68 BMIDESR0 = 0x72,
69 UDIDETCR0 = 0x73,
70 DTPR0 = 0x74,
71 BMIDECR1 = 0x78,
72 BMIDECSR = 0x79,
73 BMIDESR1 = 0x7A,
74 UDIDETCR1 = 0x7B,
75 DTPR1 = 0x7C
76 };
77
78 static int cmd64x_pre_reset(struct ata_port *ap)
79 {
80 ap->cbl = ATA_CBL_PATA40;
81 return ata_std_prereset(ap);
82 }
83
84 static int cmd648_pre_reset(struct ata_port *ap)
85 {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87 u8 r;
88
89 /* Check cable detect bits */
90 pci_read_config_byte(pdev, BMIDECSR, &r);
91 if (r & (1 << ap->port_no))
92 ap->cbl = ATA_CBL_PATA80;
93 else
94 ap->cbl = ATA_CBL_PATA40;
95
96 return ata_std_prereset(ap);
97 }
98
99 static void cmd64x_error_handler(struct ata_port *ap)
100 {
101 return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
102 }
103
104 static void cmd648_error_handler(struct ata_port *ap)
105 {
106 ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
107 }
108
109 /**
110 * cmd64x_set_piomode - set initial PIO mode data
111 * @ap: ATA interface
112 * @adev: ATA device
113 *
114 * Called to do the PIO mode setup.
115 */
116
117 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
118 {
119 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
120 struct ata_timing t;
121 const unsigned long T = 1000000 / 33;
122 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
123
124 u8 reg;
125
126 /* Port layout is not logical so use a table */
127 const u8 arttim_port[2][2] = {
128 { ARTTIM0, ARTTIM1 },
129 { ARTTIM23, ARTTIM23 }
130 };
131 const u8 drwtim_port[2][2] = {
132 { DRWTIM0, DRWTIM1 },
133 { DRWTIM2, DRWTIM3 }
134 };
135
136 int arttim = arttim_port[ap->port_no][adev->devno];
137 int drwtim = drwtim_port[ap->port_no][adev->devno];
138
139
140 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
141 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
142 return;
143 }
144 if (ap->port_no) {
145 /* Slave has shared address setup */
146 struct ata_device *pair = ata_dev_pair(adev);
147
148 if (pair) {
149 struct ata_timing tp;
150 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
151 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
152 }
153 }
154
155 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
156 t.active, t.recover, t.setup);
157 if (t.recover > 16) {
158 t.active += t.recover - 16;
159 t.recover = 16;
160 }
161 if (t.active > 16)
162 t.active = 16;
163
164 /* Now convert the clocks into values we can actually stuff into
165 the chip */
166
167 if (t.recover > 1)
168 t.recover--;
169 else
170 t.recover = 15;
171
172 if (t.setup > 4)
173 t.setup = 0xC0;
174 else
175 t.setup = setup_data[t.setup];
176
177 t.active &= 0x0F; /* 0 = 16 */
178
179 /* Load setup timing */
180 pci_read_config_byte(pdev, arttim, &reg);
181 reg &= 0x3F;
182 reg |= t.setup;
183 pci_write_config_byte(pdev, arttim, reg);
184
185 /* Load active/recovery */
186 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
187 }
188
189 /**
190 * cmd64x_set_dmamode - set initial DMA mode data
191 * @ap: ATA interface
192 * @adev: ATA device
193 *
194 * Called to do the DMA mode setup.
195 */
196
197 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
198 {
199 static const u8 udma_data[] = {
200 0x31, 0x21, 0x11, 0x25, 0x15, 0x05
201 };
202 static const u8 mwdma_data[] = {
203 0x30, 0x20, 0x10
204 };
205
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
207 u8 regU, regD;
208
209 int pciU = UDIDETCR0 + 8 * ap->port_no;
210 int pciD = BMIDESR0 + 8 * ap->port_no;
211 int shift = 2 * adev->devno;
212
213 pci_read_config_byte(pdev, pciD, &regD);
214 pci_read_config_byte(pdev, pciU, &regU);
215
216 regD &= ~(0x20 << shift);
217 regU &= ~(0x35 << shift);
218
219 if (adev->dma_mode >= XFER_UDMA_0)
220 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
221 else
222 regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
223
224 regD |= 0x20 << adev->devno;
225
226 pci_write_config_byte(pdev, pciU, regU);
227 pci_write_config_byte(pdev, pciD, regD);
228 }
229
230 /**
231 * cmd648_dma_stop - DMA stop callback
232 * @qc: Command in progress
233 *
234 * DMA has completed.
235 */
236
237 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
238 {
239 struct ata_port *ap = qc->ap;
240 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 u8 dma_intr;
242 int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
243 int dma_mask = ap->port_no ? ARTTIM2 : CFR;
244
245 ata_bmdma_stop(qc);
246
247 pci_read_config_byte(pdev, dma_reg, &dma_intr);
248 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
249 }
250
251 /**
252 * cmd646r1_dma_stop - DMA stop callback
253 * @qc: Command in progress
254 *
255 * Stub for now while investigating the r1 quirk in the old driver.
256 */
257
258 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
259 {
260 ata_bmdma_stop(qc);
261 }
262
263 static struct scsi_host_template cmd64x_sht = {
264 .module = THIS_MODULE,
265 .name = DRV_NAME,
266 .ioctl = ata_scsi_ioctl,
267 .queuecommand = ata_scsi_queuecmd,
268 .can_queue = ATA_DEF_QUEUE,
269 .this_id = ATA_SHT_THIS_ID,
270 .sg_tablesize = LIBATA_MAX_PRD,
271 .max_sectors = ATA_MAX_SECTORS,
272 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
273 .emulated = ATA_SHT_EMULATED,
274 .use_clustering = ATA_SHT_USE_CLUSTERING,
275 .proc_name = DRV_NAME,
276 .dma_boundary = ATA_DMA_BOUNDARY,
277 .slave_configure = ata_scsi_slave_config,
278 .bios_param = ata_std_bios_param,
279 };
280
281 static struct ata_port_operations cmd64x_port_ops = {
282 .port_disable = ata_port_disable,
283 .set_piomode = cmd64x_set_piomode,
284 .set_dmamode = cmd64x_set_dmamode,
285 .mode_filter = ata_pci_default_filter,
286 .tf_load = ata_tf_load,
287 .tf_read = ata_tf_read,
288 .check_status = ata_check_status,
289 .exec_command = ata_exec_command,
290 .dev_select = ata_std_dev_select,
291
292 .freeze = ata_bmdma_freeze,
293 .thaw = ata_bmdma_thaw,
294 .error_handler = cmd64x_error_handler,
295 .post_internal_cmd = ata_bmdma_post_internal_cmd,
296
297 .bmdma_setup = ata_bmdma_setup,
298 .bmdma_start = ata_bmdma_start,
299 .bmdma_stop = ata_bmdma_stop,
300 .bmdma_status = ata_bmdma_status,
301
302 .qc_prep = ata_qc_prep,
303 .qc_issue = ata_qc_issue_prot,
304
305 .data_xfer = ata_pio_data_xfer,
306
307 .irq_handler = ata_interrupt,
308 .irq_clear = ata_bmdma_irq_clear,
309
310 .port_start = ata_port_start,
311 .port_stop = ata_port_stop,
312 .host_stop = ata_host_stop
313 };
314
315 static struct ata_port_operations cmd646r1_port_ops = {
316 .port_disable = ata_port_disable,
317 .set_piomode = cmd64x_set_piomode,
318 .set_dmamode = cmd64x_set_dmamode,
319 .mode_filter = ata_pci_default_filter,
320 .tf_load = ata_tf_load,
321 .tf_read = ata_tf_read,
322 .check_status = ata_check_status,
323 .exec_command = ata_exec_command,
324 .dev_select = ata_std_dev_select,
325
326 .freeze = ata_bmdma_freeze,
327 .thaw = ata_bmdma_thaw,
328 .error_handler = cmd64x_error_handler,
329 .post_internal_cmd = ata_bmdma_post_internal_cmd,
330
331 .bmdma_setup = ata_bmdma_setup,
332 .bmdma_start = ata_bmdma_start,
333 .bmdma_stop = cmd646r1_bmdma_stop,
334 .bmdma_status = ata_bmdma_status,
335
336 .qc_prep = ata_qc_prep,
337 .qc_issue = ata_qc_issue_prot,
338
339 .data_xfer = ata_pio_data_xfer,
340
341 .irq_handler = ata_interrupt,
342 .irq_clear = ata_bmdma_irq_clear,
343
344 .port_start = ata_port_start,
345 .port_stop = ata_port_stop,
346 .host_stop = ata_host_stop
347 };
348
349 static struct ata_port_operations cmd648_port_ops = {
350 .port_disable = ata_port_disable,
351 .set_piomode = cmd64x_set_piomode,
352 .set_dmamode = cmd64x_set_dmamode,
353 .mode_filter = ata_pci_default_filter,
354 .tf_load = ata_tf_load,
355 .tf_read = ata_tf_read,
356 .check_status = ata_check_status,
357 .exec_command = ata_exec_command,
358 .dev_select = ata_std_dev_select,
359
360 .freeze = ata_bmdma_freeze,
361 .thaw = ata_bmdma_thaw,
362 .error_handler = cmd648_error_handler,
363 .post_internal_cmd = ata_bmdma_post_internal_cmd,
364
365 .bmdma_setup = ata_bmdma_setup,
366 .bmdma_start = ata_bmdma_start,
367 .bmdma_stop = cmd648_bmdma_stop,
368 .bmdma_status = ata_bmdma_status,
369
370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
372
373 .data_xfer = ata_pio_data_xfer,
374
375 .irq_handler = ata_interrupt,
376 .irq_clear = ata_bmdma_irq_clear,
377
378 .port_start = ata_port_start,
379 .port_stop = ata_port_stop,
380 .host_stop = ata_host_stop
381 };
382
383 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
384 {
385 u32 class_rev;
386
387 static struct ata_port_info cmd_info[6] = {
388 { /* CMD 643 - no UDMA */
389 .sht = &cmd64x_sht,
390 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
391 .pio_mask = 0x1f,
392 .mwdma_mask = 0x07,
393 .port_ops = &cmd64x_port_ops
394 },
395 { /* CMD 646 with broken UDMA */
396 .sht = &cmd64x_sht,
397 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
398 .pio_mask = 0x1f,
399 .mwdma_mask = 0x07,
400 .port_ops = &cmd64x_port_ops
401 },
402 { /* CMD 646 with working UDMA */
403 .sht = &cmd64x_sht,
404 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
405 .pio_mask = 0x1f,
406 .mwdma_mask = 0x07,
407 .udma_mask = ATA_UDMA1,
408 .port_ops = &cmd64x_port_ops
409 },
410 { /* CMD 646 rev 1 */
411 .sht = &cmd64x_sht,
412 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
413 .pio_mask = 0x1f,
414 .mwdma_mask = 0x07,
415 .port_ops = &cmd646r1_port_ops
416 },
417 { /* CMD 648 */
418 .sht = &cmd64x_sht,
419 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
420 .pio_mask = 0x1f,
421 .mwdma_mask = 0x07,
422 .udma_mask = ATA_UDMA2,
423 .port_ops = &cmd648_port_ops
424 },
425 { /* CMD 649 */
426 .sht = &cmd64x_sht,
427 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
428 .pio_mask = 0x1f,
429 .mwdma_mask = 0x07,
430 .udma_mask = ATA_UDMA3,
431 .port_ops = &cmd648_port_ops
432 }
433 };
434 static struct ata_port_info *port_info[2], *info;
435 u8 mrdmode;
436
437 info = &cmd_info[id->driver_data];
438
439 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
440 class_rev &= 0xFF;
441
442 if (id->driver_data == 0) /* 643 */
443 ata_pci_clear_simplex(pdev);
444
445 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
446 /* Does UDMA work ? */
447 if (class_rev > 4)
448 info = &cmd_info[2];
449 /* Early rev with other problems ? */
450 else if (class_rev == 1)
451 info = &cmd_info[3];
452 }
453
454 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
455 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
456 mrdmode &= ~ 0x30; /* IRQ set up */
457 mrdmode |= 0x02; /* Memory read line enable */
458 pci_write_config_byte(pdev, MRDMODE, mrdmode);
459
460 /* Force PIO 0 here.. */
461
462 /* PPC specific fixup copied from old driver */
463 #ifdef CONFIG_PPC
464 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
465 #endif
466
467 port_info[0] = port_info[1] = info;
468 return ata_pci_init_one(pdev, port_info, 2);
469 }
470
471 static const struct pci_device_id cmd64x[] = {
472 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
473 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
474 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
475 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
476
477 { },
478 };
479
480 static struct pci_driver cmd64x_pci_driver = {
481 .name = DRV_NAME,
482 .id_table = cmd64x,
483 .probe = cmd64x_init_one,
484 .remove = ata_pci_remove_one
485 };
486
487 static int __init cmd64x_init(void)
488 {
489 return pci_register_driver(&cmd64x_pci_driver);
490 }
491
492 static void __exit cmd64x_exit(void)
493 {
494 pci_unregister_driver(&cmd64x_pci_driver);
495 }
496
497 MODULE_AUTHOR("Alan Cox");
498 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
499 MODULE_LICENSE("GPL");
500 MODULE_DEVICE_TABLE(pci, cmd64x);
501 MODULE_VERSION(DRV_VERSION);
502
503 module_init(cmd64x_init);
504 module_exit(cmd64x_exit);
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