drivers/ata/pata_pdc2027x.c

   1 /*
   2  *  Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Ported to libata by:
  10  *  Albert Lee <albertcc@tw.ibm.com> IBM Corporation
  11  *
  12  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  13  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14  *
  15  *  Author: Frank Tiernan (frankt@promise.com)
  16  *  Released under terms of General Public License
  17  *
  18  *
  19  *  libata documentation is available via 'make {ps|pdf}docs',
  20  *  as Documentation/DocBook/libata.*
  21  *
  22  *  Hardware information only available under NDA.
  23  *
  24  */
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/blkdev.h>
  29 #include <linux/delay.h>
  30 #include <linux/device.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_host.h>
  33 #include <scsi/scsi_cmnd.h>
  34 #include <linux/libata.h>
  35
  36 #define DRV_NAME        "pata_pdc2027x"
  37 #define DRV_VERSION     "1.0"
  38 #undef PDC_DEBUG
  39
  40 #ifdef PDC_DEBUG
  41 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  42 #else
  43 #define PDPRINTK(fmt, args...)
  44 #endif
  45
  46 enum {
  47         PDC_MMIO_BAR            = 5,
  48
  49         PDC_UDMA_100            = 0,
  50         PDC_UDMA_133            = 1,
  51
  52         PDC_100_MHZ             = 100000000,
  53         PDC_133_MHZ             = 133333333,
  54
  55         PDC_SYS_CTL             = 0x1100,
  56         PDC_ATA_CTL             = 0x1104,
  57         PDC_GLOBAL_CTL          = 0x1108,
  58         PDC_CTCR0               = 0x110C,
  59         PDC_CTCR1               = 0x1110,
  60         PDC_BYTE_COUNT          = 0x1120,
  61         PDC_PLL_CTL             = 0x1202,
  62 };
  63
  64 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  65 #ifdef CONFIG_PM_SLEEP
  66 static int pdc2027x_reinit_one(struct pci_dev *pdev);
  67 #endif
  68 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
  69 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
  70 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
  71 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
  72 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
  73 static int pdc2027x_cable_detect(struct ata_port *ap);
  74 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
  75
  76 /*
  77  * ATA Timing Tables based on 133MHz controller clock.
  78  * These tables are only used when the controller is in 133MHz clock.
  79  * If the controller is in 100MHz clock, the ASIC hardware will
  80  * set the timing registers automatically when "set feature" command
  81  * is issued to the device. However, if the controller clock is 133MHz,
  82  * the following tables must be used.
  83  */
  84 static struct pdc2027x_pio_timing {
  85         u8 value0, value1, value2;
  86 } pdc2027x_pio_timing_tbl [] = {
  87         { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
  88         { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
  89         { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
  90         { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
  91         { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
  92 };
  93
  94 static struct pdc2027x_mdma_timing {
  95         u8 value0, value1;
  96 } pdc2027x_mdma_timing_tbl [] = {
  97         { 0xdf, 0x5f }, /* MDMA mode 0 */
  98         { 0x6b, 0x27 }, /* MDMA mode 1 */
  99         { 0x69, 0x25 }, /* MDMA mode 2 */
 100 };
 101
 102 static struct pdc2027x_udma_timing {
 103         u8 value0, value1, value2;
 104 } pdc2027x_udma_timing_tbl [] = {
 105         { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
 106         { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
 107         { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
 108         { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
 109         { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
 110         { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
 111         { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
 112 };
 113
 114 static const struct pci_device_id pdc2027x_pci_tbl[] = {
 115         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
 116         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
 117         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
 118         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
 119         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
 120         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
 121         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
 122
 123         { }     /* terminate list */
 124 };
 125
 126 static struct pci_driver pdc2027x_pci_driver = {
 127         .name                   = DRV_NAME,
 128         .id_table               = pdc2027x_pci_tbl,
 129         .probe                  = pdc2027x_init_one,
 130         .remove                 = ata_pci_remove_one,
 131 #ifdef CONFIG_PM_SLEEP
 132         .suspend                = ata_pci_device_suspend,
 133         .resume                 = pdc2027x_reinit_one,
 134 #endif
 135 };
 136
 137 static struct scsi_host_template pdc2027x_sht = {
 138         ATA_BMDMA_SHT(DRV_NAME),
 139 };
 140
 141 static struct ata_port_operations pdc2027x_pata100_ops = {
 142         .inherits               = &ata_bmdma_port_ops,
 143         .check_atapi_dma        = pdc2027x_check_atapi_dma,
 144         .cable_detect           = pdc2027x_cable_detect,
 145         .prereset               = pdc2027x_prereset,
 146 };
 147
 148 static struct ata_port_operations pdc2027x_pata133_ops = {
 149         .inherits               = &pdc2027x_pata100_ops,
 150         .mode_filter            = pdc2027x_mode_filter,
 151         .set_piomode            = pdc2027x_set_piomode,
 152         .set_dmamode            = pdc2027x_set_dmamode,
 153         .set_mode               = pdc2027x_set_mode,
 154 };
 155
 156 static struct ata_port_info pdc2027x_port_info[] = {
 157         /* PDC_UDMA_100 */
 158         {
 159                 .flags          = ATA_FLAG_SLAVE_POSS,
 160                 .pio_mask       = ATA_PIO4,
 161                 .mwdma_mask     = ATA_MWDMA2,
 162                 .udma_mask      = ATA_UDMA5,
 163                 .port_ops       = &pdc2027x_pata100_ops,
 164         },
 165         /* PDC_UDMA_133 */
 166         {
 167                 .flags          = ATA_FLAG_SLAVE_POSS,
 168                 .pio_mask       = ATA_PIO4,
 169                 .mwdma_mask     = ATA_MWDMA2,
 170                 .udma_mask      = ATA_UDMA6,
 171                 .port_ops       = &pdc2027x_pata133_ops,
 172         },
 173 };
 174
 175 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
 176 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
 177 MODULE_LICENSE("GPL");
 178 MODULE_VERSION(DRV_VERSION);
 179 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
 180
 181 /**
 182  *      port_mmio - Get the MMIO address of PDC2027x extended registers
 183  *      @ap: Port
 184  *      @offset: offset from mmio base
 185  */
 186 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
 187 {
 188         return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
 189 }
 190
 191 /**
 192  *      dev_mmio - Get the MMIO address of PDC2027x extended registers
 193  *      @ap: Port
 194  *      @adev: device
 195  *      @offset: offset from mmio base
 196  */
 197 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
 198 {
 199         u8 adj = (adev->devno) ? 0x08 : 0x00;
 200         return port_mmio(ap, offset) + adj;
 201 }
 202
 203 /**
 204  *      pdc2027x_pata_cable_detect - Probe host controller cable detect info
 205  *      @ap: Port for which cable detect info is desired
 206  *
 207  *      Read 80c cable indicator from Promise extended register.
 208  *      This register is latched when the system is reset.
 209  *
 210  *      LOCKING:
 211  *      None (inherited from caller).
 212  */
 213 static int pdc2027x_cable_detect(struct ata_port *ap)
 214 {
 215         u32 cgcr;
 216
 217         /* check cable detect results */
 218         cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
 219         if (cgcr & (1 << 26))
 220                 goto cbl40;
 221
 222         PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
 223
 224         return ATA_CBL_PATA80;
 225 cbl40:
 226         printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
 227         return ATA_CBL_PATA40;
 228 }
 229
 230 /**
 231  * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
 232  * @ap: Port to check
 233  */
 234 static inline int pdc2027x_port_enabled(struct ata_port *ap)
 235 {
 236         return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
 237 }
 238
 239 /**
 240  *      pdc2027x_prereset - prereset for PATA host controller
 241  *      @link: Target link
 242  *      @deadline: deadline jiffies for the operation
 243  *
 244  *      Probeinit including cable detection.
 245  *
 246  *      LOCKING:
 247  *      None (inherited from caller).
 248  */
 249
 250 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
 251 {
 252         /* Check whether port enabled */
 253         if (!pdc2027x_port_enabled(link->ap))
 254                 return -ENOENT;
 255         return ata_sff_prereset(link, deadline);
 256 }
 257
 258 /**
 259  *      pdc2720x_mode_filter    -       mode selection filter
 260  *      @adev: ATA device
 261  *      @mask: list of modes proposed
 262  *
 263  *      Block UDMA on devices that cause trouble with this controller.
 264  */
 265
 266 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
 267 {
 268         unsigned char model_num[ATA_ID_PROD_LEN + 1];
 269         struct ata_device *pair = ata_dev_pair(adev);
 270
 271         if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
 272                 return mask;
 273
 274         /* Check for slave of a Maxtor at UDMA6 */
 275         ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
 276                           ATA_ID_PROD_LEN + 1);
 277         /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
 278         if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
 279                 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
 280
 281         return mask;
 282 }
 283
 284 /**
 285  *      pdc2027x_set_piomode - Initialize host controller PATA PIO timings
 286  *      @ap: Port to configure
 287  *      @adev: um
 288  *
 289  *      Set PIO mode for device.
 290  *
 291  *      LOCKING:
 292  *      None (inherited from caller).
 293  */
 294
 295 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 296 {
 297         unsigned int pio = adev->pio_mode - XFER_PIO_0;
 298         u32 ctcr0, ctcr1;
 299
 300         PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
 301
 302         /* Sanity check */
 303         if (pio > 4) {
 304                 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
 305                 return;
 306
 307         }
 308
 309         /* Set the PIO timing registers using value table for 133MHz */
 310         PDPRINTK("Set pio regs... \n");
 311
 312         ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 313         ctcr0 &= 0xffff0000;
 314         ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
 315                 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
 316         iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 317
 318         ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 319         ctcr1 &= 0x00ffffff;
 320         ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
 321         iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 322
 323         PDPRINTK("Set pio regs done\n");
 324
 325         PDPRINTK("Set to pio mode[%u] \n", pio);
 326 }
 327
 328 /**
 329  *      pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
 330  *      @ap: Port to configure
 331  *      @adev: um
 332  *
 333  *      Set UDMA mode for device.
 334  *
 335  *      LOCKING:
 336  *      None (inherited from caller).
 337  */
 338 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 339 {
 340         unsigned int dma_mode = adev->dma_mode;
 341         u32 ctcr0, ctcr1;
 342
 343         if ((dma_mode >= XFER_UDMA_0) &&
 344            (dma_mode <= XFER_UDMA_6)) {
 345                 /* Set the UDMA timing registers with value table for 133MHz */
 346                 unsigned int udma_mode = dma_mode & 0x07;
 347
 348                 if (dma_mode == XFER_UDMA_2) {
 349                         /*
 350                          * Turn off tHOLD.
 351                          * If tHOLD is '1', the hardware will add half clock for data hold time.
 352                          * This code segment seems to be no effect. tHOLD will be overwritten below.
 353                          */
 354                         ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 355                         iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
 356                 }
 357
 358                 PDPRINTK("Set udma regs... \n");
 359
 360                 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 361                 ctcr1 &= 0xff000000;
 362                 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
 363                         (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
 364                         (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
 365                 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 366
 367                 PDPRINTK("Set udma regs done\n");
 368
 369                 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
 370
 371         } else  if ((dma_mode >= XFER_MW_DMA_0) &&
 372                    (dma_mode <= XFER_MW_DMA_2)) {
 373                 /* Set the MDMA timing registers with value table for 133MHz */
 374                 unsigned int mdma_mode = dma_mode & 0x07;
 375
 376                 PDPRINTK("Set mdma regs... \n");
 377                 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 378
 379                 ctcr0 &= 0x0000ffff;
 380                 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
 381                         (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
 382
 383                 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 384                 PDPRINTK("Set mdma regs done\n");
 385
 386                 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
 387         } else {
 388                 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
 389         }
 390 }
 391
 392 /**
 393  *      pdc2027x_set_mode - Set the timing registers back to correct values.
 394  *      @link: link to configure
 395  *      @r_failed: Returned device for failure
 396  *
 397  *      The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
 398  *      automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
 399  *      This function overwrites the possibly incorrect values set by the hardware to be correct.
 400  */
 401 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
 402 {
 403         struct ata_port *ap = link->ap;
 404         struct ata_device *dev;
 405         int rc;
 406
 407         rc = ata_do_set_mode(link, r_failed);
 408         if (rc < 0)
 409                 return rc;
 410
 411         ata_for_each_dev(dev, link, ENABLED) {
 412                 pdc2027x_set_piomode(ap, dev);
 413
 414                 /*
 415                  * Enable prefetch if the device support PIO only.
 416                  */
 417                 if (dev->xfer_shift == ATA_SHIFT_PIO) {
 418                         u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
 419                         ctcr1 |= (1 << 25);
 420                         iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
 421
 422                         PDPRINTK("Turn on prefetch\n");
 423                 } else {
 424                         pdc2027x_set_dmamode(ap, dev);
 425                 }
 426         }
 427         return 0;
 428 }
 429
 430 /**
 431  *      pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
 432  *      @qc: Metadata associated with taskfile to check
 433  *
 434  *      LOCKING:
 435  *      None (inherited from caller).
 436  *
 437  *      RETURNS: 0 when ATAPI DMA can be used
 438  *               1 otherwise
 439  */
 440 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
 441 {
 442         struct scsi_cmnd *cmd = qc->scsicmd;
 443         u8 *scsicmd = cmd->cmnd;
 444         int rc = 1; /* atapi dma off by default */
 445
 446         /*
 447          * This workaround is from Promise's GPL driver.
 448          * If ATAPI DMA is used for commands not in the
 449          * following white list, say MODE_SENSE and REQUEST_SENSE,
 450          * pdc2027x might hit the irq lost problem.
 451          */
 452         switch (scsicmd[0]) {
 453         case READ_10:
 454         case WRITE_10:
 455         case READ_12:
 456         case WRITE_12:
 457         case READ_6:
 458         case WRITE_6:
 459         case 0xad: /* READ_DVD_STRUCTURE */
 460         case 0xbe: /* READ_CD */
 461                 /* ATAPI DMA is ok */
 462                 rc = 0;
 463                 break;
 464         default:
 465                 ;
 466         }
 467
 468         return rc;
 469 }
 470
 471 /**
 472  * pdc_read_counter - Read the ctr counter
 473  * @host: target ATA host
 474  */
 475
 476 static long pdc_read_counter(struct ata_host *host)
 477 {
 478         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 479         long counter;
 480         int retry = 1;
 481         u32 bccrl, bccrh, bccrlv, bccrhv;
 482
 483 retry:
 484         bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
 485         bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 486
 487         /* Read the counter values again for verification */
 488         bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
 489         bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 490
 491         counter = (bccrh << 15) | bccrl;
 492
 493         PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
 494         PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
 495
 496         /*
 497          * The 30-bit decreasing counter are read by 2 pieces.
 498          * Incorrect value may be read when both bccrh and bccrl are changing.
 499          * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
 500          */
 501         if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
 502                 retry--;
 503                 PDPRINTK("rereading counter\n");
 504                 goto retry;
 505         }
 506
 507         return counter;
 508 }
 509
 510 /**
 511  * adjust_pll - Adjust the PLL input clock in Hz.
 512  *
 513  * @pdc_controller: controller specific information
 514  * @host: target ATA host
 515  * @pll_clock: The input of PLL in HZ
 516  */
 517 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
 518 {
 519         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 520         u16 pll_ctl;
 521         long pll_clock_khz = pll_clock / 1000;
 522         long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
 523         long ratio = pout_required / pll_clock_khz;
 524         int F, R;
 525
 526         /* Sanity check */
 527         if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
 528                 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
 529                 return;
 530         }
 531
 532 #ifdef PDC_DEBUG
 533         PDPRINTK("pout_required is %ld\n", pout_required);
 534
 535         /* Show the current clock value of PLL control register
 536          * (maybe already configured by the firmware)
 537          */
 538         pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 539
 540         PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 541 #endif
 542
 543         /*
 544          * Calculate the ratio of F, R and OD
 545          * POUT = (F + 2) / (( R + 2) * NO)
 546          */
 547         if (ratio < 8600L) { /* 8.6x */
 548                 /* Using NO = 0x01, R = 0x0D */
 549                 R = 0x0d;
 550         } else if (ratio < 12900L) { /* 12.9x */
 551                 /* Using NO = 0x01, R = 0x08 */
 552                 R = 0x08;
 553         } else if (ratio < 16100L) { /* 16.1x */
 554                 /* Using NO = 0x01, R = 0x06 */
 555                 R = 0x06;
 556         } else if (ratio < 64000L) { /* 64x */
 557                 R = 0x00;
 558         } else {
 559                 /* Invalid ratio */
 560                 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
 561                 return;
 562         }
 563
 564         F = (ratio * (R+2)) / 1000 - 2;
 565
 566         if (unlikely(F < 0 || F > 127)) {
 567                 /* Invalid F */
 568                 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
 569                 return;
 570         }
 571
 572         PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
 573
 574         pll_ctl = (R << 8) | F;
 575
 576         PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
 577
 578         iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
 579         ioread16(mmio_base + PDC_PLL_CTL); /* flush */
 580
 581         /* Wait the PLL circuit to be stable */
 582         mdelay(30);
 583
 584 #ifdef PDC_DEBUG
 585         /*
 586          *  Show the current clock value of PLL control register
 587          * (maybe configured by the firmware)
 588          */
 589         pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 590
 591         PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 592 #endif
 593
 594         return;
 595 }
 596
 597 /**
 598  * detect_pll_input_clock - Detect the PLL input clock in Hz.
 599  * @host: target ATA host
 600  * Ex. 16949000 on 33MHz PCI bus for pdc20275.
 601  *     Half of the PCI clock.
 602  */
 603 static long pdc_detect_pll_input_clock(struct ata_host *host)
 604 {
 605         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 606         u32 scr;
 607         long start_count, end_count;
 608         struct timeval start_time, end_time;
 609         long pll_clock, usec_elapsed;
 610
 611         /* Start the test mode */
 612         scr = ioread32(mmio_base + PDC_SYS_CTL);
 613         PDPRINTK("scr[%X]\n", scr);
 614         iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
 615         ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 616
 617         /* Read current counter value */
 618         start_count = pdc_read_counter(host);
 619         do_gettimeofday(&start_time);
 620
 621         /* Let the counter run for 100 ms. */
 622         mdelay(100);
 623
 624         /* Read the counter values again */
 625         end_count = pdc_read_counter(host);
 626         do_gettimeofday(&end_time);
 627
 628         /* Stop the test mode */
 629         scr = ioread32(mmio_base + PDC_SYS_CTL);
 630         PDPRINTK("scr[%X]\n", scr);
 631         iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
 632         ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 633
 634         /* calculate the input clock in Hz */
 635         usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
 636                 (end_time.tv_usec - start_time.tv_usec);
 637
 638         pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
 639                 (100000000 / usec_elapsed);
 640
 641         PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
 642         PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
 643
 644         return pll_clock;
 645 }
 646
 647 /**
 648  * pdc_hardware_init - Initialize the hardware.
 649  * @host: target ATA host
 650  * @board_idx: board identifier
 651  */
 652 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
 653 {
 654         long pll_clock;
 655
 656         /*
 657          * Detect PLL input clock rate.
 658          * On some system, where PCI bus is running at non-standard clock rate.
 659          * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
 660          * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
 661          */
 662         pll_clock = pdc_detect_pll_input_clock(host);
 663
 664         dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
 665
 666         /* Adjust PLL control register */
 667         pdc_adjust_pll(host, pll_clock, board_idx);
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * pdc_ata_setup_port - setup the mmio address
 674  * @port: ata ioports to setup
 675  * @base: base address
 676  */
 677 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 678 {
 679         port->cmd_addr          =
 680         port->data_addr         = base;
 681         port->feature_addr      =
 682         port->error_addr        = base + 0x05;
 683         port->nsect_addr        = base + 0x0a;
 684         port->lbal_addr         = base + 0x0f;
 685         port->lbam_addr         = base + 0x10;
 686         port->lbah_addr         = base + 0x15;
 687         port->device_addr       = base + 0x1a;
 688         port->command_addr      =
 689         port->status_addr       = base + 0x1f;
 690         port->altstatus_addr    =
 691         port->ctl_addr          = base + 0x81a;
 692 }
 693
 694 /**
 695  * pdc2027x_init_one - PCI probe function
 696  * Called when an instance of PCI adapter is inserted.
 697  * This function checks whether the hardware is supported,
 698  * initialize hardware and register an instance of ata_host to
 699  * libata.  (implements struct pci_driver.probe() )
 700  *
 701  * @pdev: instance of pci_dev found
 702  * @ent:  matching entry in the id_tbl[]
 703  */
 704 static int pdc2027x_init_one(struct pci_dev *pdev,
 705                              const struct pci_device_id *ent)
 706 {
 707         static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
 708         static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
 709         unsigned int board_idx = (unsigned int) ent->driver_data;
 710         const struct ata_port_info *ppi[] =
 711                 { &pdc2027x_port_info[board_idx], NULL };
 712         struct ata_host *host;
 713         void __iomem *mmio_base;
 714         int i, rc;
 715
 716         ata_print_version_once(&pdev->dev, DRV_VERSION);
 717
 718         /* alloc host */
 719         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
 720         if (!host)
 721                 return -ENOMEM;
 722
 723         /* acquire resources and fill host */
 724         rc = pcim_enable_device(pdev);
 725         if (rc)
 726                 return rc;
 727
 728         rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
 729         if (rc)
 730                 return rc;
 731         host->iomap = pcim_iomap_table(pdev);
 732
 733         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 734         if (rc)
 735                 return rc;
 736
 737         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 738         if (rc)
 739                 return rc;
 740
 741         mmio_base = host->iomap[PDC_MMIO_BAR];
 742
 743         for (i = 0; i < 2; i++) {
 744                 struct ata_port *ap = host->ports[i];
 745
 746                 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
 747                 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
 748
 749                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
 750                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
 751         }
 752
 753         //pci_enable_intx(pdev);
 754
 755         /* initialize adapter */
 756         if (pdc_hardware_init(host, board_idx) != 0)
 757                 return -EIO;
 758
 759         pci_set_master(pdev);
 760         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 761                                  IRQF_SHARED, &pdc2027x_sht);
 762 }
 763
 764 #ifdef CONFIG_PM_SLEEP
 765 static int pdc2027x_reinit_one(struct pci_dev *pdev)
 766 {
 767         struct ata_host *host = pci_get_drvdata(pdev);
 768         unsigned int board_idx;
 769         int rc;
 770
 771         rc = ata_pci_device_do_resume(pdev);
 772         if (rc)
 773                 return rc;
 774
 775         if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
 776             pdev->device == PCI_DEVICE_ID_PROMISE_20270)
 777                 board_idx = PDC_UDMA_100;
 778         else
 779                 board_idx = PDC_UDMA_133;
 780
 781         if (pdc_hardware_init(host, board_idx))
 782                 return -EIO;
 783
 784         ata_host_resume(host);
 785         return 0;
 786 }
 787 #endif
 788
 789 module_pci_driver(pdc2027x_pci_driver);