libata: add missing CONFIG_PM in LLDs
[deliverable/linux.git] / drivers / ata / pata_via.c
1 /*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 * VIA VT8237S - UDMA133
27 * VIA VT8251 - UDMA133
28 *
29 * Most registers remain compatible across chips. Others start reserved
30 * and acquire sensible semantics if set to 1 (eg cable detect). A few
31 * exceptions exist, notably around the FIFO settings.
32 *
33 * One additional quirk of the VIA design is that like ALi they use few
34 * PCI IDs for a lot of chips.
35 *
36 * Based heavily on:
37 *
38 * Version 3.38
39 *
40 * VIA IDE driver for Linux. Supported southbridges:
41 *
42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
44 * vt8235, vt8237
45 *
46 * Copyright (c) 2000-2002 Vojtech Pavlik
47 *
48 * Based on the work of:
49 * Michel Aubry
50 * Jeff Garzik
51 * Andre Hedrick
52
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/libata.h>
63
64 #define DRV_NAME "pata_via"
65 #define DRV_VERSION "0.2.1"
66
67 /*
68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
69 * driver.
70 */
71
72 enum {
73 VIA_UDMA = 0x007,
74 VIA_UDMA_NONE = 0x000,
75 VIA_UDMA_33 = 0x001,
76 VIA_UDMA_66 = 0x002,
77 VIA_UDMA_100 = 0x003,
78 VIA_UDMA_133 = 0x004,
79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
86 };
87
88 /*
89 * VIA SouthBridge chips.
90 */
91
92 static const struct via_isa_bridge {
93 const char *name;
94 u16 id;
95 u8 rev_min;
96 u8 rev_max;
97 u16 flags;
98 } via_isa_bridges[] = {
99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
103 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
104 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
105 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
106 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
107 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
108 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
109 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
110 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
111 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
112 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
113 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
114 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
115 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
118 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
119 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
120 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
122 { NULL }
123 };
124
125 /**
126 * via_cable_detect - cable detection
127 * @ap: ATA port
128 *
129 * Perform cable detection. Actually for the VIA case the BIOS
130 * already did this for us. We read the values provided by the
131 * BIOS. If you are using an 8235 in a non-PC configuration you
132 * may need to update this code.
133 *
134 * Hotplug also impacts on this.
135 */
136
137 static int via_cable_detect(struct ata_port *ap) {
138 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
139 u32 ata66;
140
141 pci_read_config_dword(pdev, 0x50, &ata66);
142 /* Check both the drive cable reporting bits, we might not have
143 two drives */
144 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
145 return ATA_CBL_PATA80;
146 else
147 return ATA_CBL_PATA40;
148 }
149
150 static int via_pre_reset(struct ata_port *ap)
151 {
152 const struct via_isa_bridge *config = ap->host->private_data;
153
154 if (!(config->flags & VIA_NO_ENABLES)) {
155 static const struct pci_bits via_enable_bits[] = {
156 { 0x40, 1, 0x02, 0x02 },
157 { 0x40, 1, 0x01, 0x01 }
158 };
159
160 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
161
162 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
163 return -ENOENT;
164 }
165
166 if ((config->flags & VIA_UDMA) >= VIA_UDMA_100)
167 ap->cbl = via_cable_detect(ap);
168 /* The UDMA66 series has no cable detect so do drive side detect */
169 else if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
170 ap->cbl = ATA_CBL_PATA40;
171 else
172 ap->cbl = ATA_CBL_PATA_UNK;
173
174
175 return ata_std_prereset(ap);
176 }
177
178
179 /**
180 * via_error_handler - reset for VIA chips
181 * @ap: ATA port
182 *
183 * Handle the reset callback for the later chips with cable detect
184 */
185
186 static void via_error_handler(struct ata_port *ap)
187 {
188 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
189 }
190
191 /**
192 * via_do_set_mode - set initial PIO mode data
193 * @ap: ATA interface
194 * @adev: ATA device
195 * @mode: ATA mode being programmed
196 * @tdiv: Clocks per PCI clock
197 * @set_ast: Set to program address setup
198 * @udma_type: UDMA mode/format of registers
199 *
200 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
201 * support in order to compute modes.
202 *
203 * FIXME: Hotplug will require we serialize multiple mode changes
204 * on the two channels.
205 */
206
207 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
208 {
209 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
210 struct ata_device *peer = ata_dev_pair(adev);
211 struct ata_timing t, p;
212 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
213 unsigned long T = 1000000000 / via_clock;
214 unsigned long UT = T/tdiv;
215 int ut;
216 int offset = 3 - (2*ap->port_no) - adev->devno;
217
218
219 /* Calculate the timing values we require */
220 ata_timing_compute(adev, mode, &t, T, UT);
221
222 /* We share 8bit timing so we must merge the constraints */
223 if (peer) {
224 if (peer->pio_mode) {
225 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
226 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
227 }
228 }
229
230 /* Address setup is programmable but breaks on UDMA133 setups */
231 if (set_ast) {
232 u8 setup; /* 2 bits per drive */
233 int shift = 2 * offset;
234
235 pci_read_config_byte(pdev, 0x4C, &setup);
236 setup &= ~(3 << shift);
237 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
238 pci_write_config_byte(pdev, 0x4C, setup);
239 }
240
241 /* Load the PIO mode bits */
242 pci_write_config_byte(pdev, 0x4F - ap->port_no,
243 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
244 pci_write_config_byte(pdev, 0x48 + offset,
245 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
246
247 /* Load the UDMA bits according to type */
248 switch(udma_type) {
249 default:
250 /* BUG() ? */
251 /* fall through */
252 case 33:
253 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
254 break;
255 case 66:
256 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
257 break;
258 case 100:
259 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
260 break;
261 case 133:
262 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
263 break;
264 }
265 /* Set UDMA unless device is not UDMA capable */
266 if (udma_type)
267 pci_write_config_byte(pdev, 0x50 + offset, ut);
268 }
269
270 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
271 {
272 const struct via_isa_bridge *config = ap->host->private_data;
273 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
274 int mode = config->flags & VIA_UDMA;
275 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
276 static u8 udma[5] = { 0, 33, 66, 100, 133 };
277
278 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
279 }
280
281 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
282 {
283 const struct via_isa_bridge *config = ap->host->private_data;
284 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
285 int mode = config->flags & VIA_UDMA;
286 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
287 static u8 udma[5] = { 0, 33, 66, 100, 133 };
288
289 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
290 }
291
292 static struct scsi_host_template via_sht = {
293 .module = THIS_MODULE,
294 .name = DRV_NAME,
295 .ioctl = ata_scsi_ioctl,
296 .queuecommand = ata_scsi_queuecmd,
297 .can_queue = ATA_DEF_QUEUE,
298 .this_id = ATA_SHT_THIS_ID,
299 .sg_tablesize = LIBATA_MAX_PRD,
300 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
301 .emulated = ATA_SHT_EMULATED,
302 .use_clustering = ATA_SHT_USE_CLUSTERING,
303 .proc_name = DRV_NAME,
304 .dma_boundary = ATA_DMA_BOUNDARY,
305 .slave_configure = ata_scsi_slave_config,
306 .slave_destroy = ata_scsi_slave_destroy,
307 .bios_param = ata_std_bios_param,
308 #ifdef CONFIG_PM
309 .resume = ata_scsi_device_resume,
310 .suspend = ata_scsi_device_suspend,
311 #endif
312 };
313
314 static struct ata_port_operations via_port_ops = {
315 .port_disable = ata_port_disable,
316 .set_piomode = via_set_piomode,
317 .set_dmamode = via_set_dmamode,
318 .mode_filter = ata_pci_default_filter,
319
320 .tf_load = ata_tf_load,
321 .tf_read = ata_tf_read,
322 .check_status = ata_check_status,
323 .exec_command = ata_exec_command,
324 .dev_select = ata_std_dev_select,
325
326 .freeze = ata_bmdma_freeze,
327 .thaw = ata_bmdma_thaw,
328 .error_handler = via_error_handler,
329 .post_internal_cmd = ata_bmdma_post_internal_cmd,
330
331 .bmdma_setup = ata_bmdma_setup,
332 .bmdma_start = ata_bmdma_start,
333 .bmdma_stop = ata_bmdma_stop,
334 .bmdma_status = ata_bmdma_status,
335
336 .qc_prep = ata_qc_prep,
337 .qc_issue = ata_qc_issue_prot,
338
339 .data_xfer = ata_data_xfer,
340
341 .irq_handler = ata_interrupt,
342 .irq_clear = ata_bmdma_irq_clear,
343 .irq_on = ata_irq_on,
344 .irq_ack = ata_irq_ack,
345
346 .port_start = ata_port_start,
347 };
348
349 static struct ata_port_operations via_port_ops_noirq = {
350 .port_disable = ata_port_disable,
351 .set_piomode = via_set_piomode,
352 .set_dmamode = via_set_dmamode,
353 .mode_filter = ata_pci_default_filter,
354
355 .tf_load = ata_tf_load,
356 .tf_read = ata_tf_read,
357 .check_status = ata_check_status,
358 .exec_command = ata_exec_command,
359 .dev_select = ata_std_dev_select,
360
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
363 .error_handler = via_error_handler,
364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
365
366 .bmdma_setup = ata_bmdma_setup,
367 .bmdma_start = ata_bmdma_start,
368 .bmdma_stop = ata_bmdma_stop,
369 .bmdma_status = ata_bmdma_status,
370
371 .qc_prep = ata_qc_prep,
372 .qc_issue = ata_qc_issue_prot,
373
374 .data_xfer = ata_data_xfer_noirq,
375
376 .irq_handler = ata_interrupt,
377 .irq_clear = ata_bmdma_irq_clear,
378 .irq_on = ata_irq_on,
379 .irq_ack = ata_irq_ack,
380
381 .port_start = ata_port_start,
382 };
383
384 /**
385 * via_config_fifo - set up the FIFO
386 * @pdev: PCI device
387 * @flags: configuration flags
388 *
389 * Set the FIFO properties for this device if neccessary. Used both on
390 * set up and on and the resume path
391 */
392
393 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
394 {
395 u8 enable;
396
397 /* 0x40 low bits indicate enabled channels */
398 pci_read_config_byte(pdev, 0x40 , &enable);
399 enable &= 3;
400
401 if (flags & VIA_SET_FIFO) {
402 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
403 u8 fifo;
404
405 pci_read_config_byte(pdev, 0x43, &fifo);
406
407 /* Clear PREQ# until DDACK# for errata */
408 if (flags & VIA_BAD_PREQ)
409 fifo &= 0x7F;
410 else
411 fifo &= 0x9f;
412 /* Turn on FIFO for enabled channels */
413 fifo |= fifo_setting[enable];
414 pci_write_config_byte(pdev, 0x43, fifo);
415 }
416 }
417
418 /**
419 * via_init_one - discovery callback
420 * @pdev: PCI device
421 * @id: PCI table info
422 *
423 * A VIA IDE interface has been discovered. Figure out what revision
424 * and perform configuration work before handing it to the ATA layer
425 */
426
427 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
428 {
429 /* Early VIA without UDMA support */
430 static struct ata_port_info via_mwdma_info = {
431 .sht = &via_sht,
432 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
433 .pio_mask = 0x1f,
434 .mwdma_mask = 0x07,
435 .port_ops = &via_port_ops
436 };
437 /* Ditto with IRQ masking required */
438 static struct ata_port_info via_mwdma_info_borked = {
439 .sht = &via_sht,
440 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
441 .pio_mask = 0x1f,
442 .mwdma_mask = 0x07,
443 .port_ops = &via_port_ops_noirq,
444 };
445 /* VIA UDMA 33 devices (and borked 66) */
446 static struct ata_port_info via_udma33_info = {
447 .sht = &via_sht,
448 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
449 .pio_mask = 0x1f,
450 .mwdma_mask = 0x07,
451 .udma_mask = 0x7,
452 .port_ops = &via_port_ops
453 };
454 /* VIA UDMA 66 devices */
455 static struct ata_port_info via_udma66_info = {
456 .sht = &via_sht,
457 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
458 .pio_mask = 0x1f,
459 .mwdma_mask = 0x07,
460 .udma_mask = 0x1f,
461 .port_ops = &via_port_ops
462 };
463 /* VIA UDMA 100 devices */
464 static struct ata_port_info via_udma100_info = {
465 .sht = &via_sht,
466 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
467 .pio_mask = 0x1f,
468 .mwdma_mask = 0x07,
469 .udma_mask = 0x3f,
470 .port_ops = &via_port_ops
471 };
472 /* UDMA133 with bad AST (All current 133) */
473 static struct ata_port_info via_udma133_info = {
474 .sht = &via_sht,
475 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
476 .pio_mask = 0x1f,
477 .mwdma_mask = 0x07,
478 .udma_mask = 0x7f, /* FIXME: should check north bridge */
479 .port_ops = &via_port_ops
480 };
481 struct ata_port_info *port_info[2], *type;
482 struct pci_dev *isa = NULL;
483 const struct via_isa_bridge *config;
484 static int printed_version;
485 u8 t;
486 u8 enable;
487 u32 timing;
488
489 if (!printed_version++)
490 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
491
492 /* To find out how the IDE will behave and what features we
493 actually have to look at the bridge not the IDE controller */
494 for (config = via_isa_bridges; config->id; config++)
495 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
496 !!(config->flags & VIA_BAD_ID),
497 config->id, NULL))) {
498
499 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
500 if (t >= config->rev_min &&
501 t <= config->rev_max)
502 break;
503 pci_dev_put(isa);
504 }
505
506 if (!config->id) {
507 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
508 return -ENODEV;
509 }
510 pci_dev_put(isa);
511
512 /* 0x40 low bits indicate enabled channels */
513 pci_read_config_byte(pdev, 0x40 , &enable);
514 enable &= 3;
515 if (enable == 0) {
516 return -ENODEV;
517 }
518
519 /* Initialise the FIFO for the enabled channels. */
520 via_config_fifo(pdev, config->flags);
521
522 /* Clock set up */
523 switch(config->flags & VIA_UDMA) {
524 case VIA_UDMA_NONE:
525 if (config->flags & VIA_NO_UNMASK)
526 type = &via_mwdma_info_borked;
527 else
528 type = &via_mwdma_info;
529 break;
530 case VIA_UDMA_33:
531 type = &via_udma33_info;
532 break;
533 case VIA_UDMA_66:
534 type = &via_udma66_info;
535 /* The 66 MHz devices require we enable the clock */
536 pci_read_config_dword(pdev, 0x50, &timing);
537 timing |= 0x80008;
538 pci_write_config_dword(pdev, 0x50, timing);
539 break;
540 case VIA_UDMA_100:
541 type = &via_udma100_info;
542 break;
543 case VIA_UDMA_133:
544 type = &via_udma133_info;
545 break;
546 default:
547 WARN_ON(1);
548 return -ENODEV;
549 }
550
551 if (config->flags & VIA_BAD_CLK66) {
552 /* Disable the 66MHz clock on problem devices */
553 pci_read_config_dword(pdev, 0x50, &timing);
554 timing &= ~0x80008;
555 pci_write_config_dword(pdev, 0x50, timing);
556 }
557
558 /* We have established the device type, now fire it up */
559 type->private_data = (void *)config;
560
561 port_info[0] = port_info[1] = type;
562 return ata_pci_init_one(pdev, port_info, 2);
563 }
564
565 #ifdef CONFIG_PM
566 /**
567 * via_reinit_one - reinit after resume
568 * @pdev; PCI device
569 *
570 * Called when the VIA PATA device is resumed. We must then
571 * reconfigure the fifo and other setup we may have altered. In
572 * addition the kernel needs to have the resume methods on PCI
573 * quirk supported.
574 */
575
576 static int via_reinit_one(struct pci_dev *pdev)
577 {
578 u32 timing;
579 struct ata_host *host = dev_get_drvdata(&pdev->dev);
580 const struct via_isa_bridge *config = host->private_data;
581
582 via_config_fifo(pdev, config->flags);
583
584 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
585 /* The 66 MHz devices require we enable the clock */
586 pci_read_config_dword(pdev, 0x50, &timing);
587 timing |= 0x80008;
588 pci_write_config_dword(pdev, 0x50, timing);
589 }
590 if (config->flags & VIA_BAD_CLK66) {
591 /* Disable the 66MHz clock on problem devices */
592 pci_read_config_dword(pdev, 0x50, &timing);
593 timing &= ~0x80008;
594 pci_write_config_dword(pdev, 0x50, timing);
595 }
596 return ata_pci_device_resume(pdev);
597 }
598 #endif
599
600 static const struct pci_device_id via[] = {
601 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
602 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
603 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
604 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
605
606 { },
607 };
608
609 static struct pci_driver via_pci_driver = {
610 .name = DRV_NAME,
611 .id_table = via,
612 .probe = via_init_one,
613 .remove = ata_pci_remove_one,
614 #ifdef CONFIG_PM
615 .suspend = ata_pci_device_suspend,
616 .resume = via_reinit_one,
617 #endif
618 };
619
620 static int __init via_init(void)
621 {
622 return pci_register_driver(&via_pci_driver);
623 }
624
625 static void __exit via_exit(void)
626 {
627 pci_unregister_driver(&via_pci_driver);
628 }
629
630 MODULE_AUTHOR("Alan Cox");
631 MODULE_DESCRIPTION("low-level driver for VIA PATA");
632 MODULE_LICENSE("GPL");
633 MODULE_DEVICE_TABLE(pci, via);
634 MODULE_VERSION(DRV_VERSION);
635
636 module_init(via_init);
637 module_exit(via_exit);
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