drivers/ata/sata_qstor.c

   1 /*
   2  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Pacific Digital Corporation.
   7  *  (OSL/GPL code release authorized by Jalil Fadavi).
   8  *
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; see the file COPYING.  If not, write to
  22  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  *
  25  *  libata documentation is available via 'make {ps|pdf}docs',
  26  *  as Documentation/DocBook/libata.*
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/gfp.h>
  33 #include <linux/pci.h>
  34 #include <linux/blkdev.h>
  35 #include <linux/delay.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/device.h>
  38 #include <scsi/scsi_host.h>
  39 #include <linux/libata.h>
  40
  41 #define DRV_NAME        "sata_qstor"
  42 #define DRV_VERSION     "0.09"
  43
  44 enum {
  45         QS_MMIO_BAR             = 4,
  46
  47         QS_PORTS                = 4,
  48         QS_MAX_PRD              = LIBATA_MAX_PRD,
  49         QS_CPB_ORDER            = 6,
  50         QS_CPB_BYTES            = (1 << QS_CPB_ORDER),
  51         QS_PRD_BYTES            = QS_MAX_PRD * 16,
  52         QS_PKT_BYTES            = QS_CPB_BYTES + QS_PRD_BYTES,
  53
  54         /* global register offsets */
  55         QS_HCF_CNFG3            = 0x0003, /* host configuration offset */
  56         QS_HID_HPHY             = 0x0004, /* host physical interface info */
  57         QS_HCT_CTRL             = 0x00e4, /* global interrupt mask offset */
  58         QS_HST_SFF              = 0x0100, /* host status fifo offset */
  59         QS_HVS_SERD3            = 0x0393, /* PHY enable offset */
  60
  61         /* global control bits */
  62         QS_HPHY_64BIT           = (1 << 1), /* 64-bit bus detected */
  63         QS_CNFG3_GSRST          = 0x01,     /* global chip reset */
  64         QS_SERD3_PHY_ENA        = 0xf0,     /* PHY detection ENAble*/
  65
  66         /* per-channel register offsets */
  67         QS_CCF_CPBA             = 0x0710, /* chan CPB base address */
  68         QS_CCF_CSEP             = 0x0718, /* chan CPB separation factor */
  69         QS_CFC_HUFT             = 0x0800, /* host upstream fifo threshold */
  70         QS_CFC_HDFT             = 0x0804, /* host downstream fifo threshold */
  71         QS_CFC_DUFT             = 0x0808, /* dev upstream fifo threshold */
  72         QS_CFC_DDFT             = 0x080c, /* dev downstream fifo threshold */
  73         QS_CCT_CTR0             = 0x0900, /* chan control-0 offset */
  74         QS_CCT_CTR1             = 0x0901, /* chan control-1 offset */
  75         QS_CCT_CFF              = 0x0a00, /* chan command fifo offset */
  76
  77         /* channel control bits */
  78         QS_CTR0_REG             = (1 << 1),   /* register mode (vs. pkt mode) */
  79         QS_CTR0_CLER            = (1 << 2),   /* clear channel errors */
  80         QS_CTR1_RDEV            = (1 << 1),   /* sata phy/comms reset */
  81         QS_CTR1_RCHN            = (1 << 4),   /* reset channel logic */
  82         QS_CCF_RUN_PKT          = 0x107,      /* RUN a new dma PKT */
  83
  84         /* pkt sub-field headers */
  85         QS_HCB_HDR              = 0x01,   /* Host Control Block header */
  86         QS_DCB_HDR              = 0x02,   /* Device Control Block header */
  87
  88         /* pkt HCB flag bits */
  89         QS_HF_DIRO              = (1 << 0),   /* data DIRection Out */
  90         QS_HF_DAT               = (1 << 3),   /* DATa pkt */
  91         QS_HF_IEN               = (1 << 4),   /* Interrupt ENable */
  92         QS_HF_VLD               = (1 << 5),   /* VaLiD pkt */
  93
  94         /* pkt DCB flag bits */
  95         QS_DF_PORD              = (1 << 2),   /* Pio OR Dma */
  96         QS_DF_ELBA              = (1 << 3),   /* Extended LBA (lba48) */
  97
  98         /* PCI device IDs */
  99         board_2068_idx          = 0,    /* QStor 4-port SATA/RAID */
 100 };
 101
 102 enum {
 103         QS_DMA_BOUNDARY         = ~0UL
 104 };
 105
 106 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
 107
 108 struct qs_port_priv {
 109         u8                      *pkt;
 110         dma_addr_t              pkt_dma;
 111         qs_state_t              state;
 112 };
 113
 114 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
 115 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
 116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 117 static int qs_port_start(struct ata_port *ap);
 118 static void qs_host_stop(struct ata_host *host);
 119 static void qs_qc_prep(struct ata_queued_cmd *qc);
 120 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
 121 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
 122 static void qs_freeze(struct ata_port *ap);
 123 static void qs_thaw(struct ata_port *ap);
 124 static int qs_prereset(struct ata_link *link, unsigned long deadline);
 125 static void qs_error_handler(struct ata_port *ap);
 126
 127 static struct scsi_host_template qs_ata_sht = {
 128         ATA_BASE_SHT(DRV_NAME),
 129         .sg_tablesize           = QS_MAX_PRD,
 130         .dma_boundary           = QS_DMA_BOUNDARY,
 131 };
 132
 133 static struct ata_port_operations qs_ata_ops = {
 134         .inherits               = &ata_sff_port_ops,
 135
 136         .check_atapi_dma        = qs_check_atapi_dma,
 137         .qc_prep                = qs_qc_prep,
 138         .qc_issue               = qs_qc_issue,
 139
 140         .freeze                 = qs_freeze,
 141         .thaw                   = qs_thaw,
 142         .prereset               = qs_prereset,
 143         .softreset              = ATA_OP_NULL,
 144         .error_handler          = qs_error_handler,
 145         .lost_interrupt         = ATA_OP_NULL,
 146
 147         .scr_read               = qs_scr_read,
 148         .scr_write              = qs_scr_write,
 149
 150         .port_start             = qs_port_start,
 151         .host_stop              = qs_host_stop,
 152 };
 153
 154 static const struct ata_port_info qs_port_info[] = {
 155         /* board_2068_idx */
 156         {
 157                 .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
 158                 .pio_mask       = ATA_PIO4_ONLY,
 159                 .udma_mask      = ATA_UDMA6,
 160                 .port_ops       = &qs_ata_ops,
 161         },
 162 };
 163
 164 static const struct pci_device_id qs_ata_pci_tbl[] = {
 165         { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
 166
 167         { }     /* terminate list */
 168 };
 169
 170 static struct pci_driver qs_ata_pci_driver = {
 171         .name                   = DRV_NAME,
 172         .id_table               = qs_ata_pci_tbl,
 173         .probe                  = qs_ata_init_one,
 174         .remove                 = ata_pci_remove_one,
 175 };
 176
 177 static void __iomem *qs_mmio_base(struct ata_host *host)
 178 {
 179         return host->iomap[QS_MMIO_BAR];
 180 }
 181
 182 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
 183 {
 184         return 1;       /* ATAPI DMA not supported */
 185 }
 186
 187 static inline void qs_enter_reg_mode(struct ata_port *ap)
 188 {
 189         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 190         struct qs_port_priv *pp = ap->private_data;
 191
 192         pp->state = qs_state_mmio;
 193         writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 194         readb(chan + QS_CCT_CTR0);        /* flush */
 195 }
 196
 197 static inline void qs_reset_channel_logic(struct ata_port *ap)
 198 {
 199         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 200
 201         writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 202         readb(chan + QS_CCT_CTR0);        /* flush */
 203         qs_enter_reg_mode(ap);
 204 }
 205
 206 static void qs_freeze(struct ata_port *ap)
 207 {
 208         u8 __iomem *mmio_base = qs_mmio_base(ap->host);
 209
 210         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 211         qs_enter_reg_mode(ap);
 212 }
 213
 214 static void qs_thaw(struct ata_port *ap)
 215 {
 216         u8 __iomem *mmio_base = qs_mmio_base(ap->host);
 217
 218         qs_enter_reg_mode(ap);
 219         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 220 }
 221
 222 static int qs_prereset(struct ata_link *link, unsigned long deadline)
 223 {
 224         struct ata_port *ap = link->ap;
 225
 226         qs_reset_channel_logic(ap);
 227         return ata_sff_prereset(link, deadline);
 228 }
 229
 230 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 231 {
 232         if (sc_reg > SCR_CONTROL)
 233                 return -EINVAL;
 234         *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
 235         return 0;
 236 }
 237
 238 static void qs_error_handler(struct ata_port *ap)
 239 {
 240         qs_enter_reg_mode(ap);
 241         ata_sff_error_handler(ap);
 242 }
 243
 244 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
 245 {
 246         if (sc_reg > SCR_CONTROL)
 247                 return -EINVAL;
 248         writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
 249         return 0;
 250 }
 251
 252 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
 253 {
 254         struct scatterlist *sg;
 255         struct ata_port *ap = qc->ap;
 256         struct qs_port_priv *pp = ap->private_data;
 257         u8 *prd = pp->pkt + QS_CPB_BYTES;
 258         unsigned int si;
 259
 260         for_each_sg(qc->sg, sg, qc->n_elem, si) {
 261                 u64 addr;
 262                 u32 len;
 263
 264                 addr = sg_dma_address(sg);
 265                 *(__le64 *)prd = cpu_to_le64(addr);
 266                 prd += sizeof(u64);
 267
 268                 len = sg_dma_len(sg);
 269                 *(__le32 *)prd = cpu_to_le32(len);
 270                 prd += sizeof(u64);
 271
 272                 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
 273                                         (unsigned long long)addr, len);
 274         }
 275
 276         return si;
 277 }
 278
 279 static void qs_qc_prep(struct ata_queued_cmd *qc)
 280 {
 281         struct qs_port_priv *pp = qc->ap->private_data;
 282         u8 dflags = QS_DF_PORD, *buf = pp->pkt;
 283         u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
 284         u64 addr;
 285         unsigned int nelem;
 286
 287         VPRINTK("ENTER\n");
 288
 289         qs_enter_reg_mode(qc->ap);
 290         if (qc->tf.protocol != ATA_PROT_DMA)
 291                 return;
 292
 293         nelem = qs_fill_sg(qc);
 294
 295         if ((qc->tf.flags & ATA_TFLAG_WRITE))
 296                 hflags |= QS_HF_DIRO;
 297         if ((qc->tf.flags & ATA_TFLAG_LBA48))
 298                 dflags |= QS_DF_ELBA;
 299
 300         /* host control block (HCB) */
 301         buf[ 0] = QS_HCB_HDR;
 302         buf[ 1] = hflags;
 303         *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
 304         *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
 305         addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
 306         *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
 307
 308         /* device control block (DCB) */
 309         buf[24] = QS_DCB_HDR;
 310         buf[28] = dflags;
 311
 312         /* frame information structure (FIS) */
 313         ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
 314 }
 315
 316 static inline void qs_packet_start(struct ata_queued_cmd *qc)
 317 {
 318         struct ata_port *ap = qc->ap;
 319         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 320
 321         VPRINTK("ENTER, ap %p\n", ap);
 322
 323         writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
 324         wmb();                             /* flush PRDs and pkt to memory */
 325         writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
 326         readl(chan + QS_CCT_CFF);          /* flush */
 327 }
 328
 329 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
 330 {
 331         struct qs_port_priv *pp = qc->ap->private_data;
 332
 333         switch (qc->tf.protocol) {
 334         case ATA_PROT_DMA:
 335                 pp->state = qs_state_pkt;
 336                 qs_packet_start(qc);
 337                 return 0;
 338
 339         case ATAPI_PROT_DMA:
 340                 BUG();
 341                 break;
 342
 343         default:
 344                 break;
 345         }
 346
 347         pp->state = qs_state_mmio;
 348         return ata_sff_qc_issue(qc);
 349 }
 350
 351 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
 352 {
 353         qc->err_mask |= ac_err_mask(status);
 354
 355         if (!qc->err_mask) {
 356                 ata_qc_complete(qc);
 357         } else {
 358                 struct ata_port    *ap  = qc->ap;
 359                 struct ata_eh_info *ehi = &ap->link.eh_info;
 360
 361                 ata_ehi_clear_desc(ehi);
 362                 ata_ehi_push_desc(ehi, "status 0x%02X", status);
 363
 364                 if (qc->err_mask == AC_ERR_DEV)
 365                         ata_port_abort(ap);
 366                 else
 367                         ata_port_freeze(ap);
 368         }
 369 }
 370
 371 static inline unsigned int qs_intr_pkt(struct ata_host *host)
 372 {
 373         unsigned int handled = 0;
 374         u8 sFFE;
 375         u8 __iomem *mmio_base = qs_mmio_base(host);
 376
 377         do {
 378                 u32 sff0 = readl(mmio_base + QS_HST_SFF);
 379                 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
 380                 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
 381                 sFFE  = sff1 >> 31;             /* empty flag */
 382
 383                 if (sEVLD) {
 384                         u8 sDST = sff0 >> 16;   /* dev status */
 385                         u8 sHST = sff1 & 0x3f;  /* host status */
 386                         unsigned int port_no = (sff1 >> 8) & 0x03;
 387                         struct ata_port *ap = host->ports[port_no];
 388                         struct qs_port_priv *pp = ap->private_data;
 389                         struct ata_queued_cmd *qc;
 390
 391                         DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
 392                                         sff1, sff0, port_no, sHST, sDST);
 393                         handled = 1;
 394                         if (!pp || pp->state != qs_state_pkt)
 395                                 continue;
 396                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
 397                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 398                                 switch (sHST) {
 399                                 case 0: /* successful CPB */
 400                                 case 3: /* device error */
 401                                         qs_enter_reg_mode(qc->ap);
 402                                         qs_do_or_die(qc, sDST);
 403                                         break;
 404                                 default:
 405                                         break;
 406                                 }
 407                         }
 408                 }
 409         } while (!sFFE);
 410         return handled;
 411 }
 412
 413 static inline unsigned int qs_intr_mmio(struct ata_host *host)
 414 {
 415         unsigned int handled = 0, port_no;
 416
 417         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 418                 struct ata_port *ap = host->ports[port_no];
 419                 struct qs_port_priv *pp = ap->private_data;
 420                 struct ata_queued_cmd *qc;
 421
 422                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 423                 if (!qc) {
 424                         /*
 425                          * The qstor hardware generates spurious
 426                          * interrupts from time to time when switching
 427                          * in and out of packet mode.  There's no
 428                          * obvious way to know if we're here now due
 429                          * to that, so just ack the irq and pretend we
 430                          * knew it was ours.. (ugh).  This does not
 431                          * affect packet mode.
 432                          */
 433                         ata_sff_check_status(ap);
 434                         handled = 1;
 435                         continue;
 436                 }
 437
 438                 if (!pp || pp->state != qs_state_mmio)
 439                         continue;
 440                 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
 441                         handled |= ata_sff_port_intr(ap, qc);
 442         }
 443         return handled;
 444 }
 445
 446 static irqreturn_t qs_intr(int irq, void *dev_instance)
 447 {
 448         struct ata_host *host = dev_instance;
 449         unsigned int handled = 0;
 450         unsigned long flags;
 451
 452         VPRINTK("ENTER\n");
 453
 454         spin_lock_irqsave(&host->lock, flags);
 455         handled  = qs_intr_pkt(host) | qs_intr_mmio(host);
 456         spin_unlock_irqrestore(&host->lock, flags);
 457
 458         VPRINTK("EXIT\n");
 459
 460         return IRQ_RETVAL(handled);
 461 }
 462
 463 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 464 {
 465         port->cmd_addr          =
 466         port->data_addr         = base + 0x400;
 467         port->error_addr        =
 468         port->feature_addr      = base + 0x408; /* hob_feature = 0x409 */
 469         port->nsect_addr        = base + 0x410; /* hob_nsect   = 0x411 */
 470         port->lbal_addr         = base + 0x418; /* hob_lbal    = 0x419 */
 471         port->lbam_addr         = base + 0x420; /* hob_lbam    = 0x421 */
 472         port->lbah_addr         = base + 0x428; /* hob_lbah    = 0x429 */
 473         port->device_addr       = base + 0x430;
 474         port->status_addr       =
 475         port->command_addr      = base + 0x438;
 476         port->altstatus_addr    =
 477         port->ctl_addr          = base + 0x440;
 478         port->scr_addr          = base + 0xc00;
 479 }
 480
 481 static int qs_port_start(struct ata_port *ap)
 482 {
 483         struct device *dev = ap->host->dev;
 484         struct qs_port_priv *pp;
 485         void __iomem *mmio_base = qs_mmio_base(ap->host);
 486         void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
 487         u64 addr;
 488
 489         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 490         if (!pp)
 491                 return -ENOMEM;
 492         pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
 493                                       GFP_KERNEL);
 494         if (!pp->pkt)
 495                 return -ENOMEM;
 496         memset(pp->pkt, 0, QS_PKT_BYTES);
 497         ap->private_data = pp;
 498
 499         qs_enter_reg_mode(ap);
 500         addr = (u64)pp->pkt_dma;
 501         writel((u32) addr,        chan + QS_CCF_CPBA);
 502         writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
 503         return 0;
 504 }
 505
 506 static void qs_host_stop(struct ata_host *host)
 507 {
 508         void __iomem *mmio_base = qs_mmio_base(host);
 509
 510         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 511         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 512 }
 513
 514 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
 515 {
 516         void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
 517         unsigned int port_no;
 518
 519         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 520         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 521
 522         /* reset each channel in turn */
 523         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 524                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 525                 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 526                 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 527                 readb(chan + QS_CCT_CTR0);        /* flush */
 528         }
 529         writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
 530
 531         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 532                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 533                 /* set FIFO depths to same settings as Windows driver */
 534                 writew(32, chan + QS_CFC_HUFT);
 535                 writew(32, chan + QS_CFC_HDFT);
 536                 writew(10, chan + QS_CFC_DUFT);
 537                 writew( 8, chan + QS_CFC_DDFT);
 538                 /* set CPB size in bytes, as a power of two */
 539                 writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
 540         }
 541         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 542 }
 543
 544 /*
 545  * The QStor understands 64-bit buses, and uses 64-bit fields
 546  * for DMA pointers regardless of bus width.  We just have to
 547  * make sure our DMA masks are set appropriately for whatever
 548  * bridge lies between us and the QStor, and then the DMA mapping
 549  * code will ensure we only ever "see" appropriate buffer addresses.
 550  * If we're 32-bit limited somewhere, then our 64-bit fields will
 551  * just end up with zeros in the upper 32-bits, without any special
 552  * logic required outside of this routine (below).
 553  */
 554 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 555 {
 556         u32 bus_info = readl(mmio_base + QS_HID_HPHY);
 557         int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
 558
 559         if (have_64bit_bus &&
 560             !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 561                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
 562                 if (rc) {
 563                         rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 564                         if (rc) {
 565                                 dev_err(&pdev->dev,
 566                                         "64-bit DMA enable failed\n");
 567                                 return rc;
 568                         }
 569                 }
 570         } else {
 571                 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 572                 if (rc) {
 573                         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 574                         return rc;
 575                 }
 576                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 577                 if (rc) {
 578                         dev_err(&pdev->dev,
 579                                 "32-bit consistent DMA enable failed\n");
 580                         return rc;
 581                 }
 582         }
 583         return 0;
 584 }
 585
 586 static int qs_ata_init_one(struct pci_dev *pdev,
 587                                 const struct pci_device_id *ent)
 588 {
 589         unsigned int board_idx = (unsigned int) ent->driver_data;
 590         const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
 591         struct ata_host *host;
 592         int rc, port_no;
 593
 594         ata_print_version_once(&pdev->dev, DRV_VERSION);
 595
 596         /* alloc host */
 597         host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
 598         if (!host)
 599                 return -ENOMEM;
 600
 601         /* acquire resources and fill host */
 602         rc = pcim_enable_device(pdev);
 603         if (rc)
 604                 return rc;
 605
 606         if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
 607                 return -ENODEV;
 608
 609         rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
 610         if (rc)
 611                 return rc;
 612         host->iomap = pcim_iomap_table(pdev);
 613
 614         rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
 615         if (rc)
 616                 return rc;
 617
 618         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 619                 struct ata_port *ap = host->ports[port_no];
 620                 unsigned int offset = port_no * 0x4000;
 621                 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
 622
 623                 qs_ata_setup_port(&ap->ioaddr, chan);
 624
 625                 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
 626                 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
 627         }
 628
 629         /* initialize adapter */
 630         qs_host_init(host, board_idx);
 631
 632         pci_set_master(pdev);
 633         return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
 634                                  &qs_ata_sht);
 635 }
 636
 637 module_pci_driver(qs_ata_pci_driver);
 638
 639 MODULE_AUTHOR("Mark Lord");
 640 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
 641 MODULE_LICENSE("GPL");
 642 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
 643 MODULE_VERSION(DRV_VERSION);