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libata: add missing CONFIG_PM in LLDs
[deliverable/linux.git] / drivers / ata / sata_sil.c
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.1"
50
51 enum {
52 SIL_MMIO_BAR = 5,
53
54 /*
55 * host flags
56 */
57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 SIL_FLAG_MOD15WRITE = (1 << 30),
60
61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
63
64 /*
65 * Controller IDs
66 */
67 sil_3112 = 0,
68 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
71
72 /*
73 * Register offsets
74 */
75 SIL_SYSCFG = 0x48,
76
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
81 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
89 /* BMDMA/BMDMA2 */
90 SIL_INTR_STEERING = (1 << 1),
91
92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
106 /*
107 * Others
108 */
109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111 };
112
113 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
114 #ifdef CONFIG_PM
115 static int sil_pci_device_resume(struct pci_dev *pdev);
116 #endif
117 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
118 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static void sil_post_set_mode (struct ata_port *ap);
121 static irqreturn_t sil_interrupt(int irq, void *dev_instance);
122 static void sil_freeze(struct ata_port *ap);
123 static void sil_thaw(struct ata_port *ap);
124
125
126 static const struct pci_device_id sil_pci_tbl[] = {
127 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
129 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
130 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
131 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
132 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
133 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
134
135 { } /* terminate list */
136 };
137
138
139 /* TODO firmware versions should be added - eric */
140 static const struct sil_drivelist {
141 const char * product;
142 unsigned int quirk;
143 } sil_blacklist [] = {
144 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
145 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
146 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
147 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
148 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
156 { }
157 };
158
159 static struct pci_driver sil_pci_driver = {
160 .name = DRV_NAME,
161 .id_table = sil_pci_tbl,
162 .probe = sil_init_one,
163 .remove = ata_pci_remove_one,
164 #ifdef CONFIG_PM
165 .suspend = ata_pci_device_suspend,
166 .resume = sil_pci_device_resume,
167 #endif
168 };
169
170 static struct scsi_host_template sil_sht = {
171 .module = THIS_MODULE,
172 .name = DRV_NAME,
173 .ioctl = ata_scsi_ioctl,
174 .queuecommand = ata_scsi_queuecmd,
175 .can_queue = ATA_DEF_QUEUE,
176 .this_id = ATA_SHT_THIS_ID,
177 .sg_tablesize = LIBATA_MAX_PRD,
178 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
179 .emulated = ATA_SHT_EMULATED,
180 .use_clustering = ATA_SHT_USE_CLUSTERING,
181 .proc_name = DRV_NAME,
182 .dma_boundary = ATA_DMA_BOUNDARY,
183 .slave_configure = ata_scsi_slave_config,
184 .slave_destroy = ata_scsi_slave_destroy,
185 .bios_param = ata_std_bios_param,
186 #ifdef CONFIG_PM
187 .suspend = ata_scsi_device_suspend,
188 .resume = ata_scsi_device_resume,
189 #endif
190 };
191
192 static const struct ata_port_operations sil_ops = {
193 .port_disable = ata_port_disable,
194 .dev_config = sil_dev_config,
195 .tf_load = ata_tf_load,
196 .tf_read = ata_tf_read,
197 .check_status = ata_check_status,
198 .exec_command = ata_exec_command,
199 .dev_select = ata_std_dev_select,
200 .post_set_mode = sil_post_set_mode,
201 .bmdma_setup = ata_bmdma_setup,
202 .bmdma_start = ata_bmdma_start,
203 .bmdma_stop = ata_bmdma_stop,
204 .bmdma_status = ata_bmdma_status,
205 .qc_prep = ata_qc_prep,
206 .qc_issue = ata_qc_issue_prot,
207 .data_xfer = ata_data_xfer,
208 .freeze = sil_freeze,
209 .thaw = sil_thaw,
210 .error_handler = ata_bmdma_error_handler,
211 .post_internal_cmd = ata_bmdma_post_internal_cmd,
212 .irq_handler = sil_interrupt,
213 .irq_clear = ata_bmdma_irq_clear,
214 .irq_on = ata_irq_on,
215 .irq_ack = ata_irq_ack,
216 .scr_read = sil_scr_read,
217 .scr_write = sil_scr_write,
218 .port_start = ata_port_start,
219 };
220
221 static const struct ata_port_info sil_port_info[] = {
222 /* sil_3112 */
223 {
224 .sht = &sil_sht,
225 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = 0x3f, /* udma0-5 */
229 .port_ops = &sil_ops,
230 },
231 /* sil_3112_no_sata_irq */
232 {
233 .sht = &sil_sht,
234 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
235 SIL_FLAG_NO_SATA_IRQ,
236 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */
238 .udma_mask = 0x3f, /* udma0-5 */
239 .port_ops = &sil_ops,
240 },
241 /* sil_3512 */
242 {
243 .sht = &sil_sht,
244 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
245 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */
247 .udma_mask = 0x3f, /* udma0-5 */
248 .port_ops = &sil_ops,
249 },
250 /* sil_3114 */
251 {
252 .sht = &sil_sht,
253 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
254 .pio_mask = 0x1f, /* pio0-4 */
255 .mwdma_mask = 0x07, /* mwdma0-2 */
256 .udma_mask = 0x3f, /* udma0-5 */
257 .port_ops = &sil_ops,
258 },
259 };
260
261 /* per-port register offsets */
262 /* TODO: we can probably calculate rather than use a table */
263 static const struct {
264 unsigned long tf; /* ATA taskfile register block */
265 unsigned long ctl; /* ATA control/altstatus register block */
266 unsigned long bmdma; /* DMA register block */
267 unsigned long bmdma2; /* DMA register block #2 */
268 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
269 unsigned long scr; /* SATA control register block */
270 unsigned long sien; /* SATA Interrupt Enable register */
271 unsigned long xfer_mode;/* data transfer mode register */
272 unsigned long sfis_cfg; /* SATA FIS reception config register */
273 } sil_port[] = {
274 /* port 0 ... */
275 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
276 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
277 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
278 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
279 /* ... port 3 */
280 };
281
282 MODULE_AUTHOR("Jeff Garzik");
283 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
284 MODULE_LICENSE("GPL");
285 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
286 MODULE_VERSION(DRV_VERSION);
287
288 static int slow_down = 0;
289 module_param(slow_down, int, 0444);
290 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
291
292
293 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
294 {
295 u8 cache_line = 0;
296 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
297 return cache_line;
298 }
299
300 static void sil_post_set_mode (struct ata_port *ap)
301 {
302 struct ata_host *host = ap->host;
303 struct ata_device *dev;
304 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
305 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
306 u32 tmp, dev_mode[2];
307 unsigned int i;
308
309 for (i = 0; i < 2; i++) {
310 dev = &ap->device[i];
311 if (!ata_dev_enabled(dev))
312 dev_mode[i] = 0; /* PIO0/1/2 */
313 else if (dev->flags & ATA_DFLAG_PIO)
314 dev_mode[i] = 1; /* PIO3/4 */
315 else
316 dev_mode[i] = 3; /* UDMA */
317 /* value 2 indicates MDMA */
318 }
319
320 tmp = readl(addr);
321 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
322 tmp |= dev_mode[0];
323 tmp |= (dev_mode[1] << 4);
324 writel(tmp, addr);
325 readl(addr); /* flush */
326 }
327
328 static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
329 {
330 void __iomem *offset = ap->ioaddr.scr_addr;
331
332 switch (sc_reg) {
333 case SCR_STATUS:
334 return offset + 4;
335 case SCR_ERROR:
336 return offset + 8;
337 case SCR_CONTROL:
338 return offset;
339 default:
340 /* do nothing */
341 break;
342 }
343
344 return NULL;
345 }
346
347 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
348 {
349 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
350 if (mmio)
351 return readl(mmio);
352 return 0xffffffffU;
353 }
354
355 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
356 {
357 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
358 if (mmio)
359 writel(val, mmio);
360 }
361
362 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
363 {
364 struct ata_eh_info *ehi = &ap->eh_info;
365 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
366 u8 status;
367
368 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
369 u32 serror;
370
371 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
372 * controllers continue to assert IRQ as long as
373 * SError bits are pending. Clear SError immediately.
374 */
375 serror = sil_scr_read(ap, SCR_ERROR);
376 sil_scr_write(ap, SCR_ERROR, serror);
377
378 /* Trigger hotplug and accumulate SError only if the
379 * port isn't already frozen. Otherwise, PHY events
380 * during hardreset makes controllers with broken SIEN
381 * repeat probing needlessly.
382 */
383 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
384 ata_ehi_hotplugged(&ap->eh_info);
385 ap->eh_info.serror |= serror;
386 }
387
388 goto freeze;
389 }
390
391 if (unlikely(!qc))
392 goto freeze;
393
394 if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
395 /* this sometimes happens, just clear IRQ */
396 ata_chk_status(ap);
397 return;
398 }
399
400 /* Check whether we are expecting interrupt in this state */
401 switch (ap->hsm_task_state) {
402 case HSM_ST_FIRST:
403 /* Some pre-ATAPI-4 devices assert INTRQ
404 * at this state when ready to receive CDB.
405 */
406
407 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
408 * The flag was turned on only for atapi devices.
409 * No need to check is_atapi_taskfile(&qc->tf) again.
410 */
411 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
412 goto err_hsm;
413 break;
414 case HSM_ST_LAST:
415 if (qc->tf.protocol == ATA_PROT_DMA ||
416 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
417 /* clear DMA-Start bit */
418 ap->ops->bmdma_stop(qc);
419
420 if (bmdma2 & SIL_DMA_ERROR) {
421 qc->err_mask |= AC_ERR_HOST_BUS;
422 ap->hsm_task_state = HSM_ST_ERR;
423 }
424 }
425 break;
426 case HSM_ST:
427 break;
428 default:
429 goto err_hsm;
430 }
431
432 /* check main status, clearing INTRQ */
433 status = ata_chk_status(ap);
434 if (unlikely(status & ATA_BUSY))
435 goto err_hsm;
436
437 /* ack bmdma irq events */
438 ata_bmdma_irq_clear(ap);
439
440 /* kick HSM in the ass */
441 ata_hsm_move(ap, qc, status, 0);
442
443 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
444 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
445 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
446
447 return;
448
449 err_hsm:
450 qc->err_mask |= AC_ERR_HSM;
451 freeze:
452 ata_port_freeze(ap);
453 }
454
455 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
456 {
457 struct ata_host *host = dev_instance;
458 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
459 int handled = 0;
460 int i;
461
462 spin_lock(&host->lock);
463
464 for (i = 0; i < host->n_ports; i++) {
465 struct ata_port *ap = host->ports[i];
466 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
467
468 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
469 continue;
470
471 /* turn off SATA_IRQ if not supported */
472 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
473 bmdma2 &= ~SIL_DMA_SATA_IRQ;
474
475 if (bmdma2 == 0xffffffff ||
476 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
477 continue;
478
479 sil_host_intr(ap, bmdma2);
480 handled = 1;
481 }
482
483 spin_unlock(&host->lock);
484
485 return IRQ_RETVAL(handled);
486 }
487
488 static void sil_freeze(struct ata_port *ap)
489 {
490 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
491 u32 tmp;
492
493 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
494 writel(0, mmio_base + sil_port[ap->port_no].sien);
495
496 /* plug IRQ */
497 tmp = readl(mmio_base + SIL_SYSCFG);
498 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
499 writel(tmp, mmio_base + SIL_SYSCFG);
500 readl(mmio_base + SIL_SYSCFG); /* flush */
501 }
502
503 static void sil_thaw(struct ata_port *ap)
504 {
505 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
506 u32 tmp;
507
508 /* clear IRQ */
509 ata_chk_status(ap);
510 ata_bmdma_irq_clear(ap);
511
512 /* turn on SATA IRQ if supported */
513 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
514 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
515
516 /* turn on IRQ */
517 tmp = readl(mmio_base + SIL_SYSCFG);
518 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
519 writel(tmp, mmio_base + SIL_SYSCFG);
520 }
521
522 /**
523 * sil_dev_config - Apply device/host-specific errata fixups
524 * @ap: Port containing device to be examined
525 * @dev: Device to be examined
526 *
527 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
528 * device is known to be present, this function is called.
529 * We apply two errata fixups which are specific to Silicon Image,
530 * a Seagate and a Maxtor fixup.
531 *
532 * For certain Seagate devices, we must limit the maximum sectors
533 * to under 8K.
534 *
535 * For certain Maxtor devices, we must not program the drive
536 * beyond udma5.
537 *
538 * Both fixups are unfairly pessimistic. As soon as I get more
539 * information on these errata, I will create a more exhaustive
540 * list, and apply the fixups to only the specific
541 * devices/hosts/firmwares that need it.
542 *
543 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
544 * The Maxtor quirk is in the blacklist, but I'm keeping the original
545 * pessimistic fix for the following reasons...
546 * - There seems to be less info on it, only one device gleaned off the
547 * Windows driver, maybe only one is affected. More info would be greatly
548 * appreciated.
549 * - But then again UDMA5 is hardly anything to complain about
550 */
551 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
552 {
553 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
554 unsigned int n, quirks = 0;
555 unsigned char model_num[ATA_ID_PROD_LEN + 1];
556
557 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
558
559 for (n = 0; sil_blacklist[n].product; n++)
560 if (!strcmp(sil_blacklist[n].product, model_num)) {
561 quirks = sil_blacklist[n].quirk;
562 break;
563 }
564
565 /* limit requests to 15 sectors */
566 if (slow_down ||
567 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
568 (quirks & SIL_QUIRK_MOD15WRITE))) {
569 if (print_info)
570 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
571 "errata fix (mod15write workaround)\n");
572 dev->max_sectors = 15;
573 return;
574 }
575
576 /* limit to udma5 */
577 if (quirks & SIL_QUIRK_UDMA5MAX) {
578 if (print_info)
579 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
580 "errata fix %s\n", model_num);
581 dev->udma_mask &= ATA_UDMA5;
582 return;
583 }
584 }
585
586 static void sil_init_controller(struct pci_dev *pdev,
587 int n_ports, unsigned long port_flags,
588 void __iomem *mmio_base)
589 {
590 u8 cls;
591 u32 tmp;
592 int i;
593
594 /* Initialize FIFO PCI bus arbitration */
595 cls = sil_get_device_cache_line(pdev);
596 if (cls) {
597 cls >>= 3;
598 cls++; /* cls = (line_size/8)+1 */
599 for (i = 0; i < n_ports; i++)
600 writew(cls << 8 | cls,
601 mmio_base + sil_port[i].fifo_cfg);
602 } else
603 dev_printk(KERN_WARNING, &pdev->dev,
604 "cache line size not set. Driver may not function\n");
605
606 /* Apply R_ERR on DMA activate FIS errata workaround */
607 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
608 int cnt;
609
610 for (i = 0, cnt = 0; i < n_ports; i++) {
611 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
612 if ((tmp & 0x3) != 0x01)
613 continue;
614 if (!cnt)
615 dev_printk(KERN_INFO, &pdev->dev,
616 "Applying R_ERR on DMA activate "
617 "FIS errata fix\n");
618 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
619 cnt++;
620 }
621 }
622
623 if (n_ports == 4) {
624 /* flip the magic "make 4 ports work" bit */
625 tmp = readl(mmio_base + sil_port[2].bmdma);
626 if ((tmp & SIL_INTR_STEERING) == 0)
627 writel(tmp | SIL_INTR_STEERING,
628 mmio_base + sil_port[2].bmdma);
629 }
630 }
631
632 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
633 {
634 static int printed_version;
635 struct device *dev = &pdev->dev;
636 struct ata_probe_ent *probe_ent;
637 void __iomem *mmio_base;
638 int rc;
639 unsigned int i;
640
641 if (!printed_version++)
642 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
643
644 rc = pcim_enable_device(pdev);
645 if (rc)
646 return rc;
647
648 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
649 if (rc == -EBUSY)
650 pcim_pin_device(pdev);
651 if (rc)
652 return rc;
653
654 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
655 if (rc)
656 return rc;
657 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
658 if (rc)
659 return rc;
660
661 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
662 if (probe_ent == NULL)
663 return -ENOMEM;
664
665 INIT_LIST_HEAD(&probe_ent->node);
666 probe_ent->dev = pci_dev_to_dev(pdev);
667 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
668 probe_ent->sht = sil_port_info[ent->driver_data].sht;
669 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
670 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
671 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
672 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
673 probe_ent->irq = pdev->irq;
674 probe_ent->irq_flags = IRQF_SHARED;
675 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
676
677 probe_ent->iomap = pcim_iomap_table(pdev);
678
679 mmio_base = probe_ent->iomap[SIL_MMIO_BAR];
680
681 for (i = 0; i < probe_ent->n_ports; i++) {
682 probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf;
683 probe_ent->port[i].altstatus_addr =
684 probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl;
685 probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma;
686 probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr;
687 ata_std_ports(&probe_ent->port[i]);
688 }
689
690 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
691 mmio_base);
692
693 pci_set_master(pdev);
694
695 if (!ata_device_add(probe_ent))
696 return -ENODEV;
697
698 devm_kfree(dev, probe_ent);
699 return 0;
700 }
701
702 #ifdef CONFIG_PM
703 static int sil_pci_device_resume(struct pci_dev *pdev)
704 {
705 struct ata_host *host = dev_get_drvdata(&pdev->dev);
706 int rc;
707
708 rc = ata_pci_device_do_resume(pdev);
709 if (rc)
710 return rc;
711
712 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags,
713 host->iomap[SIL_MMIO_BAR]);
714 ata_host_resume(host);
715
716 return 0;
717 }
718 #endif
719
720 static int __init sil_init(void)
721 {
722 return pci_register_driver(&sil_pci_driver);
723 }
724
725 static void __exit sil_exit(void)
726 {
727 pci_unregister_driver(&sil_pci_driver);
728 }
729
730
731 module_init(sil_init);
732 module_exit(sil_exit);
Linux kernel - Deliverables
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