2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
84 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <linux/ioctl.h>
88 #include <linux/synclink.h>
90 #include <asm/system.h>
94 #include <linux/bitops.h>
95 #include <asm/types.h>
96 #include <linux/termios.h>
97 #include <linux/workqueue.h>
98 #include <linux/hdlc.h>
99 #include <linux/dma-mapping.h>
101 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
102 #define SYNCLINK_GENERIC_HDLC 1
104 #define SYNCLINK_GENERIC_HDLC 0
107 #define GET_USER(error,value,addr) error = get_user(value,addr)
108 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
109 #define PUT_USER(error,value,addr) error = put_user(value,addr)
110 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112 #include <asm/uaccess.h>
114 #define RCLRVALUE 0xffff
116 static MGSL_PARAMS default_params
= {
117 MGSL_MODE_HDLC
, /* unsigned long mode */
118 0, /* unsigned char loopback; */
119 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
120 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
121 0, /* unsigned long clock_speed; */
122 0xff, /* unsigned char addr_filter; */
123 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
124 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
125 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
126 9600, /* unsigned long data_rate; */
127 8, /* unsigned char data_bits; */
128 1, /* unsigned char stop_bits; */
129 ASYNC_PARITY_NONE
/* unsigned char parity; */
132 #define SHARED_MEM_ADDRESS_SIZE 0x40000
133 #define BUFFERLISTSIZE 4096
134 #define DMABUFFERSIZE 4096
135 #define MAXRXFRAMES 7
137 typedef struct _DMABUFFERENTRY
139 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
140 volatile u16 count
; /* buffer size/data count */
141 volatile u16 status
; /* Control/status field */
142 volatile u16 rcc
; /* character count field */
143 u16 reserved
; /* padding required by 16C32 */
144 u32 link
; /* 32-bit flat link to next buffer entry */
145 char *virt_addr
; /* virtual address of data buffer */
146 u32 phys_entry
; /* physical address of this buffer entry */
148 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
150 /* The queue of BH actions to be performed */
153 #define BH_TRANSMIT 2
156 #define IO_PIN_SHUTDOWN_LIMIT 100
158 struct _input_signal_events
{
169 /* transmit holding buffer definitions*/
170 #define MAX_TX_HOLDING_BUFFERS 5
171 struct tx_holding_buffer
{
173 unsigned char * buffer
;
178 * Device instance data structure
183 struct tty_port port
;
187 struct mgsl_icount icount
;
190 int x_char
; /* xon/xoff character */
191 u16 read_status_mask
;
192 u16 ignore_status_mask
;
193 unsigned char *xmit_buf
;
198 wait_queue_head_t status_event_wait_q
;
199 wait_queue_head_t event_wait_q
;
200 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
201 struct mgsl_struct
*next_device
; /* device list link */
203 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
204 struct work_struct task
; /* task structure for scheduling bh */
206 u32 EventMask
; /* event trigger mask */
207 u32 RecordedEvents
; /* pending events */
209 u32 max_frame_size
; /* as set by device config */
213 bool bh_running
; /* Protection from multiple */
217 int dcd_chkcount
; /* check counts to prevent */
218 int cts_chkcount
; /* too many IRQs if a signal */
219 int dsr_chkcount
; /* is floating */
222 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
223 u32 buffer_list_phys
;
224 dma_addr_t buffer_list_dma_addr
;
226 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
227 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
228 unsigned int current_rx_buffer
;
230 int num_tx_dma_buffers
; /* number of tx dma frames required */
231 int tx_dma_buffers_used
;
232 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
233 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
234 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
235 int current_tx_buffer
; /* next tx dma buffer to be loaded */
237 unsigned char *intermediate_rxbuffer
;
239 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
240 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
241 int put_tx_holding_index
; /* next tx holding buffer to store user request */
242 int tx_holding_count
; /* number of tx holding buffers waiting */
243 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
247 bool rx_rcc_underrun
;
256 char device_name
[25]; /* device instance name */
258 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
259 unsigned char bus
; /* expansion bus number (zero based) */
260 unsigned char function
; /* PCI device number */
262 unsigned int io_base
; /* base I/O address of adapter */
263 unsigned int io_addr_size
; /* size of the I/O address range */
264 bool io_addr_requested
; /* true if I/O address requested */
266 unsigned int irq_level
; /* interrupt level */
267 unsigned long irq_flags
;
268 bool irq_requested
; /* true if IRQ requested */
270 unsigned int dma_level
; /* DMA channel */
271 bool dma_requested
; /* true if dma channel requested */
277 MGSL_PARAMS params
; /* communications parameters */
279 unsigned char serial_signals
; /* current serial signal states */
281 bool irq_occurred
; /* for diagnostics use */
282 unsigned int init_error
; /* Initialization startup error (DIAGS) */
283 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
286 unsigned char* memory_base
; /* shared memory address (PCI only) */
287 u32 phys_memory_base
;
288 bool shared_mem_requested
;
290 unsigned char* lcr_base
; /* local config registers (PCI only) */
293 bool lcr_mem_requested
;
296 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
297 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
298 bool drop_rts_on_tx_done
;
300 bool loopmode_insert_requested
;
301 bool loopmode_send_done_requested
;
303 struct _input_signal_events input_signal_events
;
305 /* generic HDLC device parts */
309 #if SYNCLINK_GENERIC_HDLC
310 struct net_device
*netdev
;
314 #define MGSL_MAGIC 0x5401
317 * The size of the serial xmit buffer is 1 page, or 4096 bytes
319 #ifndef SERIAL_XMIT_SIZE
320 #define SERIAL_XMIT_SIZE 4096
324 * These macros define the offsets used in calculating the
325 * I/O address of the specified USC registers.
329 #define DCPIN 2 /* Bit 1 of I/O address */
330 #define SDPIN 4 /* Bit 2 of I/O address */
332 #define DCAR 0 /* DMA command/address register */
333 #define CCAR SDPIN /* channel command/address register */
334 #define DATAREG DCPIN + SDPIN /* serial data register */
339 * These macros define the register address (ordinal number)
340 * used for writing address/value pairs to the USC.
343 #define CMR 0x02 /* Channel mode Register */
344 #define CCSR 0x04 /* Channel Command/status Register */
345 #define CCR 0x06 /* Channel Control Register */
346 #define PSR 0x08 /* Port status Register */
347 #define PCR 0x0a /* Port Control Register */
348 #define TMDR 0x0c /* Test mode Data Register */
349 #define TMCR 0x0e /* Test mode Control Register */
350 #define CMCR 0x10 /* Clock mode Control Register */
351 #define HCR 0x12 /* Hardware Configuration Register */
352 #define IVR 0x14 /* Interrupt Vector Register */
353 #define IOCR 0x16 /* Input/Output Control Register */
354 #define ICR 0x18 /* Interrupt Control Register */
355 #define DCCR 0x1a /* Daisy Chain Control Register */
356 #define MISR 0x1c /* Misc Interrupt status Register */
357 #define SICR 0x1e /* status Interrupt Control Register */
358 #define RDR 0x20 /* Receive Data Register */
359 #define RMR 0x22 /* Receive mode Register */
360 #define RCSR 0x24 /* Receive Command/status Register */
361 #define RICR 0x26 /* Receive Interrupt Control Register */
362 #define RSR 0x28 /* Receive Sync Register */
363 #define RCLR 0x2a /* Receive count Limit Register */
364 #define RCCR 0x2c /* Receive Character count Register */
365 #define TC0R 0x2e /* Time Constant 0 Register */
366 #define TDR 0x30 /* Transmit Data Register */
367 #define TMR 0x32 /* Transmit mode Register */
368 #define TCSR 0x34 /* Transmit Command/status Register */
369 #define TICR 0x36 /* Transmit Interrupt Control Register */
370 #define TSR 0x38 /* Transmit Sync Register */
371 #define TCLR 0x3a /* Transmit count Limit Register */
372 #define TCCR 0x3c /* Transmit Character count Register */
373 #define TC1R 0x3e /* Time Constant 1 Register */
377 * MACRO DEFINITIONS FOR DMA REGISTERS
380 #define DCR 0x06 /* DMA Control Register (shared) */
381 #define DACR 0x08 /* DMA Array count Register (shared) */
382 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
383 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
384 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
385 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
386 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
388 #define TDMR 0x02 /* Transmit DMA mode Register */
389 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
390 #define TBCR 0x2a /* Transmit Byte count Register */
391 #define TARL 0x2c /* Transmit Address Register (low) */
392 #define TARU 0x2e /* Transmit Address Register (high) */
393 #define NTBCR 0x3a /* Next Transmit Byte count Register */
394 #define NTARL 0x3c /* Next Transmit Address Register (low) */
395 #define NTARU 0x3e /* Next Transmit Address Register (high) */
397 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
398 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
399 #define RBCR 0xaa /* Receive Byte count Register */
400 #define RARL 0xac /* Receive Address Register (low) */
401 #define RARU 0xae /* Receive Address Register (high) */
402 #define NRBCR 0xba /* Next Receive Byte count Register */
403 #define NRARL 0xbc /* Next Receive Address Register (low) */
404 #define NRARU 0xbe /* Next Receive Address Register (high) */
408 * MACRO DEFINITIONS FOR MODEM STATUS BITS
411 #define MODEMSTATUS_DTR 0x80
412 #define MODEMSTATUS_DSR 0x40
413 #define MODEMSTATUS_RTS 0x20
414 #define MODEMSTATUS_CTS 0x10
415 #define MODEMSTATUS_RI 0x04
416 #define MODEMSTATUS_DCD 0x01
420 * Channel Command/Address Register (CCAR) Command Codes
423 #define RTCmd_Null 0x0000
424 #define RTCmd_ResetHighestIus 0x1000
425 #define RTCmd_TriggerChannelLoadDma 0x2000
426 #define RTCmd_TriggerRxDma 0x2800
427 #define RTCmd_TriggerTxDma 0x3000
428 #define RTCmd_TriggerRxAndTxDma 0x3800
429 #define RTCmd_PurgeRxFifo 0x4800
430 #define RTCmd_PurgeTxFifo 0x5000
431 #define RTCmd_PurgeRxAndTxFifo 0x5800
432 #define RTCmd_LoadRcc 0x6800
433 #define RTCmd_LoadTcc 0x7000
434 #define RTCmd_LoadRccAndTcc 0x7800
435 #define RTCmd_LoadTC0 0x8800
436 #define RTCmd_LoadTC1 0x9000
437 #define RTCmd_LoadTC0AndTC1 0x9800
438 #define RTCmd_SerialDataLSBFirst 0xa000
439 #define RTCmd_SerialDataMSBFirst 0xa800
440 #define RTCmd_SelectBigEndian 0xb000
441 #define RTCmd_SelectLittleEndian 0xb800
445 * DMA Command/Address Register (DCAR) Command Codes
448 #define DmaCmd_Null 0x0000
449 #define DmaCmd_ResetTxChannel 0x1000
450 #define DmaCmd_ResetRxChannel 0x1200
451 #define DmaCmd_StartTxChannel 0x2000
452 #define DmaCmd_StartRxChannel 0x2200
453 #define DmaCmd_ContinueTxChannel 0x3000
454 #define DmaCmd_ContinueRxChannel 0x3200
455 #define DmaCmd_PauseTxChannel 0x4000
456 #define DmaCmd_PauseRxChannel 0x4200
457 #define DmaCmd_AbortTxChannel 0x5000
458 #define DmaCmd_AbortRxChannel 0x5200
459 #define DmaCmd_InitTxChannel 0x7000
460 #define DmaCmd_InitRxChannel 0x7200
461 #define DmaCmd_ResetHighestDmaIus 0x8000
462 #define DmaCmd_ResetAllChannels 0x9000
463 #define DmaCmd_StartAllChannels 0xa000
464 #define DmaCmd_ContinueAllChannels 0xb000
465 #define DmaCmd_PauseAllChannels 0xc000
466 #define DmaCmd_AbortAllChannels 0xd000
467 #define DmaCmd_InitAllChannels 0xf000
469 #define TCmd_Null 0x0000
470 #define TCmd_ClearTxCRC 0x2000
471 #define TCmd_SelectTicrTtsaData 0x4000
472 #define TCmd_SelectTicrTxFifostatus 0x5000
473 #define TCmd_SelectTicrIntLevel 0x6000
474 #define TCmd_SelectTicrdma_level 0x7000
475 #define TCmd_SendFrame 0x8000
476 #define TCmd_SendAbort 0x9000
477 #define TCmd_EnableDleInsertion 0xc000
478 #define TCmd_DisableDleInsertion 0xd000
479 #define TCmd_ClearEofEom 0xe000
480 #define TCmd_SetEofEom 0xf000
482 #define RCmd_Null 0x0000
483 #define RCmd_ClearRxCRC 0x2000
484 #define RCmd_EnterHuntmode 0x3000
485 #define RCmd_SelectRicrRtsaData 0x4000
486 #define RCmd_SelectRicrRxFifostatus 0x5000
487 #define RCmd_SelectRicrIntLevel 0x6000
488 #define RCmd_SelectRicrdma_level 0x7000
491 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
494 #define RECEIVE_STATUS BIT5
495 #define RECEIVE_DATA BIT4
496 #define TRANSMIT_STATUS BIT3
497 #define TRANSMIT_DATA BIT2
503 * Receive status Bits in Receive Command/status Register RCSR
506 #define RXSTATUS_SHORT_FRAME BIT8
507 #define RXSTATUS_CODE_VIOLATION BIT8
508 #define RXSTATUS_EXITED_HUNT BIT7
509 #define RXSTATUS_IDLE_RECEIVED BIT6
510 #define RXSTATUS_BREAK_RECEIVED BIT5
511 #define RXSTATUS_ABORT_RECEIVED BIT5
512 #define RXSTATUS_RXBOUND BIT4
513 #define RXSTATUS_CRC_ERROR BIT3
514 #define RXSTATUS_FRAMING_ERROR BIT3
515 #define RXSTATUS_ABORT BIT2
516 #define RXSTATUS_PARITY_ERROR BIT2
517 #define RXSTATUS_OVERRUN BIT1
518 #define RXSTATUS_DATA_AVAILABLE BIT0
519 #define RXSTATUS_ALL 0x01f6
520 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
523 * Values for setting transmit idle mode in
524 * Transmit Control/status Register (TCSR)
526 #define IDLEMODE_FLAGS 0x0000
527 #define IDLEMODE_ALT_ONE_ZERO 0x0100
528 #define IDLEMODE_ZERO 0x0200
529 #define IDLEMODE_ONE 0x0300
530 #define IDLEMODE_ALT_MARK_SPACE 0x0500
531 #define IDLEMODE_SPACE 0x0600
532 #define IDLEMODE_MARK 0x0700
533 #define IDLEMODE_MASK 0x0700
536 * IUSC revision identifiers
538 #define IUSC_SL1660 0x4d44
539 #define IUSC_PRE_SL1660 0x4553
542 * Transmit status Bits in Transmit Command/status Register (TCSR)
545 #define TCSR_PRESERVE 0x0F00
547 #define TCSR_UNDERWAIT BIT11
548 #define TXSTATUS_PREAMBLE_SENT BIT7
549 #define TXSTATUS_IDLE_SENT BIT6
550 #define TXSTATUS_ABORT_SENT BIT5
551 #define TXSTATUS_EOF_SENT BIT4
552 #define TXSTATUS_EOM_SENT BIT4
553 #define TXSTATUS_CRC_SENT BIT3
554 #define TXSTATUS_ALL_SENT BIT2
555 #define TXSTATUS_UNDERRUN BIT1
556 #define TXSTATUS_FIFO_EMPTY BIT0
557 #define TXSTATUS_ALL 0x00fa
558 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
561 #define MISCSTATUS_RXC_LATCHED BIT15
562 #define MISCSTATUS_RXC BIT14
563 #define MISCSTATUS_TXC_LATCHED BIT13
564 #define MISCSTATUS_TXC BIT12
565 #define MISCSTATUS_RI_LATCHED BIT11
566 #define MISCSTATUS_RI BIT10
567 #define MISCSTATUS_DSR_LATCHED BIT9
568 #define MISCSTATUS_DSR BIT8
569 #define MISCSTATUS_DCD_LATCHED BIT7
570 #define MISCSTATUS_DCD BIT6
571 #define MISCSTATUS_CTS_LATCHED BIT5
572 #define MISCSTATUS_CTS BIT4
573 #define MISCSTATUS_RCC_UNDERRUN BIT3
574 #define MISCSTATUS_DPLL_NO_SYNC BIT2
575 #define MISCSTATUS_BRG1_ZERO BIT1
576 #define MISCSTATUS_BRG0_ZERO BIT0
578 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
579 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581 #define SICR_RXC_ACTIVE BIT15
582 #define SICR_RXC_INACTIVE BIT14
583 #define SICR_RXC (BIT15+BIT14)
584 #define SICR_TXC_ACTIVE BIT13
585 #define SICR_TXC_INACTIVE BIT12
586 #define SICR_TXC (BIT13+BIT12)
587 #define SICR_RI_ACTIVE BIT11
588 #define SICR_RI_INACTIVE BIT10
589 #define SICR_RI (BIT11+BIT10)
590 #define SICR_DSR_ACTIVE BIT9
591 #define SICR_DSR_INACTIVE BIT8
592 #define SICR_DSR (BIT9+BIT8)
593 #define SICR_DCD_ACTIVE BIT7
594 #define SICR_DCD_INACTIVE BIT6
595 #define SICR_DCD (BIT7+BIT6)
596 #define SICR_CTS_ACTIVE BIT5
597 #define SICR_CTS_INACTIVE BIT4
598 #define SICR_CTS (BIT5+BIT4)
599 #define SICR_RCC_UNDERFLOW BIT3
600 #define SICR_DPLL_NO_SYNC BIT2
601 #define SICR_BRG1_ZERO BIT1
602 #define SICR_BRG0_ZERO BIT0
604 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
605 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
606 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
607 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
608 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
610 #define usc_EnableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613 #define usc_DisableInterrupts( a, b ) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616 #define usc_EnableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619 #define usc_DisableMasterIrqBit(a) \
620 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
625 * Transmit status Bits in Transmit Control status Register (TCSR)
626 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
629 #define TXSTATUS_PREAMBLE_SENT BIT7
630 #define TXSTATUS_IDLE_SENT BIT6
631 #define TXSTATUS_ABORT_SENT BIT5
632 #define TXSTATUS_EOF BIT4
633 #define TXSTATUS_CRC_SENT BIT3
634 #define TXSTATUS_ALL_SENT BIT2
635 #define TXSTATUS_UNDERRUN BIT1
636 #define TXSTATUS_FIFO_EMPTY BIT0
638 #define DICR_MASTER BIT15
639 #define DICR_TRANSMIT BIT0
640 #define DICR_RECEIVE BIT1
642 #define usc_EnableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645 #define usc_DisableDmaInterrupts(a,b) \
646 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648 #define usc_EnableStatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651 #define usc_DisablestatusIrqs(a,b) \
652 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654 /* Transmit status Bits in Transmit Control status Register (TCSR) */
655 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
658 #define DISABLE_UNCONDITIONAL 0
659 #define DISABLE_END_OF_FRAME 1
660 #define ENABLE_UNCONDITIONAL 2
661 #define ENABLE_AUTO_CTS 3
662 #define ENABLE_AUTO_DCD 3
663 #define usc_EnableTransmitter(a,b) \
664 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
665 #define usc_EnableReceiver(a,b) \
666 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
669 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
670 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
672 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
673 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
674 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
675 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
676 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
678 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
679 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
684 static void usc_start_receiver( struct mgsl_struct
*info
);
685 static void usc_stop_receiver( struct mgsl_struct
*info
);
687 static void usc_start_transmitter( struct mgsl_struct
*info
);
688 static void usc_stop_transmitter( struct mgsl_struct
*info
);
689 static void usc_set_txidle( struct mgsl_struct
*info
);
690 static void usc_load_txfifo( struct mgsl_struct
*info
);
692 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
693 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
695 static void usc_get_serial_signals( struct mgsl_struct
*info
);
696 static void usc_set_serial_signals( struct mgsl_struct
*info
);
698 static void usc_reset( struct mgsl_struct
*info
);
700 static void usc_set_sync_mode( struct mgsl_struct
*info
);
701 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
702 static void usc_set_async_mode( struct mgsl_struct
*info
);
703 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
705 static void usc_loopback_frame( struct mgsl_struct
*info
);
707 static void mgsl_tx_timeout(unsigned long context
);
710 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
711 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
712 static int usc_loopmode_active( struct mgsl_struct
* info
);
713 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
715 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
717 #if SYNCLINK_GENERIC_HDLC
718 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
719 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
720 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
721 static int hdlcdev_init(struct mgsl_struct
*info
);
722 static void hdlcdev_exit(struct mgsl_struct
*info
);
726 * Defines a BUS descriptor value for the PCI adapter
727 * local bus address ranges.
730 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
741 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
744 * Adapter diagnostic routines
746 static bool mgsl_register_test( struct mgsl_struct
*info
);
747 static bool mgsl_irq_test( struct mgsl_struct
*info
);
748 static bool mgsl_dma_test( struct mgsl_struct
*info
);
749 static bool mgsl_memory_test( struct mgsl_struct
*info
);
750 static int mgsl_adapter_test( struct mgsl_struct
*info
);
753 * device and resource management routines
755 static int mgsl_claim_resources(struct mgsl_struct
*info
);
756 static void mgsl_release_resources(struct mgsl_struct
*info
);
757 static void mgsl_add_device(struct mgsl_struct
*info
);
758 static struct mgsl_struct
* mgsl_allocate_device(void);
761 * DMA buffer manupulation functions.
763 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
764 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
765 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
766 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
767 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
768 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
769 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
770 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
773 * DMA and Shared Memory buffer allocation and formatting
775 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
776 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
777 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
778 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
779 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
780 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
781 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
782 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
783 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
784 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
785 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
786 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
789 * Bottom half interrupt handlers
791 static void mgsl_bh_handler(struct work_struct
*work
);
792 static void mgsl_bh_receive(struct mgsl_struct
*info
);
793 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
794 static void mgsl_bh_status(struct mgsl_struct
*info
);
797 * Interrupt handler routines and dispatch table.
799 static void mgsl_isr_null( struct mgsl_struct
*info
);
800 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
801 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
802 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
803 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
804 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
805 static void mgsl_isr_misc( struct mgsl_struct
*info
);
806 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
807 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
809 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
811 static isr_dispatch_func UscIsrTable
[7] =
816 mgsl_isr_transmit_data
,
817 mgsl_isr_transmit_status
,
818 mgsl_isr_receive_data
,
819 mgsl_isr_receive_status
823 * ioctl call handlers
825 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
826 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
827 unsigned int set
, unsigned int clear
);
828 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
829 __user
*user_icount
);
830 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
831 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
832 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
833 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
834 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
835 static int mgsl_txabort(struct mgsl_struct
* info
);
836 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
837 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
838 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
840 /* set non-zero on successful registration with PCI subsystem */
841 static bool pci_registered
;
844 * Global linked list of SyncLink devices
846 static struct mgsl_struct
*mgsl_device_list
;
847 static int mgsl_device_count
;
850 * Set this param to non-zero to load eax with the
851 * .text section address and breakpoint on module load.
852 * This is useful for use with gdb and add-symbol-file command.
854 static int break_on_load
;
857 * Driver major number, defaults to zero to get auto
858 * assigned major number. May be forced as module parameter.
863 * Array of user specified options for ISA adapters.
865 static int io
[MAX_ISA_DEVICES
];
866 static int irq
[MAX_ISA_DEVICES
];
867 static int dma
[MAX_ISA_DEVICES
];
868 static int debug_level
;
869 static int maxframe
[MAX_TOTAL_DEVICES
];
870 static int txdmabufs
[MAX_TOTAL_DEVICES
];
871 static int txholdbufs
[MAX_TOTAL_DEVICES
];
873 module_param(break_on_load
, bool, 0);
874 module_param(ttymajor
, int, 0);
875 module_param_array(io
, int, NULL
, 0);
876 module_param_array(irq
, int, NULL
, 0);
877 module_param_array(dma
, int, NULL
, 0);
878 module_param(debug_level
, int, 0);
879 module_param_array(maxframe
, int, NULL
, 0);
880 module_param_array(txdmabufs
, int, NULL
, 0);
881 module_param_array(txholdbufs
, int, NULL
, 0);
883 static char *driver_name
= "SyncLink serial driver";
884 static char *driver_version
= "$Revision: 4.38 $";
886 static int synclink_init_one (struct pci_dev
*dev
,
887 const struct pci_device_id
*ent
);
888 static void synclink_remove_one (struct pci_dev
*dev
);
890 static struct pci_device_id synclink_pci_tbl
[] = {
891 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
892 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
893 { 0, }, /* terminate list */
895 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
897 MODULE_LICENSE("GPL");
899 static struct pci_driver synclink_pci_driver
= {
901 .id_table
= synclink_pci_tbl
,
902 .probe
= synclink_init_one
,
903 .remove
= __devexit_p(synclink_remove_one
),
906 static struct tty_driver
*serial_driver
;
908 /* number of characters left in xmit buffer before we ask for more */
909 #define WAKEUP_CHARS 256
912 static void mgsl_change_params(struct mgsl_struct
*info
);
913 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
916 * 1st function defined in .text section. Calling this function in
917 * init_module() followed by a breakpoint allows a remote debugger
918 * (gdb) to get the .text address for the add-symbol-file command.
919 * This allows remote debugging of dynamically loadable modules.
921 static void* mgsl_get_text_ptr(void)
923 return mgsl_get_text_ptr
;
926 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
927 char *name
, const char *routine
)
929 #ifdef MGSL_PARANOIA_CHECK
930 static const char *badmagic
=
931 "Warning: bad magic number for mgsl struct (%s) in %s\n";
932 static const char *badinfo
=
933 "Warning: null mgsl_struct for (%s) in %s\n";
936 printk(badinfo
, name
, routine
);
939 if (info
->magic
!= MGSL_MAGIC
) {
940 printk(badmagic
, name
, routine
);
951 * line discipline callback wrappers
953 * The wrappers maintain line discipline references
954 * while calling into the line discipline.
956 * ldisc_receive_buf - pass receive data to line discipline
959 static void ldisc_receive_buf(struct tty_struct
*tty
,
960 const __u8
*data
, char *flags
, int count
)
962 struct tty_ldisc
*ld
;
965 ld
= tty_ldisc_ref(tty
);
967 if (ld
->ops
->receive_buf
)
968 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
973 /* mgsl_stop() throttle (stop) transmitter
975 * Arguments: tty pointer to tty info structure
978 static void mgsl_stop(struct tty_struct
*tty
)
980 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
983 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
986 if ( debug_level
>= DEBUG_LEVEL_INFO
)
987 printk("mgsl_stop(%s)\n",info
->device_name
);
989 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
990 if (info
->tx_enabled
)
991 usc_stop_transmitter(info
);
992 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
994 } /* end of mgsl_stop() */
996 /* mgsl_start() release (start) transmitter
998 * Arguments: tty pointer to tty info structure
1001 static void mgsl_start(struct tty_struct
*tty
)
1003 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1004 unsigned long flags
;
1006 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1009 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1010 printk("mgsl_start(%s)\n",info
->device_name
);
1012 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1013 if (!info
->tx_enabled
)
1014 usc_start_transmitter(info
);
1015 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1017 } /* end of mgsl_start() */
1020 * Bottom half work queue access functions
1023 /* mgsl_bh_action() Return next bottom half action to perform.
1024 * Return Value: BH action code or 0 if nothing to do.
1026 static int mgsl_bh_action(struct mgsl_struct
*info
)
1028 unsigned long flags
;
1031 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1033 if (info
->pending_bh
& BH_RECEIVE
) {
1034 info
->pending_bh
&= ~BH_RECEIVE
;
1036 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1037 info
->pending_bh
&= ~BH_TRANSMIT
;
1039 } else if (info
->pending_bh
& BH_STATUS
) {
1040 info
->pending_bh
&= ~BH_STATUS
;
1045 /* Mark BH routine as complete */
1046 info
->bh_running
= false;
1047 info
->bh_requested
= false;
1050 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1056 * Perform bottom half processing of work items queued by ISR.
1058 static void mgsl_bh_handler(struct work_struct
*work
)
1060 struct mgsl_struct
*info
=
1061 container_of(work
, struct mgsl_struct
, task
);
1067 if ( debug_level
>= DEBUG_LEVEL_BH
)
1068 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1069 __FILE__
,__LINE__
,info
->device_name
);
1071 info
->bh_running
= true;
1073 while((action
= mgsl_bh_action(info
)) != 0) {
1075 /* Process work item */
1076 if ( debug_level
>= DEBUG_LEVEL_BH
)
1077 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1078 __FILE__
,__LINE__
,action
);
1083 mgsl_bh_receive(info
);
1086 mgsl_bh_transmit(info
);
1089 mgsl_bh_status(info
);
1092 /* unknown work item ID */
1093 printk("Unknown work item ID=%08X!\n", action
);
1098 if ( debug_level
>= DEBUG_LEVEL_BH
)
1099 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1100 __FILE__
,__LINE__
,info
->device_name
);
1103 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1105 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1106 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1108 if ( debug_level
>= DEBUG_LEVEL_BH
)
1109 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1110 __FILE__
,__LINE__
,info
->device_name
);
1114 if (info
->rx_rcc_underrun
) {
1115 unsigned long flags
;
1116 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1117 usc_start_receiver(info
);
1118 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1121 } while(get_rx_frame(info
));
1124 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1126 struct tty_struct
*tty
= info
->port
.tty
;
1127 unsigned long flags
;
1129 if ( debug_level
>= DEBUG_LEVEL_BH
)
1130 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1131 __FILE__
,__LINE__
,info
->device_name
);
1136 /* if transmitter idle and loopmode_send_done_requested
1137 * then start echoing RxD to TxD
1139 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1140 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1141 usc_loopmode_send_done( info
);
1142 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1145 static void mgsl_bh_status(struct mgsl_struct
*info
)
1147 if ( debug_level
>= DEBUG_LEVEL_BH
)
1148 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1149 __FILE__
,__LINE__
,info
->device_name
);
1151 info
->ri_chkcount
= 0;
1152 info
->dsr_chkcount
= 0;
1153 info
->dcd_chkcount
= 0;
1154 info
->cts_chkcount
= 0;
1157 /* mgsl_isr_receive_status()
1159 * Service a receive status interrupt. The type of status
1160 * interrupt is indicated by the state of the RCSR.
1161 * This is only used for HDLC mode.
1163 * Arguments: info pointer to device instance data
1164 * Return Value: None
1166 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1168 u16 status
= usc_InReg( info
, RCSR
);
1170 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1171 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1172 __FILE__
,__LINE__
,status
);
1174 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1175 info
->loopmode_insert_requested
&&
1176 usc_loopmode_active(info
) )
1178 ++info
->icount
.rxabort
;
1179 info
->loopmode_insert_requested
= false;
1181 /* clear CMR:13 to start echoing RxD to TxD */
1182 info
->cmr_value
&= ~BIT13
;
1183 usc_OutReg(info
, CMR
, info
->cmr_value
);
1185 /* disable received abort irq (no longer required) */
1186 usc_OutReg(info
, RICR
,
1187 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1190 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1191 if (status
& RXSTATUS_EXITED_HUNT
)
1192 info
->icount
.exithunt
++;
1193 if (status
& RXSTATUS_IDLE_RECEIVED
)
1194 info
->icount
.rxidle
++;
1195 wake_up_interruptible(&info
->event_wait_q
);
1198 if (status
& RXSTATUS_OVERRUN
){
1199 info
->icount
.rxover
++;
1200 usc_process_rxoverrun_sync( info
);
1203 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1204 usc_UnlatchRxstatusBits( info
, status
);
1206 } /* end of mgsl_isr_receive_status() */
1208 /* mgsl_isr_transmit_status()
1210 * Service a transmit status interrupt
1211 * HDLC mode :end of transmit frame
1212 * Async mode:all data is sent
1213 * transmit status is indicated by bits in the TCSR.
1215 * Arguments: info pointer to device instance data
1216 * Return Value: None
1218 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1220 u16 status
= usc_InReg( info
, TCSR
);
1222 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1223 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1224 __FILE__
,__LINE__
,status
);
1226 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1227 usc_UnlatchTxstatusBits( info
, status
);
1229 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1231 /* finished sending HDLC abort. This may leave */
1232 /* the TxFifo with data from the aborted frame */
1233 /* so purge the TxFifo. Also shutdown the DMA */
1234 /* channel in case there is data remaining in */
1235 /* the DMA buffer */
1236 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1237 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1240 if ( status
& TXSTATUS_EOF_SENT
)
1241 info
->icount
.txok
++;
1242 else if ( status
& TXSTATUS_UNDERRUN
)
1243 info
->icount
.txunder
++;
1244 else if ( status
& TXSTATUS_ABORT_SENT
)
1245 info
->icount
.txabort
++;
1247 info
->icount
.txunder
++;
1249 info
->tx_active
= false;
1250 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1251 del_timer(&info
->tx_timer
);
1253 if ( info
->drop_rts_on_tx_done
) {
1254 usc_get_serial_signals( info
);
1255 if ( info
->serial_signals
& SerialSignal_RTS
) {
1256 info
->serial_signals
&= ~SerialSignal_RTS
;
1257 usc_set_serial_signals( info
);
1259 info
->drop_rts_on_tx_done
= false;
1262 #if SYNCLINK_GENERIC_HDLC
1264 hdlcdev_tx_done(info
);
1268 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1269 usc_stop_transmitter(info
);
1272 info
->pending_bh
|= BH_TRANSMIT
;
1275 } /* end of mgsl_isr_transmit_status() */
1277 /* mgsl_isr_io_pin()
1279 * Service an Input/Output pin interrupt. The type of
1280 * interrupt is indicated by bits in the MISR
1282 * Arguments: info pointer to device instance data
1283 * Return Value: None
1285 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1287 struct mgsl_icount
*icount
;
1288 u16 status
= usc_InReg( info
, MISR
);
1290 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1291 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1292 __FILE__
,__LINE__
,status
);
1294 usc_ClearIrqPendingBits( info
, IO_PIN
);
1295 usc_UnlatchIostatusBits( info
, status
);
1297 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1298 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1299 icount
= &info
->icount
;
1300 /* update input line counters */
1301 if (status
& MISCSTATUS_RI_LATCHED
) {
1302 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1303 usc_DisablestatusIrqs(info
,SICR_RI
);
1305 if ( status
& MISCSTATUS_RI
)
1306 info
->input_signal_events
.ri_up
++;
1308 info
->input_signal_events
.ri_down
++;
1310 if (status
& MISCSTATUS_DSR_LATCHED
) {
1311 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1312 usc_DisablestatusIrqs(info
,SICR_DSR
);
1314 if ( status
& MISCSTATUS_DSR
)
1315 info
->input_signal_events
.dsr_up
++;
1317 info
->input_signal_events
.dsr_down
++;
1319 if (status
& MISCSTATUS_DCD_LATCHED
) {
1320 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1321 usc_DisablestatusIrqs(info
,SICR_DCD
);
1323 if (status
& MISCSTATUS_DCD
) {
1324 info
->input_signal_events
.dcd_up
++;
1326 info
->input_signal_events
.dcd_down
++;
1327 #if SYNCLINK_GENERIC_HDLC
1328 if (info
->netcount
) {
1329 if (status
& MISCSTATUS_DCD
)
1330 netif_carrier_on(info
->netdev
);
1332 netif_carrier_off(info
->netdev
);
1336 if (status
& MISCSTATUS_CTS_LATCHED
)
1338 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1339 usc_DisablestatusIrqs(info
,SICR_CTS
);
1341 if ( status
& MISCSTATUS_CTS
)
1342 info
->input_signal_events
.cts_up
++;
1344 info
->input_signal_events
.cts_down
++;
1346 wake_up_interruptible(&info
->status_event_wait_q
);
1347 wake_up_interruptible(&info
->event_wait_q
);
1349 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
1350 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1351 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1352 printk("%s CD now %s...", info
->device_name
,
1353 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1354 if (status
& MISCSTATUS_DCD
)
1355 wake_up_interruptible(&info
->port
.open_wait
);
1357 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1358 printk("doing serial hangup...");
1360 tty_hangup(info
->port
.tty
);
1364 if ( (info
->port
.flags
& ASYNC_CTS_FLOW
) &&
1365 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1366 if (info
->port
.tty
->hw_stopped
) {
1367 if (status
& MISCSTATUS_CTS
) {
1368 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1369 printk("CTS tx start...");
1371 info
->port
.tty
->hw_stopped
= 0;
1372 usc_start_transmitter(info
);
1373 info
->pending_bh
|= BH_TRANSMIT
;
1377 if (!(status
& MISCSTATUS_CTS
)) {
1378 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1379 printk("CTS tx stop...");
1381 info
->port
.tty
->hw_stopped
= 1;
1382 usc_stop_transmitter(info
);
1388 info
->pending_bh
|= BH_STATUS
;
1390 /* for diagnostics set IRQ flag */
1391 if ( status
& MISCSTATUS_TXC_LATCHED
){
1392 usc_OutReg( info
, SICR
,
1393 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1394 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1395 info
->irq_occurred
= true;
1398 } /* end of mgsl_isr_io_pin() */
1400 /* mgsl_isr_transmit_data()
1402 * Service a transmit data interrupt (async mode only).
1404 * Arguments: info pointer to device instance data
1405 * Return Value: None
1407 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1409 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1410 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1411 __FILE__
,__LINE__
,info
->xmit_cnt
);
1413 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1415 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1416 usc_stop_transmitter(info
);
1420 if ( info
->xmit_cnt
)
1421 usc_load_txfifo( info
);
1423 info
->tx_active
= false;
1425 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1426 info
->pending_bh
|= BH_TRANSMIT
;
1428 } /* end of mgsl_isr_transmit_data() */
1430 /* mgsl_isr_receive_data()
1432 * Service a receive data interrupt. This occurs
1433 * when operating in asynchronous interrupt transfer mode.
1434 * The receive data FIFO is flushed to the receive data buffers.
1436 * Arguments: info pointer to device instance data
1437 * Return Value: None
1439 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1444 unsigned char DataByte
;
1445 struct tty_struct
*tty
= info
->port
.tty
;
1446 struct mgsl_icount
*icount
= &info
->icount
;
1448 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1449 printk("%s(%d):mgsl_isr_receive_data\n",
1452 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1454 /* select FIFO status for RICR readback */
1455 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1457 /* clear the Wordstatus bit so that status readback */
1458 /* only reflects the status of this byte */
1459 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1461 /* flush the receive FIFO */
1463 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1466 /* read one byte from RxFIFO */
1467 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1468 info
->io_base
+ CCAR
);
1469 DataByte
= inb( info
->io_base
+ CCAR
);
1471 /* get the status of the received byte */
1472 status
= usc_InReg(info
, RCSR
);
1473 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1474 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1475 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1480 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1481 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1482 printk("rxerr=%04X\n",status
);
1483 /* update error statistics */
1484 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1485 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1487 } else if (status
& RXSTATUS_PARITY_ERROR
)
1489 else if (status
& RXSTATUS_FRAMING_ERROR
)
1491 else if (status
& RXSTATUS_OVERRUN
) {
1492 /* must issue purge fifo cmd before */
1493 /* 16C32 accepts more receive chars */
1494 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1498 /* discard char if tty control flags say so */
1499 if (status
& info
->ignore_status_mask
)
1502 status
&= info
->read_status_mask
;
1504 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1506 if (info
->port
.flags
& ASYNC_SAK
)
1508 } else if (status
& RXSTATUS_PARITY_ERROR
)
1510 else if (status
& RXSTATUS_FRAMING_ERROR
)
1512 } /* end of if (error) */
1513 tty_insert_flip_char(tty
, DataByte
, flag
);
1514 if (status
& RXSTATUS_OVERRUN
) {
1515 /* Overrun is special, since it's
1516 * reported immediately, and doesn't
1517 * affect the current character
1519 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1523 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1524 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1525 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1526 icount
->parity
,icount
->frame
,icount
->overrun
);
1530 tty_flip_buffer_push(tty
);
1535 * Service a miscellaneous interrupt source.
1537 * Arguments: info pointer to device extension (instance data)
1538 * Return Value: None
1540 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1542 u16 status
= usc_InReg( info
, MISR
);
1544 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1545 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1546 __FILE__
,__LINE__
,status
);
1548 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1549 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1551 /* turn off receiver and rx DMA */
1552 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1553 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1554 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1555 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1556 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1558 /* schedule BH handler to restart receiver */
1559 info
->pending_bh
|= BH_RECEIVE
;
1560 info
->rx_rcc_underrun
= true;
1563 usc_ClearIrqPendingBits( info
, MISC
);
1564 usc_UnlatchMiscstatusBits( info
, status
);
1566 } /* end of mgsl_isr_misc() */
1570 * Services undefined interrupt vectors from the
1571 * USC. (hence this function SHOULD never be called)
1573 * Arguments: info pointer to device extension (instance data)
1574 * Return Value: None
1576 static void mgsl_isr_null( struct mgsl_struct
*info
)
1579 } /* end of mgsl_isr_null() */
1581 /* mgsl_isr_receive_dma()
1583 * Service a receive DMA channel interrupt.
1584 * For this driver there are two sources of receive DMA interrupts
1585 * as identified in the Receive DMA mode Register (RDMR):
1587 * BIT3 EOA/EOL End of List, all receive buffers in receive
1588 * buffer list have been filled (no more free buffers
1589 * available). The DMA controller has shut down.
1591 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1592 * DMA buffer is terminated in response to completion
1593 * of a good frame or a frame with errors. The status
1594 * of the frame is stored in the buffer entry in the
1595 * list of receive buffer entries.
1597 * Arguments: info pointer to device instance data
1598 * Return Value: None
1600 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1604 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1605 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1607 /* Read the receive DMA status to identify interrupt type. */
1608 /* This also clears the status bits. */
1609 status
= usc_InDmaReg( info
, RDMR
);
1611 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1612 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1613 __FILE__
,__LINE__
,info
->device_name
,status
);
1615 info
->pending_bh
|= BH_RECEIVE
;
1617 if ( status
& BIT3
) {
1618 info
->rx_overflow
= true;
1619 info
->icount
.buf_overrun
++;
1622 } /* end of mgsl_isr_receive_dma() */
1624 /* mgsl_isr_transmit_dma()
1626 * This function services a transmit DMA channel interrupt.
1628 * For this driver there is one source of transmit DMA interrupts
1629 * as identified in the Transmit DMA Mode Register (TDMR):
1631 * BIT2 EOB End of Buffer. This interrupt occurs when a
1632 * transmit DMA buffer has been emptied.
1634 * The driver maintains enough transmit DMA buffers to hold at least
1635 * one max frame size transmit frame. When operating in a buffered
1636 * transmit mode, there may be enough transmit DMA buffers to hold at
1637 * least two or more max frame size frames. On an EOB condition,
1638 * determine if there are any queued transmit buffers and copy into
1639 * transmit DMA buffers if we have room.
1641 * Arguments: info pointer to device instance data
1642 * Return Value: None
1644 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1648 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1649 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1651 /* Read the transmit DMA status to identify interrupt type. */
1652 /* This also clears the status bits. */
1654 status
= usc_InDmaReg( info
, TDMR
);
1656 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1657 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1658 __FILE__
,__LINE__
,info
->device_name
,status
);
1660 if ( status
& BIT2
) {
1661 --info
->tx_dma_buffers_used
;
1663 /* if there are transmit frames queued,
1664 * try to load the next one
1666 if ( load_next_tx_holding_buffer(info
) ) {
1667 /* if call returns non-zero value, we have
1668 * at least one free tx holding buffer
1670 info
->pending_bh
|= BH_TRANSMIT
;
1674 } /* end of mgsl_isr_transmit_dma() */
1678 * Interrupt service routine entry point.
1682 * irq interrupt number that caused interrupt
1683 * dev_id device ID supplied during interrupt registration
1685 * Return Value: None
1687 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1689 struct mgsl_struct
*info
= dev_id
;
1693 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1694 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1695 __FILE__
, __LINE__
, info
->irq_level
);
1697 spin_lock(&info
->irq_spinlock
);
1700 /* Read the interrupt vectors from hardware. */
1701 UscVector
= usc_InReg(info
, IVR
) >> 9;
1702 DmaVector
= usc_InDmaReg(info
, DIVR
);
1704 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1705 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1706 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1708 if ( !UscVector
&& !DmaVector
)
1711 /* Dispatch interrupt vector */
1713 (*UscIsrTable
[UscVector
])(info
);
1714 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1715 mgsl_isr_transmit_dma(info
);
1717 mgsl_isr_receive_dma(info
);
1719 if ( info
->isr_overflow
) {
1720 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1721 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1722 usc_DisableMasterIrqBit(info
);
1723 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1728 /* Request bottom half processing if there's something
1729 * for it to do and the bh is not already running
1732 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1733 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1734 printk("%s(%d):%s queueing bh task.\n",
1735 __FILE__
,__LINE__
,info
->device_name
);
1736 schedule_work(&info
->task
);
1737 info
->bh_requested
= true;
1740 spin_unlock(&info
->irq_spinlock
);
1742 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1743 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1744 __FILE__
, __LINE__
, info
->irq_level
);
1747 } /* end of mgsl_interrupt() */
1751 * Initialize and start device.
1753 * Arguments: info pointer to device instance data
1754 * Return Value: 0 if success, otherwise error code
1756 static int startup(struct mgsl_struct
* info
)
1760 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1761 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1763 if (info
->port
.flags
& ASYNC_INITIALIZED
)
1766 if (!info
->xmit_buf
) {
1767 /* allocate a page of memory for a transmit buffer */
1768 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1769 if (!info
->xmit_buf
) {
1770 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1771 __FILE__
,__LINE__
,info
->device_name
);
1776 info
->pending_bh
= 0;
1778 memset(&info
->icount
, 0, sizeof(info
->icount
));
1780 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1782 /* Allocate and claim adapter resources */
1783 retval
= mgsl_claim_resources(info
);
1785 /* perform existence check and diagnostics */
1787 retval
= mgsl_adapter_test(info
);
1790 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1791 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1792 mgsl_release_resources(info
);
1796 /* program hardware for current parameters */
1797 mgsl_change_params(info
);
1800 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1802 info
->port
.flags
|= ASYNC_INITIALIZED
;
1806 } /* end of startup() */
1810 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1812 * Arguments: info pointer to device instance data
1813 * Return Value: None
1815 static void shutdown(struct mgsl_struct
* info
)
1817 unsigned long flags
;
1819 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1822 if (debug_level
>= DEBUG_LEVEL_INFO
)
1823 printk("%s(%d):mgsl_shutdown(%s)\n",
1824 __FILE__
,__LINE__
, info
->device_name
);
1826 /* clear status wait queue because status changes */
1827 /* can't happen after shutting down the hardware */
1828 wake_up_interruptible(&info
->status_event_wait_q
);
1829 wake_up_interruptible(&info
->event_wait_q
);
1831 del_timer_sync(&info
->tx_timer
);
1833 if (info
->xmit_buf
) {
1834 free_page((unsigned long) info
->xmit_buf
);
1835 info
->xmit_buf
= NULL
;
1838 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1839 usc_DisableMasterIrqBit(info
);
1840 usc_stop_receiver(info
);
1841 usc_stop_transmitter(info
);
1842 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1843 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1844 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1846 /* Disable DMAEN (Port 7, Bit 14) */
1847 /* This disconnects the DMA request signal from the ISA bus */
1848 /* on the ISA adapter. This has no effect for the PCI adapter */
1849 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1851 /* Disable INTEN (Port 6, Bit12) */
1852 /* This disconnects the IRQ request signal to the ISA bus */
1853 /* on the ISA adapter. This has no effect for the PCI adapter */
1854 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1856 if (!info
->port
.tty
|| info
->port
.tty
->termios
->c_cflag
& HUPCL
) {
1857 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1858 usc_set_serial_signals(info
);
1861 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1863 mgsl_release_resources(info
);
1866 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1868 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
1870 } /* end of shutdown() */
1872 static void mgsl_program_hw(struct mgsl_struct
*info
)
1874 unsigned long flags
;
1876 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1878 usc_stop_receiver(info
);
1879 usc_stop_transmitter(info
);
1880 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1882 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1883 info
->params
.mode
== MGSL_MODE_RAW
||
1885 usc_set_sync_mode(info
);
1887 usc_set_async_mode(info
);
1889 usc_set_serial_signals(info
);
1891 info
->dcd_chkcount
= 0;
1892 info
->cts_chkcount
= 0;
1893 info
->ri_chkcount
= 0;
1894 info
->dsr_chkcount
= 0;
1896 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1897 usc_EnableInterrupts(info
, IO_PIN
);
1898 usc_get_serial_signals(info
);
1900 if (info
->netcount
|| info
->port
.tty
->termios
->c_cflag
& CREAD
)
1901 usc_start_receiver(info
);
1903 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1906 /* Reconfigure adapter based on new parameters
1908 static void mgsl_change_params(struct mgsl_struct
*info
)
1913 if (!info
->port
.tty
|| !info
->port
.tty
->termios
)
1916 if (debug_level
>= DEBUG_LEVEL_INFO
)
1917 printk("%s(%d):mgsl_change_params(%s)\n",
1918 __FILE__
,__LINE__
, info
->device_name
);
1920 cflag
= info
->port
.tty
->termios
->c_cflag
;
1922 /* if B0 rate (hangup) specified then negate DTR and RTS */
1923 /* otherwise assert DTR and RTS */
1925 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1927 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1929 /* byte size and parity */
1931 switch (cflag
& CSIZE
) {
1932 case CS5
: info
->params
.data_bits
= 5; break;
1933 case CS6
: info
->params
.data_bits
= 6; break;
1934 case CS7
: info
->params
.data_bits
= 7; break;
1935 case CS8
: info
->params
.data_bits
= 8; break;
1936 /* Never happens, but GCC is too dumb to figure it out */
1937 default: info
->params
.data_bits
= 7; break;
1941 info
->params
.stop_bits
= 2;
1943 info
->params
.stop_bits
= 1;
1945 info
->params
.parity
= ASYNC_PARITY_NONE
;
1946 if (cflag
& PARENB
) {
1948 info
->params
.parity
= ASYNC_PARITY_ODD
;
1950 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1953 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1957 /* calculate number of jiffies to transmit a full
1958 * FIFO (32 bytes) at specified data rate
1960 bits_per_char
= info
->params
.data_bits
+
1961 info
->params
.stop_bits
+ 1;
1963 /* if port data rate is set to 460800 or less then
1964 * allow tty settings to override, otherwise keep the
1965 * current data rate.
1967 if (info
->params
.data_rate
<= 460800)
1968 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1970 if ( info
->params
.data_rate
) {
1971 info
->timeout
= (32*HZ
*bits_per_char
) /
1972 info
->params
.data_rate
;
1974 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1976 if (cflag
& CRTSCTS
)
1977 info
->port
.flags
|= ASYNC_CTS_FLOW
;
1979 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
1982 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
1984 info
->port
.flags
|= ASYNC_CHECK_CD
;
1986 /* process tty input control flags */
1988 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1989 if (I_INPCK(info
->port
.tty
))
1990 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1991 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1992 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1994 if (I_IGNPAR(info
->port
.tty
))
1995 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1996 if (I_IGNBRK(info
->port
.tty
)) {
1997 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1998 /* If ignoring parity and break indicators, ignore
1999 * overruns too. (For real raw support).
2001 if (I_IGNPAR(info
->port
.tty
))
2002 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2005 mgsl_program_hw(info
);
2007 } /* end of mgsl_change_params() */
2011 * Add a character to the transmit buffer.
2013 * Arguments: tty pointer to tty information structure
2014 * ch character to add to transmit buffer
2016 * Return Value: None
2018 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2020 struct mgsl_struct
*info
= tty
->driver_data
;
2021 unsigned long flags
;
2024 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2025 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2026 __FILE__
, __LINE__
, ch
, info
->device_name
);
2029 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2032 if (!tty
|| !info
->xmit_buf
)
2035 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2037 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2038 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2039 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2040 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2045 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2048 } /* end of mgsl_put_char() */
2050 /* mgsl_flush_chars()
2052 * Enable transmitter so remaining characters in the
2053 * transmit buffer are sent.
2055 * Arguments: tty pointer to tty information structure
2056 * Return Value: None
2058 static void mgsl_flush_chars(struct tty_struct
*tty
)
2060 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2061 unsigned long flags
;
2063 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2064 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2065 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2067 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2070 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2074 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2075 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2076 __FILE__
,__LINE__
,info
->device_name
);
2078 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2080 if (!info
->tx_active
) {
2081 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2082 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2083 /* operating in synchronous (frame oriented) mode */
2084 /* copy data from circular xmit_buf to */
2085 /* transmit DMA buffer. */
2086 mgsl_load_tx_dma_buffer(info
,
2087 info
->xmit_buf
,info
->xmit_cnt
);
2089 usc_start_transmitter(info
);
2092 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2094 } /* end of mgsl_flush_chars() */
2098 * Send a block of data
2102 * tty pointer to tty information structure
2103 * buf pointer to buffer containing send data
2104 * count size of send data in bytes
2106 * Return Value: number of characters written
2108 static int mgsl_write(struct tty_struct
* tty
,
2109 const unsigned char *buf
, int count
)
2112 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2113 unsigned long flags
;
2115 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2116 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2117 __FILE__
,__LINE__
,info
->device_name
,count
);
2119 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2122 if (!tty
|| !info
->xmit_buf
)
2125 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2126 info
->params
.mode
== MGSL_MODE_RAW
) {
2127 /* operating in synchronous (frame oriented) mode */
2128 /* operating in synchronous (frame oriented) mode */
2129 if (info
->tx_active
) {
2131 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2135 /* transmitter is actively sending data -
2136 * if we have multiple transmit dma and
2137 * holding buffers, attempt to queue this
2138 * frame for transmission at a later time.
2140 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2141 /* no tx holding buffers available */
2146 /* queue transmit frame request */
2148 save_tx_buffer_request(info
,buf
,count
);
2150 /* if we have sufficient tx dma buffers,
2151 * load the next buffered tx request
2153 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2154 load_next_tx_holding_buffer(info
);
2155 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2159 /* if operating in HDLC LoopMode and the adapter */
2160 /* has yet to be inserted into the loop, we can't */
2163 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2164 !usc_loopmode_active(info
) )
2170 if ( info
->xmit_cnt
) {
2171 /* Send accumulated from send_char() calls */
2172 /* as frame and wait before accepting more data. */
2175 /* copy data from circular xmit_buf to */
2176 /* transmit DMA buffer. */
2177 mgsl_load_tx_dma_buffer(info
,
2178 info
->xmit_buf
,info
->xmit_cnt
);
2179 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2180 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2181 __FILE__
,__LINE__
,info
->device_name
);
2183 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2184 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2185 __FILE__
,__LINE__
,info
->device_name
);
2187 info
->xmit_cnt
= count
;
2188 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2192 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2193 c
= min_t(int, count
,
2194 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2195 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2197 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2200 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2201 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2202 (SERIAL_XMIT_SIZE
-1));
2203 info
->xmit_cnt
+= c
;
2204 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2211 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2212 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2213 if (!info
->tx_active
)
2214 usc_start_transmitter(info
);
2215 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2218 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2219 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2220 __FILE__
,__LINE__
,info
->device_name
,ret
);
2224 } /* end of mgsl_write() */
2226 /* mgsl_write_room()
2228 * Return the count of free bytes in transmit buffer
2230 * Arguments: tty pointer to tty info structure
2231 * Return Value: None
2233 static int mgsl_write_room(struct tty_struct
*tty
)
2235 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2238 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2240 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2244 if (debug_level
>= DEBUG_LEVEL_INFO
)
2245 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2246 __FILE__
,__LINE__
, info
->device_name
,ret
);
2248 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2249 info
->params
.mode
== MGSL_MODE_RAW
) {
2250 /* operating in synchronous (frame oriented) mode */
2251 if ( info
->tx_active
)
2254 return HDLC_MAX_FRAME_SIZE
;
2259 } /* end of mgsl_write_room() */
2261 /* mgsl_chars_in_buffer()
2263 * Return the count of bytes in transmit buffer
2265 * Arguments: tty pointer to tty info structure
2266 * Return Value: None
2268 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2270 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2272 if (debug_level
>= DEBUG_LEVEL_INFO
)
2273 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2274 __FILE__
,__LINE__
, info
->device_name
);
2276 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2279 if (debug_level
>= DEBUG_LEVEL_INFO
)
2280 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2281 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2283 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2284 info
->params
.mode
== MGSL_MODE_RAW
) {
2285 /* operating in synchronous (frame oriented) mode */
2286 if ( info
->tx_active
)
2287 return info
->max_frame_size
;
2292 return info
->xmit_cnt
;
2293 } /* end of mgsl_chars_in_buffer() */
2295 /* mgsl_flush_buffer()
2297 * Discard all data in the send buffer
2299 * Arguments: tty pointer to tty info structure
2300 * Return Value: None
2302 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2304 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2305 unsigned long flags
;
2307 if (debug_level
>= DEBUG_LEVEL_INFO
)
2308 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2309 __FILE__
,__LINE__
, info
->device_name
);
2311 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2314 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2315 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2316 del_timer(&info
->tx_timer
);
2317 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2322 /* mgsl_send_xchar()
2324 * Send a high-priority XON/XOFF character
2326 * Arguments: tty pointer to tty info structure
2327 * ch character to send
2328 * Return Value: None
2330 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2332 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2333 unsigned long flags
;
2335 if (debug_level
>= DEBUG_LEVEL_INFO
)
2336 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2337 __FILE__
,__LINE__
, info
->device_name
, ch
);
2339 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2344 /* Make sure transmit interrupts are on */
2345 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2346 if (!info
->tx_enabled
)
2347 usc_start_transmitter(info
);
2348 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2350 } /* end of mgsl_send_xchar() */
2354 * Signal remote device to throttle send data (our receive data)
2356 * Arguments: tty pointer to tty info structure
2357 * Return Value: None
2359 static void mgsl_throttle(struct tty_struct
* tty
)
2361 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2362 unsigned long flags
;
2364 if (debug_level
>= DEBUG_LEVEL_INFO
)
2365 printk("%s(%d):mgsl_throttle(%s) entry\n",
2366 __FILE__
,__LINE__
, info
->device_name
);
2368 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2372 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2374 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2375 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2376 info
->serial_signals
&= ~SerialSignal_RTS
;
2377 usc_set_serial_signals(info
);
2378 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2380 } /* end of mgsl_throttle() */
2382 /* mgsl_unthrottle()
2384 * Signal remote device to stop throttling send data (our receive data)
2386 * Arguments: tty pointer to tty info structure
2387 * Return Value: None
2389 static void mgsl_unthrottle(struct tty_struct
* tty
)
2391 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2392 unsigned long flags
;
2394 if (debug_level
>= DEBUG_LEVEL_INFO
)
2395 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2396 __FILE__
,__LINE__
, info
->device_name
);
2398 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2405 mgsl_send_xchar(tty
, START_CHAR(tty
));
2408 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2409 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2410 info
->serial_signals
|= SerialSignal_RTS
;
2411 usc_set_serial_signals(info
);
2412 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2415 } /* end of mgsl_unthrottle() */
2419 * get the current serial parameters information
2421 * Arguments: info pointer to device instance data
2422 * user_icount pointer to buffer to hold returned stats
2424 * Return Value: 0 if success, otherwise error code
2426 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2430 if (debug_level
>= DEBUG_LEVEL_INFO
)
2431 printk("%s(%d):mgsl_get_params(%s)\n",
2432 __FILE__
,__LINE__
, info
->device_name
);
2435 memset(&info
->icount
, 0, sizeof(info
->icount
));
2437 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2444 } /* end of mgsl_get_stats() */
2446 /* mgsl_get_params()
2448 * get the current serial parameters information
2450 * Arguments: info pointer to device instance data
2451 * user_params pointer to buffer to hold returned params
2453 * Return Value: 0 if success, otherwise error code
2455 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2458 if (debug_level
>= DEBUG_LEVEL_INFO
)
2459 printk("%s(%d):mgsl_get_params(%s)\n",
2460 __FILE__
,__LINE__
, info
->device_name
);
2462 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2464 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2465 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2466 __FILE__
,__LINE__
,info
->device_name
);
2472 } /* end of mgsl_get_params() */
2474 /* mgsl_set_params()
2476 * set the serial parameters
2480 * info pointer to device instance data
2481 * new_params user buffer containing new serial params
2483 * Return Value: 0 if success, otherwise error code
2485 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2487 unsigned long flags
;
2488 MGSL_PARAMS tmp_params
;
2491 if (debug_level
>= DEBUG_LEVEL_INFO
)
2492 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2493 info
->device_name
);
2494 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2496 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2497 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2498 __FILE__
,__LINE__
,info
->device_name
);
2502 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2503 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2504 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2506 mgsl_change_params(info
);
2510 } /* end of mgsl_set_params() */
2512 /* mgsl_get_txidle()
2514 * get the current transmit idle mode
2516 * Arguments: info pointer to device instance data
2517 * idle_mode pointer to buffer to hold returned idle mode
2519 * Return Value: 0 if success, otherwise error code
2521 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2525 if (debug_level
>= DEBUG_LEVEL_INFO
)
2526 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2527 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2529 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2531 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2532 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2533 __FILE__
,__LINE__
,info
->device_name
);
2539 } /* end of mgsl_get_txidle() */
2541 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2543 * Arguments: info pointer to device instance data
2544 * idle_mode new idle mode
2546 * Return Value: 0 if success, otherwise error code
2548 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2550 unsigned long flags
;
2552 if (debug_level
>= DEBUG_LEVEL_INFO
)
2553 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2554 info
->device_name
, idle_mode
);
2556 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2557 info
->idle_mode
= idle_mode
;
2558 usc_set_txidle( info
);
2559 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2562 } /* end of mgsl_set_txidle() */
2566 * enable or disable the transmitter
2570 * info pointer to device instance data
2571 * enable 1 = enable, 0 = disable
2573 * Return Value: 0 if success, otherwise error code
2575 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2577 unsigned long flags
;
2579 if (debug_level
>= DEBUG_LEVEL_INFO
)
2580 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2581 info
->device_name
, enable
);
2583 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2585 if ( !info
->tx_enabled
) {
2587 usc_start_transmitter(info
);
2588 /*--------------------------------------------------
2589 * if HDLC/SDLC Loop mode, attempt to insert the
2590 * station in the 'loop' by setting CMR:13. Upon
2591 * receipt of the next GoAhead (RxAbort) sequence,
2592 * the OnLoop indicator (CCSR:7) should go active
2593 * to indicate that we are on the loop
2594 *--------------------------------------------------*/
2595 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2596 usc_loopmode_insert_request( info
);
2599 if ( info
->tx_enabled
)
2600 usc_stop_transmitter(info
);
2602 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2605 } /* end of mgsl_txenable() */
2607 /* mgsl_txabort() abort send HDLC frame
2609 * Arguments: info pointer to device instance data
2610 * Return Value: 0 if success, otherwise error code
2612 static int mgsl_txabort(struct mgsl_struct
* info
)
2614 unsigned long flags
;
2616 if (debug_level
>= DEBUG_LEVEL_INFO
)
2617 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2620 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2621 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2623 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2624 usc_loopmode_cancel_transmit( info
);
2626 usc_TCmd(info
,TCmd_SendAbort
);
2628 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2631 } /* end of mgsl_txabort() */
2633 /* mgsl_rxenable() enable or disable the receiver
2635 * Arguments: info pointer to device instance data
2636 * enable 1 = enable, 0 = disable
2637 * Return Value: 0 if success, otherwise error code
2639 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2641 unsigned long flags
;
2643 if (debug_level
>= DEBUG_LEVEL_INFO
)
2644 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2645 info
->device_name
, enable
);
2647 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2649 if ( !info
->rx_enabled
)
2650 usc_start_receiver(info
);
2652 if ( info
->rx_enabled
)
2653 usc_stop_receiver(info
);
2655 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2658 } /* end of mgsl_rxenable() */
2660 /* mgsl_wait_event() wait for specified event to occur
2662 * Arguments: info pointer to device instance data
2663 * mask pointer to bitmask of events to wait for
2664 * Return Value: 0 if successful and bit mask updated with
2665 * of events triggerred,
2666 * otherwise error code
2668 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2670 unsigned long flags
;
2673 struct mgsl_icount cprev
, cnow
;
2676 struct _input_signal_events oldsigs
, newsigs
;
2677 DECLARE_WAITQUEUE(wait
, current
);
2679 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2684 if (debug_level
>= DEBUG_LEVEL_INFO
)
2685 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2686 info
->device_name
, mask
);
2688 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2690 /* return immediately if state matches requested events */
2691 usc_get_serial_signals(info
);
2692 s
= info
->serial_signals
;
2694 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2695 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2696 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2697 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2699 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2703 /* save current irq counts */
2704 cprev
= info
->icount
;
2705 oldsigs
= info
->input_signal_events
;
2707 /* enable hunt and idle irqs if needed */
2708 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2709 u16 oldreg
= usc_InReg(info
,RICR
);
2710 u16 newreg
= oldreg
+
2711 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2712 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2713 if (oldreg
!= newreg
)
2714 usc_OutReg(info
, RICR
, newreg
);
2717 set_current_state(TASK_INTERRUPTIBLE
);
2718 add_wait_queue(&info
->event_wait_q
, &wait
);
2720 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2725 if (signal_pending(current
)) {
2730 /* get current irq counts */
2731 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2732 cnow
= info
->icount
;
2733 newsigs
= info
->input_signal_events
;
2734 set_current_state(TASK_INTERRUPTIBLE
);
2735 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2737 /* if no change, wait aborted for some reason */
2738 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2739 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2740 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2741 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2742 newsigs
.cts_up
== oldsigs
.cts_up
&&
2743 newsigs
.cts_down
== oldsigs
.cts_down
&&
2744 newsigs
.ri_up
== oldsigs
.ri_up
&&
2745 newsigs
.ri_down
== oldsigs
.ri_down
&&
2746 cnow
.exithunt
== cprev
.exithunt
&&
2747 cnow
.rxidle
== cprev
.rxidle
) {
2753 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2754 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2755 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2756 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2757 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2758 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2759 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2760 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2761 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2762 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2770 remove_wait_queue(&info
->event_wait_q
, &wait
);
2771 set_current_state(TASK_RUNNING
);
2773 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2774 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2775 if (!waitqueue_active(&info
->event_wait_q
)) {
2776 /* disable enable exit hunt mode/idle rcvd IRQs */
2777 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2778 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2780 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2784 PUT_USER(rc
, events
, mask_ptr
);
2788 } /* end of mgsl_wait_event() */
2790 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2792 unsigned long flags
;
2794 struct mgsl_icount cprev
, cnow
;
2795 DECLARE_WAITQUEUE(wait
, current
);
2797 /* save current irq counts */
2798 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2799 cprev
= info
->icount
;
2800 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2801 set_current_state(TASK_INTERRUPTIBLE
);
2802 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2806 if (signal_pending(current
)) {
2811 /* get new irq counts */
2812 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2813 cnow
= info
->icount
;
2814 set_current_state(TASK_INTERRUPTIBLE
);
2815 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2817 /* if no change, wait aborted for some reason */
2818 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2819 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2824 /* check for change in caller specified modem input */
2825 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2826 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2827 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2828 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2835 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2836 set_current_state(TASK_RUNNING
);
2840 /* return the state of the serial control and status signals
2842 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2844 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2845 unsigned int result
;
2846 unsigned long flags
;
2848 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2849 usc_get_serial_signals(info
);
2850 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2852 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2853 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2854 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2855 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2856 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2857 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2859 if (debug_level
>= DEBUG_LEVEL_INFO
)
2860 printk("%s(%d):%s tiocmget() value=%08X\n",
2861 __FILE__
,__LINE__
, info
->device_name
, result
);
2865 /* set modem control signals (DTR/RTS)
2867 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2868 unsigned int set
, unsigned int clear
)
2870 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2871 unsigned long flags
;
2873 if (debug_level
>= DEBUG_LEVEL_INFO
)
2874 printk("%s(%d):%s tiocmset(%x,%x)\n",
2875 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2877 if (set
& TIOCM_RTS
)
2878 info
->serial_signals
|= SerialSignal_RTS
;
2879 if (set
& TIOCM_DTR
)
2880 info
->serial_signals
|= SerialSignal_DTR
;
2881 if (clear
& TIOCM_RTS
)
2882 info
->serial_signals
&= ~SerialSignal_RTS
;
2883 if (clear
& TIOCM_DTR
)
2884 info
->serial_signals
&= ~SerialSignal_DTR
;
2886 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2887 usc_set_serial_signals(info
);
2888 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2893 /* mgsl_break() Set or clear transmit break condition
2895 * Arguments: tty pointer to tty instance data
2896 * break_state -1=set break condition, 0=clear
2897 * Return Value: error code
2899 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2901 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2902 unsigned long flags
;
2904 if (debug_level
>= DEBUG_LEVEL_INFO
)
2905 printk("%s(%d):mgsl_break(%s,%d)\n",
2906 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2908 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2911 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2912 if (break_state
== -1)
2913 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2915 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2916 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2919 } /* end of mgsl_break() */
2921 /* mgsl_ioctl() Service an IOCTL request
2925 * tty pointer to tty instance data
2926 * file pointer to associated file object for device
2927 * cmd IOCTL command code
2928 * arg command argument/context
2930 * Return Value: 0 if success, otherwise error code
2932 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2933 unsigned int cmd
, unsigned long arg
)
2935 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2938 if (debug_level
>= DEBUG_LEVEL_INFO
)
2939 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2940 info
->device_name
, cmd
);
2942 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2945 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2946 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2947 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2952 ret
= mgsl_ioctl_common(info
, cmd
, arg
);
2957 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2960 struct mgsl_icount cnow
; /* kernel counter temps */
2961 void __user
*argp
= (void __user
*)arg
;
2962 struct serial_icounter_struct __user
*p_cuser
; /* user space */
2963 unsigned long flags
;
2966 case MGSL_IOCGPARAMS
:
2967 return mgsl_get_params(info
, argp
);
2968 case MGSL_IOCSPARAMS
:
2969 return mgsl_set_params(info
, argp
);
2970 case MGSL_IOCGTXIDLE
:
2971 return mgsl_get_txidle(info
, argp
);
2972 case MGSL_IOCSTXIDLE
:
2973 return mgsl_set_txidle(info
,(int)arg
);
2974 case MGSL_IOCTXENABLE
:
2975 return mgsl_txenable(info
,(int)arg
);
2976 case MGSL_IOCRXENABLE
:
2977 return mgsl_rxenable(info
,(int)arg
);
2978 case MGSL_IOCTXABORT
:
2979 return mgsl_txabort(info
);
2980 case MGSL_IOCGSTATS
:
2981 return mgsl_get_stats(info
, argp
);
2982 case MGSL_IOCWAITEVENT
:
2983 return mgsl_wait_event(info
, argp
);
2984 case MGSL_IOCLOOPTXDONE
:
2985 return mgsl_loopmode_send_done(info
);
2986 /* Wait for modem input (DCD,RI,DSR,CTS) change
2987 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2990 return modem_input_wait(info
,(int)arg
);
2993 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2994 * Return: write counters to the user passed counter struct
2995 * NB: both 1->0 and 0->1 transitions are counted except for
2996 * RI where only 0->1 is counted.
2999 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3000 cnow
= info
->icount
;
3001 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3003 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3004 if (error
) return error
;
3005 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3006 if (error
) return error
;
3007 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3008 if (error
) return error
;
3009 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3010 if (error
) return error
;
3011 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3012 if (error
) return error
;
3013 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3014 if (error
) return error
;
3015 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3016 if (error
) return error
;
3017 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3018 if (error
) return error
;
3019 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3020 if (error
) return error
;
3021 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3022 if (error
) return error
;
3023 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3024 if (error
) return error
;
3027 return -ENOIOCTLCMD
;
3032 /* mgsl_set_termios()
3034 * Set new termios settings
3038 * tty pointer to tty structure
3039 * termios pointer to buffer to hold returned old termios
3041 * Return Value: None
3043 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3045 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3046 unsigned long flags
;
3048 if (debug_level
>= DEBUG_LEVEL_INFO
)
3049 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3050 tty
->driver
->name
);
3052 mgsl_change_params(info
);
3054 /* Handle transition to B0 status */
3055 if (old_termios
->c_cflag
& CBAUD
&&
3056 !(tty
->termios
->c_cflag
& CBAUD
)) {
3057 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3058 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3059 usc_set_serial_signals(info
);
3060 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3063 /* Handle transition away from B0 status */
3064 if (!(old_termios
->c_cflag
& CBAUD
) &&
3065 tty
->termios
->c_cflag
& CBAUD
) {
3066 info
->serial_signals
|= SerialSignal_DTR
;
3067 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3068 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3069 info
->serial_signals
|= SerialSignal_RTS
;
3071 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3072 usc_set_serial_signals(info
);
3073 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3076 /* Handle turning off CRTSCTS */
3077 if (old_termios
->c_cflag
& CRTSCTS
&&
3078 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3079 tty
->hw_stopped
= 0;
3083 } /* end of mgsl_set_termios() */
3087 * Called when port is closed. Wait for remaining data to be
3088 * sent. Disable port and free resources.
3092 * tty pointer to open tty structure
3093 * filp pointer to open file object
3095 * Return Value: None
3097 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3099 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3101 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3104 if (debug_level
>= DEBUG_LEVEL_INFO
)
3105 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3106 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3108 if (!info
->port
.count
)
3111 if (tty_hung_up_p(filp
))
3114 if ((tty
->count
== 1) && (info
->port
.count
!= 1)) {
3116 * tty->count is 1 and the tty structure will be freed.
3117 * info->port.count should be one in this case.
3118 * if it's not, correct it so that the port is shutdown.
3120 printk("mgsl_close: bad refcount; tty->count is 1, "
3121 "info->port.count is %d\n", info
->port
.count
);
3122 info
->port
.count
= 1;
3127 /* if at least one open remaining, leave hardware active */
3128 if (info
->port
.count
)
3131 info
->port
.flags
|= ASYNC_CLOSING
;
3133 /* set tty->closing to notify line discipline to
3134 * only process XON/XOFF characters. Only the N_TTY
3135 * discipline appears to use this (ppp does not).
3139 /* wait for transmit data to clear all layers */
3141 if (info
->port
.closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3142 if (debug_level
>= DEBUG_LEVEL_INFO
)
3143 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3144 __FILE__
,__LINE__
, info
->device_name
);
3145 tty_wait_until_sent(tty
, info
->port
.closing_wait
);
3148 if (info
->port
.flags
& ASYNC_INITIALIZED
)
3149 mgsl_wait_until_sent(tty
, info
->timeout
);
3151 mgsl_flush_buffer(tty
);
3153 tty_ldisc_flush(tty
);
3158 info
->port
.tty
= NULL
;
3160 if (info
->port
.blocked_open
) {
3161 if (info
->port
.close_delay
) {
3162 msleep_interruptible(jiffies_to_msecs(info
->port
.close_delay
));
3164 wake_up_interruptible(&info
->port
.open_wait
);
3167 info
->port
.flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
3169 wake_up_interruptible(&info
->port
.close_wait
);
3172 if (debug_level
>= DEBUG_LEVEL_INFO
)
3173 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3174 tty
->driver
->name
, info
->port
.count
);
3176 } /* end of mgsl_close() */
3178 /* mgsl_wait_until_sent()
3180 * Wait until the transmitter is empty.
3184 * tty pointer to tty info structure
3185 * timeout time to wait for send completion
3187 * Return Value: None
3189 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3191 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3192 unsigned long orig_jiffies
, char_time
;
3197 if (debug_level
>= DEBUG_LEVEL_INFO
)
3198 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3199 __FILE__
,__LINE__
, info
->device_name
);
3201 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3204 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
3207 orig_jiffies
= jiffies
;
3209 /* Set check interval to 1/5 of estimated time to
3210 * send a character, and make it at least 1. The check
3211 * interval should also be less than the timeout.
3212 * Note: use tight timings here to satisfy the NIST-PCTS.
3216 if ( info
->params
.data_rate
) {
3217 char_time
= info
->timeout
/(32 * 5);
3224 char_time
= min_t(unsigned long, char_time
, timeout
);
3226 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3227 info
->params
.mode
== MGSL_MODE_RAW
) {
3228 while (info
->tx_active
) {
3229 msleep_interruptible(jiffies_to_msecs(char_time
));
3230 if (signal_pending(current
))
3232 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3236 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3238 msleep_interruptible(jiffies_to_msecs(char_time
));
3239 if (signal_pending(current
))
3241 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3248 if (debug_level
>= DEBUG_LEVEL_INFO
)
3249 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3250 __FILE__
,__LINE__
, info
->device_name
);
3252 } /* end of mgsl_wait_until_sent() */
3256 * Called by tty_hangup() when a hangup is signaled.
3257 * This is the same as to closing all open files for the port.
3259 * Arguments: tty pointer to associated tty object
3260 * Return Value: None
3262 static void mgsl_hangup(struct tty_struct
*tty
)
3264 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3266 if (debug_level
>= DEBUG_LEVEL_INFO
)
3267 printk("%s(%d):mgsl_hangup(%s)\n",
3268 __FILE__
,__LINE__
, info
->device_name
);
3270 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3273 mgsl_flush_buffer(tty
);
3276 info
->port
.count
= 0;
3277 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
3278 info
->port
.tty
= NULL
;
3280 wake_up_interruptible(&info
->port
.open_wait
);
3282 } /* end of mgsl_hangup() */
3287 * Return true if carrier is raised
3290 static int carrier_raised(struct tty_port
*port
)
3292 unsigned long flags
;
3293 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3295 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3296 usc_get_serial_signals(info
);
3297 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3298 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3301 /* block_til_ready()
3303 * Block the current process until the specified port
3304 * is ready to be opened.
3308 * tty pointer to tty info structure
3309 * filp pointer to open file object
3310 * info pointer to device instance data
3312 * Return Value: 0 if success, otherwise error code
3314 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3315 struct mgsl_struct
*info
)
3317 DECLARE_WAITQUEUE(wait
, current
);
3319 bool do_clocal
= false;
3320 bool extra_count
= false;
3321 unsigned long flags
;
3323 struct tty_port
*port
= &info
->port
;
3325 if (debug_level
>= DEBUG_LEVEL_INFO
)
3326 printk("%s(%d):block_til_ready on %s\n",
3327 __FILE__
,__LINE__
, tty
->driver
->name
);
3329 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3330 /* nonblock mode is set or port is not enabled */
3331 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3335 if (tty
->termios
->c_cflag
& CLOCAL
)
3338 /* Wait for carrier detect and the line to become
3339 * free (i.e., not in use by the callout). While we are in
3340 * this loop, port->count is dropped by one, so that
3341 * mgsl_close() knows when to free things. We restore it upon
3342 * exit, either normal or abnormal.
3346 add_wait_queue(&port
->open_wait
, &wait
);
3348 if (debug_level
>= DEBUG_LEVEL_INFO
)
3349 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3350 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3352 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3353 if (!tty_hung_up_p(filp
)) {
3357 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3358 port
->blocked_open
++;
3361 if (tty
->termios
->c_cflag
& CBAUD
) {
3362 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3363 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3364 usc_set_serial_signals(info
);
3365 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3368 set_current_state(TASK_INTERRUPTIBLE
);
3370 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3371 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3372 -EAGAIN
: -ERESTARTSYS
;
3376 dcd
= tty_port_carrier_raised(&info
->port
);
3378 if (!(port
->flags
& ASYNC_CLOSING
) && (do_clocal
|| dcd
))
3381 if (signal_pending(current
)) {
3382 retval
= -ERESTARTSYS
;
3386 if (debug_level
>= DEBUG_LEVEL_INFO
)
3387 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3388 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3393 set_current_state(TASK_RUNNING
);
3394 remove_wait_queue(&port
->open_wait
, &wait
);
3398 port
->blocked_open
--;
3400 if (debug_level
>= DEBUG_LEVEL_INFO
)
3401 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3402 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3405 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3409 } /* end of block_til_ready() */
3413 * Called when a port is opened. Init and enable port.
3414 * Perform serial-specific initialization for the tty structure.
3416 * Arguments: tty pointer to tty info structure
3417 * filp associated file pointer
3419 * Return Value: 0 if success, otherwise error code
3421 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3423 struct mgsl_struct
*info
;
3425 unsigned long flags
;
3427 /* verify range of specified line number */
3429 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3430 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3431 __FILE__
,__LINE__
,line
);
3435 /* find the info structure for the specified line */
3436 info
= mgsl_device_list
;
3437 while(info
&& info
->line
!= line
)
3438 info
= info
->next_device
;
3439 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3442 tty
->driver_data
= info
;
3443 info
->port
.tty
= tty
;
3445 if (debug_level
>= DEBUG_LEVEL_INFO
)
3446 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3447 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3449 /* If port is closing, signal caller to try again */
3450 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
3451 if (info
->port
.flags
& ASYNC_CLOSING
)
3452 interruptible_sleep_on(&info
->port
.close_wait
);
3453 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
3454 -EAGAIN
: -ERESTARTSYS
);
3458 info
->port
.tty
->low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3460 spin_lock_irqsave(&info
->netlock
, flags
);
3461 if (info
->netcount
) {
3463 spin_unlock_irqrestore(&info
->netlock
, flags
);
3467 spin_unlock_irqrestore(&info
->netlock
, flags
);
3469 if (info
->port
.count
== 1) {
3470 /* 1st open on this device, init hardware */
3471 retval
= startup(info
);
3476 retval
= block_til_ready(tty
, filp
, info
);
3478 if (debug_level
>= DEBUG_LEVEL_INFO
)
3479 printk("%s(%d):block_til_ready(%s) returned %d\n",
3480 __FILE__
,__LINE__
, info
->device_name
, retval
);
3484 if (debug_level
>= DEBUG_LEVEL_INFO
)
3485 printk("%s(%d):mgsl_open(%s) success\n",
3486 __FILE__
,__LINE__
, info
->device_name
);
3491 if (tty
->count
== 1)
3492 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3493 if(info
->port
.count
)
3499 } /* end of mgsl_open() */
3502 * /proc fs routines....
3505 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3509 unsigned long flags
;
3511 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3512 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3513 info
->device_name
, info
->io_base
, info
->irq_level
,
3514 info
->phys_memory_base
, info
->phys_lcr_base
);
3516 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3517 info
->device_name
, info
->io_base
,
3518 info
->irq_level
, info
->dma_level
);
3521 /* output current serial signal states */
3522 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3523 usc_get_serial_signals(info
);
3524 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3528 if (info
->serial_signals
& SerialSignal_RTS
)
3529 strcat(stat_buf
, "|RTS");
3530 if (info
->serial_signals
& SerialSignal_CTS
)
3531 strcat(stat_buf
, "|CTS");
3532 if (info
->serial_signals
& SerialSignal_DTR
)
3533 strcat(stat_buf
, "|DTR");
3534 if (info
->serial_signals
& SerialSignal_DSR
)
3535 strcat(stat_buf
, "|DSR");
3536 if (info
->serial_signals
& SerialSignal_DCD
)
3537 strcat(stat_buf
, "|CD");
3538 if (info
->serial_signals
& SerialSignal_RI
)
3539 strcat(stat_buf
, "|RI");
3541 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3542 info
->params
.mode
== MGSL_MODE_RAW
) {
3543 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3544 info
->icount
.txok
, info
->icount
.rxok
);
3545 if (info
->icount
.txunder
)
3546 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3547 if (info
->icount
.txabort
)
3548 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3549 if (info
->icount
.rxshort
)
3550 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3551 if (info
->icount
.rxlong
)
3552 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3553 if (info
->icount
.rxover
)
3554 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3555 if (info
->icount
.rxcrc
)
3556 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
3558 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3559 info
->icount
.tx
, info
->icount
.rx
);
3560 if (info
->icount
.frame
)
3561 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3562 if (info
->icount
.parity
)
3563 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3564 if (info
->icount
.brk
)
3565 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3566 if (info
->icount
.overrun
)
3567 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3570 /* Append serial signal status to end */
3571 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3573 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3574 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3577 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3579 u16 Tcsr
= usc_InReg( info
, TCSR
);
3580 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3581 u16 Ticr
= usc_InReg( info
, TICR
);
3582 u16 Rscr
= usc_InReg( info
, RCSR
);
3583 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3584 u16 Ricr
= usc_InReg( info
, RICR
);
3585 u16 Icr
= usc_InReg( info
, ICR
);
3586 u16 Dccr
= usc_InReg( info
, DCCR
);
3587 u16 Tmr
= usc_InReg( info
, TMR
);
3588 u16 Tccr
= usc_InReg( info
, TCCR
);
3589 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3590 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3591 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3592 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3594 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3598 } /* end of line_info() */
3602 * Called to print information about devices
3605 * page page of memory to hold returned info
3614 static int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3615 int *eof
, void *data
)
3619 struct mgsl_struct
*info
;
3621 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3623 info
= mgsl_device_list
;
3625 l
= line_info(page
+ len
, info
);
3627 if (len
+begin
> off
+count
)
3629 if (len
+begin
< off
) {
3633 info
= info
->next_device
;
3638 if (off
>= len
+begin
)
3640 *start
= page
+ (off
-begin
);
3641 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3643 } /* end of mgsl_read_proc() */
3645 /* mgsl_allocate_dma_buffers()
3647 * Allocate and format DMA buffers (ISA adapter)
3648 * or format shared memory buffers (PCI adapter).
3650 * Arguments: info pointer to device instance data
3651 * Return Value: 0 if success, otherwise error
3653 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3655 unsigned short BuffersPerFrame
;
3657 info
->last_mem_alloc
= 0;
3659 /* Calculate the number of DMA buffers necessary to hold the */
3660 /* largest allowable frame size. Note: If the max frame size is */
3661 /* not an even multiple of the DMA buffer size then we need to */
3662 /* round the buffer count per frame up one. */
3664 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3665 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3668 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3670 * The PCI adapter has 256KBytes of shared memory to use.
3671 * This is 64 PAGE_SIZE buffers.
3673 * The first page is used for padding at this time so the
3674 * buffer list does not begin at offset 0 of the PCI
3675 * adapter's shared memory.
3677 * The 2nd page is used for the buffer list. A 4K buffer
3678 * list can hold 128 DMA_BUFFER structures at 32 bytes
3681 * This leaves 62 4K pages.
3683 * The next N pages are used for transmit frame(s). We
3684 * reserve enough 4K page blocks to hold the required
3685 * number of transmit dma buffers (num_tx_dma_buffers),
3686 * each of MaxFrameSize size.
3688 * Of the remaining pages (62-N), determine how many can
3689 * be used to receive full MaxFrameSize inbound frames
3691 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3692 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3694 /* Calculate the number of PAGE_SIZE buffers needed for */
3695 /* receive and transmit DMA buffers. */
3698 /* Calculate the number of DMA buffers necessary to */
3699 /* hold 7 max size receive frames and one max size transmit frame. */
3700 /* The receive buffer count is bumped by one so we avoid an */
3701 /* End of List condition if all receive buffers are used when */
3702 /* using linked list DMA buffers. */
3704 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3705 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3708 * limit total TxBuffers & RxBuffers to 62 4K total
3709 * (ala PCI Allocation)
3712 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3713 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3717 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3718 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3719 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3721 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3722 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3723 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3724 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3725 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3726 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3730 mgsl_reset_rx_dma_buffers( info
);
3731 mgsl_reset_tx_dma_buffers( info
);
3735 } /* end of mgsl_allocate_dma_buffers() */
3738 * mgsl_alloc_buffer_list_memory()
3740 * Allocate a common DMA buffer for use as the
3741 * receive and transmit buffer lists.
3743 * A buffer list is a set of buffer entries where each entry contains
3744 * a pointer to an actual buffer and a pointer to the next buffer entry
3745 * (plus some other info about the buffer).
3747 * The buffer entries for a list are built to form a circular list so
3748 * that when the entire list has been traversed you start back at the
3751 * This function allocates memory for just the buffer entries.
3752 * The links (pointer to next entry) are filled in with the physical
3753 * address of the next entry so the adapter can navigate the list
3754 * using bus master DMA. The pointers to the actual buffers are filled
3755 * out later when the actual buffers are allocated.
3757 * Arguments: info pointer to device instance data
3758 * Return Value: 0 if success, otherwise error
3760 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3764 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3765 /* PCI adapter uses shared memory. */
3766 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3767 info
->buffer_list_phys
= info
->last_mem_alloc
;
3768 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3770 /* ISA adapter uses system memory. */
3771 /* The buffer lists are allocated as a common buffer that both */
3772 /* the processor and adapter can access. This allows the driver to */
3773 /* inspect portions of the buffer while other portions are being */
3774 /* updated by the adapter using Bus Master DMA. */
3776 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3777 if (info
->buffer_list
== NULL
)
3779 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3782 /* We got the memory for the buffer entry lists. */
3783 /* Initialize the memory block to all zeros. */
3784 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3786 /* Save virtual address pointers to the receive and */
3787 /* transmit buffer lists. (Receive 1st). These pointers will */
3788 /* be used by the processor to access the lists. */
3789 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3790 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3791 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3794 * Build the links for the buffer entry lists such that
3795 * two circular lists are built. (Transmit and Receive).
3797 * Note: the links are physical addresses
3798 * which are read by the adapter to determine the next
3799 * buffer entry to use.
3802 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3803 /* calculate and store physical address of this buffer entry */
3804 info
->rx_buffer_list
[i
].phys_entry
=
3805 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3807 /* calculate and store physical address of */
3808 /* next entry in cirular list of entries */
3810 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3812 if ( i
< info
->rx_buffer_count
- 1 )
3813 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3816 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3817 /* calculate and store physical address of this buffer entry */
3818 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3819 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3821 /* calculate and store physical address of */
3822 /* next entry in cirular list of entries */
3824 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3825 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3827 if ( i
< info
->tx_buffer_count
- 1 )
3828 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3833 } /* end of mgsl_alloc_buffer_list_memory() */
3835 /* Free DMA buffers allocated for use as the
3836 * receive and transmit buffer lists.
3839 * The data transfer buffers associated with the buffer list
3840 * MUST be freed before freeing the buffer list itself because
3841 * the buffer list contains the information necessary to free
3842 * the individual buffers!
3844 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3846 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3847 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3849 info
->buffer_list
= NULL
;
3850 info
->rx_buffer_list
= NULL
;
3851 info
->tx_buffer_list
= NULL
;
3853 } /* end of mgsl_free_buffer_list_memory() */
3856 * mgsl_alloc_frame_memory()
3858 * Allocate the frame DMA buffers used by the specified buffer list.
3859 * Each DMA buffer will be one memory page in size. This is necessary
3860 * because memory can fragment enough that it may be impossible
3865 * info pointer to device instance data
3866 * BufferList pointer to list of buffer entries
3867 * Buffercount count of buffer entries in buffer list
3869 * Return Value: 0 if success, otherwise -ENOMEM
3871 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3876 /* Allocate page sized buffers for the receive buffer list */
3878 for ( i
= 0; i
< Buffercount
; i
++ ) {
3879 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3880 /* PCI adapter uses shared memory buffers. */
3881 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3882 phys_addr
= info
->last_mem_alloc
;
3883 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3885 /* ISA adapter uses system memory. */
3886 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3887 if (BufferList
[i
].virt_addr
== NULL
)
3889 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3891 BufferList
[i
].phys_addr
= phys_addr
;
3896 } /* end of mgsl_alloc_frame_memory() */
3899 * mgsl_free_frame_memory()
3901 * Free the buffers associated with
3902 * each buffer entry of a buffer list.
3906 * info pointer to device instance data
3907 * BufferList pointer to list of buffer entries
3908 * Buffercount count of buffer entries in buffer list
3910 * Return Value: None
3912 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3917 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3918 if ( BufferList
[i
].virt_addr
) {
3919 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3920 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3921 BufferList
[i
].virt_addr
= NULL
;
3926 } /* end of mgsl_free_frame_memory() */
3928 /* mgsl_free_dma_buffers()
3932 * Arguments: info pointer to device instance data
3933 * Return Value: None
3935 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3937 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3938 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3939 mgsl_free_buffer_list_memory( info
);
3941 } /* end of mgsl_free_dma_buffers() */
3945 * mgsl_alloc_intermediate_rxbuffer_memory()
3947 * Allocate a buffer large enough to hold max_frame_size. This buffer
3948 * is used to pass an assembled frame to the line discipline.
3952 * info pointer to device instance data
3954 * Return Value: 0 if success, otherwise -ENOMEM
3956 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3958 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3959 if ( info
->intermediate_rxbuffer
== NULL
)
3964 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3967 * mgsl_free_intermediate_rxbuffer_memory()
3972 * info pointer to device instance data
3974 * Return Value: None
3976 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3978 kfree(info
->intermediate_rxbuffer
);
3979 info
->intermediate_rxbuffer
= NULL
;
3981 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3984 * mgsl_alloc_intermediate_txbuffer_memory()
3986 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3987 * This buffer is used to load transmit frames into the adapter's dma transfer
3988 * buffers when there is sufficient space.
3992 * info pointer to device instance data
3994 * Return Value: 0 if success, otherwise -ENOMEM
3996 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4000 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4001 printk("%s %s(%d) allocating %d tx holding buffers\n",
4002 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
4004 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
4006 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4007 info
->tx_holding_buffers
[i
].buffer
=
4008 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
4009 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
4010 for (--i
; i
>= 0; i
--) {
4011 kfree(info
->tx_holding_buffers
[i
].buffer
);
4012 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4020 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4023 * mgsl_free_intermediate_txbuffer_memory()
4028 * info pointer to device instance data
4030 * Return Value: None
4032 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4036 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4037 kfree(info
->tx_holding_buffers
[i
].buffer
);
4038 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4041 info
->get_tx_holding_index
= 0;
4042 info
->put_tx_holding_index
= 0;
4043 info
->tx_holding_count
= 0;
4045 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4049 * load_next_tx_holding_buffer()
4051 * attempts to load the next buffered tx request into the
4056 * info pointer to device instance data
4058 * Return Value: true if next buffered tx request loaded
4059 * into adapter's tx dma buffer,
4062 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4066 if ( info
->tx_holding_count
) {
4067 /* determine if we have enough tx dma buffers
4068 * to accommodate the next tx frame
4070 struct tx_holding_buffer
*ptx
=
4071 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4072 int num_free
= num_free_tx_dma_buffers(info
);
4073 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4074 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4077 if (num_needed
<= num_free
) {
4078 info
->xmit_cnt
= ptx
->buffer_size
;
4079 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4081 --info
->tx_holding_count
;
4082 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4083 info
->get_tx_holding_index
=0;
4085 /* restart transmit timer */
4086 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4096 * save_tx_buffer_request()
4098 * attempt to store transmit frame request for later transmission
4102 * info pointer to device instance data
4103 * Buffer pointer to buffer containing frame to load
4104 * BufferSize size in bytes of frame in Buffer
4106 * Return Value: 1 if able to store, 0 otherwise
4108 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4110 struct tx_holding_buffer
*ptx
;
4112 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4113 return 0; /* all buffers in use */
4116 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4117 ptx
->buffer_size
= BufferSize
;
4118 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4120 ++info
->tx_holding_count
;
4121 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4122 info
->put_tx_holding_index
=0;
4127 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4129 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4130 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4131 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4134 info
->io_addr_requested
= true;
4136 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4137 info
->device_name
, info
) < 0 ) {
4138 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4139 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4142 info
->irq_requested
= true;
4144 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4145 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4146 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4147 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4150 info
->shared_mem_requested
= true;
4151 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4152 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4153 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4156 info
->lcr_mem_requested
= true;
4158 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4160 if (!info
->memory_base
) {
4161 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4162 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4166 if ( !mgsl_memory_test(info
) ) {
4167 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4168 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4172 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4174 if (!info
->lcr_base
) {
4175 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4176 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4179 info
->lcr_base
+= info
->lcr_offset
;
4182 /* claim DMA channel */
4184 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4185 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4186 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4187 mgsl_release_resources( info
);
4190 info
->dma_requested
= true;
4192 /* ISA adapter uses bus master DMA */
4193 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4194 enable_dma(info
->dma_level
);
4197 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4198 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4199 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4205 mgsl_release_resources(info
);
4208 } /* end of mgsl_claim_resources() */
4210 static void mgsl_release_resources(struct mgsl_struct
*info
)
4212 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4213 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4214 __FILE__
,__LINE__
,info
->device_name
);
4216 if ( info
->irq_requested
) {
4217 free_irq(info
->irq_level
, info
);
4218 info
->irq_requested
= false;
4220 if ( info
->dma_requested
) {
4221 disable_dma(info
->dma_level
);
4222 free_dma(info
->dma_level
);
4223 info
->dma_requested
= false;
4225 mgsl_free_dma_buffers(info
);
4226 mgsl_free_intermediate_rxbuffer_memory(info
);
4227 mgsl_free_intermediate_txbuffer_memory(info
);
4229 if ( info
->io_addr_requested
) {
4230 release_region(info
->io_base
,info
->io_addr_size
);
4231 info
->io_addr_requested
= false;
4233 if ( info
->shared_mem_requested
) {
4234 release_mem_region(info
->phys_memory_base
,0x40000);
4235 info
->shared_mem_requested
= false;
4237 if ( info
->lcr_mem_requested
) {
4238 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4239 info
->lcr_mem_requested
= false;
4241 if (info
->memory_base
){
4242 iounmap(info
->memory_base
);
4243 info
->memory_base
= NULL
;
4245 if (info
->lcr_base
){
4246 iounmap(info
->lcr_base
- info
->lcr_offset
);
4247 info
->lcr_base
= NULL
;
4250 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4251 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4252 __FILE__
,__LINE__
,info
->device_name
);
4254 } /* end of mgsl_release_resources() */
4256 /* mgsl_add_device()
4258 * Add the specified device instance data structure to the
4259 * global linked list of devices and increment the device count.
4261 * Arguments: info pointer to device instance data
4262 * Return Value: None
4264 static void mgsl_add_device( struct mgsl_struct
*info
)
4266 info
->next_device
= NULL
;
4267 info
->line
= mgsl_device_count
;
4268 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4270 if (info
->line
< MAX_TOTAL_DEVICES
) {
4271 if (maxframe
[info
->line
])
4272 info
->max_frame_size
= maxframe
[info
->line
];
4274 if (txdmabufs
[info
->line
]) {
4275 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4276 if (info
->num_tx_dma_buffers
< 1)
4277 info
->num_tx_dma_buffers
= 1;
4280 if (txholdbufs
[info
->line
]) {
4281 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4282 if (info
->num_tx_holding_buffers
< 1)
4283 info
->num_tx_holding_buffers
= 1;
4284 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4285 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4289 mgsl_device_count
++;
4291 if ( !mgsl_device_list
)
4292 mgsl_device_list
= info
;
4294 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4295 while( current_dev
->next_device
)
4296 current_dev
= current_dev
->next_device
;
4297 current_dev
->next_device
= info
;
4300 if ( info
->max_frame_size
< 4096 )
4301 info
->max_frame_size
= 4096;
4302 else if ( info
->max_frame_size
> 65535 )
4303 info
->max_frame_size
= 65535;
4305 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4306 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4307 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4308 info
->phys_memory_base
, info
->phys_lcr_base
,
4309 info
->max_frame_size
);
4311 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4312 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4313 info
->max_frame_size
);
4316 #if SYNCLINK_GENERIC_HDLC
4320 } /* end of mgsl_add_device() */
4322 static const struct tty_port_operations mgsl_port_ops
= {
4323 .carrier_raised
= carrier_raised
,
4327 /* mgsl_allocate_device()
4329 * Allocate and initialize a device instance structure
4332 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4334 static struct mgsl_struct
* mgsl_allocate_device(void)
4336 struct mgsl_struct
*info
;
4338 info
= kzalloc(sizeof(struct mgsl_struct
),
4342 printk("Error can't allocate device instance data\n");
4344 tty_port_init(&info
->port
);
4345 info
->port
.ops
= &mgsl_port_ops
;
4346 info
->magic
= MGSL_MAGIC
;
4347 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4348 info
->max_frame_size
= 4096;
4349 info
->port
.close_delay
= 5*HZ
/10;
4350 info
->port
.closing_wait
= 30*HZ
;
4351 init_waitqueue_head(&info
->status_event_wait_q
);
4352 init_waitqueue_head(&info
->event_wait_q
);
4353 spin_lock_init(&info
->irq_spinlock
);
4354 spin_lock_init(&info
->netlock
);
4355 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4356 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4357 info
->num_tx_dma_buffers
= 1;
4358 info
->num_tx_holding_buffers
= 0;
4363 } /* end of mgsl_allocate_device()*/
4365 static const struct tty_operations mgsl_ops
= {
4367 .close
= mgsl_close
,
4368 .write
= mgsl_write
,
4369 .put_char
= mgsl_put_char
,
4370 .flush_chars
= mgsl_flush_chars
,
4371 .write_room
= mgsl_write_room
,
4372 .chars_in_buffer
= mgsl_chars_in_buffer
,
4373 .flush_buffer
= mgsl_flush_buffer
,
4374 .ioctl
= mgsl_ioctl
,
4375 .throttle
= mgsl_throttle
,
4376 .unthrottle
= mgsl_unthrottle
,
4377 .send_xchar
= mgsl_send_xchar
,
4378 .break_ctl
= mgsl_break
,
4379 .wait_until_sent
= mgsl_wait_until_sent
,
4380 .read_proc
= mgsl_read_proc
,
4381 .set_termios
= mgsl_set_termios
,
4383 .start
= mgsl_start
,
4384 .hangup
= mgsl_hangup
,
4385 .tiocmget
= tiocmget
,
4386 .tiocmset
= tiocmset
,
4390 * perform tty device initialization
4392 static int mgsl_init_tty(void)
4396 serial_driver
= alloc_tty_driver(128);
4400 serial_driver
->owner
= THIS_MODULE
;
4401 serial_driver
->driver_name
= "synclink";
4402 serial_driver
->name
= "ttySL";
4403 serial_driver
->major
= ttymajor
;
4404 serial_driver
->minor_start
= 64;
4405 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4406 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4407 serial_driver
->init_termios
= tty_std_termios
;
4408 serial_driver
->init_termios
.c_cflag
=
4409 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4410 serial_driver
->init_termios
.c_ispeed
= 9600;
4411 serial_driver
->init_termios
.c_ospeed
= 9600;
4412 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4413 tty_set_operations(serial_driver
, &mgsl_ops
);
4414 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4415 printk("%s(%d):Couldn't register serial driver\n",
4417 put_tty_driver(serial_driver
);
4418 serial_driver
= NULL
;
4422 printk("%s %s, tty major#%d\n",
4423 driver_name
, driver_version
,
4424 serial_driver
->major
);
4428 /* enumerate user specified ISA adapters
4430 static void mgsl_enum_isa_devices(void)
4432 struct mgsl_struct
*info
;
4435 /* Check for user specified ISA devices */
4437 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4438 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4439 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4440 io
[i
], irq
[i
], dma
[i
] );
4442 info
= mgsl_allocate_device();
4444 /* error allocating device instance data */
4445 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4446 printk( "can't allocate device instance data.\n");
4450 /* Copy user configuration info to device instance data */
4451 info
->io_base
= (unsigned int)io
[i
];
4452 info
->irq_level
= (unsigned int)irq
[i
];
4453 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4454 info
->dma_level
= (unsigned int)dma
[i
];
4455 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4456 info
->io_addr_size
= 16;
4457 info
->irq_flags
= 0;
4459 mgsl_add_device( info
);
4463 static void synclink_cleanup(void)
4466 struct mgsl_struct
*info
;
4467 struct mgsl_struct
*tmp
;
4469 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4471 if (serial_driver
) {
4472 if ((rc
= tty_unregister_driver(serial_driver
)))
4473 printk("%s(%d) failed to unregister tty driver err=%d\n",
4474 __FILE__
,__LINE__
,rc
);
4475 put_tty_driver(serial_driver
);
4478 info
= mgsl_device_list
;
4480 #if SYNCLINK_GENERIC_HDLC
4483 mgsl_release_resources(info
);
4485 info
= info
->next_device
;
4490 pci_unregister_driver(&synclink_pci_driver
);
4493 static int __init
synclink_init(void)
4497 if (break_on_load
) {
4498 mgsl_get_text_ptr();
4502 printk("%s %s\n", driver_name
, driver_version
);
4504 mgsl_enum_isa_devices();
4505 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4506 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4508 pci_registered
= true;
4510 if ((rc
= mgsl_init_tty()) < 0)
4520 static void __exit
synclink_exit(void)
4525 module_init(synclink_init
);
4526 module_exit(synclink_exit
);
4531 * Issue a USC Receive/Transmit command to the
4532 * Channel Command/Address Register (CCAR).
4536 * The command is encoded in the most significant 5 bits <15..11>
4537 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4538 * and Bits <6..0> must be written as zeros.
4542 * info pointer to device information structure
4543 * Cmd command mask (use symbolic macros)
4549 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4551 /* output command to CCAR in bits <15..11> */
4552 /* preserve bits <10..7>, bits <6..0> must be zero */
4554 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4556 /* Read to flush write to CCAR */
4557 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4558 inw( info
->io_base
+ CCAR
);
4560 } /* end of usc_RTCmd() */
4565 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4569 * info pointer to device information structure
4570 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4576 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4578 /* write command mask to DCAR */
4579 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4581 /* Read to flush write to DCAR */
4582 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4583 inw( info
->io_base
);
4585 } /* end of usc_DmaCmd() */
4590 * Write a 16-bit value to a USC DMA register
4594 * info pointer to device info structure
4595 * RegAddr register address (number) for write
4596 * RegValue 16-bit value to write to register
4603 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4605 /* Note: The DCAR is located at the adapter base address */
4606 /* Note: must preserve state of BIT8 in DCAR */
4608 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4609 outw( RegValue
, info
->io_base
);
4611 /* Read to flush write to DCAR */
4612 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4613 inw( info
->io_base
);
4615 } /* end of usc_OutDmaReg() */
4620 * Read a 16-bit value from a DMA register
4624 * info pointer to device info structure
4625 * RegAddr register address (number) to read from
4629 * The 16-bit value read from register
4632 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4634 /* Note: The DCAR is located at the adapter base address */
4635 /* Note: must preserve state of BIT8 in DCAR */
4637 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4638 return inw( info
->io_base
);
4640 } /* end of usc_InDmaReg() */
4646 * Write a 16-bit value to a USC serial channel register
4650 * info pointer to device info structure
4651 * RegAddr register address (number) to write to
4652 * RegValue 16-bit value to write to register
4659 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4661 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4662 outw( RegValue
, info
->io_base
+ CCAR
);
4664 /* Read to flush write to CCAR */
4665 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4666 inw( info
->io_base
+ CCAR
);
4668 } /* end of usc_OutReg() */
4673 * Reads a 16-bit value from a USC serial channel register
4677 * info pointer to device extension
4678 * RegAddr register address (number) to read from
4682 * 16-bit value read from register
4684 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4686 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4687 return inw( info
->io_base
+ CCAR
);
4689 } /* end of usc_InReg() */
4691 /* usc_set_sdlc_mode()
4693 * Set up the adapter for SDLC DMA communications.
4695 * Arguments: info pointer to device instance data
4696 * Return Value: NONE
4698 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4704 * determine if the IUSC on the adapter is pre-SL1660. If
4705 * not, take advantage of the UnderWait feature of more
4706 * modern chips. If an underrun occurs and this bit is set,
4707 * the transmitter will idle the programmed idle pattern
4708 * until the driver has time to service the underrun. Otherwise,
4709 * the dma controller may get the cycles previously requested
4710 * and begin transmitting queued tx data.
4712 usc_OutReg(info
,TMCR
,0x1f);
4713 RegValue
=usc_InReg(info
,TMDR
);
4714 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4716 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4719 ** Channel Mode Register (CMR)
4721 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4722 ** <13> 0 0 = Transmit Disabled (initially)
4723 ** <12> 0 1 = Consecutive Idles share common 0
4724 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4725 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4726 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4728 ** 1000 1110 0000 0110 = 0x8e06
4732 /*--------------------------------------------------
4733 * ignore user options for UnderRun Actions and
4735 *--------------------------------------------------*/
4739 /* Channel mode Register (CMR)
4741 * <15..14> 00 Tx Sub modes, Underrun Action
4742 * <13> 0 1 = Send Preamble before opening flag
4743 * <12> 0 1 = Consecutive Idles share common 0
4744 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4745 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4746 * <3..0> 0110 Receiver mode = HDLC/SDLC
4748 * 0000 0110 0000 0110 = 0x0606
4750 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4751 RegValue
= 0x0001; /* Set Receive mode = external sync */
4753 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4754 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4758 * CMR <15> 0 Don't send CRC on Tx Underrun
4759 * CMR <14> x undefined
4760 * CMR <13> 0 Send preamble before openning sync
4761 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4764 * CMR <11-8) 0100 MonoSync
4766 * 0x00 0100 xxxx xxxx 04xx
4774 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4776 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4778 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4779 RegValue
|= BIT15
+ BIT14
;
4782 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4786 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4787 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4790 if ( info
->params
.addr_filter
!= 0xff )
4792 /* set up receive address filtering */
4793 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4797 usc_OutReg( info
, CMR
, RegValue
);
4798 info
->cmr_value
= RegValue
;
4800 /* Receiver mode Register (RMR)
4802 * <15..13> 000 encoding
4803 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4804 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4805 * <9> 0 1 = Include Receive chars in CRC
4806 * <8> 1 1 = Use Abort/PE bit as abort indicator
4807 * <7..6> 00 Even parity
4808 * <5> 0 parity disabled
4809 * <4..2> 000 Receive Char Length = 8 bits
4810 * <1..0> 00 Disable Receiver
4812 * 0000 0101 0000 0000 = 0x0500
4817 switch ( info
->params
.encoding
) {
4818 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4819 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4820 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4821 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4822 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4823 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4824 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4827 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4829 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4830 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4832 usc_OutReg( info
, RMR
, RegValue
);
4834 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4835 /* When an opening flag of an SDLC frame is recognized the */
4836 /* Receive Character count (RCC) is loaded with the value in */
4837 /* RCLR. The RCC is decremented for each received byte. The */
4838 /* value of RCC is stored after the closing flag of the frame */
4839 /* allowing the frame size to be computed. */
4841 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4843 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4845 /* Receive Interrupt Control Register (RICR)
4847 * <15..8> ? RxFIFO DMA Request Level
4848 * <7> 0 Exited Hunt IA (Interrupt Arm)
4849 * <6> 0 Idle Received IA
4850 * <5> 0 Break/Abort IA
4852 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4854 * <1> 1 Rx Overrun IA
4855 * <0> 0 Select TC0 value for readback
4857 * 0000 0000 0000 1000 = 0x000a
4860 /* Carry over the Exit Hunt and Idle Received bits */
4861 /* in case they have been armed by usc_ArmEvents. */
4863 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4865 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4866 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4868 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4870 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4872 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4873 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4875 /* Transmit mode Register (TMR)
4877 * <15..13> 000 encoding
4878 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4879 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4880 * <9> 0 1 = Tx CRC Enabled
4881 * <8> 0 1 = Append CRC to end of transmit frame
4882 * <7..6> 00 Transmit parity Even
4883 * <5> 0 Transmit parity Disabled
4884 * <4..2> 000 Tx Char Length = 8 bits
4885 * <1..0> 00 Disable Transmitter
4887 * 0000 0100 0000 0000 = 0x0400
4892 switch ( info
->params
.encoding
) {
4893 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4894 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4895 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4896 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4897 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4898 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4899 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4902 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4903 RegValue
|= BIT9
+ BIT8
;
4904 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4905 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4907 usc_OutReg( info
, TMR
, RegValue
);
4909 usc_set_txidle( info
);
4912 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4914 /* Transmit Interrupt Control Register (TICR)
4916 * <15..8> ? Transmit FIFO DMA Level
4917 * <7> 0 Present IA (Interrupt Arm)
4918 * <6> 0 Idle Sent IA
4919 * <5> 1 Abort Sent IA
4920 * <4> 1 EOF/EOM Sent IA
4922 * <2> 1 1 = Wait for SW Trigger to Start Frame
4923 * <1> 1 Tx Underrun IA
4924 * <0> 0 TC0 constant on read back
4926 * 0000 0000 0011 0110 = 0x0036
4929 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4930 usc_OutReg( info
, TICR
, 0x0736 );
4932 usc_OutReg( info
, TICR
, 0x1436 );
4934 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4935 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4938 ** Transmit Command/Status Register (TCSR)
4940 ** <15..12> 0000 TCmd
4941 ** <11> 0/1 UnderWait
4942 ** <10..08> 000 TxIdle
4946 ** <4> x EOF/EOM Sent
4952 ** 0000 0000 0000 0000 = 0x0000
4954 info
->tcsr_value
= 0;
4957 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4959 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4961 /* Clock mode Control Register (CMCR)
4963 * <15..14> 00 counter 1 Source = Disabled
4964 * <13..12> 00 counter 0 Source = Disabled
4965 * <11..10> 11 BRG1 Input is TxC Pin
4966 * <9..8> 11 BRG0 Input is TxC Pin
4967 * <7..6> 01 DPLL Input is BRG1 Output
4968 * <5..3> XXX TxCLK comes from Port 0
4969 * <2..0> XXX RxCLK comes from Port 1
4971 * 0000 1111 0111 0111 = 0x0f77
4976 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4977 RegValue
|= 0x0003; /* RxCLK from DPLL */
4978 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4979 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4980 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4981 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4983 RegValue
|= 0x0007; /* RxCLK from Port1 */
4985 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4986 RegValue
|= 0x0018; /* TxCLK from DPLL */
4987 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4988 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4989 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4990 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4992 RegValue
|= 0x0030; /* TxCLK from Port0 */
4994 usc_OutReg( info
, CMCR
, RegValue
);
4997 /* Hardware Configuration Register (HCR)
4999 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5000 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5001 * <12> 0 CVOK:0=report code violation in biphase
5002 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5003 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5004 * <7..6> 00 reserved
5005 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5007 * <3..2> 00 reserved
5008 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5014 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
5019 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5020 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5022 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5023 XtalSpeed
= 11059200;
5025 XtalSpeed
= 14745600;
5027 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
5031 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
5038 /* Tc = (Xtal/Speed) - 1 */
5039 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5040 /* then rounding up gives a more precise time constant. Instead */
5041 /* of rounding up and then subtracting 1 we just don't subtract */
5042 /* the one in this case. */
5044 /*--------------------------------------------------
5045 * ejz: for DPLL mode, application should use the
5046 * same clock speed as the partner system, even
5047 * though clocking is derived from the input RxData.
5048 * In case the user uses a 0 for the clock speed,
5049 * default to 0xffffffff and don't try to divide by
5051 *--------------------------------------------------*/
5052 if ( info
->params
.clock_speed
)
5054 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5055 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5056 / info
->params
.clock_speed
) )
5063 /* Write 16-bit Time Constant for BRG1 */
5064 usc_OutReg( info
, TC1R
, Tc
);
5066 RegValue
|= BIT4
; /* enable BRG1 */
5068 switch ( info
->params
.encoding
) {
5069 case HDLC_ENCODING_NRZ
:
5070 case HDLC_ENCODING_NRZB
:
5071 case HDLC_ENCODING_NRZI_MARK
:
5072 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5073 case HDLC_ENCODING_BIPHASE_MARK
:
5074 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5075 case HDLC_ENCODING_BIPHASE_LEVEL
:
5076 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5080 usc_OutReg( info
, HCR
, RegValue
);
5083 /* Channel Control/status Register (CCSR)
5085 * <15> X RCC FIFO Overflow status (RO)
5086 * <14> X RCC FIFO Not Empty status (RO)
5087 * <13> 0 1 = Clear RCC FIFO (WO)
5088 * <12> X DPLL Sync (RW)
5089 * <11> X DPLL 2 Missed Clocks status (RO)
5090 * <10> X DPLL 1 Missed Clock status (RO)
5091 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5092 * <7> X SDLC Loop On status (RO)
5093 * <6> X SDLC Loop Send status (RO)
5094 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5095 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5096 * <1..0> 00 reserved
5098 * 0000 0000 0010 0000 = 0x0020
5101 usc_OutReg( info
, CCSR
, 0x1020 );
5104 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5105 usc_OutReg( info
, SICR
,
5106 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5110 /* enable Master Interrupt Enable bit (MIE) */
5111 usc_EnableMasterIrqBit( info
);
5113 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5114 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5116 /* arm RCC underflow interrupt */
5117 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5118 usc_EnableInterrupts(info
, MISC
);
5121 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5122 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5123 info
->mbre_bit
= BIT8
;
5124 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5126 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5127 /* Enable DMAEN (Port 7, Bit 14) */
5128 /* This connects the DMA request signal to the ISA bus */
5129 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5132 /* DMA Control Register (DCR)
5134 * <15..14> 10 Priority mode = Alternating Tx/Rx
5135 * 01 Rx has priority
5136 * 00 Tx has priority
5138 * <13> 1 Enable Priority Preempt per DCR<15..14>
5139 * (WARNING DCR<11..10> must be 00 when this is 1)
5140 * 0 Choose activate channel per DCR<11..10>
5142 * <12> 0 Little Endian for Array/List
5143 * <11..10> 00 Both Channels can use each bus grant
5144 * <9..6> 0000 reserved
5145 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5146 * <4> 0 1 = drive D/C and S/D pins
5147 * <3> 1 1 = Add one wait state to all DMA cycles.
5148 * <2> 0 1 = Strobe /UAS on every transfer.
5149 * <1..0> 11 Addr incrementing only affects LS24 bits
5151 * 0110 0000 0000 1011 = 0x600b
5154 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5155 /* PCI adapter does not need DMA wait state */
5156 usc_OutDmaReg( info
, DCR
, 0xa00b );
5159 usc_OutDmaReg( info
, DCR
, 0x800b );
5162 /* Receive DMA mode Register (RDMR)
5164 * <15..14> 11 DMA mode = Linked List Buffer mode
5165 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5166 * <12> 1 Clear count of List Entry after fetching
5167 * <11..10> 00 Address mode = Increment
5168 * <9> 1 Terminate Buffer on RxBound
5169 * <8> 0 Bus Width = 16bits
5170 * <7..0> ? status Bits (write as 0s)
5172 * 1111 0010 0000 0000 = 0xf200
5175 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5178 /* Transmit DMA mode Register (TDMR)
5180 * <15..14> 11 DMA mode = Linked List Buffer mode
5181 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5182 * <12> 1 Clear count of List Entry after fetching
5183 * <11..10> 00 Address mode = Increment
5184 * <9> 1 Terminate Buffer on end of frame
5185 * <8> 0 Bus Width = 16bits
5186 * <7..0> ? status Bits (Read Only so write as 0)
5188 * 1111 0010 0000 0000 = 0xf200
5191 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5194 /* DMA Interrupt Control Register (DICR)
5196 * <15> 1 DMA Interrupt Enable
5197 * <14> 0 1 = Disable IEO from USC
5198 * <13> 0 1 = Don't provide vector during IntAck
5199 * <12> 1 1 = Include status in Vector
5200 * <10..2> 0 reserved, Must be 0s
5201 * <1> 0 1 = Rx DMA Interrupt Enabled
5202 * <0> 0 1 = Tx DMA Interrupt Enabled
5204 * 1001 0000 0000 0000 = 0x9000
5207 usc_OutDmaReg( info
, DICR
, 0x9000 );
5209 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5210 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5211 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5213 /* Channel Control Register (CCR)
5215 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5216 * <13> 0 Trigger Tx on SW Command Disabled
5217 * <12> 0 Flag Preamble Disabled
5218 * <11..10> 00 Preamble Length
5219 * <9..8> 00 Preamble Pattern
5220 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5221 * <5> 0 Trigger Rx on SW Command Disabled
5224 * 1000 0000 1000 0000 = 0x8080
5229 switch ( info
->params
.preamble_length
) {
5230 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5231 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5232 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5235 switch ( info
->params
.preamble
) {
5236 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5237 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5238 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5239 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5242 usc_OutReg( info
, CCR
, RegValue
);
5246 * Burst/Dwell Control Register
5248 * <15..8> 0x20 Maximum number of transfers per bus grant
5249 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5252 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5253 /* don't limit bus occupancy on PCI adapter */
5254 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5257 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5259 usc_stop_transmitter(info
);
5260 usc_stop_receiver(info
);
5262 } /* end of usc_set_sdlc_mode() */
5264 /* usc_enable_loopback()
5266 * Set the 16C32 for internal loopback mode.
5267 * The TxCLK and RxCLK signals are generated from the BRG0 and
5268 * the TxD is looped back to the RxD internally.
5270 * Arguments: info pointer to device instance data
5271 * enable 1 = enable loopback, 0 = disable
5272 * Return Value: None
5274 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5277 /* blank external TXD output */
5278 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5280 /* Clock mode Control Register (CMCR)
5282 * <15..14> 00 counter 1 Disabled
5283 * <13..12> 00 counter 0 Disabled
5284 * <11..10> 11 BRG1 Input is TxC Pin
5285 * <9..8> 11 BRG0 Input is TxC Pin
5286 * <7..6> 01 DPLL Input is BRG1 Output
5287 * <5..3> 100 TxCLK comes from BRG0
5288 * <2..0> 100 RxCLK comes from BRG0
5290 * 0000 1111 0110 0100 = 0x0f64
5293 usc_OutReg( info
, CMCR
, 0x0f64 );
5295 /* Write 16-bit Time Constant for BRG0 */
5296 /* use clock speed if available, otherwise use 8 for diagnostics */
5297 if (info
->params
.clock_speed
) {
5298 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5299 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5301 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5303 usc_OutReg(info
, TC0R
, (u16
)8);
5305 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5306 mode = Continuous Set Bit 0 to enable BRG0. */
5307 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5309 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5310 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5312 /* set Internal Data loopback mode */
5313 info
->loopback_bits
= 0x300;
5314 outw( 0x0300, info
->io_base
+ CCAR
);
5316 /* enable external TXD output */
5317 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5319 /* clear Internal Data loopback mode */
5320 info
->loopback_bits
= 0;
5321 outw( 0,info
->io_base
+ CCAR
);
5324 } /* end of usc_enable_loopback() */
5326 /* usc_enable_aux_clock()
5328 * Enabled the AUX clock output at the specified frequency.
5332 * info pointer to device extension
5333 * data_rate data rate of clock in bits per second
5334 * A data rate of 0 disables the AUX clock.
5336 * Return Value: None
5338 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5344 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5345 XtalSpeed
= 11059200;
5347 XtalSpeed
= 14745600;
5350 /* Tc = (Xtal/Speed) - 1 */
5351 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5352 /* then rounding up gives a more precise time constant. Instead */
5353 /* of rounding up and then subtracting 1 we just don't subtract */
5354 /* the one in this case. */
5357 Tc
= (u16
)(XtalSpeed
/data_rate
);
5358 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5361 /* Write 16-bit Time Constant for BRG0 */
5362 usc_OutReg( info
, TC0R
, Tc
);
5365 * Hardware Configuration Register (HCR)
5366 * Clear Bit 1, BRG0 mode = Continuous
5367 * Set Bit 0 to enable BRG0.
5370 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5372 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5373 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5375 /* data rate == 0 so turn off BRG0 */
5376 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5379 } /* end of usc_enable_aux_clock() */
5383 * usc_process_rxoverrun_sync()
5385 * This function processes a receive overrun by resetting the
5386 * receive DMA buffers and issuing a Purge Rx FIFO command
5387 * to allow the receiver to continue receiving.
5391 * info pointer to device extension
5393 * Return Value: None
5395 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5399 int frame_start_index
;
5400 bool start_of_frame_found
= false;
5401 bool end_of_frame_found
= false;
5402 bool reprogram_dma
= false;
5404 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5407 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5408 usc_RCmd( info
, RCmd_EnterHuntmode
);
5409 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5411 /* CurrentRxBuffer points to the 1st buffer of the next */
5412 /* possibly available receive frame. */
5414 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5416 /* Search for an unfinished string of buffers. This means */
5417 /* that a receive frame started (at least one buffer with */
5418 /* count set to zero) but there is no terminiting buffer */
5419 /* (status set to non-zero). */
5421 while( !buffer_list
[end_index
].count
)
5423 /* Count field has been reset to zero by 16C32. */
5424 /* This buffer is currently in use. */
5426 if ( !start_of_frame_found
)
5428 start_of_frame_found
= true;
5429 frame_start_index
= end_index
;
5430 end_of_frame_found
= false;
5433 if ( buffer_list
[end_index
].status
)
5435 /* Status field has been set by 16C32. */
5436 /* This is the last buffer of a received frame. */
5438 /* We want to leave the buffers for this frame intact. */
5439 /* Move on to next possible frame. */
5441 start_of_frame_found
= false;
5442 end_of_frame_found
= true;
5445 /* advance to next buffer entry in linked list */
5447 if ( end_index
== info
->rx_buffer_count
)
5450 if ( start_index
== end_index
)
5452 /* The entire list has been searched with all Counts == 0 and */
5453 /* all Status == 0. The receive buffers are */
5454 /* completely screwed, reset all receive buffers! */
5455 mgsl_reset_rx_dma_buffers( info
);
5456 frame_start_index
= 0;
5457 start_of_frame_found
= false;
5458 reprogram_dma
= true;
5463 if ( start_of_frame_found
&& !end_of_frame_found
)
5465 /* There is an unfinished string of receive DMA buffers */
5466 /* as a result of the receiver overrun. */
5468 /* Reset the buffers for the unfinished frame */
5469 /* and reprogram the receive DMA controller to start */
5470 /* at the 1st buffer of unfinished frame. */
5472 start_index
= frame_start_index
;
5476 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5478 /* Adjust index for wrap around. */
5479 if ( start_index
== info
->rx_buffer_count
)
5482 } while( start_index
!= end_index
);
5484 reprogram_dma
= true;
5487 if ( reprogram_dma
)
5489 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5490 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5491 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5493 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5495 /* This empties the receive FIFO and loads the RCC with RCLR */
5496 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5498 /* program 16C32 with physical address of 1st DMA buffer entry */
5499 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5500 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5501 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5503 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5504 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5505 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5507 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5508 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5510 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5511 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5512 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5513 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5514 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5516 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5520 /* This empties the receive FIFO and loads the RCC with RCLR */
5521 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5522 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5525 } /* end of usc_process_rxoverrun_sync() */
5527 /* usc_stop_receiver()
5529 * Disable USC receiver
5531 * Arguments: info pointer to device instance data
5532 * Return Value: None
5534 static void usc_stop_receiver( struct mgsl_struct
*info
)
5536 if (debug_level
>= DEBUG_LEVEL_ISR
)
5537 printk("%s(%d):usc_stop_receiver(%s)\n",
5538 __FILE__
,__LINE__
, info
->device_name
);
5540 /* Disable receive DMA channel. */
5541 /* This also disables receive DMA channel interrupts */
5542 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5544 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5545 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5546 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5548 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5550 /* This empties the receive FIFO and loads the RCC with RCLR */
5551 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5552 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5554 info
->rx_enabled
= false;
5555 info
->rx_overflow
= false;
5556 info
->rx_rcc_underrun
= false;
5558 } /* end of stop_receiver() */
5560 /* usc_start_receiver()
5562 * Enable the USC receiver
5564 * Arguments: info pointer to device instance data
5565 * Return Value: None
5567 static void usc_start_receiver( struct mgsl_struct
*info
)
5571 if (debug_level
>= DEBUG_LEVEL_ISR
)
5572 printk("%s(%d):usc_start_receiver(%s)\n",
5573 __FILE__
,__LINE__
, info
->device_name
);
5575 mgsl_reset_rx_dma_buffers( info
);
5576 usc_stop_receiver( info
);
5578 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5579 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5581 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5582 info
->params
.mode
== MGSL_MODE_RAW
) {
5583 /* DMA mode Transfers */
5584 /* Program the DMA controller. */
5585 /* Enable the DMA controller end of buffer interrupt. */
5587 /* program 16C32 with physical address of 1st DMA buffer entry */
5588 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5589 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5590 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5592 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5593 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5594 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5596 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5597 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5599 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5600 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5601 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5602 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5603 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5605 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5607 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5608 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5609 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5611 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5612 usc_RCmd( info
, RCmd_EnterHuntmode
);
5614 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5617 usc_OutReg( info
, CCSR
, 0x1020 );
5619 info
->rx_enabled
= true;
5621 } /* end of usc_start_receiver() */
5623 /* usc_start_transmitter()
5625 * Enable the USC transmitter and send a transmit frame if
5626 * one is loaded in the DMA buffers.
5628 * Arguments: info pointer to device instance data
5629 * Return Value: None
5631 static void usc_start_transmitter( struct mgsl_struct
*info
)
5634 unsigned int FrameSize
;
5636 if (debug_level
>= DEBUG_LEVEL_ISR
)
5637 printk("%s(%d):usc_start_transmitter(%s)\n",
5638 __FILE__
,__LINE__
, info
->device_name
);
5640 if ( info
->xmit_cnt
) {
5642 /* If auto RTS enabled and RTS is inactive, then assert */
5643 /* RTS and set a flag indicating that the driver should */
5644 /* negate RTS when the transmission completes. */
5646 info
->drop_rts_on_tx_done
= false;
5648 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5649 usc_get_serial_signals( info
);
5650 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5651 info
->serial_signals
|= SerialSignal_RTS
;
5652 usc_set_serial_signals( info
);
5653 info
->drop_rts_on_tx_done
= true;
5658 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5659 if ( !info
->tx_active
) {
5660 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5661 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5662 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5663 usc_load_txfifo(info
);
5666 /* Disable transmit DMA controller while programming. */
5667 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5669 /* Transmit DMA buffer is loaded, so program USC */
5670 /* to send the frame contained in the buffers. */
5672 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5674 /* if operating in Raw sync mode, reset the rcc component
5675 * of the tx dma buffer entry, otherwise, the serial controller
5676 * will send a closing sync char after this count.
5678 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5679 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5681 /* Program the Transmit Character Length Register (TCLR) */
5682 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5683 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5685 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5687 /* Program the address of the 1st DMA Buffer Entry in linked list */
5688 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5689 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5690 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5692 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5693 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5694 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5696 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5697 info
->num_tx_dma_buffers
> 1 ) {
5698 /* When running external sync mode, attempt to 'stream' transmit */
5699 /* by filling tx dma buffers as they become available. To do this */
5700 /* we need to enable Tx DMA EOB Status interrupts : */
5702 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5703 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5705 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5706 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5709 /* Initialize Transmit DMA Channel */
5710 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5712 usc_TCmd( info
, TCmd_SendFrame
);
5714 mod_timer(&info
->tx_timer
, jiffies
+
5715 msecs_to_jiffies(5000));
5717 info
->tx_active
= true;
5720 if ( !info
->tx_enabled
) {
5721 info
->tx_enabled
= true;
5722 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5723 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5725 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5728 } /* end of usc_start_transmitter() */
5730 /* usc_stop_transmitter()
5732 * Stops the transmitter and DMA
5734 * Arguments: info pointer to device isntance data
5735 * Return Value: None
5737 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5739 if (debug_level
>= DEBUG_LEVEL_ISR
)
5740 printk("%s(%d):usc_stop_transmitter(%s)\n",
5741 __FILE__
,__LINE__
, info
->device_name
);
5743 del_timer(&info
->tx_timer
);
5745 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5746 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5747 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5749 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5750 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5751 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5753 info
->tx_enabled
= false;
5754 info
->tx_active
= false;
5756 } /* end of usc_stop_transmitter() */
5758 /* usc_load_txfifo()
5760 * Fill the transmit FIFO until the FIFO is full or
5761 * there is no more data to load.
5763 * Arguments: info pointer to device extension (instance data)
5764 * Return Value: None
5766 static void usc_load_txfifo( struct mgsl_struct
*info
)
5771 if ( !info
->xmit_cnt
&& !info
->x_char
)
5774 /* Select transmit FIFO status readback in TICR */
5775 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5777 /* load the Transmit FIFO until FIFOs full or all data sent */
5779 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5780 /* there is more space in the transmit FIFO and */
5781 /* there is more data in transmit buffer */
5783 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5784 /* write a 16-bit word from transmit buffer to 16C32 */
5786 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5787 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5788 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5789 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5791 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5793 info
->xmit_cnt
-= 2;
5794 info
->icount
.tx
+= 2;
5796 /* only 1 byte left to transmit or 1 FIFO slot left */
5798 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5799 info
->io_base
+ CCAR
);
5802 /* transmit pending high priority char */
5803 outw( info
->x_char
,info
->io_base
+ CCAR
);
5806 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5807 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5814 } /* end of usc_load_txfifo() */
5818 * Reset the adapter to a known state and prepare it for further use.
5820 * Arguments: info pointer to device instance data
5821 * Return Value: None
5823 static void usc_reset( struct mgsl_struct
*info
)
5825 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5829 /* Set BIT30 of Misc Control Register */
5830 /* (Local Control Register 0x50) to force reset of USC. */
5832 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5833 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5835 info
->misc_ctrl_value
|= BIT30
;
5836 *MiscCtrl
= info
->misc_ctrl_value
;
5839 * Force at least 170ns delay before clearing
5840 * reset bit. Each read from LCR takes at least
5841 * 30ns so 10 times for 300ns to be safe.
5844 readval
= *MiscCtrl
;
5846 info
->misc_ctrl_value
&= ~BIT30
;
5847 *MiscCtrl
= info
->misc_ctrl_value
;
5849 *LCR0BRDR
= BUS_DESCRIPTOR(
5850 1, // Write Strobe Hold (0-3)
5851 2, // Write Strobe Delay (0-3)
5852 2, // Read Strobe Delay (0-3)
5853 0, // NWDD (Write data-data) (0-3)
5854 4, // NWAD (Write Addr-data) (0-31)
5855 0, // NXDA (Read/Write Data-Addr) (0-3)
5856 0, // NRDD (Read Data-Data) (0-3)
5857 5 // NRAD (Read Addr-Data) (0-31)
5861 outb( 0,info
->io_base
+ 8 );
5865 info
->loopback_bits
= 0;
5866 info
->usc_idle_mode
= 0;
5869 * Program the Bus Configuration Register (BCR)
5871 * <15> 0 Don't use separate address
5872 * <14..6> 0 reserved
5873 * <5..4> 00 IAckmode = Default, don't care
5874 * <3> 1 Bus Request Totem Pole output
5875 * <2> 1 Use 16 Bit data bus
5876 * <1> 0 IRQ Totem Pole output
5877 * <0> 0 Don't Shift Right Addr
5879 * 0000 0000 0000 1100 = 0x000c
5881 * By writing to io_base + SDPIN the Wait/Ack pin is
5882 * programmed to work as a Wait pin.
5885 outw( 0x000c,info
->io_base
+ SDPIN
);
5888 outw( 0,info
->io_base
);
5889 outw( 0,info
->io_base
+ CCAR
);
5891 /* select little endian byte ordering */
5892 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5895 /* Port Control Register (PCR)
5897 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5898 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5899 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5900 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5901 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5902 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5903 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5904 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5906 * 1111 0000 1111 0101 = 0xf0f5
5909 usc_OutReg( info
, PCR
, 0xf0f5 );
5913 * Input/Output Control Register
5915 * <15..14> 00 CTS is active low input
5916 * <13..12> 00 DCD is active low input
5917 * <11..10> 00 TxREQ pin is input (DSR)
5918 * <9..8> 00 RxREQ pin is input (RI)
5919 * <7..6> 00 TxD is output (Transmit Data)
5920 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5921 * <2..0> 100 RxC is Output (drive with BRG0)
5923 * 0000 0000 0000 0100 = 0x0004
5926 usc_OutReg( info
, IOCR
, 0x0004 );
5928 } /* end of usc_reset() */
5930 /* usc_set_async_mode()
5932 * Program adapter for asynchronous communications.
5934 * Arguments: info pointer to device instance data
5935 * Return Value: None
5937 static void usc_set_async_mode( struct mgsl_struct
*info
)
5941 /* disable interrupts while programming USC */
5942 usc_DisableMasterIrqBit( info
);
5944 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5945 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5947 usc_loopback_frame( info
);
5949 /* Channel mode Register (CMR)
5951 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5952 * <13..12> 00 00 = 16X Clock
5953 * <11..8> 0000 Transmitter mode = Asynchronous
5954 * <7..6> 00 reserved?
5955 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5956 * <3..0> 0000 Receiver mode = Asynchronous
5958 * 0000 0000 0000 0000 = 0x0
5962 if ( info
->params
.stop_bits
!= 1 )
5964 usc_OutReg( info
, CMR
, RegValue
);
5967 /* Receiver mode Register (RMR)
5969 * <15..13> 000 encoding = None
5970 * <12..08> 00000 reserved (Sync Only)
5971 * <7..6> 00 Even parity
5972 * <5> 0 parity disabled
5973 * <4..2> 000 Receive Char Length = 8 bits
5974 * <1..0> 00 Disable Receiver
5976 * 0000 0000 0000 0000 = 0x0
5981 if ( info
->params
.data_bits
!= 8 )
5982 RegValue
|= BIT4
+BIT3
+BIT2
;
5984 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5986 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5990 usc_OutReg( info
, RMR
, RegValue
);
5993 /* Set IRQ trigger level */
5995 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5998 /* Receive Interrupt Control Register (RICR)
6000 * <15..8> ? RxFIFO IRQ Request Level
6002 * Note: For async mode the receive FIFO level must be set
6003 * to 0 to avoid the situation where the FIFO contains fewer bytes
6004 * than the trigger level and no more data is expected.
6006 * <7> 0 Exited Hunt IA (Interrupt Arm)
6007 * <6> 0 Idle Received IA
6008 * <5> 0 Break/Abort IA
6010 * <3> 0 Queued status reflects oldest byte in FIFO
6012 * <1> 0 Rx Overrun IA
6013 * <0> 0 Select TC0 value for readback
6015 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6018 usc_OutReg( info
, RICR
, 0x0000 );
6020 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
6021 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
6024 /* Transmit mode Register (TMR)
6026 * <15..13> 000 encoding = None
6027 * <12..08> 00000 reserved (Sync Only)
6028 * <7..6> 00 Transmit parity Even
6029 * <5> 0 Transmit parity Disabled
6030 * <4..2> 000 Tx Char Length = 8 bits
6031 * <1..0> 00 Disable Transmitter
6033 * 0000 0000 0000 0000 = 0x0
6038 if ( info
->params
.data_bits
!= 8 )
6039 RegValue
|= BIT4
+BIT3
+BIT2
;
6041 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6043 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6047 usc_OutReg( info
, TMR
, RegValue
);
6049 usc_set_txidle( info
);
6052 /* Set IRQ trigger level */
6054 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6057 /* Transmit Interrupt Control Register (TICR)
6059 * <15..8> ? Transmit FIFO IRQ Level
6060 * <7> 0 Present IA (Interrupt Arm)
6061 * <6> 1 Idle Sent IA
6062 * <5> 0 Abort Sent IA
6063 * <4> 0 EOF/EOM Sent IA
6065 * <2> 0 1 = Wait for SW Trigger to Start Frame
6066 * <1> 0 Tx Underrun IA
6067 * <0> 0 TC0 constant on read back
6069 * 0000 0000 0100 0000 = 0x0040
6072 usc_OutReg( info
, TICR
, 0x1f40 );
6074 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6075 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6077 usc_enable_async_clock( info
, info
->params
.data_rate
);
6080 /* Channel Control/status Register (CCSR)
6082 * <15> X RCC FIFO Overflow status (RO)
6083 * <14> X RCC FIFO Not Empty status (RO)
6084 * <13> 0 1 = Clear RCC FIFO (WO)
6085 * <12> X DPLL in Sync status (RO)
6086 * <11> X DPLL 2 Missed Clocks status (RO)
6087 * <10> X DPLL 1 Missed Clock status (RO)
6088 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6089 * <7> X SDLC Loop On status (RO)
6090 * <6> X SDLC Loop Send status (RO)
6091 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6092 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6093 * <1..0> 00 reserved
6095 * 0000 0000 0010 0000 = 0x0020
6098 usc_OutReg( info
, CCSR
, 0x0020 );
6100 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6101 RECEIVE_DATA
+ RECEIVE_STATUS
);
6103 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6104 RECEIVE_DATA
+ RECEIVE_STATUS
);
6106 usc_EnableMasterIrqBit( info
);
6108 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6109 /* Enable INTEN (Port 6, Bit12) */
6110 /* This connects the IRQ request signal to the ISA bus */
6111 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6114 if (info
->params
.loopback
) {
6115 info
->loopback_bits
= 0x300;
6116 outw(0x0300, info
->io_base
+ CCAR
);
6119 } /* end of usc_set_async_mode() */
6121 /* usc_loopback_frame()
6123 * Loop back a small (2 byte) dummy SDLC frame.
6124 * Interrupts and DMA are NOT used. The purpose of this is to
6125 * clear any 'stale' status info left over from running in async mode.
6127 * The 16C32 shows the strange behaviour of marking the 1st
6128 * received SDLC frame with a CRC error even when there is no
6129 * CRC error. To get around this a small dummy from of 2 bytes
6130 * is looped back when switching from async to sync mode.
6132 * Arguments: info pointer to device instance data
6133 * Return Value: None
6135 static void usc_loopback_frame( struct mgsl_struct
*info
)
6138 unsigned long oldmode
= info
->params
.mode
;
6140 info
->params
.mode
= MGSL_MODE_HDLC
;
6142 usc_DisableMasterIrqBit( info
);
6144 usc_set_sdlc_mode( info
);
6145 usc_enable_loopback( info
, 1 );
6147 /* Write 16-bit Time Constant for BRG0 */
6148 usc_OutReg( info
, TC0R
, 0 );
6150 /* Channel Control Register (CCR)
6152 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6153 * <13> 0 Trigger Tx on SW Command Disabled
6154 * <12> 0 Flag Preamble Disabled
6155 * <11..10> 00 Preamble Length = 8-Bits
6156 * <9..8> 01 Preamble Pattern = flags
6157 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6158 * <5> 0 Trigger Rx on SW Command Disabled
6161 * 0000 0001 0000 0000 = 0x0100
6164 usc_OutReg( info
, CCR
, 0x0100 );
6166 /* SETUP RECEIVER */
6167 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6168 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6170 /* SETUP TRANSMITTER */
6171 /* Program the Transmit Character Length Register (TCLR) */
6172 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6173 usc_OutReg( info
, TCLR
, 2 );
6174 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6176 /* unlatch Tx status bits, and start transmit channel. */
6177 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6178 outw(0,info
->io_base
+ DATAREG
);
6180 /* ENABLE TRANSMITTER */
6181 usc_TCmd( info
, TCmd_SendFrame
);
6182 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6184 /* WAIT FOR RECEIVE COMPLETE */
6185 for (i
=0 ; i
<1000 ; i
++)
6186 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6189 /* clear Internal Data loopback mode */
6190 usc_enable_loopback(info
, 0);
6192 usc_EnableMasterIrqBit(info
);
6194 info
->params
.mode
= oldmode
;
6196 } /* end of usc_loopback_frame() */
6198 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6200 * Arguments: info pointer to adapter info structure
6201 * Return Value: None
6203 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6205 usc_loopback_frame( info
);
6206 usc_set_sdlc_mode( info
);
6208 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6209 /* Enable INTEN (Port 6, Bit12) */
6210 /* This connects the IRQ request signal to the ISA bus */
6211 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6214 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6216 if (info
->params
.loopback
)
6217 usc_enable_loopback(info
,1);
6219 } /* end of mgsl_set_sync_mode() */
6221 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6223 * Arguments: info pointer to device instance data
6224 * Return Value: None
6226 static void usc_set_txidle( struct mgsl_struct
*info
)
6228 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6230 /* Map API idle mode to USC register bits */
6232 switch( info
->idle_mode
){
6233 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6234 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6235 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6236 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6237 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6238 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6239 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6242 info
->usc_idle_mode
= usc_idle_mode
;
6243 //usc_OutReg(info, TCSR, usc_idle_mode);
6244 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6245 info
->tcsr_value
+= usc_idle_mode
;
6246 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6249 * if SyncLink WAN adapter is running in external sync mode, the
6250 * transmitter has been set to Monosync in order to try to mimic
6251 * a true raw outbound bit stream. Monosync still sends an open/close
6252 * sync char at the start/end of a frame. Try to match those sync
6253 * patterns to the idle mode set here
6255 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6256 unsigned char syncpat
= 0;
6257 switch( info
->idle_mode
) {
6258 case HDLC_TXIDLE_FLAGS
:
6261 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6264 case HDLC_TXIDLE_ZEROS
:
6265 case HDLC_TXIDLE_SPACE
:
6268 case HDLC_TXIDLE_ONES
:
6269 case HDLC_TXIDLE_MARK
:
6272 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6277 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6280 } /* end of usc_set_txidle() */
6282 /* usc_get_serial_signals()
6284 * Query the adapter for the state of the V24 status (input) signals.
6286 * Arguments: info pointer to device instance data
6287 * Return Value: None
6289 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6293 /* clear all serial signals except DTR and RTS */
6294 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6296 /* Read the Misc Interrupt status Register (MISR) to get */
6297 /* the V24 status signals. */
6299 status
= usc_InReg( info
, MISR
);
6301 /* set serial signal bits to reflect MISR */
6303 if ( status
& MISCSTATUS_CTS
)
6304 info
->serial_signals
|= SerialSignal_CTS
;
6306 if ( status
& MISCSTATUS_DCD
)
6307 info
->serial_signals
|= SerialSignal_DCD
;
6309 if ( status
& MISCSTATUS_RI
)
6310 info
->serial_signals
|= SerialSignal_RI
;
6312 if ( status
& MISCSTATUS_DSR
)
6313 info
->serial_signals
|= SerialSignal_DSR
;
6315 } /* end of usc_get_serial_signals() */
6317 /* usc_set_serial_signals()
6319 * Set the state of DTR and RTS based on contents of
6320 * serial_signals member of device extension.
6322 * Arguments: info pointer to device instance data
6323 * Return Value: None
6325 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6328 unsigned char V24Out
= info
->serial_signals
;
6330 /* get the current value of the Port Control Register (PCR) */
6332 Control
= usc_InReg( info
, PCR
);
6334 if ( V24Out
& SerialSignal_RTS
)
6339 if ( V24Out
& SerialSignal_DTR
)
6344 usc_OutReg( info
, PCR
, Control
);
6346 } /* end of usc_set_serial_signals() */
6348 /* usc_enable_async_clock()
6350 * Enable the async clock at the specified frequency.
6352 * Arguments: info pointer to device instance data
6353 * data_rate data rate of clock in bps
6354 * 0 disables the AUX clock.
6355 * Return Value: None
6357 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6361 * Clock mode Control Register (CMCR)
6363 * <15..14> 00 counter 1 Disabled
6364 * <13..12> 00 counter 0 Disabled
6365 * <11..10> 11 BRG1 Input is TxC Pin
6366 * <9..8> 11 BRG0 Input is TxC Pin
6367 * <7..6> 01 DPLL Input is BRG1 Output
6368 * <5..3> 100 TxCLK comes from BRG0
6369 * <2..0> 100 RxCLK comes from BRG0
6371 * 0000 1111 0110 0100 = 0x0f64
6374 usc_OutReg( info
, CMCR
, 0x0f64 );
6378 * Write 16-bit Time Constant for BRG0
6379 * Time Constant = (ClkSpeed / data_rate) - 1
6380 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6383 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6384 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6386 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6390 * Hardware Configuration Register (HCR)
6391 * Clear Bit 1, BRG0 mode = Continuous
6392 * Set Bit 0 to enable BRG0.
6395 usc_OutReg( info
, HCR
,
6396 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6399 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6401 usc_OutReg( info
, IOCR
,
6402 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6404 /* data rate == 0 so turn off BRG0 */
6405 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6408 } /* end of usc_enable_async_clock() */
6411 * Buffer Structures:
6413 * Normal memory access uses virtual addresses that can make discontiguous
6414 * physical memory pages appear to be contiguous in the virtual address
6415 * space (the processors memory mapping handles the conversions).
6417 * DMA transfers require physically contiguous memory. This is because
6418 * the DMA system controller and DMA bus masters deal with memory using
6419 * only physical addresses.
6421 * This causes a problem under Windows NT when large DMA buffers are
6422 * needed. Fragmentation of the nonpaged pool prevents allocations of
6423 * physically contiguous buffers larger than the PAGE_SIZE.
6425 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6426 * allows DMA transfers to physically discontiguous buffers. Information
6427 * about each data transfer buffer is contained in a memory structure
6428 * called a 'buffer entry'. A list of buffer entries is maintained
6429 * to track and control the use of the data transfer buffers.
6431 * To support this strategy we will allocate sufficient PAGE_SIZE
6432 * contiguous memory buffers to allow for the total required buffer
6435 * The 16C32 accesses the list of buffer entries using Bus Master
6436 * DMA. Control information is read from the buffer entries by the
6437 * 16C32 to control data transfers. status information is written to
6438 * the buffer entries by the 16C32 to indicate the status of completed
6441 * The CPU writes control information to the buffer entries to control
6442 * the 16C32 and reads status information from the buffer entries to
6443 * determine information about received and transmitted frames.
6445 * Because the CPU and 16C32 (adapter) both need simultaneous access
6446 * to the buffer entries, the buffer entry memory is allocated with
6447 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6448 * entry list to PAGE_SIZE.
6450 * The actual data buffers on the other hand will only be accessed
6451 * by the CPU or the adapter but not by both simultaneously. This allows
6452 * Scatter/Gather packet based DMA procedures for using physically
6453 * discontiguous pages.
6457 * mgsl_reset_tx_dma_buffers()
6459 * Set the count for all transmit buffers to 0 to indicate the
6460 * buffer is available for use and set the current buffer to the
6461 * first buffer. This effectively makes all buffers free and
6462 * discards any data in buffers.
6464 * Arguments: info pointer to device instance data
6465 * Return Value: None
6467 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6471 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6472 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6475 info
->current_tx_buffer
= 0;
6476 info
->start_tx_dma_buffer
= 0;
6477 info
->tx_dma_buffers_used
= 0;
6479 info
->get_tx_holding_index
= 0;
6480 info
->put_tx_holding_index
= 0;
6481 info
->tx_holding_count
= 0;
6483 } /* end of mgsl_reset_tx_dma_buffers() */
6486 * num_free_tx_dma_buffers()
6488 * returns the number of free tx dma buffers available
6490 * Arguments: info pointer to device instance data
6491 * Return Value: number of free tx dma buffers
6493 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6495 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6499 * mgsl_reset_rx_dma_buffers()
6501 * Set the count for all receive buffers to DMABUFFERSIZE
6502 * and set the current buffer to the first buffer. This effectively
6503 * makes all buffers free and discards any data in buffers.
6505 * Arguments: info pointer to device instance data
6506 * Return Value: None
6508 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6512 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6513 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6514 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6515 // info->rx_buffer_list[i].status = 0;
6518 info
->current_rx_buffer
= 0;
6520 } /* end of mgsl_reset_rx_dma_buffers() */
6523 * mgsl_free_rx_frame_buffers()
6525 * Free the receive buffers used by a received SDLC
6526 * frame such that the buffers can be reused.
6530 * info pointer to device instance data
6531 * StartIndex index of 1st receive buffer of frame
6532 * EndIndex index of last receive buffer of frame
6534 * Return Value: None
6536 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6539 DMABUFFERENTRY
*pBufEntry
;
6542 /* Starting with 1st buffer entry of the frame clear the status */
6543 /* field and set the count field to DMA Buffer Size. */
6548 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6550 if ( Index
== EndIndex
) {
6551 /* This is the last buffer of the frame! */
6555 /* reset current buffer for reuse */
6556 // pBufEntry->status = 0;
6557 // pBufEntry->count = DMABUFFERSIZE;
6558 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6560 /* advance to next buffer entry in linked list */
6562 if ( Index
== info
->rx_buffer_count
)
6566 /* set current buffer to next buffer after last buffer of frame */
6567 info
->current_rx_buffer
= Index
;
6569 } /* end of free_rx_frame_buffers() */
6571 /* mgsl_get_rx_frame()
6573 * This function attempts to return a received SDLC frame from the
6574 * receive DMA buffers. Only frames received without errors are returned.
6576 * Arguments: info pointer to device extension
6577 * Return Value: true if frame returned, otherwise false
6579 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6581 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6582 unsigned short status
;
6583 DMABUFFERENTRY
*pBufEntry
;
6584 unsigned int framesize
= 0;
6585 bool ReturnCode
= false;
6586 unsigned long flags
;
6587 struct tty_struct
*tty
= info
->port
.tty
;
6588 bool return_frame
= false;
6591 * current_rx_buffer points to the 1st buffer of the next available
6592 * receive frame. To find the last buffer of the frame look for
6593 * a non-zero status field in the buffer entries. (The status
6594 * field is set by the 16C32 after completing a receive frame.
6597 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6599 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6601 * If the count field of the buffer entry is non-zero then
6602 * this buffer has not been used. (The 16C32 clears the count
6603 * field when it starts using the buffer.) If an unused buffer
6604 * is encountered then there are no frames available.
6607 if ( info
->rx_buffer_list
[EndIndex
].count
)
6610 /* advance to next buffer entry in linked list */
6612 if ( EndIndex
== info
->rx_buffer_count
)
6615 /* if entire list searched then no frame available */
6616 if ( EndIndex
== StartIndex
) {
6617 /* If this occurs then something bad happened,
6618 * all buffers have been 'used' but none mark
6619 * the end of a frame. Reset buffers and receiver.
6622 if ( info
->rx_enabled
){
6623 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6624 usc_start_receiver(info
);
6625 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6632 /* check status of receive frame */
6634 status
= info
->rx_buffer_list
[EndIndex
].status
;
6636 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6637 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6638 if ( status
& RXSTATUS_SHORT_FRAME
)
6639 info
->icount
.rxshort
++;
6640 else if ( status
& RXSTATUS_ABORT
)
6641 info
->icount
.rxabort
++;
6642 else if ( status
& RXSTATUS_OVERRUN
)
6643 info
->icount
.rxover
++;
6645 info
->icount
.rxcrc
++;
6646 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6647 return_frame
= true;
6650 #if SYNCLINK_GENERIC_HDLC
6652 info
->netdev
->stats
.rx_errors
++;
6653 info
->netdev
->stats
.rx_frame_errors
++;
6657 return_frame
= true;
6659 if ( return_frame
) {
6660 /* receive frame has no errors, get frame size.
6661 * The frame size is the starting value of the RCC (which was
6662 * set to 0xffff) minus the ending value of the RCC (decremented
6663 * once for each receive character) minus 2 for the 16-bit CRC.
6666 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6668 /* adjust frame size for CRC if any */
6669 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6671 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6675 if ( debug_level
>= DEBUG_LEVEL_BH
)
6676 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6677 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6679 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6680 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6681 min_t(int, framesize
, DMABUFFERSIZE
),0);
6684 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6685 ((framesize
+1) > info
->max_frame_size
) ) ||
6686 (framesize
> info
->max_frame_size
) )
6687 info
->icount
.rxlong
++;
6689 /* copy dma buffer(s) to contiguous intermediate buffer */
6690 int copy_count
= framesize
;
6691 int index
= StartIndex
;
6692 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6694 if ( !(status
& RXSTATUS_CRC_ERROR
))
6695 info
->icount
.rxok
++;
6699 if ( copy_count
> DMABUFFERSIZE
)
6700 partial_count
= DMABUFFERSIZE
;
6702 partial_count
= copy_count
;
6704 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6705 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6706 ptmp
+= partial_count
;
6707 copy_count
-= partial_count
;
6709 if ( ++index
== info
->rx_buffer_count
)
6713 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6715 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6719 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6720 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6721 __FILE__
,__LINE__
,info
->device_name
,
6725 #if SYNCLINK_GENERIC_HDLC
6727 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6730 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6733 /* Free the buffers used by this frame. */
6734 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6740 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6741 /* The receiver needs to restarted because of
6742 * a receive overflow (buffer or FIFO). If the
6743 * receive buffers are now empty, then restart receiver.
6746 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6747 info
->rx_buffer_list
[EndIndex
].count
) {
6748 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6749 usc_start_receiver(info
);
6750 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6756 } /* end of mgsl_get_rx_frame() */
6758 /* mgsl_get_raw_rx_frame()
6760 * This function attempts to return a received frame from the
6761 * receive DMA buffers when running in external loop mode. In this mode,
6762 * we will return at most one DMABUFFERSIZE frame to the application.
6763 * The USC receiver is triggering off of DCD going active to start a new
6764 * frame, and DCD going inactive to terminate the frame (similar to
6765 * processing a closing flag character).
6767 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6768 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6769 * status field and the RCC field will indicate the length of the
6770 * entire received frame. We take this RCC field and get the modulus
6771 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6772 * last Rx DMA buffer and return that last portion of the frame.
6774 * Arguments: info pointer to device extension
6775 * Return Value: true if frame returned, otherwise false
6777 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6779 unsigned int CurrentIndex
, NextIndex
;
6780 unsigned short status
;
6781 DMABUFFERENTRY
*pBufEntry
;
6782 unsigned int framesize
= 0;
6783 bool ReturnCode
= false;
6784 unsigned long flags
;
6785 struct tty_struct
*tty
= info
->port
.tty
;
6788 * current_rx_buffer points to the 1st buffer of the next available
6789 * receive frame. The status field is set by the 16C32 after
6790 * completing a receive frame. If the status field of this buffer
6791 * is zero, either the USC is still filling this buffer or this
6792 * is one of a series of buffers making up a received frame.
6794 * If the count field of this buffer is zero, the USC is either
6795 * using this buffer or has used this buffer. Look at the count
6796 * field of the next buffer. If that next buffer's count is
6797 * non-zero, the USC is still actively using the current buffer.
6798 * Otherwise, if the next buffer's count field is zero, the
6799 * current buffer is complete and the USC is using the next
6802 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6804 if ( NextIndex
== info
->rx_buffer_count
)
6807 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6808 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6809 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6811 * Either the status field of this dma buffer is non-zero
6812 * (indicating the last buffer of a receive frame) or the next
6813 * buffer is marked as in use -- implying this buffer is complete
6814 * and an intermediate buffer for this received frame.
6817 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6819 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6820 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6821 if ( status
& RXSTATUS_SHORT_FRAME
)
6822 info
->icount
.rxshort
++;
6823 else if ( status
& RXSTATUS_ABORT
)
6824 info
->icount
.rxabort
++;
6825 else if ( status
& RXSTATUS_OVERRUN
)
6826 info
->icount
.rxover
++;
6828 info
->icount
.rxcrc
++;
6832 * A receive frame is available, get frame size and status.
6834 * The frame size is the starting value of the RCC (which was
6835 * set to 0xffff) minus the ending value of the RCC (decremented
6836 * once for each receive character) minus 2 or 4 for the 16-bit
6839 * If the status field is zero, this is an intermediate buffer.
6842 * If the DMA Buffer Entry's Status field is non-zero, the
6843 * receive operation completed normally (ie: DCD dropped). The
6844 * RCC field is valid and holds the received frame size.
6845 * It is possible that the RCC field will be zero on a DMA buffer
6846 * entry with a non-zero status. This can occur if the total
6847 * frame size (number of bytes between the time DCD goes active
6848 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6849 * case the 16C32 has underrun on the RCC count and appears to
6850 * stop updating this counter to let us know the actual received
6851 * frame size. If this happens (non-zero status and zero RCC),
6852 * simply return the entire RxDMA Buffer
6856 * In the event that the final RxDMA Buffer is
6857 * terminated with a non-zero status and the RCC
6858 * field is zero, we interpret this as the RCC
6859 * having underflowed (received frame > 65535 bytes).
6861 * Signal the event to the user by passing back
6862 * a status of RxStatus_CrcError returning the full
6863 * buffer and let the app figure out what data is
6866 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6867 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6869 framesize
= DMABUFFERSIZE
;
6872 framesize
= DMABUFFERSIZE
;
6875 if ( framesize
> DMABUFFERSIZE
) {
6877 * if running in raw sync mode, ISR handler for
6878 * End Of Buffer events terminates all buffers at 4K.
6879 * If this frame size is said to be >4K, get the
6880 * actual number of bytes of the frame in this buffer.
6882 framesize
= framesize
% DMABUFFERSIZE
;
6886 if ( debug_level
>= DEBUG_LEVEL_BH
)
6887 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6888 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6890 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6891 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6892 min_t(int, framesize
, DMABUFFERSIZE
),0);
6895 /* copy dma buffer(s) to contiguous intermediate buffer */
6896 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6898 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6899 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6900 info
->icount
.rxok
++;
6902 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6905 /* Free the buffers used by this frame. */
6906 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6912 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6913 /* The receiver needs to restarted because of
6914 * a receive overflow (buffer or FIFO). If the
6915 * receive buffers are now empty, then restart receiver.
6918 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6919 info
->rx_buffer_list
[CurrentIndex
].count
) {
6920 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6921 usc_start_receiver(info
);
6922 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6928 } /* end of mgsl_get_raw_rx_frame() */
6930 /* mgsl_load_tx_dma_buffer()
6932 * Load the transmit DMA buffer with the specified data.
6936 * info pointer to device extension
6937 * Buffer pointer to buffer containing frame to load
6938 * BufferSize size in bytes of frame in Buffer
6940 * Return Value: None
6942 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6943 const char *Buffer
, unsigned int BufferSize
)
6945 unsigned short Copycount
;
6947 DMABUFFERENTRY
*pBufEntry
;
6949 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6950 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6952 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6953 /* set CMR:13 to start transmit when
6954 * next GoAhead (abort) is received
6956 info
->cmr_value
|= BIT13
;
6959 /* begin loading the frame in the next available tx dma
6960 * buffer, remember it's starting location for setting
6961 * up tx dma operation
6963 i
= info
->current_tx_buffer
;
6964 info
->start_tx_dma_buffer
= i
;
6966 /* Setup the status and RCC (Frame Size) fields of the 1st */
6967 /* buffer entry in the transmit DMA buffer list. */
6969 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6970 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6971 info
->tx_buffer_list
[i
].count
= BufferSize
;
6973 /* Copy frame data from 1st source buffer to the DMA buffers. */
6974 /* The frame data may span multiple DMA buffers. */
6976 while( BufferSize
){
6977 /* Get a pointer to next DMA buffer entry. */
6978 pBufEntry
= &info
->tx_buffer_list
[i
++];
6980 if ( i
== info
->tx_buffer_count
)
6983 /* Calculate the number of bytes that can be copied from */
6984 /* the source buffer to this DMA buffer. */
6985 if ( BufferSize
> DMABUFFERSIZE
)
6986 Copycount
= DMABUFFERSIZE
;
6988 Copycount
= BufferSize
;
6990 /* Actually copy data from source buffer to DMA buffer. */
6991 /* Also set the data count for this individual DMA buffer. */
6992 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6993 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6995 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6997 pBufEntry
->count
= Copycount
;
6999 /* Advance source pointer and reduce remaining data count. */
7000 Buffer
+= Copycount
;
7001 BufferSize
-= Copycount
;
7003 ++info
->tx_dma_buffers_used
;
7006 /* remember next available tx dma buffer */
7007 info
->current_tx_buffer
= i
;
7009 } /* end of mgsl_load_tx_dma_buffer() */
7012 * mgsl_register_test()
7014 * Performs a register test of the 16C32.
7016 * Arguments: info pointer to device instance data
7017 * Return Value: true if test passed, otherwise false
7019 static bool mgsl_register_test( struct mgsl_struct
*info
)
7021 static unsigned short BitPatterns
[] =
7022 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7023 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
7026 unsigned long flags
;
7028 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7031 /* Verify the reset state of some registers. */
7033 if ( (usc_InReg( info
, SICR
) != 0) ||
7034 (usc_InReg( info
, IVR
) != 0) ||
7035 (usc_InDmaReg( info
, DIVR
) != 0) ){
7040 /* Write bit patterns to various registers but do it out of */
7041 /* sync, then read back and verify values. */
7043 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7044 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
7045 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
7046 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
7047 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
7048 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
7049 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
7051 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
7052 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
7053 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7054 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7055 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7056 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7064 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7068 } /* end of mgsl_register_test() */
7070 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7072 * Arguments: info pointer to device instance data
7073 * Return Value: true if test passed, otherwise false
7075 static bool mgsl_irq_test( struct mgsl_struct
*info
)
7077 unsigned long EndTime
;
7078 unsigned long flags
;
7080 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7084 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7085 * The ISR sets irq_occurred to true.
7088 info
->irq_occurred
= false;
7090 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7091 /* Enable INTEN (Port 6, Bit12) */
7092 /* This connects the IRQ request signal to the ISA bus */
7093 /* on the ISA adapter. This has no effect for the PCI adapter */
7094 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7096 usc_EnableMasterIrqBit(info
);
7097 usc_EnableInterrupts(info
, IO_PIN
);
7098 usc_ClearIrqPendingBits(info
, IO_PIN
);
7100 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7101 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7103 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7106 while( EndTime
-- && !info
->irq_occurred
) {
7107 msleep_interruptible(10);
7110 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7112 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7114 return info
->irq_occurred
;
7116 } /* end of mgsl_irq_test() */
7120 * Perform a DMA test of the 16C32. A small frame is
7121 * transmitted via DMA from a transmit buffer to a receive buffer
7122 * using single buffer DMA mode.
7124 * Arguments: info pointer to device instance data
7125 * Return Value: true if test passed, otherwise false
7127 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7129 unsigned short FifoLevel
;
7130 unsigned long phys_addr
;
7131 unsigned int FrameSize
;
7135 unsigned short status
=0;
7136 unsigned long EndTime
;
7137 unsigned long flags
;
7138 MGSL_PARAMS tmp_params
;
7140 /* save current port options */
7141 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7142 /* load default port options */
7143 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7145 #define TESTFRAMESIZE 40
7147 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7149 /* setup 16C32 for SDLC DMA transfer mode */
7152 usc_set_sdlc_mode(info
);
7153 usc_enable_loopback(info
,1);
7155 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7156 * field of the buffer entry after fetching buffer address. This
7157 * way we can detect a DMA failure for a DMA read (which should be
7158 * non-destructive to system memory) before we try and write to
7159 * memory (where a failure could corrupt system memory).
7162 /* Receive DMA mode Register (RDMR)
7164 * <15..14> 11 DMA mode = Linked List Buffer mode
7165 * <13> 1 RSBinA/L = store Rx status Block in List entry
7166 * <12> 0 1 = Clear count of List Entry after fetching
7167 * <11..10> 00 Address mode = Increment
7168 * <9> 1 Terminate Buffer on RxBound
7169 * <8> 0 Bus Width = 16bits
7170 * <7..0> ? status Bits (write as 0s)
7172 * 1110 0010 0000 0000 = 0xe200
7175 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7177 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7180 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7182 FrameSize
= TESTFRAMESIZE
;
7184 /* setup 1st transmit buffer entry: */
7185 /* with frame size and transmit control word */
7187 info
->tx_buffer_list
[0].count
= FrameSize
;
7188 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7189 info
->tx_buffer_list
[0].status
= 0x4000;
7191 /* build a transmit frame in 1st transmit DMA buffer */
7193 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7194 for (i
= 0; i
< FrameSize
; i
++ )
7197 /* setup 1st receive buffer entry: */
7198 /* clear status, set max receive buffer size */
7200 info
->rx_buffer_list
[0].status
= 0;
7201 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7203 /* zero out the 1st receive buffer */
7205 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7207 /* Set count field of next buffer entries to prevent */
7208 /* 16C32 from using buffers after the 1st one. */
7210 info
->tx_buffer_list
[1].count
= 0;
7211 info
->rx_buffer_list
[1].count
= 0;
7214 /***************************/
7215 /* Program 16C32 receiver. */
7216 /***************************/
7218 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7220 /* setup DMA transfers */
7221 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7223 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7224 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7225 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7226 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7228 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7229 usc_InDmaReg( info
, RDMR
);
7230 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7232 /* Enable Receiver (RMR <1..0> = 10) */
7233 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7235 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7238 /*************************************************************/
7239 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7240 /*************************************************************/
7242 /* Wait 100ms for interrupt. */
7243 EndTime
= jiffies
+ msecs_to_jiffies(100);
7246 if (time_after(jiffies
, EndTime
)) {
7251 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7252 status
= usc_InDmaReg( info
, RDMR
);
7253 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7255 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7256 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7257 /* BUSY (BIT 5) is active (channel still active). */
7258 /* This means the buffer entry read has completed. */
7264 /******************************/
7265 /* Program 16C32 transmitter. */
7266 /******************************/
7268 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7270 /* Program the Transmit Character Length Register (TCLR) */
7271 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7273 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7274 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7276 /* Program the address of the 1st DMA Buffer Entry in linked list */
7278 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7279 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7280 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7282 /* unlatch Tx status bits, and start transmit channel. */
7284 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7285 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7287 /* wait for DMA controller to fill transmit FIFO */
7289 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7291 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7294 /**********************************/
7295 /* WAIT FOR TRANSMIT FIFO TO FILL */
7296 /**********************************/
7299 EndTime
= jiffies
+ msecs_to_jiffies(100);
7302 if (time_after(jiffies
, EndTime
)) {
7307 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7308 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7309 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7311 if ( FifoLevel
< 16 )
7314 if ( FrameSize
< 32 ) {
7315 /* This frame is smaller than the entire transmit FIFO */
7316 /* so wait for the entire frame to be loaded. */
7317 if ( FifoLevel
<= (32 - FrameSize
) )
7325 /* Enable 16C32 transmitter. */
7327 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7329 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7330 usc_TCmd( info
, TCmd_SendFrame
);
7331 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7333 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7336 /******************************/
7337 /* WAIT FOR TRANSMIT COMPLETE */
7338 /******************************/
7341 EndTime
= jiffies
+ msecs_to_jiffies(100);
7343 /* While timer not expired wait for transmit complete */
7345 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7346 status
= usc_InReg( info
, TCSR
);
7347 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7349 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7350 if (time_after(jiffies
, EndTime
)) {
7355 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7356 status
= usc_InReg( info
, TCSR
);
7357 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7363 /* CHECK FOR TRANSMIT ERRORS */
7364 if ( status
& (BIT5
+ BIT1
) )
7369 /* WAIT FOR RECEIVE COMPLETE */
7372 EndTime
= jiffies
+ msecs_to_jiffies(100);
7374 /* Wait for 16C32 to write receive status to buffer entry. */
7375 status
=info
->rx_buffer_list
[0].status
;
7376 while ( status
== 0 ) {
7377 if (time_after(jiffies
, EndTime
)) {
7381 status
=info
->rx_buffer_list
[0].status
;
7387 /* CHECK FOR RECEIVE ERRORS */
7388 status
= info
->rx_buffer_list
[0].status
;
7390 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7391 /* receive error has occurred */
7394 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7395 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7401 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7403 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7405 /* restore current port options */
7406 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7410 } /* end of mgsl_dma_test() */
7412 /* mgsl_adapter_test()
7414 * Perform the register, IRQ, and DMA tests for the 16C32.
7416 * Arguments: info pointer to device instance data
7417 * Return Value: 0 if success, otherwise -ENODEV
7419 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7421 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7422 printk( "%s(%d):Testing device %s\n",
7423 __FILE__
,__LINE__
,info
->device_name
);
7425 if ( !mgsl_register_test( info
) ) {
7426 info
->init_error
= DiagStatus_AddressFailure
;
7427 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7428 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7432 if ( !mgsl_irq_test( info
) ) {
7433 info
->init_error
= DiagStatus_IrqFailure
;
7434 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7435 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7439 if ( !mgsl_dma_test( info
) ) {
7440 info
->init_error
= DiagStatus_DmaFailure
;
7441 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7442 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7446 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7447 printk( "%s(%d):device %s passed diagnostics\n",
7448 __FILE__
,__LINE__
,info
->device_name
);
7452 } /* end of mgsl_adapter_test() */
7454 /* mgsl_memory_test()
7456 * Test the shared memory on a PCI adapter.
7458 * Arguments: info pointer to device instance data
7459 * Return Value: true if test passed, otherwise false
7461 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7463 static unsigned long BitPatterns
[] =
7464 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7465 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7467 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7468 unsigned long * TestAddr
;
7470 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7473 TestAddr
= (unsigned long *)info
->memory_base
;
7475 /* Test data lines with test pattern at one location. */
7477 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7478 *TestAddr
= BitPatterns
[i
];
7479 if ( *TestAddr
!= BitPatterns
[i
] )
7483 /* Test address lines with incrementing pattern over */
7484 /* entire address range. */
7486 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7491 TestAddr
= (unsigned long *)info
->memory_base
;
7493 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7494 if ( *TestAddr
!= i
* 4 )
7499 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7503 } /* End Of mgsl_memory_test() */
7506 /* mgsl_load_pci_memory()
7508 * Load a large block of data into the PCI shared memory.
7509 * Use this instead of memcpy() or memmove() to move data
7510 * into the PCI shared memory.
7514 * This function prevents the PCI9050 interface chip from hogging
7515 * the adapter local bus, which can starve the 16C32 by preventing
7516 * 16C32 bus master cycles.
7518 * The PCI9050 documentation says that the 9050 will always release
7519 * control of the local bus after completing the current read
7520 * or write operation.
7522 * It appears that as long as the PCI9050 write FIFO is full, the
7523 * PCI9050 treats all of the writes as a single burst transaction
7524 * and will not release the bus. This causes DMA latency problems
7525 * at high speeds when copying large data blocks to the shared
7528 * This function in effect, breaks the a large shared memory write
7529 * into multiple transations by interleaving a shared memory read
7530 * which will flush the write FIFO and 'complete' the write
7531 * transation. This allows any pending DMA request to gain control
7532 * of the local bus in a timely fasion.
7536 * TargetPtr pointer to target address in PCI shared memory
7537 * SourcePtr pointer to source buffer for data
7538 * count count in bytes of data to copy
7540 * Return Value: None
7542 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7543 unsigned short count
)
7545 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7546 #define PCI_LOAD_INTERVAL 64
7548 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7549 unsigned short Index
;
7550 unsigned long Dummy
;
7552 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7554 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7555 Dummy
= *((volatile unsigned long *)TargetPtr
);
7556 TargetPtr
+= PCI_LOAD_INTERVAL
;
7557 SourcePtr
+= PCI_LOAD_INTERVAL
;
7560 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7562 } /* End Of mgsl_load_pci_memory() */
7564 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7569 printk("%s tx data:\n",info
->device_name
);
7571 printk("%s rx data:\n",info
->device_name
);
7579 for(i
=0;i
<linecount
;i
++)
7580 printk("%02X ",(unsigned char)data
[i
]);
7583 for(i
=0;i
<linecount
;i
++) {
7584 if (data
[i
]>=040 && data
[i
]<=0176)
7585 printk("%c",data
[i
]);
7594 } /* end of mgsl_trace_block() */
7596 /* mgsl_tx_timeout()
7598 * called when HDLC frame times out
7599 * update stats and do tx completion processing
7601 * Arguments: context pointer to device instance data
7602 * Return Value: None
7604 static void mgsl_tx_timeout(unsigned long context
)
7606 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7607 unsigned long flags
;
7609 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7610 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7611 __FILE__
,__LINE__
,info
->device_name
);
7612 if(info
->tx_active
&&
7613 (info
->params
.mode
== MGSL_MODE_HDLC
||
7614 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7615 info
->icount
.txtimeout
++;
7617 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7618 info
->tx_active
= false;
7619 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7621 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7622 usc_loopmode_cancel_transmit( info
);
7624 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7626 #if SYNCLINK_GENERIC_HDLC
7628 hdlcdev_tx_done(info
);
7631 mgsl_bh_transmit(info
);
7633 } /* end of mgsl_tx_timeout() */
7635 /* signal that there are no more frames to send, so that
7636 * line is 'released' by echoing RxD to TxD when current
7637 * transmission is complete (or immediately if no tx in progress).
7639 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7641 unsigned long flags
;
7643 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7644 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7645 if (info
->tx_active
)
7646 info
->loopmode_send_done_requested
= true;
7648 usc_loopmode_send_done(info
);
7650 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7655 /* release the line by echoing RxD to TxD
7656 * upon completion of a transmit frame
7658 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7660 info
->loopmode_send_done_requested
= false;
7661 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7662 info
->cmr_value
&= ~BIT13
;
7663 usc_OutReg(info
, CMR
, info
->cmr_value
);
7666 /* abort a transmit in progress while in HDLC LoopMode
7668 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7670 /* reset tx dma channel and purge TxFifo */
7671 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7672 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7673 usc_loopmode_send_done( info
);
7676 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7677 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7678 * we must clear CMR:13 to begin repeating TxData to RxData
7680 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7682 info
->loopmode_insert_requested
= true;
7684 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7685 * begin repeating TxData on RxData (complete insertion)
7687 usc_OutReg( info
, RICR
,
7688 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7690 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7691 info
->cmr_value
|= BIT13
;
7692 usc_OutReg(info
, CMR
, info
->cmr_value
);
7695 /* return 1 if station is inserted into the loop, otherwise 0
7697 static int usc_loopmode_active( struct mgsl_struct
* info
)
7699 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7702 #if SYNCLINK_GENERIC_HDLC
7705 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7706 * set encoding and frame check sequence (FCS) options
7708 * dev pointer to network device structure
7709 * encoding serial encoding setting
7710 * parity FCS setting
7712 * returns 0 if success, otherwise error code
7714 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7715 unsigned short parity
)
7717 struct mgsl_struct
*info
= dev_to_port(dev
);
7718 unsigned char new_encoding
;
7719 unsigned short new_crctype
;
7721 /* return error if TTY interface open */
7722 if (info
->port
.count
)
7727 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7728 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7729 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7730 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7731 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7732 default: return -EINVAL
;
7737 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7738 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7739 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7740 default: return -EINVAL
;
7743 info
->params
.encoding
= new_encoding
;
7744 info
->params
.crc_type
= new_crctype
;
7746 /* if network interface up, reprogram hardware */
7748 mgsl_program_hw(info
);
7754 * called by generic HDLC layer to send frame
7756 * skb socket buffer containing HDLC frame
7757 * dev pointer to network device structure
7759 * returns 0 if success, otherwise error code
7761 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7763 struct mgsl_struct
*info
= dev_to_port(dev
);
7764 unsigned long flags
;
7766 if (debug_level
>= DEBUG_LEVEL_INFO
)
7767 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7769 /* stop sending until this frame completes */
7770 netif_stop_queue(dev
);
7772 /* copy data to device buffers */
7773 info
->xmit_cnt
= skb
->len
;
7774 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7776 /* update network statistics */
7777 dev
->stats
.tx_packets
++;
7778 dev
->stats
.tx_bytes
+= skb
->len
;
7780 /* done with socket buffer, so free it */
7783 /* save start time for transmit timeout detection */
7784 dev
->trans_start
= jiffies
;
7786 /* start hardware transmitter if necessary */
7787 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7788 if (!info
->tx_active
)
7789 usc_start_transmitter(info
);
7790 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7796 * called by network layer when interface enabled
7797 * claim resources and initialize hardware
7799 * dev pointer to network device structure
7801 * returns 0 if success, otherwise error code
7803 static int hdlcdev_open(struct net_device
*dev
)
7805 struct mgsl_struct
*info
= dev_to_port(dev
);
7807 unsigned long flags
;
7809 if (debug_level
>= DEBUG_LEVEL_INFO
)
7810 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7812 /* generic HDLC layer open processing */
7813 if ((rc
= hdlc_open(dev
)))
7816 /* arbitrate between network and tty opens */
7817 spin_lock_irqsave(&info
->netlock
, flags
);
7818 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7819 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7820 spin_unlock_irqrestore(&info
->netlock
, flags
);
7824 spin_unlock_irqrestore(&info
->netlock
, flags
);
7826 /* claim resources and init adapter */
7827 if ((rc
= startup(info
)) != 0) {
7828 spin_lock_irqsave(&info
->netlock
, flags
);
7830 spin_unlock_irqrestore(&info
->netlock
, flags
);
7834 /* assert DTR and RTS, apply hardware settings */
7835 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7836 mgsl_program_hw(info
);
7838 /* enable network layer transmit */
7839 dev
->trans_start
= jiffies
;
7840 netif_start_queue(dev
);
7842 /* inform generic HDLC layer of current DCD status */
7843 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7844 usc_get_serial_signals(info
);
7845 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7846 if (info
->serial_signals
& SerialSignal_DCD
)
7847 netif_carrier_on(dev
);
7849 netif_carrier_off(dev
);
7854 * called by network layer when interface is disabled
7855 * shutdown hardware and release resources
7857 * dev pointer to network device structure
7859 * returns 0 if success, otherwise error code
7861 static int hdlcdev_close(struct net_device
*dev
)
7863 struct mgsl_struct
*info
= dev_to_port(dev
);
7864 unsigned long flags
;
7866 if (debug_level
>= DEBUG_LEVEL_INFO
)
7867 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7869 netif_stop_queue(dev
);
7871 /* shutdown adapter and release resources */
7876 spin_lock_irqsave(&info
->netlock
, flags
);
7878 spin_unlock_irqrestore(&info
->netlock
, flags
);
7884 * called by network layer to process IOCTL call to network device
7886 * dev pointer to network device structure
7887 * ifr pointer to network interface request structure
7888 * cmd IOCTL command code
7890 * returns 0 if success, otherwise error code
7892 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7894 const size_t size
= sizeof(sync_serial_settings
);
7895 sync_serial_settings new_line
;
7896 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7897 struct mgsl_struct
*info
= dev_to_port(dev
);
7900 if (debug_level
>= DEBUG_LEVEL_INFO
)
7901 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7903 /* return error if TTY interface open */
7904 if (info
->port
.count
)
7907 if (cmd
!= SIOCWANDEV
)
7908 return hdlc_ioctl(dev
, ifr
, cmd
);
7910 switch(ifr
->ifr_settings
.type
) {
7911 case IF_GET_IFACE
: /* return current sync_serial_settings */
7913 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7914 if (ifr
->ifr_settings
.size
< size
) {
7915 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7919 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7920 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7921 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7922 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7925 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7926 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7927 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7928 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7929 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7932 new_line
.clock_rate
= info
->params
.clock_speed
;
7933 new_line
.loopback
= info
->params
.loopback
? 1:0;
7935 if (copy_to_user(line
, &new_line
, size
))
7939 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7941 if(!capable(CAP_NET_ADMIN
))
7943 if (copy_from_user(&new_line
, line
, size
))
7946 switch (new_line
.clock_type
)
7948 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7949 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7950 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7951 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7952 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7953 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7954 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7955 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7956 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7957 default: return -EINVAL
;
7960 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7963 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7964 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7965 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7966 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7967 info
->params
.flags
|= flags
;
7969 info
->params
.loopback
= new_line
.loopback
;
7971 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7972 info
->params
.clock_speed
= new_line
.clock_rate
;
7974 info
->params
.clock_speed
= 0;
7976 /* if network interface up, reprogram hardware */
7978 mgsl_program_hw(info
);
7982 return hdlc_ioctl(dev
, ifr
, cmd
);
7987 * called by network layer when transmit timeout is detected
7989 * dev pointer to network device structure
7991 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7993 struct mgsl_struct
*info
= dev_to_port(dev
);
7994 unsigned long flags
;
7996 if (debug_level
>= DEBUG_LEVEL_INFO
)
7997 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7999 dev
->stats
.tx_errors
++;
8000 dev
->stats
.tx_aborted_errors
++;
8002 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
8003 usc_stop_transmitter(info
);
8004 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
8006 netif_wake_queue(dev
);
8010 * called by device driver when transmit completes
8011 * reenable network layer transmit if stopped
8013 * info pointer to device instance information
8015 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
8017 if (netif_queue_stopped(info
->netdev
))
8018 netif_wake_queue(info
->netdev
);
8022 * called by device driver when frame received
8023 * pass frame to network layer
8025 * info pointer to device instance information
8026 * buf pointer to buffer contianing frame data
8027 * size count of data bytes in buf
8029 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
8031 struct sk_buff
*skb
= dev_alloc_skb(size
);
8032 struct net_device
*dev
= info
->netdev
;
8034 if (debug_level
>= DEBUG_LEVEL_INFO
)
8035 printk("hdlcdev_rx(%s)\n", dev
->name
);
8038 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
8040 dev
->stats
.rx_dropped
++;
8044 memcpy(skb_put(skb
, size
), buf
, size
);
8046 skb
->protocol
= hdlc_type_trans(skb
, dev
);
8048 dev
->stats
.rx_packets
++;
8049 dev
->stats
.rx_bytes
+= size
;
8053 dev
->last_rx
= jiffies
;
8057 * called by device driver when adding device instance
8058 * do generic HDLC initialization
8060 * info pointer to device instance information
8062 * returns 0 if success, otherwise error code
8064 static int hdlcdev_init(struct mgsl_struct
*info
)
8067 struct net_device
*dev
;
8070 /* allocate and initialize network and HDLC layer objects */
8072 if (!(dev
= alloc_hdlcdev(info
))) {
8073 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8077 /* for network layer reporting purposes only */
8078 dev
->base_addr
= info
->io_base
;
8079 dev
->irq
= info
->irq_level
;
8080 dev
->dma
= info
->dma_level
;
8082 /* network layer callbacks and settings */
8083 dev
->do_ioctl
= hdlcdev_ioctl
;
8084 dev
->open
= hdlcdev_open
;
8085 dev
->stop
= hdlcdev_close
;
8086 dev
->tx_timeout
= hdlcdev_tx_timeout
;
8087 dev
->watchdog_timeo
= 10*HZ
;
8088 dev
->tx_queue_len
= 50;
8090 /* generic HDLC layer callbacks and settings */
8091 hdlc
= dev_to_hdlc(dev
);
8092 hdlc
->attach
= hdlcdev_attach
;
8093 hdlc
->xmit
= hdlcdev_xmit
;
8095 /* register objects with HDLC layer */
8096 if ((rc
= register_hdlc_device(dev
))) {
8097 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8107 * called by device driver when removing device instance
8108 * do generic HDLC cleanup
8110 * info pointer to device instance information
8112 static void hdlcdev_exit(struct mgsl_struct
*info
)
8114 unregister_hdlc_device(info
->netdev
);
8115 free_netdev(info
->netdev
);
8116 info
->netdev
= NULL
;
8119 #endif /* CONFIG_HDLC */
8122 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8123 const struct pci_device_id
*ent
)
8125 struct mgsl_struct
*info
;
8127 if (pci_enable_device(dev
)) {
8128 printk("error enabling pci device %p\n", dev
);
8132 if (!(info
= mgsl_allocate_device())) {
8133 printk("can't allocate device instance data.\n");
8137 /* Copy user configuration info to device instance data */
8139 info
->io_base
= pci_resource_start(dev
, 2);
8140 info
->irq_level
= dev
->irq
;
8141 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8143 /* Because veremap only works on page boundaries we must map
8144 * a larger area than is actually implemented for the LCR
8145 * memory range. We map a full page starting at the page boundary.
8147 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8148 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8149 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8151 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8152 info
->io_addr_size
= 8;
8153 info
->irq_flags
= IRQF_SHARED
;
8155 if (dev
->device
== 0x0210) {
8156 /* Version 1 PCI9030 based universal PCI adapter */
8157 info
->misc_ctrl_value
= 0x007c4080;
8158 info
->hw_version
= 1;
8160 /* Version 0 PCI9050 based 5V PCI adapter
8161 * A PCI9050 bug prevents reading LCR registers if
8162 * LCR base address bit 7 is set. Maintain shadow
8163 * value so we can write to LCR misc control reg.
8165 info
->misc_ctrl_value
= 0x087e4546;
8166 info
->hw_version
= 0;
8169 mgsl_add_device(info
);
8174 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)