drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/version.h>
  38
  39 #define EDAC_MC_LABEL_LEN       31
  40 #define EDAC_DEVICE_NAME_LEN    31
  41 #define EDAC_ATTRIB_VALUE_LEN   15
  42 #define MC_PROC_NAME_MAX_LEN    7
  43
  44 #if PAGE_SHIFT < 20
  45 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  46 #else                           /* PAGE_SHIFT > 20 */
  47 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  48 #endif
  49
  50 #define edac_printk(level, prefix, fmt, arg...) \
  51         printk(level "EDAC " prefix ": " fmt, ##arg)
  52
  53 #define edac_mc_printk(mci, level, fmt, arg...) \
  54         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  55
  56 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  57         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 /* edac_device printk */
  60 #define edac_device_printk(ctl, level, fmt, arg...) \
  61         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  62
  63 /* prefixes for edac_printk() and edac_mc_printk() */
  64 #define EDAC_MC "MC"
  65 #define EDAC_PCI "PCI"
  66 #define EDAC_DEBUG "DEBUG"
  67
  68 #ifdef CONFIG_EDAC_DEBUG
  69 extern int edac_debug_level;
  70
  71 #define edac_debug_printk(level, fmt, arg...)                            \
  72         do {                                                             \
  73                 if (level <= edac_debug_level)                           \
  74                         edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \
  75         } while(0)
  76
  77 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  78 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  79 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  80 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  81 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  82
  83 #else  /* !CONFIG_EDAC_DEBUG */
  84
  85 #define debugf0( ... )
  86 #define debugf1( ... )
  87 #define debugf2( ... )
  88 #define debugf3( ... )
  89 #define debugf4( ... )
  90
  91 #endif  /* !CONFIG_EDAC_DEBUG */
  92
  93 #define BIT(x) (1 << (x))
  94
  95 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  96         PCI_DEVICE_ID_ ## vend ## _ ## dev
  97
  98 #define dev_name(dev) (dev)->dev_name
  99
 100 /* memory devices */
 101 enum dev_type {
 102         DEV_UNKNOWN = 0,
 103         DEV_X1,
 104         DEV_X2,
 105         DEV_X4,
 106         DEV_X8,
 107         DEV_X16,
 108         DEV_X32,                /* Do these parts exist? */
 109         DEV_X64                 /* Do these parts exist? */
 110 };
 111
 112 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 113 #define DEV_FLAG_X1             BIT(DEV_X1)
 114 #define DEV_FLAG_X2             BIT(DEV_X2)
 115 #define DEV_FLAG_X4             BIT(DEV_X4)
 116 #define DEV_FLAG_X8             BIT(DEV_X8)
 117 #define DEV_FLAG_X16            BIT(DEV_X16)
 118 #define DEV_FLAG_X32            BIT(DEV_X32)
 119 #define DEV_FLAG_X64            BIT(DEV_X64)
 120
 121 /* memory types */
 122 enum mem_type {
 123         MEM_EMPTY = 0,          /* Empty csrow */
 124         MEM_RESERVED,           /* Reserved csrow type */
 125         MEM_UNKNOWN,            /* Unknown csrow type */
 126         MEM_FPM,                /* Fast page mode */
 127         MEM_EDO,                /* Extended data out */
 128         MEM_BEDO,               /* Burst Extended data out */
 129         MEM_SDR,                /* Single data rate SDRAM */
 130         MEM_RDR,                /* Registered single data rate SDRAM */
 131         MEM_DDR,                /* Double data rate SDRAM */
 132         MEM_RDDR,               /* Registered Double data rate SDRAM */
 133         MEM_RMBS,               /* Rambus DRAM */
 134         MEM_DDR2,               /* DDR2 RAM */
 135         MEM_FB_DDR2,            /* fully buffered DDR2 */
 136         MEM_RDDR2,              /* Registered DDR2 RAM */
 137 };
 138
 139 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 140 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 141 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 142 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 143 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 144 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 145 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 146 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 147 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 148 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 149 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 150 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 151 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 152 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 153
 154 /* chipset Error Detection and Correction capabilities and mode */
 155 enum edac_type {
 156         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 157         EDAC_NONE,              /* Doesnt support ECC */
 158         EDAC_RESERVED,          /* Reserved ECC type */
 159         EDAC_PARITY,            /* Detects parity errors */
 160         EDAC_EC,                /* Error Checking - no correction */
 161         EDAC_SECDED,            /* Single bit error correction, Double detection */
 162         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 163         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 164         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 165         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 166 };
 167
 168 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 169 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 170 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 171 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 172 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 173 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 174 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 175 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 176 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 177
 178 /* scrubbing capabilities */
 179 enum scrub_type {
 180         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 181         SCRUB_NONE,             /* No scrubber */
 182         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 183         SCRUB_SW_SRC,           /* Software scrub only errors */
 184         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 185         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 186         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 187         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 188         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 189         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 190 };
 191
 192 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 193 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 194 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 195 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 196 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 197 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 198 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 199 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 200
 201 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 202
 203 extern char * edac_align_ptr(void *ptr, unsigned size);
 204
 205 /*
 206  * There are several things to be aware of that aren't at all obvious:
 207  *
 208  *
 209  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 210  *
 211  * These are some of the many terms that are thrown about that don't always
 212  * mean what people think they mean (Inconceivable!).  In the interest of
 213  * creating a common ground for discussion, terms and their definitions
 214  * will be established.
 215  *
 216  * Memory devices:      The individual chip on a memory stick.  These devices
 217  *                      commonly output 4 and 8 bits each.  Grouping several
 218  *                      of these in parallel provides 64 bits which is common
 219  *                      for a memory stick.
 220  *
 221  * Memory Stick:        A printed circuit board that agregates multiple
 222  *                      memory devices in parallel.  This is the atomic
 223  *                      memory component that is purchaseable by Joe consumer
 224  *                      and loaded into a memory socket.
 225  *
 226  * Socket:              A physical connector on the motherboard that accepts
 227  *                      a single memory stick.
 228  *
 229  * Channel:             Set of memory devices on a memory stick that must be
 230  *                      grouped in parallel with one or more additional
 231  *                      channels from other memory sticks.  This parallel
 232  *                      grouping of the output from multiple channels are
 233  *                      necessary for the smallest granularity of memory access.
 234  *                      Some memory controllers are capable of single channel -
 235  *                      which means that memory sticks can be loaded
 236  *                      individually.  Other memory controllers are only
 237  *                      capable of dual channel - which means that memory
 238  *                      sticks must be loaded as pairs (see "socket set").
 239  *
 240  * Chip-select row:     All of the memory devices that are selected together.
 241  *                      for a single, minimum grain of memory access.
 242  *                      This selects all of the parallel memory devices across
 243  *                      all of the parallel channels.  Common chip-select rows
 244  *                      for single channel are 64 bits, for dual channel 128
 245  *                      bits.
 246  *
 247  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 248  *                      Motherboards commonly drive two chip-select pins to
 249  *                      a memory stick. A single-ranked stick, will occupy
 250  *                      only one of those rows. The other will be unused.
 251  *
 252  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 253  *                      access different sets of memory devices.  The two
 254  *                      rows cannot be accessed concurrently.
 255  *
 256  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 257  *                      A double-sided stick has two chip-select rows which
 258  *                      access different sets of memory devices.  The two
 259  *                      rows cannot be accessed concurrently.  "Double-sided"
 260  *                      is irrespective of the memory devices being mounted
 261  *                      on both sides of the memory stick.
 262  *
 263  * Socket set:          All of the memory sticks that are required for for
 264  *                      a single memory access or all of the memory sticks
 265  *                      spanned by a chip-select row.  A single socket set
 266  *                      has two chip-select rows and if double-sided sticks
 267  *                      are used these will occupy those chip-select rows.
 268  *
 269  * Bank:                This term is avoided because it is unclear when
 270  *                      needing to distinguish between chip-select rows and
 271  *                      socket sets.
 272  *
 273  * Controller pages:
 274  *
 275  * Physical pages:
 276  *
 277  * Virtual pages:
 278  *
 279  *
 280  * STRUCTURE ORGANIZATION AND CHOICES
 281  *
 282  *
 283  *
 284  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 285  */
 286
 287 struct channel_info {
 288         int chan_idx;           /* channel index */
 289         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 290         char label[EDAC_MC_LABEL_LEN + 1];  /* DIMM label on motherboard */
 291         struct csrow_info *csrow;       /* the parent */
 292 };
 293
 294 struct csrow_info {
 295         unsigned long first_page;       /* first page number in dimm */
 296         unsigned long last_page;        /* last page number in dimm */
 297         unsigned long page_mask;        /* used for interleaving -
 298                                          * 0UL for non intlv
 299                                          */
 300         u32 nr_pages;           /* number of pages in csrow */
 301         u32 grain;              /* granularity of reported error in bytes */
 302         int csrow_idx;          /* the chip-select row */
 303         enum dev_type dtype;    /* memory device type */
 304         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 305         u32 ce_count;           /* Correctable Errors for this csrow */
 306         enum mem_type mtype;    /* memory csrow type */
 307         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 308         struct mem_ctl_info *mci;       /* the parent */
 309
 310         struct kobject kobj;    /* sysfs kobject for this csrow */
 311         struct completion kobj_complete;
 312
 313         /* FIXME the number of CHANNELs might need to become dynamic */
 314         u32 nr_channels;
 315         struct channel_info *channels;
 316 };
 317
 318 struct mem_ctl_info {
 319         struct list_head link;  /* for global list of mem_ctl_info structs */
 320         unsigned long mtype_cap;        /* memory types supported by mc */
 321         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 322         unsigned long edac_cap; /* configuration capabilities - this is
 323                                  * closely related to edac_ctl_cap.  The
 324                                  * difference is that the controller may be
 325                                  * capable of s4ecd4ed which would be listed
 326                                  * in edac_ctl_cap, but if channels aren't
 327                                  * capable of s4ecd4ed then the edac_cap would
 328                                  * not have that capability.
 329                                  */
 330         unsigned long scrub_cap;        /* chipset scrub capabilities */
 331         enum scrub_type scrub_mode;     /* current scrub mode */
 332
 333         /* Translates sdram memory scrub rate given in bytes/sec to the
 334            internal representation and configures whatever else needs
 335            to be configured.
 336         */
 337         int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 338
 339         /* Get the current sdram memory scrub rate from the internal
 340            representation and converts it to the closest matching
 341            bandwith in bytes/sec.
 342         */
 343         int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 344
 345         /* pointer to edac checking routine */
 346         void (*edac_check) (struct mem_ctl_info * mci);
 347
 348         /*
 349          * Remaps memory pages: controller pages to physical pages.
 350          * For most MC's, this will be NULL.
 351          */
 352         /* FIXME - why not send the phys page to begin with? */
 353         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 354                                         unsigned long page);
 355         int mc_idx;
 356         int nr_csrows;
 357         struct csrow_info *csrows;
 358         /*
 359          * FIXME - what about controllers on other busses? - IDs must be
 360          * unique.  dev pointer should be sufficiently unique, but
 361          * BUS:SLOT.FUNC numbers may not be unique.
 362          */
 363         struct device *dev;
 364         const char *mod_name;
 365         const char *mod_ver;
 366         const char *ctl_name;
 367         const char *dev_name;
 368         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 369         void *pvt_info;
 370         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 371         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 372         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 373         u32 ce_count;           /* Total Correctable Errors for this MC */
 374         unsigned long start_time;       /* mci load start time (in jiffies) */
 375
 376         /* this stuff is for safe removal of mc devices from global list while
 377          * NMI handlers may be traversing list
 378          */
 379         struct rcu_head rcu;
 380         struct completion complete;
 381
 382         /* edac sysfs device control */
 383         struct kobject edac_mci_kobj;
 384         struct completion kobj_complete;
 385
 386         /* work struct for this MC */
 387 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
 388         struct delayed_work work;
 389 #else
 390         struct work_struct work;
 391 #endif
 392         /* the internal state of this controller instance */
 393         int op_state;
 394 };
 395
 396 /*
 397  * The following are the structures to provide for a generice
 398  * or abstract 'edac_device'. This set of structures and the
 399  * code that implements the APIs for the same, provide for
 400  * registering EDAC type devices which are NOT standard memory.
 401  *
 402  * CPU caches (L1 and L2)
 403  * DMA engines
 404  * Core CPU swithces
 405  * Fabric switch units
 406  * PCIe interface controllers
 407  * other EDAC/ECC type devices that can be monitored for
 408  * errors, etc.
 409  *
 410  * It allows for a 2 level set of hiearchry. For example:
 411  *
 412  * cache could be composed of L1, L2 and L3 levels of cache.
 413  * Each CPU core would have its own L1 cache, while sharing
 414  * L2 and maybe L3 caches.
 415  *
 416  * View them arranged, via the sysfs presentation:
 417  * /sys/devices/system/edac/..
 418  *
 419  *      mc/             <existing memory device directory>
 420  *      cpu/cpu0/..     <L1 and L2 block directory>
 421  *              /L1-cache/ce_count
 422  *                       /ue_count
 423  *              /L2-cache/ce_count
 424  *                       /ue_count
 425  *      cpu/cpu1/..     <L1 and L2 block directory>
 426  *              /L1-cache/ce_count
 427  *                       /ue_count
 428  *              /L2-cache/ce_count
 429  *                       /ue_count
 430  *      ...
 431  *
 432  *      the L1 and L2 directories would be "edac_device_block's"
 433  */
 434
 435 struct edac_device_counter {
 436         u32     ue_count;
 437         u32     ce_count;
 438 };
 439
 440 #define INC_COUNTER(cnt)        (cnt++)
 441
 442 /*
 443  * An array of these is passed to the alloc() function
 444  * to specify attributes of the edac_block
 445  */
 446 struct edac_attrib_spec {
 447         char  name[EDAC_DEVICE_NAME_LEN + 1];
 448
 449         int type;
 450 #define EDAC_ATTR_INT           0x01
 451 #define EDAC_ATTR_CHAR          0x02
 452 };
 453
 454
 455 /* Attribute control structure
 456  * In this structure is a pointer to the driver's edac_attrib_spec
 457  * The life of this pointer is inclusive in the life of the driver's
 458  * life cycle.
 459  */
 460 struct edac_attrib {
 461         struct edac_device_block *block;        /* Up Pointer */
 462
 463         struct edac_attrib_spec *spec;          /* ptr to module spec entry */
 464
 465         union {                                 /* actual value */
 466                 int edac_attrib_int_value;
 467                 char edac_attrib_char_value[EDAC_ATTRIB_VALUE_LEN + 1];
 468         } edac_attrib_value;
 469 };
 470
 471 /* device block control structure */
 472 struct edac_device_block {
 473         struct edac_device_instance *instance;  /* Up Pointer */
 474         char  name[EDAC_DEVICE_NAME_LEN + 1];
 475
 476         struct edac_device_counter counters;    /* basic UE and CE counters */
 477
 478         int nr_attribs;                         /* how many attributes */
 479         struct edac_attrib *attribs;            /* this block's attributes */
 480
 481         /* edac sysfs device control */
 482         struct kobject kobj;
 483         struct completion kobj_complete;
 484 };
 485
 486 /* device instance control structure */
 487 struct edac_device_instance {
 488         struct edac_device_ctl_info *ctl;       /* Up pointer */
 489         char name[EDAC_DEVICE_NAME_LEN + 4];
 490
 491         struct edac_device_counter counters;    /* instance counters */
 492
 493         u32 nr_blocks;                          /* how many blocks */
 494         struct edac_device_block *blocks;       /* block array */
 495
 496         /* edac sysfs device control */
 497         struct kobject kobj;
 498         struct completion kobj_complete;
 499 };
 500
 501
 502 /*
 503  * Abstract edac_device control info structure
 504  *
 505  */
 506 struct edac_device_ctl_info {
 507         /* for global list of edac_device_ctl_info structs */
 508         struct list_head link;
 509
 510         int dev_idx;
 511
 512         /* Per instance controls for this edac_device */
 513         int log_ue;             /* boolean for logging UEs */
 514         int log_ce;             /* boolean for logging CEs */
 515         int panic_on_ue;        /* boolean for panic'ing on an UE */
 516         unsigned poll_msec;     /* number of milliseconds to poll interval */
 517         unsigned long delay;    /* number of jiffies for poll_msec */
 518
 519         struct sysdev_class *edac_class;        /* pointer to class */
 520
 521         /* the internal state of this controller instance */
 522         int op_state;
 523 #define OP_ALLOC                0x100
 524 #define OP_RUNNING_POLL         0x201
 525 #define OP_RUNNING_INTERRUPT    0x202
 526 #define OP_RUNNING_POLL_INTR    0x203
 527 #define OP_OFFLINE              0x300
 528
 529         /* work struct for this instance */
 530 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
 531         struct delayed_work work;
 532 #else
 533         struct work_struct work;
 534 #endif
 535
 536         /* pointer to edac polling checking routine:
 537          *      If NOT NULL: points to polling check routine
 538          *      If NULL: Then assumes INTERRUPT operation, where
 539          *              MC driver will receive events
 540          */
 541         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 542
 543         struct device *dev;     /* pointer to device structure */
 544
 545         const char *mod_name;   /* module name */
 546         const char *ctl_name;   /* edac controller  name */
 547         const char *dev_name;   /* pci/platform/etc... name */
 548
 549         void *pvt_info;         /* pointer to 'private driver' info */
 550
 551         unsigned long start_time;/* edac_device load start time (jiffies)*/
 552
 553         /* these are for safe removal of mc devices from global list while
 554          * NMI handlers may be traversing list
 555          */
 556         struct rcu_head rcu;
 557         struct completion complete;
 558
 559         /* sysfs top name under 'edac' directory
 560          * and instance name:
 561          *      cpu/cpu0/...
 562          *      cpu/cpu1/...
 563          *      cpu/cpu2/...
 564          *      ...
 565          */
 566         char name[EDAC_DEVICE_NAME_LEN + 1];
 567
 568         /* Number of instances supported on this control structure
 569          * and the array of those instances
 570          */
 571         u32 nr_instances;
 572         struct edac_device_instance *instances;
 573
 574         /* Event counters for the this whole EDAC Device */
 575         struct edac_device_counter counters;
 576
 577         /* edac sysfs device control for the 'name'
 578          * device this structure controls
 579          */
 580         struct kobject kobj;
 581         struct completion kobj_complete;
 582 };
 583
 584 /* To get from the instance's wq to the beginning of the ctl structure */
 585 #define to_edac_mem_ctl_work(w) \
 586                 container_of(w, struct mem_ctl_info, work)
 587
 588 #define to_edac_device_ctl_work(w) \
 589                 container_of(w,struct edac_device_ctl_info,work)
 590
 591 /* Function to calc the number of delay jiffies from poll_msec */
 592 static inline void edac_device_calc_delay(
 593                                 struct edac_device_ctl_info *edac_dev)
 594 {
 595         /* convert from msec to jiffies */
 596         edac_dev->delay = edac_dev->poll_msec * HZ / 1000;
 597 }
 598
 599 #define edac_calc_delay(dev) dev->delay = dev->poll_msec * HZ / 1000;
 600
 601 /*
 602  * The alloc() and free() functions for the 'edac_device' control info
 603  * structure. A MC driver will allocate one of these for each edac_device
 604  * it is going to control/register with the EDAC CORE.
 605  */
 606 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 607         unsigned sizeof_private,
 608         char *edac_device_name,
 609         unsigned nr_instances,
 610         char *edac_block_name,
 611         unsigned nr_blocks,
 612         unsigned offset_value,
 613         struct edac_attrib_spec *attrib_spec,
 614         unsigned nr_attribs
 615 );
 616
 617 /* The offset value can be:
 618  *      -1 indicating no offset value
 619  *      0 for zero-based block numbers
 620  *      1 for 1-based block number
 621  *      other for other-based block number
 622  */
 623 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 624
 625 extern void edac_device_free_ctl_info( struct edac_device_ctl_info *ctl_info);
 626
 627 #ifdef CONFIG_PCI
 628
 629 /* write all or some bits in a byte-register*/
 630 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 631                 u8 mask)
 632 {
 633         if (mask != 0xff) {
 634                 u8 buf;
 635
 636                 pci_read_config_byte(pdev, offset, &buf);
 637                 value &= mask;
 638                 buf &= ~mask;
 639                 value |= buf;
 640         }
 641
 642         pci_write_config_byte(pdev, offset, value);
 643 }
 644
 645 /* write all or some bits in a word-register*/
 646 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 647                 u16 value, u16 mask)
 648 {
 649         if (mask != 0xffff) {
 650                 u16 buf;
 651
 652                 pci_read_config_word(pdev, offset, &buf);
 653                 value &= mask;
 654                 buf &= ~mask;
 655                 value |= buf;
 656         }
 657
 658         pci_write_config_word(pdev, offset, value);
 659 }
 660
 661 /* write all or some bits in a dword-register*/
 662 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 663                 u32 value, u32 mask)
 664 {
 665         if (mask != 0xffff) {
 666                 u32 buf;
 667
 668                 pci_read_config_dword(pdev, offset, &buf);
 669                 value &= mask;
 670                 buf &= ~mask;
 671                 value |= buf;
 672         }
 673
 674         pci_write_config_dword(pdev, offset, value);
 675 }
 676
 677 #endif /* CONFIG_PCI */
 678
 679 extern struct mem_ctl_info * edac_mc_find(int idx);
 680 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
 681 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
 682 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 683                                         unsigned long page);
 684
 685 /*
 686  * The no info errors are used when error overflows are reported.
 687  * There are a limited number of error logging registers that can
 688  * be exausted.  When all registers are exhausted and an additional
 689  * error occurs then an error overflow register records that an
 690  * error occured and the type of error, but doesn't have any
 691  * further information.  The ce/ue versions make for cleaner
 692  * reporting logic and function interface - reduces conditional
 693  * statement clutter and extra function arguments.
 694  */
 695 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 696                 unsigned long page_frame_number, unsigned long offset_in_page,
 697                 unsigned long syndrome, int row, int channel,
 698                 const char *msg);
 699 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 700                 const char *msg);
 701 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 702                 unsigned long page_frame_number, unsigned long offset_in_page,
 703                 int row, const char *msg);
 704 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 705                 const char *msg);
 706 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci,
 707                 unsigned int csrow,
 708                 unsigned int channel0,
 709                 unsigned int channel1,
 710                 char *msg);
 711 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci,
 712                 unsigned int csrow,
 713                 unsigned int channel,
 714                 char *msg);
 715
 716 /*
 717  * edac_device APIs
 718  */
 719 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 720                 unsigned nr_chans);
 721 extern void edac_mc_free(struct mem_ctl_info *mci);
 722 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev, int edac_idx);
 723 extern struct edac_device_ctl_info * edac_device_del_device(struct device *dev);
 724 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 725                 int inst_nr, int block_nr, const char *msg);
 726 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 727                 int inst_nr, int block_nr, const char *msg);
 728
 729
 730 #endif                          /* _EDAC_CORE_H_ */