drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <drm/drmP.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include "amdgpu.h"
  34 #include "atom.h"
  35
  36 /*
  37  * IB
  38  * IBs (Indirect Buffers) and areas of GPU accessible memory where
  39  * commands are stored.  You can put a pointer to the IB in the
  40  * command ring and the hw will fetch the commands from the IB
  41  * and execute them.  Generally userspace acceleration drivers
  42  * produce command buffers which are send to the kernel and
  43  * put in IBs for execution by the requested ring.
  44  */
  45 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
  46
  47 /**
  48  * amdgpu_ib_get - request an IB (Indirect Buffer)
  49  *
  50  * @ring: ring index the IB is associated with
  51  * @size: requested IB size
  52  * @ib: IB object returned
  53  *
  54  * Request an IB (all asics).  IBs are allocated using the
  55  * suballocator.
  56  * Returns 0 on success, error on failure.
  57  */
  58 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  59                   unsigned size, struct amdgpu_ib *ib)
  60 {
  61         int r;
  62
  63         if (size) {
  64                 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
  65                                       &ib->sa_bo, size, 256);
  66                 if (r) {
  67                         dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
  68                         return r;
  69                 }
  70
  71                 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
  72
  73                 if (!vm)
  74                         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
  75         }
  76
  77         return 0;
  78 }
  79
  80 /**
  81  * amdgpu_ib_free - free an IB (Indirect Buffer)
  82  *
  83  * @adev: amdgpu_device pointer
  84  * @ib: IB object to free
  85  * @f: the fence SA bo need wait on for the ib alloation
  86  *
  87  * Free an IB (all asics).
  88  */
  89 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
  90                     struct fence *f)
  91 {
  92         amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
  93 }
  94
  95 /**
  96  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  97  *
  98  * @adev: amdgpu_device pointer
  99  * @num_ibs: number of IBs to schedule
 100  * @ibs: IB objects to schedule
 101  * @f: fence created during this submission
 102  *
 103  * Schedule an IB on the associated ring (all asics).
 104  * Returns 0 on success, error on failure.
 105  *
 106  * On SI, there are two parallel engines fed from the primary ring,
 107  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
 108  * resource descriptors have moved to memory, the CE allows you to
 109  * prime the caches while the DE is updating register state so that
 110  * the resource descriptors will be already in cache when the draw is
 111  * processed.  To accomplish this, the userspace driver submits two
 112  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
 113  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
 114  * to SI there was just a DE IB.
 115  */
 116 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 117                        struct amdgpu_ib *ibs, struct fence *last_vm_update,
 118                        struct amdgpu_job *job, struct fence **f)
 119 {
 120         struct amdgpu_device *adev = ring->adev;
 121         struct amdgpu_ib *ib = &ibs[0];
 122         bool skip_preamble, need_ctx_switch;
 123         unsigned patch_offset = ~0;
 124         struct amdgpu_vm *vm;
 125         int vmid = 0, old_vmid = ring->vmid;
 126         struct fence *hwf;
 127         uint64_t ctx;
 128
 129         unsigned i;
 130         int r = 0;
 131
 132         if (num_ibs == 0)
 133                 return -EINVAL;
 134
 135         /* ring tests don't use a job */
 136         if (job) {
 137                 vm = job->vm;
 138                 ctx = job->ctx;
 139                 vmid = job->vm_id;
 140         } else {
 141                 vm = NULL;
 142                 ctx = 0;
 143                 vmid = 0;
 144         }
 145
 146         if (!ring->ready) {
 147                 dev_err(adev->dev, "couldn't schedule ib\n");
 148                 return -EINVAL;
 149         }
 150
 151         if (vm && !job->vm_id) {
 152                 dev_err(adev->dev, "VM IB without ID\n");
 153                 return -EINVAL;
 154         }
 155
 156         r = amdgpu_ring_alloc(ring, 256 * num_ibs);
 157         if (r) {
 158                 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
 159                 return r;
 160         }
 161
 162         if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec)
 163                 patch_offset = amdgpu_ring_init_cond_exec(ring);
 164
 165         if (vm) {
 166                 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
 167                                     job->gds_base, job->gds_size,
 168                                     job->gws_base, job->gws_size,
 169                                     job->oa_base, job->oa_size,
 170                                     (ring->current_ctx == ctx) && (old_vmid != vmid));
 171                 if (r) {
 172                         amdgpu_ring_undo(ring);
 173                         return r;
 174                 }
 175         }
 176
 177         if (ring->funcs->emit_hdp_flush)
 178                 amdgpu_ring_emit_hdp_flush(ring);
 179
 180         /* always set cond_exec_polling to CONTINUE */
 181         *ring->cond_exe_cpu_addr = 1;
 182
 183         skip_preamble = ring->current_ctx == ctx;
 184         need_ctx_switch = ring->current_ctx != ctx;
 185         for (i = 0; i < num_ibs; ++i) {
 186                 ib = &ibs[i];
 187                 /* drop preamble IBs if we don't have a context switch */
 188                 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
 189                         continue;
 190
 191                 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
 192                                     need_ctx_switch);
 193                 need_ctx_switch = false;
 194                 ring->vmid = vmid;
 195         }
 196
 197         if (ring->funcs->emit_hdp_invalidate)
 198                 amdgpu_ring_emit_hdp_invalidate(ring);
 199
 200         r = amdgpu_fence_emit(ring, &hwf);
 201         if (r) {
 202                 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
 203                 if (job && job->vm_id)
 204                         amdgpu_vm_reset_id(adev, job->vm_id);
 205                 ring->vmid = old_vmid;
 206                 amdgpu_ring_undo(ring);
 207                 return r;
 208         }
 209
 210         /* wrap the last IB with fence */
 211         if (job && job->uf_bo) {
 212                 uint64_t addr = amdgpu_bo_gpu_offset(job->uf_bo);
 213
 214                 addr += job->uf_offset;
 215                 amdgpu_ring_emit_fence(ring, addr, job->uf_sequence,
 216                                        AMDGPU_FENCE_FLAG_64BIT);
 217         }
 218
 219         if (f)
 220                 *f = fence_get(hwf);
 221
 222         if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
 223                 amdgpu_ring_patch_cond_exec(ring, patch_offset);
 224
 225         ring->current_ctx = ctx;
 226         amdgpu_ring_commit(ring);
 227         return 0;
 228 }
 229
 230 /**
 231  * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
 232  *
 233  * @adev: amdgpu_device pointer
 234  *
 235  * Initialize the suballocator to manage a pool of memory
 236  * for use as IBs (all asics).
 237  * Returns 0 on success, error on failure.
 238  */
 239 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 240 {
 241         int r;
 242
 243         if (adev->ib_pool_ready) {
 244                 return 0;
 245         }
 246         r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
 247                                       AMDGPU_IB_POOL_SIZE*64*1024,
 248                                       AMDGPU_GPU_PAGE_SIZE,
 249                                       AMDGPU_GEM_DOMAIN_GTT);
 250         if (r) {
 251                 return r;
 252         }
 253
 254         r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
 255         if (r) {
 256                 return r;
 257         }
 258
 259         adev->ib_pool_ready = true;
 260         if (amdgpu_debugfs_sa_init(adev)) {
 261                 dev_err(adev->dev, "failed to register debugfs file for SA\n");
 262         }
 263         return 0;
 264 }
 265
 266 /**
 267  * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
 268  *
 269  * @adev: amdgpu_device pointer
 270  *
 271  * Tear down the suballocator managing the pool of memory
 272  * for use as IBs (all asics).
 273  */
 274 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
 275 {
 276         if (adev->ib_pool_ready) {
 277                 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
 278                 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
 279                 adev->ib_pool_ready = false;
 280         }
 281 }
 282
 283 /**
 284  * amdgpu_ib_ring_tests - test IBs on the rings
 285  *
 286  * @adev: amdgpu_device pointer
 287  *
 288  * Test an IB (Indirect Buffer) on each ring.
 289  * If the test fails, disable the ring.
 290  * Returns 0 on success, error if the primary GFX ring
 291  * IB test fails.
 292  */
 293 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
 294 {
 295         unsigned i;
 296         int r;
 297
 298         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 299                 struct amdgpu_ring *ring = adev->rings[i];
 300
 301                 if (!ring || !ring->ready)
 302                         continue;
 303
 304                 r = amdgpu_ring_test_ib(ring);
 305                 if (r) {
 306                         ring->ready = false;
 307
 308                         if (ring == &adev->gfx.gfx_ring[0]) {
 309                                 /* oh, oh, that's really bad */
 310                                 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
 311                                 adev->accel_working = false;
 312                                 return r;
 313
 314                         } else {
 315                                 /* still not good, but we can live with it */
 316                                 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
 317                         }
 318                 }
 319         }
 320         return 0;
 321 }
 322
 323 /*
 324  * Debugfs info
 325  */
 326 #if defined(CONFIG_DEBUG_FS)
 327
 328 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
 329 {
 330         struct drm_info_node *node = (struct drm_info_node *) m->private;
 331         struct drm_device *dev = node->minor->dev;
 332         struct amdgpu_device *adev = dev->dev_private;
 333
 334         amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
 335
 336         return 0;
 337
 338 }
 339
 340 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
 341         {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
 342 };
 343
 344 #endif
 345
 346 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
 347 {
 348 #if defined(CONFIG_DEBUG_FS)
 349         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
 350 #else
 351         return 0;
 352 #endif
 353 }