drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  38 {
  39         if (adev->pp_enabled)
  40                 /* TODO */
  41                 return;
  42
  43         if (adev->pm.dpm_enabled) {
  44                 mutex_lock(&adev->pm.mutex);
  45                 if (power_supply_is_system_supplied() > 0)
  46                         adev->pm.dpm.ac_power = true;
  47                 else
  48                         adev->pm.dpm.ac_power = false;
  49                 if (adev->pm.funcs->enable_bapm)
  50                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  51                 mutex_unlock(&adev->pm.mutex);
  52         }
  53 }
  54
  55 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  56                                     struct device_attribute *attr,
  57                                     char *buf)
  58 {
  59         struct drm_device *ddev = dev_get_drvdata(dev);
  60         struct amdgpu_device *adev = ddev->dev_private;
  61         enum amd_pm_state_type pm;
  62
  63         if (adev->pp_enabled) {
  64                 pm = amdgpu_dpm_get_current_power_state(adev);
  65         } else
  66                 pm = adev->pm.dpm.user_state;
  67
  68         return snprintf(buf, PAGE_SIZE, "%s\n",
  69                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  70                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  71 }
  72
  73 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  74                                     struct device_attribute *attr,
  75                                     const char *buf,
  76                                     size_t count)
  77 {
  78         struct drm_device *ddev = dev_get_drvdata(dev);
  79         struct amdgpu_device *adev = ddev->dev_private;
  80         enum amd_pm_state_type  state;
  81
  82         if (strncmp("battery", buf, strlen("battery")) == 0)
  83                 state = POWER_STATE_TYPE_BATTERY;
  84         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
  85                 state = POWER_STATE_TYPE_BALANCED;
  86         else if (strncmp("performance", buf, strlen("performance")) == 0)
  87                 state = POWER_STATE_TYPE_PERFORMANCE;
  88         else {
  89                 count = -EINVAL;
  90                 goto fail;
  91         }
  92
  93         if (adev->pp_enabled) {
  94                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
  95         } else {
  96                 mutex_lock(&adev->pm.mutex);
  97                 adev->pm.dpm.user_state = state;
  98                 mutex_unlock(&adev->pm.mutex);
  99
 100                 /* Can't set dpm state when the card is off */
 101                 if (!(adev->flags & AMD_IS_PX) ||
 102                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 103                         amdgpu_pm_compute_clocks(adev);
 104         }
 105 fail:
 106         return count;
 107 }
 108
 109 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 110                                                 struct device_attribute *attr,
 111                                                                 char *buf)
 112 {
 113         struct drm_device *ddev = dev_get_drvdata(dev);
 114         struct amdgpu_device *adev = ddev->dev_private;
 115
 116         if  ((adev->flags & AMD_IS_PX) &&
 117              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 118                 return snprintf(buf, PAGE_SIZE, "off\n");
 119
 120         if (adev->pp_enabled) {
 121                 enum amd_dpm_forced_level level;
 122
 123                 level = amdgpu_dpm_get_performance_level(adev);
 124                 return snprintf(buf, PAGE_SIZE, "%s\n",
 125                                 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 126                                 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 127                                 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 128                                 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
 129         } else {
 130                 enum amdgpu_dpm_forced_level level;
 131
 132                 level = adev->pm.dpm.forced_level;
 133                 return snprintf(buf, PAGE_SIZE, "%s\n",
 134                                 (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 135                                 (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 136         }
 137 }
 138
 139 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 140                                                        struct device_attribute *attr,
 141                                                        const char *buf,
 142                                                        size_t count)
 143 {
 144         struct drm_device *ddev = dev_get_drvdata(dev);
 145         struct amdgpu_device *adev = ddev->dev_private;
 146         enum amdgpu_dpm_forced_level level;
 147         int ret = 0;
 148
 149         /* Can't force performance level when the card is off */
 150         if  ((adev->flags & AMD_IS_PX) &&
 151              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 152                 return -EINVAL;
 153
 154         if (strncmp("low", buf, strlen("low")) == 0) {
 155                 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
 156         } else if (strncmp("high", buf, strlen("high")) == 0) {
 157                 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
 158         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 159                 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
 160         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 161                 level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
 162         } else {
 163                 count = -EINVAL;
 164                 goto fail;
 165         }
 166
 167         if (adev->pp_enabled)
 168                 amdgpu_dpm_force_performance_level(adev, level);
 169         else {
 170                 mutex_lock(&adev->pm.mutex);
 171                 if (adev->pm.dpm.thermal_active) {
 172                         count = -EINVAL;
 173                         mutex_unlock(&adev->pm.mutex);
 174                         goto fail;
 175                 }
 176                 ret = amdgpu_dpm_force_performance_level(adev, level);
 177                 if (ret)
 178                         count = -EINVAL;
 179                 else
 180                         adev->pm.dpm.forced_level = level;
 181                 mutex_unlock(&adev->pm.mutex);
 182         }
 183 fail:
 184         return count;
 185 }
 186
 187 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 188                 struct device_attribute *attr,
 189                 char *buf)
 190 {
 191         struct drm_device *ddev = dev_get_drvdata(dev);
 192         struct amdgpu_device *adev = ddev->dev_private;
 193         struct pp_states_info data;
 194         int i, buf_len;
 195
 196         if (adev->pp_enabled)
 197                 amdgpu_dpm_get_pp_num_states(adev, &data);
 198
 199         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 200         for (i = 0; i < data.nums; i++)
 201                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 202                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 203                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 204                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 205                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 206
 207         return buf_len;
 208 }
 209
 210 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 211                 struct device_attribute *attr,
 212                 char *buf)
 213 {
 214         struct drm_device *ddev = dev_get_drvdata(dev);
 215         struct amdgpu_device *adev = ddev->dev_private;
 216         struct pp_states_info data;
 217         enum amd_pm_state_type pm = 0;
 218         int i = 0;
 219
 220         if (adev->pp_enabled) {
 221
 222                 pm = amdgpu_dpm_get_current_power_state(adev);
 223                 amdgpu_dpm_get_pp_num_states(adev, &data);
 224
 225                 for (i = 0; i < data.nums; i++) {
 226                         if (pm == data.states[i])
 227                                 break;
 228                 }
 229
 230                 if (i == data.nums)
 231                         i = -EINVAL;
 232         }
 233
 234         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 235 }
 236
 237 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 238                 struct device_attribute *attr,
 239                 char *buf)
 240 {
 241         struct drm_device *ddev = dev_get_drvdata(dev);
 242         struct amdgpu_device *adev = ddev->dev_private;
 243         struct pp_states_info data;
 244         enum amd_pm_state_type pm = 0;
 245         int i;
 246
 247         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 248                 pm = amdgpu_dpm_get_current_power_state(adev);
 249                 amdgpu_dpm_get_pp_num_states(adev, &data);
 250
 251                 for (i = 0; i < data.nums; i++) {
 252                         if (pm == data.states[i])
 253                                 break;
 254                 }
 255
 256                 if (i == data.nums)
 257                         i = -EINVAL;
 258
 259                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 260
 261         } else
 262                 return snprintf(buf, PAGE_SIZE, "\n");
 263 }
 264
 265 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 266                 struct device_attribute *attr,
 267                 const char *buf,
 268                 size_t count)
 269 {
 270         struct drm_device *ddev = dev_get_drvdata(dev);
 271         struct amdgpu_device *adev = ddev->dev_private;
 272         enum amd_pm_state_type state = 0;
 273         long idx;
 274         int ret;
 275
 276         if (strlen(buf) == 1)
 277                 adev->pp_force_state_enabled = false;
 278         else {
 279                 ret = kstrtol(buf, 0, &idx);
 280
 281                 if (ret) {
 282                         count = -EINVAL;
 283                         goto fail;
 284                 }
 285
 286                 if (adev->pp_enabled) {
 287                         struct pp_states_info data;
 288                         amdgpu_dpm_get_pp_num_states(adev, &data);
 289                         state = data.states[idx];
 290                         /* only set user selected power states */
 291                         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 292                                 state != POWER_STATE_TYPE_DEFAULT) {
 293                                 amdgpu_dpm_dispatch_task(adev,
 294                                                 AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 295                                 adev->pp_force_state_enabled = true;
 296                         }
 297                 }
 298         }
 299 fail:
 300         return count;
 301 }
 302
 303 static ssize_t amdgpu_get_pp_table(struct device *dev,
 304                 struct device_attribute *attr,
 305                 char *buf)
 306 {
 307         struct drm_device *ddev = dev_get_drvdata(dev);
 308         struct amdgpu_device *adev = ddev->dev_private;
 309         char *table = NULL;
 310         int size, i;
 311
 312         if (adev->pp_enabled)
 313                 size = amdgpu_dpm_get_pp_table(adev, &table);
 314         else
 315                 return 0;
 316
 317         if (size >= PAGE_SIZE)
 318                 size = PAGE_SIZE - 1;
 319
 320         for (i = 0; i < size; i++) {
 321                 sprintf(buf + i, "%02x", table[i]);
 322         }
 323         sprintf(buf + i, "\n");
 324
 325         return size;
 326 }
 327
 328 static ssize_t amdgpu_set_pp_table(struct device *dev,
 329                 struct device_attribute *attr,
 330                 const char *buf,
 331                 size_t count)
 332 {
 333         struct drm_device *ddev = dev_get_drvdata(dev);
 334         struct amdgpu_device *adev = ddev->dev_private;
 335
 336         if (adev->pp_enabled)
 337                 amdgpu_dpm_set_pp_table(adev, buf, count);
 338
 339         return count;
 340 }
 341
 342 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 343                 struct device_attribute *attr,
 344                 char *buf)
 345 {
 346         struct drm_device *ddev = dev_get_drvdata(dev);
 347         struct amdgpu_device *adev = ddev->dev_private;
 348         ssize_t size = 0;
 349
 350         if (adev->pp_enabled)
 351                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 352
 353         return size;
 354 }
 355
 356 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 357                 struct device_attribute *attr,
 358                 const char *buf,
 359                 size_t count)
 360 {
 361         struct drm_device *ddev = dev_get_drvdata(dev);
 362         struct amdgpu_device *adev = ddev->dev_private;
 363         int ret;
 364         long level;
 365         uint32_t i, mask = 0;
 366         char sub_str[2];
 367
 368         for (i = 0; i < strlen(buf) - 1; i++) {
 369                 sub_str[0] = *(buf + i);
 370                 sub_str[1] = '\0';
 371                 ret = kstrtol(sub_str, 0, &level);
 372
 373                 if (ret) {
 374                         count = -EINVAL;
 375                         goto fail;
 376                 }
 377                 mask |= 1 << level;
 378         }
 379
 380         if (adev->pp_enabled)
 381                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 382 fail:
 383         return count;
 384 }
 385
 386 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 387                 struct device_attribute *attr,
 388                 char *buf)
 389 {
 390         struct drm_device *ddev = dev_get_drvdata(dev);
 391         struct amdgpu_device *adev = ddev->dev_private;
 392         ssize_t size = 0;
 393
 394         if (adev->pp_enabled)
 395                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 396
 397         return size;
 398 }
 399
 400 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 401                 struct device_attribute *attr,
 402                 const char *buf,
 403                 size_t count)
 404 {
 405         struct drm_device *ddev = dev_get_drvdata(dev);
 406         struct amdgpu_device *adev = ddev->dev_private;
 407         int ret;
 408         long level;
 409         uint32_t i, mask = 0;
 410         char sub_str[2];
 411
 412         for (i = 0; i < strlen(buf) - 1; i++) {
 413                 sub_str[0] = *(buf + i);
 414                 sub_str[1] = '\0';
 415                 ret = kstrtol(sub_str, 0, &level);
 416
 417                 if (ret) {
 418                         count = -EINVAL;
 419                         goto fail;
 420                 }
 421                 mask |= 1 << level;
 422         }
 423
 424         if (adev->pp_enabled)
 425                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 426 fail:
 427         return count;
 428 }
 429
 430 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 431                 struct device_attribute *attr,
 432                 char *buf)
 433 {
 434         struct drm_device *ddev = dev_get_drvdata(dev);
 435         struct amdgpu_device *adev = ddev->dev_private;
 436         ssize_t size = 0;
 437
 438         if (adev->pp_enabled)
 439                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 440
 441         return size;
 442 }
 443
 444 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 445                 struct device_attribute *attr,
 446                 const char *buf,
 447                 size_t count)
 448 {
 449         struct drm_device *ddev = dev_get_drvdata(dev);
 450         struct amdgpu_device *adev = ddev->dev_private;
 451         int ret;
 452         long level;
 453         uint32_t i, mask = 0;
 454         char sub_str[2];
 455
 456         for (i = 0; i < strlen(buf) - 1; i++) {
 457                 sub_str[0] = *(buf + i);
 458                 sub_str[1] = '\0';
 459                 ret = kstrtol(sub_str, 0, &level);
 460
 461                 if (ret) {
 462                         count = -EINVAL;
 463                         goto fail;
 464                 }
 465                 mask |= 1 << level;
 466         }
 467
 468         if (adev->pp_enabled)
 469                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 470 fail:
 471         return count;
 472 }
 473
 474 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 475 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 476                    amdgpu_get_dpm_forced_performance_level,
 477                    amdgpu_set_dpm_forced_performance_level);
 478 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 479 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 480 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 481                 amdgpu_get_pp_force_state,
 482                 amdgpu_set_pp_force_state);
 483 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 484                 amdgpu_get_pp_table,
 485                 amdgpu_set_pp_table);
 486 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 487                 amdgpu_get_pp_dpm_sclk,
 488                 amdgpu_set_pp_dpm_sclk);
 489 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 490                 amdgpu_get_pp_dpm_mclk,
 491                 amdgpu_set_pp_dpm_mclk);
 492 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 493                 amdgpu_get_pp_dpm_pcie,
 494                 amdgpu_set_pp_dpm_pcie);
 495
 496 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 497                                       struct device_attribute *attr,
 498                                       char *buf)
 499 {
 500         struct amdgpu_device *adev = dev_get_drvdata(dev);
 501         struct drm_device *ddev = adev->ddev;
 502         int temp;
 503
 504         /* Can't get temperature when the card is off */
 505         if  ((adev->flags & AMD_IS_PX) &&
 506              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 507                 return -EINVAL;
 508
 509         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 510                 temp = 0;
 511         else
 512                 temp = amdgpu_dpm_get_temperature(adev);
 513
 514         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 515 }
 516
 517 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 518                                              struct device_attribute *attr,
 519                                              char *buf)
 520 {
 521         struct amdgpu_device *adev = dev_get_drvdata(dev);
 522         int hyst = to_sensor_dev_attr(attr)->index;
 523         int temp;
 524
 525         if (hyst)
 526                 temp = adev->pm.dpm.thermal.min_temp;
 527         else
 528                 temp = adev->pm.dpm.thermal.max_temp;
 529
 530         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 531 }
 532
 533 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 534                                             struct device_attribute *attr,
 535                                             char *buf)
 536 {
 537         struct amdgpu_device *adev = dev_get_drvdata(dev);
 538         u32 pwm_mode = 0;
 539
 540         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 541                 return -EINVAL;
 542
 543         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 544
 545         /* never 0 (full-speed), fuse or smc-controlled always */
 546         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 547 }
 548
 549 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 550                                             struct device_attribute *attr,
 551                                             const char *buf,
 552                                             size_t count)
 553 {
 554         struct amdgpu_device *adev = dev_get_drvdata(dev);
 555         int err;
 556         int value;
 557
 558         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 559                 return -EINVAL;
 560
 561         err = kstrtoint(buf, 10, &value);
 562         if (err)
 563                 return err;
 564
 565         switch (value) {
 566         case 1: /* manual, percent-based */
 567                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 568                 break;
 569         default: /* disable */
 570                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 571                 break;
 572         }
 573
 574         return count;
 575 }
 576
 577 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 578                                          struct device_attribute *attr,
 579                                          char *buf)
 580 {
 581         return sprintf(buf, "%i\n", 0);
 582 }
 583
 584 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 585                                          struct device_attribute *attr,
 586                                          char *buf)
 587 {
 588         return sprintf(buf, "%i\n", 255);
 589 }
 590
 591 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 592                                      struct device_attribute *attr,
 593                                      const char *buf, size_t count)
 594 {
 595         struct amdgpu_device *adev = dev_get_drvdata(dev);
 596         int err;
 597         u32 value;
 598
 599         err = kstrtou32(buf, 10, &value);
 600         if (err)
 601                 return err;
 602
 603         value = (value * 100) / 255;
 604
 605         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 606         if (err)
 607                 return err;
 608
 609         return count;
 610 }
 611
 612 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 613                                      struct device_attribute *attr,
 614                                      char *buf)
 615 {
 616         struct amdgpu_device *adev = dev_get_drvdata(dev);
 617         int err;
 618         u32 speed;
 619
 620         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 621         if (err)
 622                 return err;
 623
 624         speed = (speed * 255) / 100;
 625
 626         return sprintf(buf, "%i\n", speed);
 627 }
 628
 629 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 630 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 631 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 632 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 633 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 634 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 635 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 636
 637 static struct attribute *hwmon_attributes[] = {
 638         &sensor_dev_attr_temp1_input.dev_attr.attr,
 639         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 640         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 641         &sensor_dev_attr_pwm1.dev_attr.attr,
 642         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 643         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 644         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 645         NULL
 646 };
 647
 648 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 649                                         struct attribute *attr, int index)
 650 {
 651         struct device *dev = kobj_to_dev(kobj);
 652         struct amdgpu_device *adev = dev_get_drvdata(dev);
 653         umode_t effective_mode = attr->mode;
 654
 655         /* Skip limit attributes if DPM is not enabled */
 656         if (!adev->pm.dpm_enabled &&
 657             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 658              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 659              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 660              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 661              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 662              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 663                 return 0;
 664
 665         if (adev->pp_enabled)
 666                 return effective_mode;
 667
 668         /* Skip fan attributes if fan is not present */
 669         if (adev->pm.no_fan &&
 670             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 671              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 672              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 673              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 674                 return 0;
 675
 676         /* mask fan attributes if we have no bindings for this asic to expose */
 677         if ((!adev->pm.funcs->get_fan_speed_percent &&
 678              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 679             (!adev->pm.funcs->get_fan_control_mode &&
 680              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 681                 effective_mode &= ~S_IRUGO;
 682
 683         if ((!adev->pm.funcs->set_fan_speed_percent &&
 684              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 685             (!adev->pm.funcs->set_fan_control_mode &&
 686              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 687                 effective_mode &= ~S_IWUSR;
 688
 689         /* hide max/min values if we can't both query and manage the fan */
 690         if ((!adev->pm.funcs->set_fan_speed_percent &&
 691              !adev->pm.funcs->get_fan_speed_percent) &&
 692             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 693              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 694                 return 0;
 695
 696         return effective_mode;
 697 }
 698
 699 static const struct attribute_group hwmon_attrgroup = {
 700         .attrs = hwmon_attributes,
 701         .is_visible = hwmon_attributes_visible,
 702 };
 703
 704 static const struct attribute_group *hwmon_groups[] = {
 705         &hwmon_attrgroup,
 706         NULL
 707 };
 708
 709 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 710 {
 711         struct amdgpu_device *adev =
 712                 container_of(work, struct amdgpu_device,
 713                              pm.dpm.thermal.work);
 714         /* switch to the thermal state */
 715         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 716
 717         if (!adev->pm.dpm_enabled)
 718                 return;
 719
 720         if (adev->pm.funcs->get_temperature) {
 721                 int temp = amdgpu_dpm_get_temperature(adev);
 722
 723                 if (temp < adev->pm.dpm.thermal.min_temp)
 724                         /* switch back the user state */
 725                         dpm_state = adev->pm.dpm.user_state;
 726         } else {
 727                 if (adev->pm.dpm.thermal.high_to_low)
 728                         /* switch back the user state */
 729                         dpm_state = adev->pm.dpm.user_state;
 730         }
 731         mutex_lock(&adev->pm.mutex);
 732         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 733                 adev->pm.dpm.thermal_active = true;
 734         else
 735                 adev->pm.dpm.thermal_active = false;
 736         adev->pm.dpm.state = dpm_state;
 737         mutex_unlock(&adev->pm.mutex);
 738
 739         amdgpu_pm_compute_clocks(adev);
 740 }
 741
 742 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 743                                                      enum amd_pm_state_type dpm_state)
 744 {
 745         int i;
 746         struct amdgpu_ps *ps;
 747         u32 ui_class;
 748         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 749                 true : false;
 750
 751         /* check if the vblank period is too short to adjust the mclk */
 752         if (single_display && adev->pm.funcs->vblank_too_short) {
 753                 if (amdgpu_dpm_vblank_too_short(adev))
 754                         single_display = false;
 755         }
 756
 757         /* certain older asics have a separare 3D performance state,
 758          * so try that first if the user selected performance
 759          */
 760         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 761                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 762         /* balanced states don't exist at the moment */
 763         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 764                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 765
 766 restart_search:
 767         /* Pick the best power state based on current conditions */
 768         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 769                 ps = &adev->pm.dpm.ps[i];
 770                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 771                 switch (dpm_state) {
 772                 /* user states */
 773                 case POWER_STATE_TYPE_BATTERY:
 774                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 775                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 776                                         if (single_display)
 777                                                 return ps;
 778                                 } else
 779                                         return ps;
 780                         }
 781                         break;
 782                 case POWER_STATE_TYPE_BALANCED:
 783                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 784                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 785                                         if (single_display)
 786                                                 return ps;
 787                                 } else
 788                                         return ps;
 789                         }
 790                         break;
 791                 case POWER_STATE_TYPE_PERFORMANCE:
 792                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 793                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 794                                         if (single_display)
 795                                                 return ps;
 796                                 } else
 797                                         return ps;
 798                         }
 799                         break;
 800                 /* internal states */
 801                 case POWER_STATE_TYPE_INTERNAL_UVD:
 802                         if (adev->pm.dpm.uvd_ps)
 803                                 return adev->pm.dpm.uvd_ps;
 804                         else
 805                                 break;
 806                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 807                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 808                                 return ps;
 809                         break;
 810                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 811                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 812                                 return ps;
 813                         break;
 814                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 815                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 816                                 return ps;
 817                         break;
 818                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 819                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 820                                 return ps;
 821                         break;
 822                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 823                         return adev->pm.dpm.boot_ps;
 824                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 825                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 826                                 return ps;
 827                         break;
 828                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 829                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 830                                 return ps;
 831                         break;
 832                 case POWER_STATE_TYPE_INTERNAL_ULV:
 833                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 834                                 return ps;
 835                         break;
 836                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 837                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 838                                 return ps;
 839                         break;
 840                 default:
 841                         break;
 842                 }
 843         }
 844         /* use a fallback state if we didn't match */
 845         switch (dpm_state) {
 846         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 847                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 848                 goto restart_search;
 849         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 850         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 851         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 852                 if (adev->pm.dpm.uvd_ps) {
 853                         return adev->pm.dpm.uvd_ps;
 854                 } else {
 855                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 856                         goto restart_search;
 857                 }
 858         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 859                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 860                 goto restart_search;
 861         case POWER_STATE_TYPE_INTERNAL_ACPI:
 862                 dpm_state = POWER_STATE_TYPE_BATTERY;
 863                 goto restart_search;
 864         case POWER_STATE_TYPE_BATTERY:
 865         case POWER_STATE_TYPE_BALANCED:
 866         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 867                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 868                 goto restart_search;
 869         default:
 870                 break;
 871         }
 872
 873         return NULL;
 874 }
 875
 876 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 877 {
 878         int i;
 879         struct amdgpu_ps *ps;
 880         enum amd_pm_state_type dpm_state;
 881         int ret;
 882
 883         /* if dpm init failed */
 884         if (!adev->pm.dpm_enabled)
 885                 return;
 886
 887         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
 888                 /* add other state override checks here */
 889                 if ((!adev->pm.dpm.thermal_active) &&
 890                     (!adev->pm.dpm.uvd_active))
 891                         adev->pm.dpm.state = adev->pm.dpm.user_state;
 892         }
 893         dpm_state = adev->pm.dpm.state;
 894
 895         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
 896         if (ps)
 897                 adev->pm.dpm.requested_ps = ps;
 898         else
 899                 return;
 900
 901         /* no need to reprogram if nothing changed unless we are on BTC+ */
 902         if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
 903                 /* vce just modifies an existing state so force a change */
 904                 if (ps->vce_active != adev->pm.dpm.vce_active)
 905                         goto force;
 906                 if (adev->flags & AMD_IS_APU) {
 907                         /* for APUs if the num crtcs changed but state is the same,
 908                          * all we need to do is update the display configuration.
 909                          */
 910                         if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
 911                                 /* update display watermarks based on new power state */
 912                                 amdgpu_display_bandwidth_update(adev);
 913                                 /* update displays */
 914                                 amdgpu_dpm_display_configuration_changed(adev);
 915                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 916                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 917                         }
 918                         return;
 919                 } else {
 920                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 921                          * nothing to do, if the num crtcs is > 1 and state is the same,
 922                          * update display configuration.
 923                          */
 924                         if (adev->pm.dpm.new_active_crtcs ==
 925                             adev->pm.dpm.current_active_crtcs) {
 926                                 return;
 927                         } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
 928                                    (adev->pm.dpm.new_active_crtc_count > 1)) {
 929                                 /* update display watermarks based on new power state */
 930                                 amdgpu_display_bandwidth_update(adev);
 931                                 /* update displays */
 932                                 amdgpu_dpm_display_configuration_changed(adev);
 933                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 934                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 935                                 return;
 936                         }
 937                 }
 938         }
 939
 940 force:
 941         if (amdgpu_dpm == 1) {
 942                 printk("switching from power state:\n");
 943                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
 944                 printk("switching to power state:\n");
 945                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
 946         }
 947
 948         /* update whether vce is active */
 949         ps->vce_active = adev->pm.dpm.vce_active;
 950
 951         ret = amdgpu_dpm_pre_set_power_state(adev);
 952         if (ret)
 953                 return;
 954
 955         /* update display watermarks based on new power state */
 956         amdgpu_display_bandwidth_update(adev);
 957
 958         /* wait for the rings to drain */
 959         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 960                 struct amdgpu_ring *ring = adev->rings[i];
 961                 if (ring && ring->ready)
 962                         amdgpu_fence_wait_empty(ring);
 963         }
 964
 965         /* program the new power state */
 966         amdgpu_dpm_set_power_state(adev);
 967
 968         /* update current power state */
 969         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
 970
 971         amdgpu_dpm_post_set_power_state(adev);
 972
 973         /* update displays */
 974         amdgpu_dpm_display_configuration_changed(adev);
 975
 976         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
 977         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
 978
 979         if (adev->pm.funcs->force_performance_level) {
 980                 if (adev->pm.dpm.thermal_active) {
 981                         enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
 982                         /* force low perf level for thermal */
 983                         amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
 984                         /* save the user's level */
 985                         adev->pm.dpm.forced_level = level;
 986                 } else {
 987                         /* otherwise, user selected level */
 988                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
 989                 }
 990         }
 991 }
 992
 993 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 994 {
 995         if (adev->pp_enabled)
 996                 amdgpu_dpm_powergate_uvd(adev, !enable);
 997         else {
 998                 if (adev->pm.funcs->powergate_uvd) {
 999                         mutex_lock(&adev->pm.mutex);
1000                         /* enable/disable UVD */
1001                         amdgpu_dpm_powergate_uvd(adev, !enable);
1002                         mutex_unlock(&adev->pm.mutex);
1003                 } else {
1004                         if (enable) {
1005                                 mutex_lock(&adev->pm.mutex);
1006                                 adev->pm.dpm.uvd_active = true;
1007                                 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1008                                 mutex_unlock(&adev->pm.mutex);
1009                         } else {
1010                                 mutex_lock(&adev->pm.mutex);
1011                                 adev->pm.dpm.uvd_active = false;
1012                                 mutex_unlock(&adev->pm.mutex);
1013                         }
1014                         amdgpu_pm_compute_clocks(adev);
1015                 }
1016
1017         }
1018 }
1019
1020 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1021 {
1022         if (adev->pp_enabled)
1023                 amdgpu_dpm_powergate_vce(adev, !enable);
1024         else {
1025                 if (adev->pm.funcs->powergate_vce) {
1026                         mutex_lock(&adev->pm.mutex);
1027                         amdgpu_dpm_powergate_vce(adev, !enable);
1028                         mutex_unlock(&adev->pm.mutex);
1029                 } else {
1030                         if (enable) {
1031                                 mutex_lock(&adev->pm.mutex);
1032                                 adev->pm.dpm.vce_active = true;
1033                                 /* XXX select vce level based on ring/task */
1034                                 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
1035                                 mutex_unlock(&adev->pm.mutex);
1036                         } else {
1037                                 mutex_lock(&adev->pm.mutex);
1038                                 adev->pm.dpm.vce_active = false;
1039                                 mutex_unlock(&adev->pm.mutex);
1040                         }
1041                         amdgpu_pm_compute_clocks(adev);
1042                 }
1043         }
1044 }
1045
1046 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1047 {
1048         int i;
1049
1050         if (adev->pp_enabled)
1051                 /* TO DO */
1052                 return;
1053
1054         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1055                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1056
1057 }
1058
1059 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1060 {
1061         int ret;
1062
1063         if (adev->pm.sysfs_initialized)
1064                 return 0;
1065
1066         if (!adev->pp_enabled) {
1067                 if (adev->pm.funcs->get_temperature == NULL)
1068                         return 0;
1069         }
1070
1071         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1072                                                                    DRIVER_NAME, adev,
1073                                                                    hwmon_groups);
1074         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1075                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1076                 dev_err(adev->dev,
1077                         "Unable to register hwmon device: %d\n", ret);
1078                 return ret;
1079         }
1080
1081         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1082         if (ret) {
1083                 DRM_ERROR("failed to create device file for dpm state\n");
1084                 return ret;
1085         }
1086         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1087         if (ret) {
1088                 DRM_ERROR("failed to create device file for dpm state\n");
1089                 return ret;
1090         }
1091
1092         if (adev->pp_enabled) {
1093                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1094                 if (ret) {
1095                         DRM_ERROR("failed to create device file pp_num_states\n");
1096                         return ret;
1097                 }
1098                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1099                 if (ret) {
1100                         DRM_ERROR("failed to create device file pp_cur_state\n");
1101                         return ret;
1102                 }
1103                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1104                 if (ret) {
1105                         DRM_ERROR("failed to create device file pp_force_state\n");
1106                         return ret;
1107                 }
1108                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1109                 if (ret) {
1110                         DRM_ERROR("failed to create device file pp_table\n");
1111                         return ret;
1112                 }
1113                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1114                 if (ret) {
1115                         DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1116                         return ret;
1117                 }
1118                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1119                 if (ret) {
1120                         DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1121                         return ret;
1122                 }
1123                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1124                 if (ret) {
1125                         DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1126                         return ret;
1127                 }
1128         }
1129         ret = amdgpu_debugfs_pm_init(adev);
1130         if (ret) {
1131                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1132                 return ret;
1133         }
1134
1135         adev->pm.sysfs_initialized = true;
1136
1137         return 0;
1138 }
1139
1140 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1141 {
1142         if (adev->pm.int_hwmon_dev)
1143                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1144         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1145         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1146         if (adev->pp_enabled) {
1147                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1148                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1149                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1150                 device_remove_file(adev->dev, &dev_attr_pp_table);
1151                 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1152                 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1153                 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1154         }
1155 }
1156
1157 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1158 {
1159         struct drm_device *ddev = adev->ddev;
1160         struct drm_crtc *crtc;
1161         struct amdgpu_crtc *amdgpu_crtc;
1162
1163         if (!adev->pm.dpm_enabled)
1164                 return;
1165
1166         if (adev->pp_enabled) {
1167                 int i = 0;
1168
1169                 amdgpu_display_bandwidth_update(adev);
1170                 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1171                         struct amdgpu_ring *ring = adev->rings[i];
1172                         if (ring && ring->ready)
1173                                 amdgpu_fence_wait_empty(ring);
1174                 }
1175
1176                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1177         } else {
1178                 mutex_lock(&adev->pm.mutex);
1179                 adev->pm.dpm.new_active_crtcs = 0;
1180                 adev->pm.dpm.new_active_crtc_count = 0;
1181                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1182                         list_for_each_entry(crtc,
1183                                             &ddev->mode_config.crtc_list, head) {
1184                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1185                                 if (crtc->enabled) {
1186                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1187                                         adev->pm.dpm.new_active_crtc_count++;
1188                                 }
1189                         }
1190                 }
1191                 /* update battery/ac status */
1192                 if (power_supply_is_system_supplied() > 0)
1193                         adev->pm.dpm.ac_power = true;
1194                 else
1195                         adev->pm.dpm.ac_power = false;
1196
1197                 amdgpu_dpm_change_power_state_locked(adev);
1198
1199                 mutex_unlock(&adev->pm.mutex);
1200         }
1201 }
1202
1203 /*
1204  * Debugfs info
1205  */
1206 #if defined(CONFIG_DEBUG_FS)
1207
1208 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1209 {
1210         struct drm_info_node *node = (struct drm_info_node *) m->private;
1211         struct drm_device *dev = node->minor->dev;
1212         struct amdgpu_device *adev = dev->dev_private;
1213         struct drm_device *ddev = adev->ddev;
1214
1215         if (!adev->pm.dpm_enabled) {
1216                 seq_printf(m, "dpm not enabled\n");
1217                 return 0;
1218         }
1219         if  ((adev->flags & AMD_IS_PX) &&
1220              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1221                 seq_printf(m, "PX asic powered off\n");
1222         } else if (adev->pp_enabled) {
1223                 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1224         } else {
1225                 mutex_lock(&adev->pm.mutex);
1226                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1227                         amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1228                 else
1229                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1230                 mutex_unlock(&adev->pm.mutex);
1231         }
1232
1233         return 0;
1234 }
1235
1236 static const struct drm_info_list amdgpu_pm_info_list[] = {
1237         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1238 };
1239 #endif
1240
1241 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1242 {
1243 #if defined(CONFIG_DEBUG_FS)
1244         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1245 #else
1246         return 0;
1247 #endif
1248 }