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[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44 #define FIMD_DEFAULT_FRAMERATE 60
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70 /* I80 / RGB trigger control register */
71 #define TRIGCON 0x1A4
72 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
73 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
74
75 /* display mode change control register except exynos4 */
76 #define VIDOUT_CON 0x000
77 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
78
79 /* I80 interface control for main LDI register */
80 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
81 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
82 #define LCD_CS_SETUP(x) ((x) << 16)
83 #define LCD_WR_SETUP(x) ((x) << 12)
84 #define LCD_WR_ACTIVE(x) ((x) << 8)
85 #define LCD_WR_HOLD(x) ((x) << 4)
86 #define I80IFEN_ENABLE (1 << 0)
87
88 /* FIMD has totally five hardware windows. */
89 #define WINDOWS_NR 5
90
91 struct fimd_driver_data {
92 unsigned int timing_base;
93 unsigned int lcdblk_offset;
94 unsigned int lcdblk_vt_shift;
95 unsigned int lcdblk_bypass_shift;
96
97 unsigned int has_shadowcon:1;
98 unsigned int has_clksel:1;
99 unsigned int has_limited_fmt:1;
100 unsigned int has_vidoutcon:1;
101 unsigned int has_vtsel:1;
102 };
103
104 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
105 .timing_base = 0x0,
106 .has_clksel = 1,
107 .has_limited_fmt = 1,
108 };
109
110 static struct fimd_driver_data exynos3_fimd_driver_data = {
111 .timing_base = 0x20000,
112 .lcdblk_offset = 0x210,
113 .lcdblk_bypass_shift = 1,
114 .has_shadowcon = 1,
115 .has_vidoutcon = 1,
116 };
117
118 static struct fimd_driver_data exynos4_fimd_driver_data = {
119 .timing_base = 0x0,
120 .lcdblk_offset = 0x210,
121 .lcdblk_vt_shift = 10,
122 .lcdblk_bypass_shift = 1,
123 .has_shadowcon = 1,
124 .has_vtsel = 1,
125 };
126
127 static struct fimd_driver_data exynos4415_fimd_driver_data = {
128 .timing_base = 0x20000,
129 .lcdblk_offset = 0x210,
130 .lcdblk_vt_shift = 10,
131 .lcdblk_bypass_shift = 1,
132 .has_shadowcon = 1,
133 .has_vidoutcon = 1,
134 .has_vtsel = 1,
135 };
136
137 static struct fimd_driver_data exynos5_fimd_driver_data = {
138 .timing_base = 0x20000,
139 .lcdblk_offset = 0x214,
140 .lcdblk_vt_shift = 24,
141 .lcdblk_bypass_shift = 15,
142 .has_shadowcon = 1,
143 .has_vidoutcon = 1,
144 .has_vtsel = 1,
145 };
146
147 struct fimd_context {
148 struct device *dev;
149 struct drm_device *drm_dev;
150 struct exynos_drm_crtc *crtc;
151 struct exynos_drm_plane planes[WINDOWS_NR];
152 struct clk *bus_clk;
153 struct clk *lcd_clk;
154 void __iomem *regs;
155 struct regmap *sysreg;
156 unsigned int default_win;
157 unsigned long irq_flags;
158 u32 vidcon0;
159 u32 vidcon1;
160 u32 vidout_con;
161 u32 i80ifcon;
162 bool i80_if;
163 bool suspended;
164 int pipe;
165 wait_queue_head_t wait_vsync_queue;
166 atomic_t wait_vsync_event;
167 atomic_t win_updated;
168 atomic_t triggering;
169
170 struct exynos_drm_panel_info panel;
171 struct fimd_driver_data *driver_data;
172 struct exynos_drm_display *display;
173 };
174
175 static const struct of_device_id fimd_driver_dt_match[] = {
176 { .compatible = "samsung,s3c6400-fimd",
177 .data = &s3c64xx_fimd_driver_data },
178 { .compatible = "samsung,exynos3250-fimd",
179 .data = &exynos3_fimd_driver_data },
180 { .compatible = "samsung,exynos4210-fimd",
181 .data = &exynos4_fimd_driver_data },
182 { .compatible = "samsung,exynos4415-fimd",
183 .data = &exynos4415_fimd_driver_data },
184 { .compatible = "samsung,exynos5250-fimd",
185 .data = &exynos5_fimd_driver_data },
186 {},
187 };
188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
189
190 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
191 struct platform_device *pdev)
192 {
193 const struct of_device_id *of_id =
194 of_match_device(fimd_driver_dt_match, &pdev->dev);
195
196 return (struct fimd_driver_data *)of_id->data;
197 }
198
199 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
200 {
201 struct fimd_context *ctx = crtc->ctx;
202
203 if (ctx->suspended)
204 return;
205
206 atomic_set(&ctx->wait_vsync_event, 1);
207
208 /*
209 * wait for FIMD to signal VSYNC interrupt or return after
210 * timeout which is set to 50ms (refresh rate of 20).
211 */
212 if (!wait_event_timeout(ctx->wait_vsync_queue,
213 !atomic_read(&ctx->wait_vsync_event),
214 HZ/20))
215 DRM_DEBUG_KMS("vblank wait timed out.\n");
216 }
217
218 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
219 bool enable)
220 {
221 u32 val = readl(ctx->regs + WINCON(win));
222
223 if (enable)
224 val |= WINCONx_ENWIN;
225 else
226 val &= ~WINCONx_ENWIN;
227
228 writel(val, ctx->regs + WINCON(win));
229 }
230
231 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
232 bool enable)
233 {
234 u32 val = readl(ctx->regs + SHADOWCON);
235
236 if (enable)
237 val |= SHADOWCON_CHx_ENABLE(win);
238 else
239 val &= ~SHADOWCON_CHx_ENABLE(win);
240
241 writel(val, ctx->regs + SHADOWCON);
242 }
243
244 static void fimd_clear_channel(struct fimd_context *ctx)
245 {
246 int win, ch_enabled = 0;
247
248 DRM_DEBUG_KMS("%s\n", __FILE__);
249
250 /* Check if any channel is enabled. */
251 for (win = 0; win < WINDOWS_NR; win++) {
252 u32 val = readl(ctx->regs + WINCON(win));
253
254 if (val & WINCONx_ENWIN) {
255 fimd_enable_video_output(ctx, win, false);
256
257 if (ctx->driver_data->has_shadowcon)
258 fimd_enable_shadow_channel_path(ctx, win,
259 false);
260
261 ch_enabled = 1;
262 }
263 }
264
265 /* Wait for vsync, as disable channel takes effect at next vsync */
266 if (ch_enabled) {
267 unsigned int state = ctx->suspended;
268
269 ctx->suspended = 0;
270 fimd_wait_for_vblank(ctx->crtc);
271 ctx->suspended = state;
272 }
273 }
274
275 static int fimd_iommu_attach_devices(struct fimd_context *ctx,
276 struct drm_device *drm_dev)
277 {
278
279 /* attach this sub driver to iommu mapping if supported. */
280 if (is_drm_iommu_supported(ctx->drm_dev)) {
281 int ret;
282
283 /*
284 * If any channel is already active, iommu will throw
285 * a PAGE FAULT when enabled. So clear any channel if enabled.
286 */
287 fimd_clear_channel(ctx);
288 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
289 if (ret) {
290 DRM_ERROR("drm_iommu_attach failed.\n");
291 return ret;
292 }
293
294 }
295
296 return 0;
297 }
298
299 static void fimd_iommu_detach_devices(struct fimd_context *ctx)
300 {
301 /* detach this sub driver from iommu mapping if supported. */
302 if (is_drm_iommu_supported(ctx->drm_dev))
303 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
304 }
305
306 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
307 const struct drm_display_mode *mode)
308 {
309 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
310 u32 clkdiv;
311
312 if (ctx->i80_if) {
313 /*
314 * The frame done interrupt should be occurred prior to the
315 * next TE signal.
316 */
317 ideal_clk *= 2;
318 }
319
320 /* Find the clock divider value that gets us closest to ideal_clk */
321 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
322
323 return (clkdiv < 0x100) ? clkdiv : 0xff;
324 }
325
326 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
327 const struct drm_display_mode *mode,
328 struct drm_display_mode *adjusted_mode)
329 {
330 if (adjusted_mode->vrefresh == 0)
331 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
332
333 return true;
334 }
335
336 static void fimd_commit(struct exynos_drm_crtc *crtc)
337 {
338 struct fimd_context *ctx = crtc->ctx;
339 struct drm_display_mode *mode = &crtc->base.mode;
340 struct fimd_driver_data *driver_data = ctx->driver_data;
341 void *timing_base = ctx->regs + driver_data->timing_base;
342 u32 val, clkdiv;
343
344 if (ctx->suspended)
345 return;
346
347 /* nothing to do if we haven't set the mode yet */
348 if (mode->htotal == 0 || mode->vtotal == 0)
349 return;
350
351 if (ctx->i80_if) {
352 val = ctx->i80ifcon | I80IFEN_ENABLE;
353 writel(val, timing_base + I80IFCONFAx(0));
354
355 /* disable auto frame rate */
356 writel(0, timing_base + I80IFCONFBx(0));
357
358 /* set video type selection to I80 interface */
359 if (driver_data->has_vtsel && ctx->sysreg &&
360 regmap_update_bits(ctx->sysreg,
361 driver_data->lcdblk_offset,
362 0x3 << driver_data->lcdblk_vt_shift,
363 0x1 << driver_data->lcdblk_vt_shift)) {
364 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
365 return;
366 }
367 } else {
368 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
369 u32 vidcon1;
370
371 /* setup polarity values */
372 vidcon1 = ctx->vidcon1;
373 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
374 vidcon1 |= VIDCON1_INV_VSYNC;
375 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
376 vidcon1 |= VIDCON1_INV_HSYNC;
377 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
378
379 /* setup vertical timing values. */
380 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
381 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
382 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
383
384 val = VIDTCON0_VBPD(vbpd - 1) |
385 VIDTCON0_VFPD(vfpd - 1) |
386 VIDTCON0_VSPW(vsync_len - 1);
387 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
388
389 /* setup horizontal timing values. */
390 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
391 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
392 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
393
394 val = VIDTCON1_HBPD(hbpd - 1) |
395 VIDTCON1_HFPD(hfpd - 1) |
396 VIDTCON1_HSPW(hsync_len - 1);
397 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
398 }
399
400 if (driver_data->has_vidoutcon)
401 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
402
403 /* set bypass selection */
404 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
405 driver_data->lcdblk_offset,
406 0x1 << driver_data->lcdblk_bypass_shift,
407 0x1 << driver_data->lcdblk_bypass_shift)) {
408 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
409 return;
410 }
411
412 /* setup horizontal and vertical display size. */
413 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
414 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
415 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
416 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
417 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
418
419 /*
420 * fields of register with prefix '_F' would be updated
421 * at vsync(same as dma start)
422 */
423 val = ctx->vidcon0;
424 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
425
426 if (ctx->driver_data->has_clksel)
427 val |= VIDCON0_CLKSEL_LCD;
428
429 clkdiv = fimd_calc_clkdiv(ctx, mode);
430 if (clkdiv > 1)
431 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
432
433 writel(val, ctx->regs + VIDCON0);
434 }
435
436 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
437 {
438 struct fimd_context *ctx = crtc->ctx;
439 u32 val;
440
441 if (ctx->suspended)
442 return -EPERM;
443
444 if (!test_and_set_bit(0, &ctx->irq_flags)) {
445 val = readl(ctx->regs + VIDINTCON0);
446
447 val |= VIDINTCON0_INT_ENABLE;
448
449 if (ctx->i80_if) {
450 val |= VIDINTCON0_INT_I80IFDONE;
451 val |= VIDINTCON0_INT_SYSMAINCON;
452 val &= ~VIDINTCON0_INT_SYSSUBCON;
453 } else {
454 val |= VIDINTCON0_INT_FRAME;
455
456 val &= ~VIDINTCON0_FRAMESEL0_MASK;
457 val |= VIDINTCON0_FRAMESEL0_VSYNC;
458 val &= ~VIDINTCON0_FRAMESEL1_MASK;
459 val |= VIDINTCON0_FRAMESEL1_NONE;
460 }
461
462 writel(val, ctx->regs + VIDINTCON0);
463 }
464
465 return 0;
466 }
467
468 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
469 {
470 struct fimd_context *ctx = crtc->ctx;
471 u32 val;
472
473 if (ctx->suspended)
474 return;
475
476 if (test_and_clear_bit(0, &ctx->irq_flags)) {
477 val = readl(ctx->regs + VIDINTCON0);
478
479 val &= ~VIDINTCON0_INT_ENABLE;
480
481 if (ctx->i80_if) {
482 val &= ~VIDINTCON0_INT_I80IFDONE;
483 val &= ~VIDINTCON0_INT_SYSMAINCON;
484 val &= ~VIDINTCON0_INT_SYSSUBCON;
485 } else
486 val &= ~VIDINTCON0_INT_FRAME;
487
488 writel(val, ctx->regs + VIDINTCON0);
489 }
490 }
491
492 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
493 {
494 struct exynos_drm_plane *plane = &ctx->planes[win];
495 unsigned long val;
496
497 val = WINCONx_ENWIN;
498
499 /*
500 * In case of s3c64xx, window 0 doesn't support alpha channel.
501 * So the request format is ARGB8888 then change it to XRGB8888.
502 */
503 if (ctx->driver_data->has_limited_fmt && !win) {
504 if (plane->pixel_format == DRM_FORMAT_ARGB8888)
505 plane->pixel_format = DRM_FORMAT_XRGB8888;
506 }
507
508 switch (plane->pixel_format) {
509 case DRM_FORMAT_C8:
510 val |= WINCON0_BPPMODE_8BPP_PALETTE;
511 val |= WINCONx_BURSTLEN_8WORD;
512 val |= WINCONx_BYTSWP;
513 break;
514 case DRM_FORMAT_XRGB1555:
515 val |= WINCON0_BPPMODE_16BPP_1555;
516 val |= WINCONx_HAWSWP;
517 val |= WINCONx_BURSTLEN_16WORD;
518 break;
519 case DRM_FORMAT_RGB565:
520 val |= WINCON0_BPPMODE_16BPP_565;
521 val |= WINCONx_HAWSWP;
522 val |= WINCONx_BURSTLEN_16WORD;
523 break;
524 case DRM_FORMAT_XRGB8888:
525 val |= WINCON0_BPPMODE_24BPP_888;
526 val |= WINCONx_WSWP;
527 val |= WINCONx_BURSTLEN_16WORD;
528 break;
529 case DRM_FORMAT_ARGB8888:
530 val |= WINCON1_BPPMODE_25BPP_A1888
531 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
532 val |= WINCONx_WSWP;
533 val |= WINCONx_BURSTLEN_16WORD;
534 break;
535 default:
536 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
537
538 val |= WINCON0_BPPMODE_24BPP_888;
539 val |= WINCONx_WSWP;
540 val |= WINCONx_BURSTLEN_16WORD;
541 break;
542 }
543
544 DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
545
546 /*
547 * In case of exynos, setting dma-burst to 16Word causes permanent
548 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
549 * switching which is based on plane size is not recommended as
550 * plane size varies alot towards the end of the screen and rapid
551 * movement causes unstable DMA which results into iommu crash/tear.
552 */
553
554 if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
555 val &= ~WINCONx_BURSTLEN_MASK;
556 val |= WINCONx_BURSTLEN_4WORD;
557 }
558
559 writel(val, ctx->regs + WINCON(win));
560
561 /* hardware window 0 doesn't support alpha channel. */
562 if (win != 0) {
563 /* OSD alpha */
564 val = VIDISD14C_ALPHA0_R(0xf) |
565 VIDISD14C_ALPHA0_G(0xf) |
566 VIDISD14C_ALPHA0_B(0xf) |
567 VIDISD14C_ALPHA1_R(0xf) |
568 VIDISD14C_ALPHA1_G(0xf) |
569 VIDISD14C_ALPHA1_B(0xf);
570
571 writel(val, ctx->regs + VIDOSD_C(win));
572
573 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
574 VIDW_ALPHA_G(0xf);
575 writel(val, ctx->regs + VIDWnALPHA0(win));
576 writel(val, ctx->regs + VIDWnALPHA1(win));
577 }
578 }
579
580 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
581 {
582 unsigned int keycon0 = 0, keycon1 = 0;
583
584 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
585 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
586
587 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
588
589 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
590 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
591 }
592
593 /**
594 * shadow_protect_win() - disable updating values from shadow registers at vsync
595 *
596 * @win: window to protect registers for
597 * @protect: 1 to protect (disable updates)
598 */
599 static void fimd_shadow_protect_win(struct fimd_context *ctx,
600 unsigned int win, bool protect)
601 {
602 u32 reg, bits, val;
603
604 if (ctx->driver_data->has_shadowcon) {
605 reg = SHADOWCON;
606 bits = SHADOWCON_WINx_PROTECT(win);
607 } else {
608 reg = PRTCON;
609 bits = PRTCON_PROTECT;
610 }
611
612 val = readl(ctx->regs + reg);
613 if (protect)
614 val |= bits;
615 else
616 val &= ~bits;
617 writel(val, ctx->regs + reg);
618 }
619
620 static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
621 {
622 struct fimd_context *ctx = crtc->ctx;
623 struct exynos_drm_plane *plane;
624 dma_addr_t dma_addr;
625 unsigned long val, size, offset;
626 unsigned int last_x, last_y, buf_offsize, line_size;
627
628 if (ctx->suspended)
629 return;
630
631 if (win < 0 || win >= WINDOWS_NR)
632 return;
633
634 plane = &ctx->planes[win];
635
636 /* If suspended, enable this on resume */
637 if (ctx->suspended) {
638 plane->resume = true;
639 return;
640 }
641
642 /*
643 * SHADOWCON/PRTCON register is used for enabling timing.
644 *
645 * for example, once only width value of a register is set,
646 * if the dma is started then fimd hardware could malfunction so
647 * with protect window setting, the register fields with prefix '_F'
648 * wouldn't be updated at vsync also but updated once unprotect window
649 * is set.
650 */
651
652 /* protect windows */
653 fimd_shadow_protect_win(ctx, win, true);
654
655
656 offset = plane->fb_x * (plane->bpp >> 3);
657 offset += plane->fb_y * plane->pitch;
658
659 /* buffer start address */
660 dma_addr = plane->dma_addr[0] + offset;
661 val = (unsigned long)dma_addr;
662 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
663
664 /* buffer end address */
665 size = plane->pitch * plane->crtc_height * (plane->bpp >> 3);
666 val = (unsigned long)(dma_addr + size);
667 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
668
669 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
670 (unsigned long)dma_addr, val, size);
671 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
672 plane->crtc_width, plane->crtc_height);
673
674 /* buffer size */
675 buf_offsize = (plane->fb_width - plane->crtc_width) * (plane->bpp >> 3);
676 line_size = plane->crtc_width * (plane->bpp >> 3);
677 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
678 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
679 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
680 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
681 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
682
683 /* OSD position */
684 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
685 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
686 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
687 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
688 writel(val, ctx->regs + VIDOSD_A(win));
689
690 last_x = plane->crtc_x + plane->crtc_width;
691 if (last_x)
692 last_x--;
693 last_y = plane->crtc_y + plane->crtc_height;
694 if (last_y)
695 last_y--;
696
697 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
698 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
699
700 writel(val, ctx->regs + VIDOSD_B(win));
701
702 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
703 plane->crtc_x, plane->crtc_y, last_x, last_y);
704
705 /* OSD size */
706 if (win != 3 && win != 4) {
707 u32 offset = VIDOSD_D(win);
708 if (win == 0)
709 offset = VIDOSD_C(win);
710 val = plane->crtc_width * plane->crtc_height;
711 writel(val, ctx->regs + offset);
712
713 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
714 }
715
716 fimd_win_set_pixfmt(ctx, win);
717
718 /* hardware window 0 doesn't support color key. */
719 if (win != 0)
720 fimd_win_set_colkey(ctx, win);
721
722 fimd_enable_video_output(ctx, win, true);
723
724 if (ctx->driver_data->has_shadowcon)
725 fimd_enable_shadow_channel_path(ctx, win, true);
726
727 /* Enable DMA channel and unprotect windows */
728 fimd_shadow_protect_win(ctx, win, false);
729
730 plane->enabled = true;
731
732 if (ctx->i80_if)
733 atomic_set(&ctx->win_updated, 1);
734 }
735
736 static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
737 {
738 struct fimd_context *ctx = crtc->ctx;
739 struct exynos_drm_plane *plane;
740
741 if (win < 0 || win >= WINDOWS_NR)
742 return;
743
744 plane = &ctx->planes[win];
745
746 if (ctx->suspended) {
747 /* do not resume this window*/
748 plane->resume = false;
749 return;
750 }
751
752 /* protect windows */
753 fimd_shadow_protect_win(ctx, win, true);
754
755 fimd_enable_video_output(ctx, win, false);
756
757 if (ctx->driver_data->has_shadowcon)
758 fimd_enable_shadow_channel_path(ctx, win, false);
759
760 /* unprotect windows */
761 fimd_shadow_protect_win(ctx, win, false);
762
763 plane->enabled = false;
764 }
765
766 static void fimd_window_suspend(struct fimd_context *ctx)
767 {
768 struct exynos_drm_plane *plane;
769 int i;
770
771 for (i = 0; i < WINDOWS_NR; i++) {
772 plane = &ctx->planes[i];
773 plane->resume = plane->enabled;
774 if (plane->enabled)
775 fimd_win_disable(ctx->crtc, i);
776 }
777 }
778
779 static void fimd_window_resume(struct fimd_context *ctx)
780 {
781 struct exynos_drm_plane *plane;
782 int i;
783
784 for (i = 0; i < WINDOWS_NR; i++) {
785 plane = &ctx->planes[i];
786 plane->enabled = plane->resume;
787 plane->resume = false;
788 }
789 }
790
791 static void fimd_apply(struct fimd_context *ctx)
792 {
793 struct exynos_drm_plane *plane;
794 int i;
795
796 for (i = 0; i < WINDOWS_NR; i++) {
797 plane = &ctx->planes[i];
798 if (plane->enabled)
799 fimd_win_commit(ctx->crtc, i);
800 else
801 fimd_win_disable(ctx->crtc, i);
802 }
803
804 fimd_commit(ctx->crtc);
805 }
806
807 static int fimd_poweron(struct fimd_context *ctx)
808 {
809 int ret;
810
811 if (!ctx->suspended)
812 return 0;
813
814 ctx->suspended = false;
815
816 pm_runtime_get_sync(ctx->dev);
817
818 ret = clk_prepare_enable(ctx->bus_clk);
819 if (ret < 0) {
820 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
821 goto bus_clk_err;
822 }
823
824 ret = clk_prepare_enable(ctx->lcd_clk);
825 if (ret < 0) {
826 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
827 goto lcd_clk_err;
828 }
829
830 /* if vblank was enabled status, enable it again. */
831 if (test_and_clear_bit(0, &ctx->irq_flags)) {
832 ret = fimd_enable_vblank(ctx->crtc);
833 if (ret) {
834 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
835 goto enable_vblank_err;
836 }
837 }
838
839 fimd_window_resume(ctx);
840
841 fimd_apply(ctx);
842
843 return 0;
844
845 enable_vblank_err:
846 clk_disable_unprepare(ctx->lcd_clk);
847 lcd_clk_err:
848 clk_disable_unprepare(ctx->bus_clk);
849 bus_clk_err:
850 ctx->suspended = true;
851 return ret;
852 }
853
854 static int fimd_poweroff(struct fimd_context *ctx)
855 {
856 if (ctx->suspended)
857 return 0;
858
859 /*
860 * We need to make sure that all windows are disabled before we
861 * suspend that connector. Otherwise we might try to scan from
862 * a destroyed buffer later.
863 */
864 fimd_window_suspend(ctx);
865
866 clk_disable_unprepare(ctx->lcd_clk);
867 clk_disable_unprepare(ctx->bus_clk);
868
869 pm_runtime_put_sync(ctx->dev);
870
871 ctx->suspended = true;
872 return 0;
873 }
874
875 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
876 {
877 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
878
879 switch (mode) {
880 case DRM_MODE_DPMS_ON:
881 fimd_poweron(crtc->ctx);
882 break;
883 case DRM_MODE_DPMS_STANDBY:
884 case DRM_MODE_DPMS_SUSPEND:
885 case DRM_MODE_DPMS_OFF:
886 fimd_poweroff(crtc->ctx);
887 break;
888 default:
889 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
890 break;
891 }
892 }
893
894 static void fimd_trigger(struct device *dev)
895 {
896 struct fimd_context *ctx = dev_get_drvdata(dev);
897 struct fimd_driver_data *driver_data = ctx->driver_data;
898 void *timing_base = ctx->regs + driver_data->timing_base;
899 u32 reg;
900
901 /*
902 * Skips triggering if in triggering state, because multiple triggering
903 * requests can cause panel reset.
904 */
905 if (atomic_read(&ctx->triggering))
906 return;
907
908 /* Enters triggering mode */
909 atomic_set(&ctx->triggering, 1);
910
911 reg = readl(timing_base + TRIGCON);
912 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
913 writel(reg, timing_base + TRIGCON);
914
915 /*
916 * Exits triggering mode if vblank is not enabled yet, because when the
917 * VIDINTCON0 register is not set, it can not exit from triggering mode.
918 */
919 if (!test_bit(0, &ctx->irq_flags))
920 atomic_set(&ctx->triggering, 0);
921 }
922
923 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
924 {
925 struct fimd_context *ctx = crtc->ctx;
926
927 /* Checks the crtc is detached already from encoder */
928 if (ctx->pipe < 0 || !ctx->drm_dev)
929 return;
930
931 /*
932 * If there is a page flip request, triggers and handles the page flip
933 * event so that current fb can be updated into panel GRAM.
934 */
935 if (atomic_add_unless(&ctx->win_updated, -1, 0))
936 fimd_trigger(ctx->dev);
937
938 /* Wakes up vsync event queue */
939 if (atomic_read(&ctx->wait_vsync_event)) {
940 atomic_set(&ctx->wait_vsync_event, 0);
941 wake_up(&ctx->wait_vsync_queue);
942 }
943
944 if (test_bit(0, &ctx->irq_flags))
945 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
946 }
947
948 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
949 .dpms = fimd_dpms,
950 .mode_fixup = fimd_mode_fixup,
951 .commit = fimd_commit,
952 .enable_vblank = fimd_enable_vblank,
953 .disable_vblank = fimd_disable_vblank,
954 .wait_for_vblank = fimd_wait_for_vblank,
955 .win_commit = fimd_win_commit,
956 .win_disable = fimd_win_disable,
957 .te_handler = fimd_te_handler,
958 };
959
960 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
961 {
962 struct fimd_context *ctx = (struct fimd_context *)dev_id;
963 u32 val, clear_bit;
964
965 val = readl(ctx->regs + VIDINTCON1);
966
967 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
968 if (val & clear_bit)
969 writel(clear_bit, ctx->regs + VIDINTCON1);
970
971 /* check the crtc is detached already from encoder */
972 if (ctx->pipe < 0 || !ctx->drm_dev)
973 goto out;
974
975 if (ctx->i80_if) {
976 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
977
978 /* Exits triggering mode */
979 atomic_set(&ctx->triggering, 0);
980 } else {
981 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
982 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
983
984 /* set wait vsync event to zero and wake up queue. */
985 if (atomic_read(&ctx->wait_vsync_event)) {
986 atomic_set(&ctx->wait_vsync_event, 0);
987 wake_up(&ctx->wait_vsync_queue);
988 }
989 }
990
991 out:
992 return IRQ_HANDLED;
993 }
994
995 static int fimd_bind(struct device *dev, struct device *master, void *data)
996 {
997 struct fimd_context *ctx = dev_get_drvdata(dev);
998 struct drm_device *drm_dev = data;
999 struct exynos_drm_private *priv = drm_dev->dev_private;
1000 struct exynos_drm_plane *exynos_plane;
1001 enum drm_plane_type type;
1002 unsigned int zpos;
1003 int ret;
1004
1005 ctx->drm_dev = drm_dev;
1006 ctx->pipe = priv->pipe++;
1007
1008 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
1009 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
1010 DRM_PLANE_TYPE_OVERLAY;
1011 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1012 1 << ctx->pipe, type, zpos);
1013 if (ret)
1014 return ret;
1015 }
1016
1017 exynos_plane = &ctx->planes[ctx->default_win];
1018 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1019 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1020 &fimd_crtc_ops, ctx);
1021
1022 if (ctx->display)
1023 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1024
1025 ret = fimd_iommu_attach_devices(ctx, drm_dev);
1026 if (ret)
1027 return ret;
1028
1029 return 0;
1030
1031 }
1032
1033 static void fimd_unbind(struct device *dev, struct device *master,
1034 void *data)
1035 {
1036 struct fimd_context *ctx = dev_get_drvdata(dev);
1037
1038 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1039
1040 fimd_iommu_detach_devices(ctx);
1041
1042 if (ctx->display)
1043 exynos_dpi_remove(ctx->display);
1044 }
1045
1046 static const struct component_ops fimd_component_ops = {
1047 .bind = fimd_bind,
1048 .unbind = fimd_unbind,
1049 };
1050
1051 static int fimd_probe(struct platform_device *pdev)
1052 {
1053 struct device *dev = &pdev->dev;
1054 struct fimd_context *ctx;
1055 struct device_node *i80_if_timings;
1056 struct resource *res;
1057 int ret;
1058
1059 if (!dev->of_node)
1060 return -ENODEV;
1061
1062 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1063 if (!ctx)
1064 return -ENOMEM;
1065
1066 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1067 EXYNOS_DISPLAY_TYPE_LCD);
1068 if (ret)
1069 return ret;
1070
1071 ctx->dev = dev;
1072 ctx->suspended = true;
1073 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1074
1075 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1076 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1077 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1078 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1079
1080 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1081 if (i80_if_timings) {
1082 u32 val;
1083
1084 ctx->i80_if = true;
1085
1086 if (ctx->driver_data->has_vidoutcon)
1087 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1088 else
1089 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1090 /*
1091 * The user manual describes that this "DSI_EN" bit is required
1092 * to enable I80 24-bit data interface.
1093 */
1094 ctx->vidcon0 |= VIDCON0_DSI_EN;
1095
1096 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1097 val = 0;
1098 ctx->i80ifcon = LCD_CS_SETUP(val);
1099 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1100 val = 0;
1101 ctx->i80ifcon |= LCD_WR_SETUP(val);
1102 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1103 val = 1;
1104 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1105 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1106 val = 0;
1107 ctx->i80ifcon |= LCD_WR_HOLD(val);
1108 }
1109 of_node_put(i80_if_timings);
1110
1111 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1112 "samsung,sysreg");
1113 if (IS_ERR(ctx->sysreg)) {
1114 dev_warn(dev, "failed to get system register.\n");
1115 ctx->sysreg = NULL;
1116 }
1117
1118 ctx->bus_clk = devm_clk_get(dev, "fimd");
1119 if (IS_ERR(ctx->bus_clk)) {
1120 dev_err(dev, "failed to get bus clock\n");
1121 ret = PTR_ERR(ctx->bus_clk);
1122 goto err_del_component;
1123 }
1124
1125 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1126 if (IS_ERR(ctx->lcd_clk)) {
1127 dev_err(dev, "failed to get lcd clock\n");
1128 ret = PTR_ERR(ctx->lcd_clk);
1129 goto err_del_component;
1130 }
1131
1132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1133
1134 ctx->regs = devm_ioremap_resource(dev, res);
1135 if (IS_ERR(ctx->regs)) {
1136 ret = PTR_ERR(ctx->regs);
1137 goto err_del_component;
1138 }
1139
1140 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1141 ctx->i80_if ? "lcd_sys" : "vsync");
1142 if (!res) {
1143 dev_err(dev, "irq request failed.\n");
1144 ret = -ENXIO;
1145 goto err_del_component;
1146 }
1147
1148 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1149 0, "drm_fimd", ctx);
1150 if (ret) {
1151 dev_err(dev, "irq request failed.\n");
1152 goto err_del_component;
1153 }
1154
1155 init_waitqueue_head(&ctx->wait_vsync_queue);
1156 atomic_set(&ctx->wait_vsync_event, 0);
1157
1158 platform_set_drvdata(pdev, ctx);
1159
1160 ctx->display = exynos_dpi_probe(dev);
1161 if (IS_ERR(ctx->display)) {
1162 ret = PTR_ERR(ctx->display);
1163 goto err_del_component;
1164 }
1165
1166 pm_runtime_enable(dev);
1167
1168 ret = component_add(dev, &fimd_component_ops);
1169 if (ret)
1170 goto err_disable_pm_runtime;
1171
1172 return ret;
1173
1174 err_disable_pm_runtime:
1175 pm_runtime_disable(dev);
1176
1177 err_del_component:
1178 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1179 return ret;
1180 }
1181
1182 static int fimd_remove(struct platform_device *pdev)
1183 {
1184 pm_runtime_disable(&pdev->dev);
1185
1186 component_del(&pdev->dev, &fimd_component_ops);
1187 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1188
1189 return 0;
1190 }
1191
1192 struct platform_driver fimd_driver = {
1193 .probe = fimd_probe,
1194 .remove = fimd_remove,
1195 .driver = {
1196 .name = "exynos4-fb",
1197 .owner = THIS_MODULE,
1198 .of_match_table = fimd_driver_dt_match,
1199 },
1200 };
Linux kernel - Deliverables
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