2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
100 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (obj
->tiling_mode
) {
104 case I915_TILING_NONE
: return " ";
105 case I915_TILING_X
: return "X";
106 case I915_TILING_Y
: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
115 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
118 struct i915_vma
*vma
;
120 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
121 if (i915_is_ggtt(vma
->vm
) &&
122 drm_mm_node_allocated(&vma
->node
))
123 size
+= vma
->node
.size
;
130 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
132 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
133 struct intel_engine_cs
*ring
;
134 struct i915_vma
*vma
;
138 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 obj
->active
? "*" : " ",
142 get_tiling_flag(obj
),
143 get_global_flag(obj
),
144 obj
->base
.size
/ 1024,
145 obj
->base
.read_domains
,
146 obj
->base
.write_domain
);
147 for_each_ring(ring
, dev_priv
, i
)
149 i915_gem_request_get_seqno(obj
->last_read_req
[i
]));
150 seq_printf(m
, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj
->last_write_req
),
152 i915_gem_request_get_seqno(obj
->last_fenced_req
),
153 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
154 obj
->dirty
? " dirty" : "",
155 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
157 seq_printf(m
, " (name: %d)", obj
->base
.name
);
158 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
159 if (vma
->pin_count
> 0)
162 seq_printf(m
, " (pinned x %d)", pin_count
);
163 if (obj
->pin_display
)
164 seq_printf(m
, " (display)");
165 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
166 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
167 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
168 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma
->vm
) ? "g" : "pp",
170 vma
->node
.start
, vma
->node
.size
);
171 if (i915_is_ggtt(vma
->vm
))
172 seq_printf(m
, ", type: %u)", vma
->ggtt_view
.type
);
177 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
178 if (obj
->pin_display
|| obj
->fault_mappable
) {
180 if (obj
->pin_display
)
182 if (obj
->fault_mappable
)
185 seq_printf(m
, " (%s mappable)", s
);
187 if (obj
->last_write_req
!= NULL
)
188 seq_printf(m
, " (%s)",
189 i915_gem_request_get_ring(obj
->last_write_req
)->name
);
190 if (obj
->frontbuffer_bits
)
191 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
194 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
196 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
197 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
201 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
203 struct drm_info_node
*node
= m
->private;
204 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
205 struct list_head
*head
;
206 struct drm_device
*dev
= node
->minor
->dev
;
207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
208 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
209 struct i915_vma
*vma
;
210 u64 total_obj_size
, total_gtt_size
;
213 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
217 /* FIXME: the user of this interface might want more than just GGTT */
220 seq_puts(m
, "Active:\n");
221 head
= &vm
->active_list
;
224 seq_puts(m
, "Inactive:\n");
225 head
= &vm
->inactive_list
;
228 mutex_unlock(&dev
->struct_mutex
);
232 total_obj_size
= total_gtt_size
= count
= 0;
233 list_for_each_entry(vma
, head
, mm_list
) {
235 describe_obj(m
, vma
->obj
);
237 total_obj_size
+= vma
->obj
->base
.size
;
238 total_gtt_size
+= vma
->node
.size
;
241 mutex_unlock(&dev
->struct_mutex
);
243 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count
, total_obj_size
, total_gtt_size
);
248 static int obj_rank_by_stolen(void *priv
,
249 struct list_head
*A
, struct list_head
*B
)
251 struct drm_i915_gem_object
*a
=
252 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
253 struct drm_i915_gem_object
*b
=
254 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
256 if (a
->stolen
->start
< b
->stolen
->start
)
258 if (a
->stolen
->start
> b
->stolen
->start
)
263 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
265 struct drm_info_node
*node
= m
->private;
266 struct drm_device
*dev
= node
->minor
->dev
;
267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 struct drm_i915_gem_object
*obj
;
269 u64 total_obj_size
, total_gtt_size
;
273 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
277 total_obj_size
= total_gtt_size
= count
= 0;
278 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
279 if (obj
->stolen
== NULL
)
282 list_add(&obj
->obj_exec_link
, &stolen
);
284 total_obj_size
+= obj
->base
.size
;
285 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
288 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
289 if (obj
->stolen
== NULL
)
292 list_add(&obj
->obj_exec_link
, &stolen
);
294 total_obj_size
+= obj
->base
.size
;
297 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
298 seq_puts(m
, "Stolen:\n");
299 while (!list_empty(&stolen
)) {
300 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
302 describe_obj(m
, obj
);
304 list_del_init(&obj
->obj_exec_link
);
306 mutex_unlock(&dev
->struct_mutex
);
308 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count
, total_obj_size
, total_gtt_size
);
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
325 struct drm_i915_file_private
*file_priv
;
329 u64 active
, inactive
;
332 static int per_file_stats(int id
, void *ptr
, void *data
)
334 struct drm_i915_gem_object
*obj
= ptr
;
335 struct file_stats
*stats
= data
;
336 struct i915_vma
*vma
;
339 stats
->total
+= obj
->base
.size
;
341 if (obj
->base
.name
|| obj
->base
.dma_buf
)
342 stats
->shared
+= obj
->base
.size
;
344 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
345 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
346 struct i915_hw_ppgtt
*ppgtt
;
348 if (!drm_mm_node_allocated(&vma
->node
))
351 if (i915_is_ggtt(vma
->vm
)) {
352 stats
->global
+= obj
->base
.size
;
356 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
357 if (ppgtt
->file_priv
!= stats
->file_priv
)
360 if (obj
->active
) /* XXX per-vma statistic */
361 stats
->active
+= obj
->base
.size
;
363 stats
->inactive
+= obj
->base
.size
;
368 if (i915_gem_obj_ggtt_bound(obj
)) {
369 stats
->global
+= obj
->base
.size
;
371 stats
->active
+= obj
->base
.size
;
373 stats
->inactive
+= obj
->base
.size
;
378 if (!list_empty(&obj
->global_list
))
379 stats
->unbound
+= obj
->base
.size
;
384 #define print_file_stats(m, name, stats) do { \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
397 static void print_batch_pool_stats(struct seq_file
*m
,
398 struct drm_i915_private
*dev_priv
)
400 struct drm_i915_gem_object
*obj
;
401 struct file_stats stats
;
402 struct intel_engine_cs
*ring
;
405 memset(&stats
, 0, sizeof(stats
));
407 for_each_ring(ring
, dev_priv
, i
) {
408 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
409 list_for_each_entry(obj
,
410 &ring
->batch_pool
.cache_list
[j
],
412 per_file_stats(0, obj
, &stats
);
416 print_file_stats(m
, "[k]batch pool", stats
);
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
430 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
432 struct drm_info_node
*node
= m
->private;
433 struct drm_device
*dev
= node
->minor
->dev
;
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
435 u32 count
, mappable_count
, purgeable_count
;
436 u64 size
, mappable_size
, purgeable_size
;
437 struct drm_i915_gem_object
*obj
;
438 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
439 struct drm_file
*file
;
440 struct i915_vma
*vma
;
443 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
447 seq_printf(m
, "%u objects, %zu bytes\n",
448 dev_priv
->mm
.object_count
,
449 dev_priv
->mm
.object_memory
);
451 size
= count
= mappable_size
= mappable_count
= 0;
452 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
453 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count
, mappable_count
, size
, mappable_size
);
456 size
= count
= mappable_size
= mappable_count
= 0;
457 count_vmas(&vm
->active_list
, mm_list
);
458 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count
, mappable_count
, size
, mappable_size
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_vmas(&vm
->inactive_list
, mm_list
);
463 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= purgeable_size
= purgeable_count
= 0;
467 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
468 size
+= obj
->base
.size
, ++count
;
469 if (obj
->madv
== I915_MADV_DONTNEED
)
470 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
472 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
474 size
= count
= mappable_size
= mappable_count
= 0;
475 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
476 if (obj
->fault_mappable
) {
477 size
+= i915_gem_obj_ggtt_size(obj
);
480 if (obj
->pin_display
) {
481 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
484 if (obj
->madv
== I915_MADV_DONTNEED
) {
485 purgeable_size
+= obj
->base
.size
;
489 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
490 purgeable_count
, purgeable_size
);
491 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count
, mappable_size
);
493 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
496 seq_printf(m
, "%llu [%llu] gtt total\n",
497 dev_priv
->gtt
.base
.total
,
498 (u64
)dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
501 print_batch_pool_stats(m
, dev_priv
);
502 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
503 struct file_stats stats
;
504 struct task_struct
*task
;
506 memset(&stats
, 0, sizeof(stats
));
507 stats
.file_priv
= file
->driver_priv
;
508 spin_lock(&file
->table_lock
);
509 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
510 spin_unlock(&file
->table_lock
);
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
518 task
= pid_task(file
->pid
, PIDTYPE_PID
);
519 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
523 mutex_unlock(&dev
->struct_mutex
);
528 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
530 struct drm_info_node
*node
= m
->private;
531 struct drm_device
*dev
= node
->minor
->dev
;
532 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
534 struct drm_i915_gem_object
*obj
;
535 u64 total_obj_size
, total_gtt_size
;
538 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
542 total_obj_size
= total_gtt_size
= count
= 0;
543 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
544 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
548 describe_obj(m
, obj
);
550 total_obj_size
+= obj
->base
.size
;
551 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
555 mutex_unlock(&dev
->struct_mutex
);
557 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count
, total_obj_size
, total_gtt_size
);
563 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
565 struct drm_info_node
*node
= m
->private;
566 struct drm_device
*dev
= node
->minor
->dev
;
567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
568 struct intel_crtc
*crtc
;
571 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
575 for_each_intel_crtc(dev
, crtc
) {
576 const char pipe
= pipe_name(crtc
->pipe
);
577 const char plane
= plane_name(crtc
->plane
);
578 struct intel_unpin_work
*work
;
580 spin_lock_irq(&dev
->event_lock
);
581 work
= crtc
->unpin_work
;
583 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
588 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
589 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
592 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
595 if (work
->flip_queued_req
) {
596 struct intel_engine_cs
*ring
=
597 i915_gem_request_get_ring(work
->flip_queued_req
);
599 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
601 i915_gem_request_get_seqno(work
->flip_queued_req
),
602 dev_priv
->next_seqno
,
603 ring
->get_seqno(ring
, true),
604 i915_gem_request_completed(work
->flip_queued_req
, true));
606 seq_printf(m
, "Flip not associated with any ring\n");
607 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work
->flip_queued_vblank
,
609 work
->flip_ready_vblank
,
610 drm_crtc_vblank_count(&crtc
->base
));
611 if (work
->enable_stall_check
)
612 seq_puts(m
, "Stall check enabled, ");
614 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
617 if (INTEL_INFO(dev
)->gen
>= 4)
618 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
620 addr
= I915_READ(DSPADDR(crtc
->plane
));
621 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
623 if (work
->pending_flip_obj
) {
624 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
625 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
628 spin_unlock_irq(&dev
->event_lock
);
631 mutex_unlock(&dev
->struct_mutex
);
636 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
638 struct drm_info_node
*node
= m
->private;
639 struct drm_device
*dev
= node
->minor
->dev
;
640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 struct drm_i915_gem_object
*obj
;
642 struct intel_engine_cs
*ring
;
646 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
650 for_each_ring(ring
, dev_priv
, i
) {
651 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
655 list_for_each_entry(obj
,
656 &ring
->batch_pool
.cache_list
[j
],
659 seq_printf(m
, "%s cache[%d]: %d objects\n",
660 ring
->name
, j
, count
);
662 list_for_each_entry(obj
,
663 &ring
->batch_pool
.cache_list
[j
],
666 describe_obj(m
, obj
);
674 seq_printf(m
, "total: %d\n", total
);
676 mutex_unlock(&dev
->struct_mutex
);
681 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
683 struct drm_info_node
*node
= m
->private;
684 struct drm_device
*dev
= node
->minor
->dev
;
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
686 struct intel_engine_cs
*ring
;
687 struct drm_i915_gem_request
*req
;
690 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
695 for_each_ring(ring
, dev_priv
, i
) {
699 list_for_each_entry(req
, &ring
->request_list
, list
)
704 seq_printf(m
, "%s requests: %d\n", ring
->name
, count
);
705 list_for_each_entry(req
, &ring
->request_list
, list
) {
706 struct task_struct
*task
;
711 task
= pid_task(req
->pid
, PIDTYPE_PID
);
712 seq_printf(m
, " %x @ %d: %s [%d]\n",
714 (int) (jiffies
- req
->emitted_jiffies
),
715 task
? task
->comm
: "<unknown>",
716 task
? task
->pid
: -1);
722 mutex_unlock(&dev
->struct_mutex
);
725 seq_puts(m
, "No requests\n");
730 static void i915_ring_seqno_info(struct seq_file
*m
,
731 struct intel_engine_cs
*ring
)
733 if (ring
->get_seqno
) {
734 seq_printf(m
, "Current sequence (%s): %x\n",
735 ring
->name
, ring
->get_seqno(ring
, false));
739 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
741 struct drm_info_node
*node
= m
->private;
742 struct drm_device
*dev
= node
->minor
->dev
;
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 struct intel_engine_cs
*ring
;
747 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
750 intel_runtime_pm_get(dev_priv
);
752 for_each_ring(ring
, dev_priv
, i
)
753 i915_ring_seqno_info(m
, ring
);
755 intel_runtime_pm_put(dev_priv
);
756 mutex_unlock(&dev
->struct_mutex
);
762 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
764 struct drm_info_node
*node
= m
->private;
765 struct drm_device
*dev
= node
->minor
->dev
;
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 struct intel_engine_cs
*ring
;
770 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
773 intel_runtime_pm_get(dev_priv
);
775 if (IS_CHERRYVIEW(dev
)) {
776 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ
));
779 seq_printf(m
, "Display IER:\t%08x\n",
781 seq_printf(m
, "Display IIR:\t%08x\n",
783 seq_printf(m
, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW
));
785 seq_printf(m
, "Display IMR:\t%08x\n",
787 for_each_pipe(dev_priv
, pipe
)
788 seq_printf(m
, "Pipe %c stat:\t%08x\n",
790 I915_READ(PIPESTAT(pipe
)));
792 seq_printf(m
, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN
));
794 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT
));
796 seq_printf(m
, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT
));
799 for (i
= 0; i
< 4; i
++) {
800 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IMR(i
)));
802 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IIR(i
)));
804 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
805 i
, I915_READ(GEN8_GT_IER(i
)));
808 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR
));
810 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR
));
812 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER
));
814 } else if (INTEL_INFO(dev
)->gen
>= 8) {
815 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ
));
818 for (i
= 0; i
< 4; i
++) {
819 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
820 i
, I915_READ(GEN8_GT_IMR(i
)));
821 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
822 i
, I915_READ(GEN8_GT_IIR(i
)));
823 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
824 i
, I915_READ(GEN8_GT_IER(i
)));
827 for_each_pipe(dev_priv
, pipe
) {
828 if (!intel_display_power_is_enabled(dev_priv
,
829 POWER_DOMAIN_PIPE(pipe
))) {
830 seq_printf(m
, "Pipe %c power disabled\n",
834 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
836 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
837 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
839 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
840 seq_printf(m
, "Pipe %c IER:\t%08x\n",
842 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
845 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR
));
847 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR
));
849 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER
));
852 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR
));
854 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR
));
856 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER
));
859 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR
));
861 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR
));
863 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER
));
865 } else if (IS_VALLEYVIEW(dev
)) {
866 seq_printf(m
, "Display IER:\t%08x\n",
868 seq_printf(m
, "Display IIR:\t%08x\n",
870 seq_printf(m
, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW
));
872 seq_printf(m
, "Display IMR:\t%08x\n",
874 for_each_pipe(dev_priv
, pipe
)
875 seq_printf(m
, "Pipe %c stat:\t%08x\n",
877 I915_READ(PIPESTAT(pipe
)));
879 seq_printf(m
, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER
));
882 seq_printf(m
, "Render IER:\t%08x\n",
884 seq_printf(m
, "Render IIR:\t%08x\n",
886 seq_printf(m
, "Render IMR:\t%08x\n",
889 seq_printf(m
, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER
));
891 seq_printf(m
, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR
));
893 seq_printf(m
, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR
));
896 seq_printf(m
, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN
));
898 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT
));
900 seq_printf(m
, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT
));
903 } else if (!HAS_PCH_SPLIT(dev
)) {
904 seq_printf(m
, "Interrupt enable: %08x\n",
906 seq_printf(m
, "Interrupt identity: %08x\n",
908 seq_printf(m
, "Interrupt mask: %08x\n",
910 for_each_pipe(dev_priv
, pipe
)
911 seq_printf(m
, "Pipe %c stat: %08x\n",
913 I915_READ(PIPESTAT(pipe
)));
915 seq_printf(m
, "North Display Interrupt enable: %08x\n",
917 seq_printf(m
, "North Display Interrupt identity: %08x\n",
919 seq_printf(m
, "North Display Interrupt mask: %08x\n",
921 seq_printf(m
, "South Display Interrupt enable: %08x\n",
923 seq_printf(m
, "South Display Interrupt identity: %08x\n",
925 seq_printf(m
, "South Display Interrupt mask: %08x\n",
927 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
929 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
931 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
934 for_each_ring(ring
, dev_priv
, i
) {
935 if (INTEL_INFO(dev
)->gen
>= 6) {
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring
->name
, I915_READ_IMR(ring
));
940 i915_ring_seqno_info(m
, ring
);
942 intel_runtime_pm_put(dev_priv
);
943 mutex_unlock(&dev
->struct_mutex
);
948 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
950 struct drm_info_node
*node
= m
->private;
951 struct drm_device
*dev
= node
->minor
->dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
955 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
959 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
960 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
961 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
963 seq_printf(m
, "Fence %d, pin count = %d, object = ",
964 i
, dev_priv
->fence_regs
[i
].pin_count
);
966 seq_puts(m
, "unused");
968 describe_obj(m
, obj
);
972 mutex_unlock(&dev
->struct_mutex
);
976 static int i915_hws_info(struct seq_file
*m
, void *data
)
978 struct drm_info_node
*node
= m
->private;
979 struct drm_device
*dev
= node
->minor
->dev
;
980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
981 struct intel_engine_cs
*ring
;
985 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
986 hws
= ring
->status_page
.page_addr
;
990 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
991 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
999 i915_error_state_write(struct file
*filp
,
1000 const char __user
*ubuf
,
1004 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1005 struct drm_device
*dev
= error_priv
->dev
;
1008 DRM_DEBUG_DRIVER("Resetting error state\n");
1010 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1014 i915_destroy_error_state(dev
);
1015 mutex_unlock(&dev
->struct_mutex
);
1020 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1022 struct drm_device
*dev
= inode
->i_private
;
1023 struct i915_error_state_file_priv
*error_priv
;
1025 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1029 error_priv
->dev
= dev
;
1031 i915_error_state_get(dev
, error_priv
);
1033 file
->private_data
= error_priv
;
1038 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1040 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1042 i915_error_state_put(error_priv
);
1048 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1049 size_t count
, loff_t
*pos
)
1051 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1052 struct drm_i915_error_state_buf error_str
;
1054 ssize_t ret_count
= 0;
1057 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1061 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1065 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1072 *pos
= error_str
.start
+ ret_count
;
1074 i915_error_state_buf_release(&error_str
);
1075 return ret
?: ret_count
;
1078 static const struct file_operations i915_error_state_fops
= {
1079 .owner
= THIS_MODULE
,
1080 .open
= i915_error_state_open
,
1081 .read
= i915_error_state_read
,
1082 .write
= i915_error_state_write
,
1083 .llseek
= default_llseek
,
1084 .release
= i915_error_state_release
,
1088 i915_next_seqno_get(void *data
, u64
*val
)
1090 struct drm_device
*dev
= data
;
1091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1098 *val
= dev_priv
->next_seqno
;
1099 mutex_unlock(&dev
->struct_mutex
);
1105 i915_next_seqno_set(void *data
, u64 val
)
1107 struct drm_device
*dev
= data
;
1110 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1114 ret
= i915_gem_set_seqno(dev
, val
);
1115 mutex_unlock(&dev
->struct_mutex
);
1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1121 i915_next_seqno_get
, i915_next_seqno_set
,
1124 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1126 struct drm_info_node
*node
= m
->private;
1127 struct drm_device
*dev
= node
->minor
->dev
;
1128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1131 intel_runtime_pm_get(dev_priv
);
1133 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1136 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1137 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1139 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1140 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1141 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1143 seq_printf(m
, "Current P-state: %d\n",
1144 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1145 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1148 mutex_lock(&dev_priv
->rps
.hw_lock
);
1149 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1150 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1151 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1153 seq_printf(m
, "actual GPU freq: %d MHz\n",
1154 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1156 seq_printf(m
, "current GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1159 seq_printf(m
, "max GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1162 seq_printf(m
, "min GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1165 seq_printf(m
, "idle GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1169 "efficient (RPe) frequency: %d MHz\n",
1170 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1171 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1172 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1173 u32 rp_state_limits
;
1176 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1177 u32 rpstat
, cagf
, reqf
;
1178 u32 rpupei
, rpcurup
, rpprevup
;
1179 u32 rpdownei
, rpcurdown
, rpprevdown
;
1180 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1183 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1184 if (IS_BROXTON(dev
)) {
1185 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1186 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1188 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1189 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1192 /* RPSTAT1 is in the GT power well */
1193 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1197 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1199 reqf
= I915_READ(GEN6_RPNSWREQ
);
1203 reqf
&= ~GEN6_TURBO_DISABLE
;
1204 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1209 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1211 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1212 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1213 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1215 rpstat
= I915_READ(GEN6_RPSTAT1
);
1216 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1217 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1218 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1219 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1220 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1221 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1223 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1224 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1225 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1227 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1228 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1230 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1231 mutex_unlock(&dev
->struct_mutex
);
1233 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1234 pm_ier
= I915_READ(GEN6_PMIER
);
1235 pm_imr
= I915_READ(GEN6_PMIMR
);
1236 pm_isr
= I915_READ(GEN6_PMISR
);
1237 pm_iir
= I915_READ(GEN6_PMIIR
);
1238 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1240 pm_ier
= I915_READ(GEN8_GT_IER(2));
1241 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1242 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1243 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1244 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1246 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1247 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1248 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1249 seq_printf(m
, "Render p-state ratio: %d\n",
1250 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1251 seq_printf(m
, "Render p-state VID: %d\n",
1252 gt_perf_status
& 0xff);
1253 seq_printf(m
, "Render p-state limit: %d\n",
1254 rp_state_limits
& 0xff);
1255 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1256 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1257 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1258 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1259 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1260 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1261 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1262 GEN6_CURICONT_MASK
);
1263 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1264 GEN6_CURBSYTAVG_MASK
);
1265 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1266 GEN6_CURBSYTAVG_MASK
);
1267 seq_printf(m
, "Up threshold: %d%%\n",
1268 dev_priv
->rps
.up_threshold
);
1270 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1272 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1273 GEN6_CURBSYTAVG_MASK
);
1274 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1275 GEN6_CURBSYTAVG_MASK
);
1276 seq_printf(m
, "Down threshold: %d%%\n",
1277 dev_priv
->rps
.down_threshold
);
1279 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1280 rp_state_cap
>> 16) & 0xff;
1281 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1282 GEN9_FREQ_SCALER
: 1);
1283 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1284 intel_gpu_freq(dev_priv
, max_freq
));
1286 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1287 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1288 GEN9_FREQ_SCALER
: 1);
1289 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1290 intel_gpu_freq(dev_priv
, max_freq
));
1292 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1293 rp_state_cap
>> 0) & 0xff;
1294 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1295 GEN9_FREQ_SCALER
: 1);
1296 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1297 intel_gpu_freq(dev_priv
, max_freq
));
1298 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1299 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1301 seq_printf(m
, "Current freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1303 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1304 seq_printf(m
, "Idle freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1306 seq_printf(m
, "Min freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1308 seq_printf(m
, "Max freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1311 "efficient (RPe) frequency: %d MHz\n",
1312 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1314 seq_puts(m
, "no P-state info available\n");
1317 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1318 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1319 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1322 intel_runtime_pm_put(dev_priv
);
1326 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1328 struct drm_info_node
*node
= m
->private;
1329 struct drm_device
*dev
= node
->minor
->dev
;
1330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1331 struct intel_engine_cs
*ring
;
1332 u64 acthd
[I915_NUM_RINGS
];
1333 u32 seqno
[I915_NUM_RINGS
];
1336 if (!i915
.enable_hangcheck
) {
1337 seq_printf(m
, "Hangcheck disabled\n");
1341 intel_runtime_pm_get(dev_priv
);
1343 for_each_ring(ring
, dev_priv
, i
) {
1344 seqno
[i
] = ring
->get_seqno(ring
, false);
1345 acthd
[i
] = intel_ring_get_active_head(ring
);
1348 intel_runtime_pm_put(dev_priv
);
1350 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1351 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1352 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1355 seq_printf(m
, "Hangcheck inactive\n");
1357 for_each_ring(ring
, dev_priv
, i
) {
1358 seq_printf(m
, "%s:\n", ring
->name
);
1359 seq_printf(m
, "\tseqno = %x [current %x]\n",
1360 ring
->hangcheck
.seqno
, seqno
[i
]);
1361 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1362 (long long)ring
->hangcheck
.acthd
,
1363 (long long)acthd
[i
]);
1364 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1365 (long long)ring
->hangcheck
.max_acthd
);
1366 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1367 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1373 static int ironlake_drpc_info(struct seq_file
*m
)
1375 struct drm_info_node
*node
= m
->private;
1376 struct drm_device
*dev
= node
->minor
->dev
;
1377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1378 u32 rgvmodectl
, rstdbyctl
;
1382 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1385 intel_runtime_pm_get(dev_priv
);
1387 rgvmodectl
= I915_READ(MEMMODECTL
);
1388 rstdbyctl
= I915_READ(RSTDBYCTL
);
1389 crstandvid
= I915_READ16(CRSTANDVID
);
1391 intel_runtime_pm_put(dev_priv
);
1392 mutex_unlock(&dev
->struct_mutex
);
1394 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1395 seq_printf(m
, "Boost freq: %d\n",
1396 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1397 MEMMODE_BOOST_FREQ_SHIFT
);
1398 seq_printf(m
, "HW control enabled: %s\n",
1399 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1400 seq_printf(m
, "SW control enabled: %s\n",
1401 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1402 seq_printf(m
, "Gated voltage change: %s\n",
1403 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1404 seq_printf(m
, "Starting frequency: P%d\n",
1405 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1406 seq_printf(m
, "Max P-state: P%d\n",
1407 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1408 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1409 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1410 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1411 seq_printf(m
, "Render standby enabled: %s\n",
1412 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1413 seq_puts(m
, "Current RS state: ");
1414 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1416 seq_puts(m
, "on\n");
1418 case RSX_STATUS_RC1
:
1419 seq_puts(m
, "RC1\n");
1421 case RSX_STATUS_RC1E
:
1422 seq_puts(m
, "RC1E\n");
1424 case RSX_STATUS_RS1
:
1425 seq_puts(m
, "RS1\n");
1427 case RSX_STATUS_RS2
:
1428 seq_puts(m
, "RS2 (RC6)\n");
1430 case RSX_STATUS_RS3
:
1431 seq_puts(m
, "RC3 (RC6+)\n");
1434 seq_puts(m
, "unknown\n");
1441 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1443 struct drm_info_node
*node
= m
->private;
1444 struct drm_device
*dev
= node
->minor
->dev
;
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1446 struct intel_uncore_forcewake_domain
*fw_domain
;
1449 spin_lock_irq(&dev_priv
->uncore
.lock
);
1450 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1451 seq_printf(m
, "%s.wake_count = %u\n",
1452 intel_uncore_forcewake_domain_to_str(i
),
1453 fw_domain
->wake_count
);
1455 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1460 static int vlv_drpc_info(struct seq_file
*m
)
1462 struct drm_info_node
*node
= m
->private;
1463 struct drm_device
*dev
= node
->minor
->dev
;
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 u32 rpmodectl1
, rcctl1
, pw_status
;
1467 intel_runtime_pm_get(dev_priv
);
1469 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1470 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1471 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1473 intel_runtime_pm_put(dev_priv
);
1475 seq_printf(m
, "Video Turbo Mode: %s\n",
1476 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1477 seq_printf(m
, "Turbo enabled: %s\n",
1478 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1479 seq_printf(m
, "HW control enabled: %s\n",
1480 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1481 seq_printf(m
, "SW control enabled: %s\n",
1482 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1483 GEN6_RP_MEDIA_SW_MODE
));
1484 seq_printf(m
, "RC6 Enabled: %s\n",
1485 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1486 GEN6_RC_CTL_EI_MODE(1))));
1487 seq_printf(m
, "Render Power Well: %s\n",
1488 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1489 seq_printf(m
, "Media Power Well: %s\n",
1490 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1492 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1493 I915_READ(VLV_GT_RENDER_RC6
));
1494 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1495 I915_READ(VLV_GT_MEDIA_RC6
));
1497 return i915_forcewake_domains(m
, NULL
);
1500 static int gen6_drpc_info(struct seq_file
*m
)
1502 struct drm_info_node
*node
= m
->private;
1503 struct drm_device
*dev
= node
->minor
->dev
;
1504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1505 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1506 unsigned forcewake_count
;
1509 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1512 intel_runtime_pm_get(dev_priv
);
1514 spin_lock_irq(&dev_priv
->uncore
.lock
);
1515 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1516 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1518 if (forcewake_count
) {
1519 seq_puts(m
, "RC information inaccurate because somebody "
1520 "holds a forcewake reference \n");
1522 /* NB: we cannot use forcewake, else we read the wrong values */
1523 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1525 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1528 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1529 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1531 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1532 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1533 mutex_unlock(&dev
->struct_mutex
);
1534 mutex_lock(&dev_priv
->rps
.hw_lock
);
1535 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1536 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1538 intel_runtime_pm_put(dev_priv
);
1540 seq_printf(m
, "Video Turbo Mode: %s\n",
1541 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1542 seq_printf(m
, "HW control enabled: %s\n",
1543 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1544 seq_printf(m
, "SW control enabled: %s\n",
1545 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1546 GEN6_RP_MEDIA_SW_MODE
));
1547 seq_printf(m
, "RC1e Enabled: %s\n",
1548 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1549 seq_printf(m
, "RC6 Enabled: %s\n",
1550 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1551 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1552 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1553 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1554 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1555 seq_puts(m
, "Current RC state: ");
1556 switch (gt_core_status
& GEN6_RCn_MASK
) {
1558 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1559 seq_puts(m
, "Core Power Down\n");
1561 seq_puts(m
, "on\n");
1564 seq_puts(m
, "RC3\n");
1567 seq_puts(m
, "RC6\n");
1570 seq_puts(m
, "RC7\n");
1573 seq_puts(m
, "Unknown\n");
1577 seq_printf(m
, "Core Power Down: %s\n",
1578 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1580 /* Not exactly sure what this is */
1581 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1582 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1583 seq_printf(m
, "RC6 residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6
));
1585 seq_printf(m
, "RC6+ residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6p
));
1587 seq_printf(m
, "RC6++ residency since boot: %u\n",
1588 I915_READ(GEN6_GT_GFX_RC6pp
));
1590 seq_printf(m
, "RC6 voltage: %dmV\n",
1591 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1592 seq_printf(m
, "RC6+ voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1594 seq_printf(m
, "RC6++ voltage: %dmV\n",
1595 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1599 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1601 struct drm_info_node
*node
= m
->private;
1602 struct drm_device
*dev
= node
->minor
->dev
;
1604 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1605 return vlv_drpc_info(m
);
1606 else if (INTEL_INFO(dev
)->gen
>= 6)
1607 return gen6_drpc_info(m
);
1609 return ironlake_drpc_info(m
);
1612 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1614 struct drm_info_node
*node
= m
->private;
1615 struct drm_device
*dev
= node
->minor
->dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1619 dev_priv
->fb_tracking
.busy_bits
);
1621 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1622 dev_priv
->fb_tracking
.flip_bits
);
1627 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1629 struct drm_info_node
*node
= m
->private;
1630 struct drm_device
*dev
= node
->minor
->dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1633 if (!HAS_FBC(dev
)) {
1634 seq_puts(m
, "FBC unsupported on this chipset\n");
1638 intel_runtime_pm_get(dev_priv
);
1639 mutex_lock(&dev_priv
->fbc
.lock
);
1641 if (intel_fbc_is_active(dev_priv
))
1642 seq_puts(m
, "FBC enabled\n");
1644 seq_printf(m
, "FBC disabled: %s\n",
1645 dev_priv
->fbc
.no_fbc_reason
);
1647 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1648 seq_printf(m
, "Compressing: %s\n",
1649 yesno(I915_READ(FBC_STATUS2
) &
1650 FBC_COMPRESSION_MASK
));
1652 mutex_unlock(&dev_priv
->fbc
.lock
);
1653 intel_runtime_pm_put(dev_priv
);
1658 static int i915_fbc_fc_get(void *data
, u64
*val
)
1660 struct drm_device
*dev
= data
;
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1663 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1666 *val
= dev_priv
->fbc
.false_color
;
1671 static int i915_fbc_fc_set(void *data
, u64 val
)
1673 struct drm_device
*dev
= data
;
1674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1677 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1680 mutex_lock(&dev_priv
->fbc
.lock
);
1682 reg
= I915_READ(ILK_DPFC_CONTROL
);
1683 dev_priv
->fbc
.false_color
= val
;
1685 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1686 (reg
| FBC_CTL_FALSE_COLOR
) :
1687 (reg
& ~FBC_CTL_FALSE_COLOR
));
1689 mutex_unlock(&dev_priv
->fbc
.lock
);
1693 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1694 i915_fbc_fc_get
, i915_fbc_fc_set
,
1697 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1699 struct drm_info_node
*node
= m
->private;
1700 struct drm_device
*dev
= node
->minor
->dev
;
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 if (!HAS_IPS(dev
)) {
1704 seq_puts(m
, "not supported\n");
1708 intel_runtime_pm_get(dev_priv
);
1710 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1711 yesno(i915
.enable_ips
));
1713 if (INTEL_INFO(dev
)->gen
>= 8) {
1714 seq_puts(m
, "Currently: unknown\n");
1716 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1717 seq_puts(m
, "Currently: enabled\n");
1719 seq_puts(m
, "Currently: disabled\n");
1722 intel_runtime_pm_put(dev_priv
);
1727 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1729 struct drm_info_node
*node
= m
->private;
1730 struct drm_device
*dev
= node
->minor
->dev
;
1731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1732 bool sr_enabled
= false;
1734 intel_runtime_pm_get(dev_priv
);
1736 if (HAS_PCH_SPLIT(dev
))
1737 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1738 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1739 IS_I945G(dev
) || IS_I945GM(dev
))
1740 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1741 else if (IS_I915GM(dev
))
1742 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1743 else if (IS_PINEVIEW(dev
))
1744 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1745 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1746 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1748 intel_runtime_pm_put(dev_priv
);
1750 seq_printf(m
, "self-refresh: %s\n",
1751 sr_enabled
? "enabled" : "disabled");
1756 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1758 struct drm_info_node
*node
= m
->private;
1759 struct drm_device
*dev
= node
->minor
->dev
;
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1761 unsigned long temp
, chipset
, gfx
;
1767 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1771 temp
= i915_mch_val(dev_priv
);
1772 chipset
= i915_chipset_val(dev_priv
);
1773 gfx
= i915_gfx_val(dev_priv
);
1774 mutex_unlock(&dev
->struct_mutex
);
1776 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1777 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1778 seq_printf(m
, "GFX power: %ld\n", gfx
);
1779 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1784 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1786 struct drm_info_node
*node
= m
->private;
1787 struct drm_device
*dev
= node
->minor
->dev
;
1788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1790 int gpu_freq
, ia_freq
;
1791 unsigned int max_gpu_freq
, min_gpu_freq
;
1793 if (!HAS_CORE_RING_FREQ(dev
)) {
1794 seq_puts(m
, "unsupported on this chipset\n");
1798 intel_runtime_pm_get(dev_priv
);
1800 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1802 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1806 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1807 /* Convert GT frequency to 50 HZ units */
1809 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1811 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1813 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1814 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1817 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1819 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1821 sandybridge_pcode_read(dev_priv
,
1822 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1824 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1825 intel_gpu_freq(dev_priv
, (gpu_freq
*
1826 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1827 GEN9_FREQ_SCALER
: 1))),
1828 ((ia_freq
>> 0) & 0xff) * 100,
1829 ((ia_freq
>> 8) & 0xff) * 100);
1832 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1835 intel_runtime_pm_put(dev_priv
);
1839 static int i915_opregion(struct seq_file
*m
, void *unused
)
1841 struct drm_info_node
*node
= m
->private;
1842 struct drm_device
*dev
= node
->minor
->dev
;
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1844 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1847 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1851 if (opregion
->header
)
1852 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1854 mutex_unlock(&dev
->struct_mutex
);
1860 static int i915_vbt(struct seq_file
*m
, void *unused
)
1862 struct drm_info_node
*node
= m
->private;
1863 struct drm_device
*dev
= node
->minor
->dev
;
1864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1865 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1868 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1873 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1875 struct drm_info_node
*node
= m
->private;
1876 struct drm_device
*dev
= node
->minor
->dev
;
1877 struct intel_framebuffer
*fbdev_fb
= NULL
;
1878 struct drm_framebuffer
*drm_fb
;
1880 #ifdef CONFIG_DRM_FBDEV_EMULATION
1881 if (to_i915(dev
)->fbdev
) {
1882 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1884 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1885 fbdev_fb
->base
.width
,
1886 fbdev_fb
->base
.height
,
1887 fbdev_fb
->base
.depth
,
1888 fbdev_fb
->base
.bits_per_pixel
,
1889 fbdev_fb
->base
.modifier
[0],
1890 atomic_read(&fbdev_fb
->base
.refcount
.refcount
));
1891 describe_obj(m
, fbdev_fb
->obj
);
1896 mutex_lock(&dev
->mode_config
.fb_lock
);
1897 drm_for_each_fb(drm_fb
, dev
) {
1898 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1902 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1906 fb
->base
.bits_per_pixel
,
1907 fb
->base
.modifier
[0],
1908 atomic_read(&fb
->base
.refcount
.refcount
));
1909 describe_obj(m
, fb
->obj
);
1912 mutex_unlock(&dev
->mode_config
.fb_lock
);
1917 static void describe_ctx_ringbuf(struct seq_file
*m
,
1918 struct intel_ringbuffer
*ringbuf
)
1920 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1921 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1922 ringbuf
->last_retired_head
);
1925 static int i915_context_status(struct seq_file
*m
, void *unused
)
1927 struct drm_info_node
*node
= m
->private;
1928 struct drm_device
*dev
= node
->minor
->dev
;
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct intel_engine_cs
*ring
;
1931 struct intel_context
*ctx
;
1934 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1938 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1939 if (!i915
.enable_execlists
&&
1940 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1943 seq_puts(m
, "HW context ");
1944 describe_ctx(m
, ctx
);
1945 for_each_ring(ring
, dev_priv
, i
) {
1946 if (ring
->default_context
== ctx
)
1947 seq_printf(m
, "(default context %s) ",
1951 if (i915
.enable_execlists
) {
1953 for_each_ring(ring
, dev_priv
, i
) {
1954 struct drm_i915_gem_object
*ctx_obj
=
1955 ctx
->engine
[i
].state
;
1956 struct intel_ringbuffer
*ringbuf
=
1957 ctx
->engine
[i
].ringbuf
;
1959 seq_printf(m
, "%s: ", ring
->name
);
1961 describe_obj(m
, ctx_obj
);
1963 describe_ctx_ringbuf(m
, ringbuf
);
1967 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1973 mutex_unlock(&dev
->struct_mutex
);
1978 static void i915_dump_lrc_obj(struct seq_file
*m
,
1979 struct intel_engine_cs
*ring
,
1980 struct drm_i915_gem_object
*ctx_obj
)
1983 uint32_t *reg_state
;
1985 unsigned long ggtt_offset
= 0;
1987 if (ctx_obj
== NULL
) {
1988 seq_printf(m
, "Context on %s with no gem object\n",
1993 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1994 intel_execlists_ctx_id(ctx_obj
));
1996 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1997 seq_puts(m
, "\tNot bound in GGTT\n");
1999 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2001 if (i915_gem_object_get_pages(ctx_obj
)) {
2002 seq_puts(m
, "\tFailed to get pages for context object\n");
2006 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2007 if (!WARN_ON(page
== NULL
)) {
2008 reg_state
= kmap_atomic(page
);
2010 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2011 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2012 ggtt_offset
+ 4096 + (j
* 4),
2013 reg_state
[j
], reg_state
[j
+ 1],
2014 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2016 kunmap_atomic(reg_state
);
2022 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2024 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2025 struct drm_device
*dev
= node
->minor
->dev
;
2026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2027 struct intel_engine_cs
*ring
;
2028 struct intel_context
*ctx
;
2031 if (!i915
.enable_execlists
) {
2032 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2036 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2040 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2041 for_each_ring(ring
, dev_priv
, i
) {
2042 if (ring
->default_context
!= ctx
)
2043 i915_dump_lrc_obj(m
, ring
,
2044 ctx
->engine
[i
].state
);
2048 mutex_unlock(&dev
->struct_mutex
);
2053 static int i915_execlists(struct seq_file
*m
, void *data
)
2055 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2056 struct drm_device
*dev
= node
->minor
->dev
;
2057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2058 struct intel_engine_cs
*ring
;
2064 struct list_head
*cursor
;
2068 if (!i915
.enable_execlists
) {
2069 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2073 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2077 intel_runtime_pm_get(dev_priv
);
2079 for_each_ring(ring
, dev_priv
, ring_id
) {
2080 struct drm_i915_gem_request
*head_req
= NULL
;
2082 unsigned long flags
;
2084 seq_printf(m
, "%s\n", ring
->name
);
2086 status
= I915_READ(RING_EXECLIST_STATUS_LO(ring
));
2087 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(ring
));
2088 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2091 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2092 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2094 read_pointer
= ring
->next_context_status_buffer
;
2095 write_pointer
= status_pointer
& 0x07;
2096 if (read_pointer
> write_pointer
)
2098 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2099 read_pointer
, write_pointer
);
2101 for (i
= 0; i
< 6; i
++) {
2102 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, i
));
2103 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, i
));
2105 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2109 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2110 list_for_each(cursor
, &ring
->execlist_queue
)
2112 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2113 struct drm_i915_gem_request
, execlist_link
);
2114 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2116 seq_printf(m
, "\t%d requests in queue\n", count
);
2118 struct drm_i915_gem_object
*ctx_obj
;
2120 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2121 seq_printf(m
, "\tHead request id: %u\n",
2122 intel_execlists_ctx_id(ctx_obj
));
2123 seq_printf(m
, "\tHead request tail: %u\n",
2130 intel_runtime_pm_put(dev_priv
);
2131 mutex_unlock(&dev
->struct_mutex
);
2136 static const char *swizzle_string(unsigned swizzle
)
2139 case I915_BIT_6_SWIZZLE_NONE
:
2141 case I915_BIT_6_SWIZZLE_9
:
2143 case I915_BIT_6_SWIZZLE_9_10
:
2144 return "bit9/bit10";
2145 case I915_BIT_6_SWIZZLE_9_11
:
2146 return "bit9/bit11";
2147 case I915_BIT_6_SWIZZLE_9_10_11
:
2148 return "bit9/bit10/bit11";
2149 case I915_BIT_6_SWIZZLE_9_17
:
2150 return "bit9/bit17";
2151 case I915_BIT_6_SWIZZLE_9_10_17
:
2152 return "bit9/bit10/bit17";
2153 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2160 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2162 struct drm_info_node
*node
= m
->private;
2163 struct drm_device
*dev
= node
->minor
->dev
;
2164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2167 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2170 intel_runtime_pm_get(dev_priv
);
2172 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2173 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2174 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2175 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2177 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2178 seq_printf(m
, "DDC = 0x%08x\n",
2180 seq_printf(m
, "DDC2 = 0x%08x\n",
2182 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2183 I915_READ16(C0DRB3
));
2184 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2185 I915_READ16(C1DRB3
));
2186 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2187 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2188 I915_READ(MAD_DIMM_C0
));
2189 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2190 I915_READ(MAD_DIMM_C1
));
2191 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2192 I915_READ(MAD_DIMM_C2
));
2193 seq_printf(m
, "TILECTL = 0x%08x\n",
2194 I915_READ(TILECTL
));
2195 if (INTEL_INFO(dev
)->gen
>= 8)
2196 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2197 I915_READ(GAMTARBMODE
));
2199 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2200 I915_READ(ARB_MODE
));
2201 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2202 I915_READ(DISP_ARB_CTL
));
2205 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2206 seq_puts(m
, "L-shaped memory detected\n");
2208 intel_runtime_pm_put(dev_priv
);
2209 mutex_unlock(&dev
->struct_mutex
);
2214 static int per_file_ctx(int id
, void *ptr
, void *data
)
2216 struct intel_context
*ctx
= ptr
;
2217 struct seq_file
*m
= data
;
2218 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2221 seq_printf(m
, " no ppgtt for context %d\n",
2226 if (i915_gem_context_is_default(ctx
))
2227 seq_puts(m
, " default context:\n");
2229 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2230 ppgtt
->debug_dump(ppgtt
, m
);
2235 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2238 struct intel_engine_cs
*ring
;
2239 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2245 for_each_ring(ring
, dev_priv
, unused
) {
2246 seq_printf(m
, "%s\n", ring
->name
);
2247 for (i
= 0; i
< 4; i
++) {
2248 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(ring
, i
));
2250 pdp
|= I915_READ(GEN8_RING_PDP_LDW(ring
, i
));
2251 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2256 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 struct intel_engine_cs
*ring
;
2262 if (INTEL_INFO(dev
)->gen
== 6)
2263 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2265 for_each_ring(ring
, dev_priv
, i
) {
2266 seq_printf(m
, "%s\n", ring
->name
);
2267 if (INTEL_INFO(dev
)->gen
== 7)
2268 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2269 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2270 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2271 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2273 if (dev_priv
->mm
.aliasing_ppgtt
) {
2274 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2276 seq_puts(m
, "aliasing PPGTT:\n");
2277 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2279 ppgtt
->debug_dump(ppgtt
, m
);
2282 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2285 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2287 struct drm_info_node
*node
= m
->private;
2288 struct drm_device
*dev
= node
->minor
->dev
;
2289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2290 struct drm_file
*file
;
2292 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2295 intel_runtime_pm_get(dev_priv
);
2297 if (INTEL_INFO(dev
)->gen
>= 8)
2298 gen8_ppgtt_info(m
, dev
);
2299 else if (INTEL_INFO(dev
)->gen
>= 6)
2300 gen6_ppgtt_info(m
, dev
);
2302 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2303 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2304 struct task_struct
*task
;
2306 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2311 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2312 put_task_struct(task
);
2313 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2314 (void *)(unsigned long)m
);
2318 intel_runtime_pm_put(dev_priv
);
2319 mutex_unlock(&dev
->struct_mutex
);
2324 static int count_irq_waiters(struct drm_i915_private
*i915
)
2326 struct intel_engine_cs
*ring
;
2330 for_each_ring(ring
, i915
, i
)
2331 count
+= ring
->irq_refcount
;
2336 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2338 struct drm_info_node
*node
= m
->private;
2339 struct drm_device
*dev
= node
->minor
->dev
;
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2341 struct drm_file
*file
;
2343 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2344 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2345 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2346 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2347 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2348 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2349 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2350 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2351 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2352 spin_lock(&dev_priv
->rps
.client_lock
);
2353 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2354 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2355 struct task_struct
*task
;
2358 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2359 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2360 task
? task
->comm
: "<unknown>",
2361 task
? task
->pid
: -1,
2362 file_priv
->rps
.boosts
,
2363 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2366 seq_printf(m
, "Semaphore boosts: %d%s\n",
2367 dev_priv
->rps
.semaphores
.boosts
,
2368 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2369 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2370 dev_priv
->rps
.mmioflips
.boosts
,
2371 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2372 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2373 spin_unlock(&dev_priv
->rps
.client_lock
);
2378 static int i915_llc(struct seq_file
*m
, void *data
)
2380 struct drm_info_node
*node
= m
->private;
2381 struct drm_device
*dev
= node
->minor
->dev
;
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2385 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2386 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2391 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2393 struct drm_info_node
*node
= m
->private;
2394 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2395 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2398 if (!HAS_GUC_UCODE(dev_priv
->dev
))
2401 seq_printf(m
, "GuC firmware status:\n");
2402 seq_printf(m
, "\tpath: %s\n",
2403 guc_fw
->guc_fw_path
);
2404 seq_printf(m
, "\tfetch: %s\n",
2405 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2406 seq_printf(m
, "\tload: %s\n",
2407 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2408 seq_printf(m
, "\tversion wanted: %d.%d\n",
2409 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2410 seq_printf(m
, "\tversion found: %d.%d\n",
2411 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2412 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2413 guc_fw
->header_offset
, guc_fw
->header_size
);
2414 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2415 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2416 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2417 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2419 tmp
= I915_READ(GUC_STATUS
);
2421 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2422 seq_printf(m
, "\tBootrom status = 0x%x\n",
2423 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2424 seq_printf(m
, "\tuKernel status = 0x%x\n",
2425 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2426 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2427 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2428 seq_puts(m
, "\nScratch registers:\n");
2429 for (i
= 0; i
< 16; i
++)
2430 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2435 static void i915_guc_client_info(struct seq_file
*m
,
2436 struct drm_i915_private
*dev_priv
,
2437 struct i915_guc_client
*client
)
2439 struct intel_engine_cs
*ring
;
2443 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2444 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2445 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2446 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2447 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2448 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2450 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2451 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2452 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2454 for_each_ring(ring
, dev_priv
, i
) {
2455 seq_printf(m
, "\tSubmissions: %llu %s\n",
2456 client
->submissions
[i
],
2458 tot
+= client
->submissions
[i
];
2460 seq_printf(m
, "\tTotal: %llu\n", tot
);
2463 static int i915_guc_info(struct seq_file
*m
, void *data
)
2465 struct drm_info_node
*node
= m
->private;
2466 struct drm_device
*dev
= node
->minor
->dev
;
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_guc guc
;
2469 struct i915_guc_client client
= {};
2470 struct intel_engine_cs
*ring
;
2471 enum intel_ring_id i
;
2474 if (!HAS_GUC_SCHED(dev_priv
->dev
))
2477 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2480 /* Take a local copy of the GuC data, so we can dump it at leisure */
2481 guc
= dev_priv
->guc
;
2482 if (guc
.execbuf_client
)
2483 client
= *guc
.execbuf_client
;
2485 mutex_unlock(&dev
->struct_mutex
);
2487 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2488 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2489 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2490 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2491 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2493 seq_printf(m
, "\nGuC submissions:\n");
2494 for_each_ring(ring
, dev_priv
, i
) {
2495 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2496 ring
->name
, guc
.submissions
[i
],
2497 guc
.last_seqno
[i
], guc
.last_seqno
[i
]);
2498 total
+= guc
.submissions
[i
];
2500 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2502 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2503 i915_guc_client_info(m
, dev_priv
, &client
);
2505 /* Add more as required ... */
2510 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2512 struct drm_info_node
*node
= m
->private;
2513 struct drm_device
*dev
= node
->minor
->dev
;
2514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2515 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2522 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2523 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2525 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2526 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2527 *(log
+ i
), *(log
+ i
+ 1),
2528 *(log
+ i
+ 2), *(log
+ i
+ 3));
2538 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2540 struct drm_info_node
*node
= m
->private;
2541 struct drm_device
*dev
= node
->minor
->dev
;
2542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2546 bool enabled
= false;
2548 if (!HAS_PSR(dev
)) {
2549 seq_puts(m
, "PSR not supported\n");
2553 intel_runtime_pm_get(dev_priv
);
2555 mutex_lock(&dev_priv
->psr
.lock
);
2556 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2557 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2558 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2559 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2560 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2561 dev_priv
->psr
.busy_frontbuffer_bits
);
2562 seq_printf(m
, "Re-enable work scheduled: %s\n",
2563 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2566 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2568 for_each_pipe(dev_priv
, pipe
) {
2569 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2570 VLV_EDP_PSR_CURR_STATE_MASK
;
2571 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2572 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2576 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2579 for_each_pipe(dev_priv
, pipe
) {
2580 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2581 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2582 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2587 * VLV/CHV PSR has no kind of performance counter
2588 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2590 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2591 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2592 EDP_PSR_PERF_CNT_MASK
;
2594 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2596 mutex_unlock(&dev_priv
->psr
.lock
);
2598 intel_runtime_pm_put(dev_priv
);
2602 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2604 struct drm_info_node
*node
= m
->private;
2605 struct drm_device
*dev
= node
->minor
->dev
;
2606 struct intel_encoder
*encoder
;
2607 struct intel_connector
*connector
;
2608 struct intel_dp
*intel_dp
= NULL
;
2612 drm_modeset_lock_all(dev
);
2613 for_each_intel_connector(dev
, connector
) {
2615 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2618 if (!connector
->base
.encoder
)
2621 encoder
= to_intel_encoder(connector
->base
.encoder
);
2622 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2625 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2627 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2631 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2632 crc
[0], crc
[1], crc
[2],
2633 crc
[3], crc
[4], crc
[5]);
2638 drm_modeset_unlock_all(dev
);
2642 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2644 struct drm_info_node
*node
= m
->private;
2645 struct drm_device
*dev
= node
->minor
->dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2650 if (INTEL_INFO(dev
)->gen
< 6)
2653 intel_runtime_pm_get(dev_priv
);
2655 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2656 power
= (power
& 0x1f00) >> 8;
2657 units
= 1000000 / (1 << power
); /* convert to uJ */
2658 power
= I915_READ(MCH_SECP_NRG_STTS
);
2661 intel_runtime_pm_put(dev_priv
);
2663 seq_printf(m
, "%llu", (long long unsigned)power
);
2668 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2670 struct drm_info_node
*node
= m
->private;
2671 struct drm_device
*dev
= node
->minor
->dev
;
2672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2674 if (!HAS_RUNTIME_PM(dev
)) {
2675 seq_puts(m
, "not supported\n");
2679 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2680 seq_printf(m
, "IRQs disabled: %s\n",
2681 yesno(!intel_irqs_enabled(dev_priv
)));
2683 seq_printf(m
, "Usage count: %d\n",
2684 atomic_read(&dev
->dev
->power
.usage_count
));
2686 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2692 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2694 struct drm_info_node
*node
= m
->private;
2695 struct drm_device
*dev
= node
->minor
->dev
;
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2700 mutex_lock(&power_domains
->lock
);
2702 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2703 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2704 struct i915_power_well
*power_well
;
2705 enum intel_display_power_domain power_domain
;
2707 power_well
= &power_domains
->power_wells
[i
];
2708 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2711 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2713 if (!(BIT(power_domain
) & power_well
->domains
))
2716 seq_printf(m
, " %-23s %d\n",
2717 intel_display_power_domain_str(power_domain
),
2718 power_domains
->domain_use_count
[power_domain
]);
2722 mutex_unlock(&power_domains
->lock
);
2727 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2729 struct drm_info_node
*node
= m
->private;
2730 struct drm_device
*dev
= node
->minor
->dev
;
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 struct intel_csr
*csr
;
2734 if (!HAS_CSR(dev
)) {
2735 seq_puts(m
, "not supported\n");
2739 csr
= &dev_priv
->csr
;
2741 intel_runtime_pm_get(dev_priv
);
2743 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2744 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2746 if (!csr
->dmc_payload
)
2749 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2750 CSR_VERSION_MINOR(csr
->version
));
2752 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2753 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2754 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2755 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2756 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2757 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2758 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2759 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2763 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2764 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2765 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2767 intel_runtime_pm_put(dev_priv
);
2772 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2773 struct drm_display_mode
*mode
)
2777 for (i
= 0; i
< tabs
; i
++)
2780 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2781 mode
->base
.id
, mode
->name
,
2782 mode
->vrefresh
, mode
->clock
,
2783 mode
->hdisplay
, mode
->hsync_start
,
2784 mode
->hsync_end
, mode
->htotal
,
2785 mode
->vdisplay
, mode
->vsync_start
,
2786 mode
->vsync_end
, mode
->vtotal
,
2787 mode
->type
, mode
->flags
);
2790 static void intel_encoder_info(struct seq_file
*m
,
2791 struct intel_crtc
*intel_crtc
,
2792 struct intel_encoder
*intel_encoder
)
2794 struct drm_info_node
*node
= m
->private;
2795 struct drm_device
*dev
= node
->minor
->dev
;
2796 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2797 struct intel_connector
*intel_connector
;
2798 struct drm_encoder
*encoder
;
2800 encoder
= &intel_encoder
->base
;
2801 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2802 encoder
->base
.id
, encoder
->name
);
2803 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2804 struct drm_connector
*connector
= &intel_connector
->base
;
2805 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2808 drm_get_connector_status_name(connector
->status
));
2809 if (connector
->status
== connector_status_connected
) {
2810 struct drm_display_mode
*mode
= &crtc
->mode
;
2811 seq_printf(m
, ", mode:\n");
2812 intel_seq_print_mode(m
, 2, mode
);
2819 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2821 struct drm_info_node
*node
= m
->private;
2822 struct drm_device
*dev
= node
->minor
->dev
;
2823 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2824 struct intel_encoder
*intel_encoder
;
2825 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2826 struct drm_framebuffer
*fb
= plane_state
->fb
;
2829 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2830 fb
->base
.id
, plane_state
->src_x
>> 16,
2831 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2833 seq_puts(m
, "\tprimary plane disabled\n");
2834 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2835 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2838 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2840 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2842 seq_printf(m
, "\tfixed mode:\n");
2843 intel_seq_print_mode(m
, 2, mode
);
2846 static void intel_dp_info(struct seq_file
*m
,
2847 struct intel_connector
*intel_connector
)
2849 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2850 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2852 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2853 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2854 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2855 intel_panel_info(m
, &intel_connector
->panel
);
2858 static void intel_dp_mst_info(struct seq_file
*m
,
2859 struct intel_connector
*intel_connector
)
2861 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2862 struct intel_dp_mst_encoder
*intel_mst
=
2863 enc_to_mst(&intel_encoder
->base
);
2864 struct intel_digital_port
*intel_dig_port
= intel_mst
->primary
;
2865 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2866 bool has_audio
= drm_dp_mst_port_has_audio(&intel_dp
->mst_mgr
,
2867 intel_connector
->port
);
2869 seq_printf(m
, "\taudio support: %s\n", yesno(has_audio
));
2872 static void intel_hdmi_info(struct seq_file
*m
,
2873 struct intel_connector
*intel_connector
)
2875 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2876 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2878 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2881 static void intel_lvds_info(struct seq_file
*m
,
2882 struct intel_connector
*intel_connector
)
2884 intel_panel_info(m
, &intel_connector
->panel
);
2887 static void intel_connector_info(struct seq_file
*m
,
2888 struct drm_connector
*connector
)
2890 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2891 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2892 struct drm_display_mode
*mode
;
2894 seq_printf(m
, "connector %d: type %s, status: %s\n",
2895 connector
->base
.id
, connector
->name
,
2896 drm_get_connector_status_name(connector
->status
));
2897 if (connector
->status
== connector_status_connected
) {
2898 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2899 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2900 connector
->display_info
.width_mm
,
2901 connector
->display_info
.height_mm
);
2902 seq_printf(m
, "\tsubpixel order: %s\n",
2903 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2904 seq_printf(m
, "\tCEA rev: %d\n",
2905 connector
->display_info
.cea_rev
);
2907 if (intel_encoder
) {
2908 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2909 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2910 intel_dp_info(m
, intel_connector
);
2911 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2912 intel_hdmi_info(m
, intel_connector
);
2913 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2914 intel_lvds_info(m
, intel_connector
);
2915 else if (intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2916 intel_dp_mst_info(m
, intel_connector
);
2919 seq_printf(m
, "\tmodes:\n");
2920 list_for_each_entry(mode
, &connector
->modes
, head
)
2921 intel_seq_print_mode(m
, 2, mode
);
2924 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2929 if (IS_845G(dev
) || IS_I865G(dev
))
2930 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2932 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2937 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2942 pos
= I915_READ(CURPOS(pipe
));
2944 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2945 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2948 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2949 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2952 return cursor_active(dev
, pipe
);
2955 static const char *plane_type(enum drm_plane_type type
)
2958 case DRM_PLANE_TYPE_OVERLAY
:
2960 case DRM_PLANE_TYPE_PRIMARY
:
2962 case DRM_PLANE_TYPE_CURSOR
:
2965 * Deliberately omitting default: to generate compiler warnings
2966 * when a new drm_plane_type gets added.
2973 static const char *plane_rotation(unsigned int rotation
)
2975 static char buf
[48];
2977 * According to doc only one DRM_ROTATE_ is allowed but this
2978 * will print them all to visualize if the values are misused
2980 snprintf(buf
, sizeof(buf
),
2981 "%s%s%s%s%s%s(0x%08x)",
2982 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
2983 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
2984 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
2985 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
2986 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
2987 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
2993 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2995 struct drm_info_node
*node
= m
->private;
2996 struct drm_device
*dev
= node
->minor
->dev
;
2997 struct intel_plane
*intel_plane
;
2999 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3000 struct drm_plane_state
*state
;
3001 struct drm_plane
*plane
= &intel_plane
->base
;
3003 if (!plane
->state
) {
3004 seq_puts(m
, "plane->state is NULL!\n");
3008 state
= plane
->state
;
3010 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3012 plane_type(intel_plane
->base
.type
),
3013 state
->crtc_x
, state
->crtc_y
,
3014 state
->crtc_w
, state
->crtc_h
,
3015 (state
->src_x
>> 16),
3016 ((state
->src_x
& 0xffff) * 15625) >> 10,
3017 (state
->src_y
>> 16),
3018 ((state
->src_y
& 0xffff) * 15625) >> 10,
3019 (state
->src_w
>> 16),
3020 ((state
->src_w
& 0xffff) * 15625) >> 10,
3021 (state
->src_h
>> 16),
3022 ((state
->src_h
& 0xffff) * 15625) >> 10,
3023 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3024 plane_rotation(state
->rotation
));
3028 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3030 struct intel_crtc_state
*pipe_config
;
3031 int num_scalers
= intel_crtc
->num_scalers
;
3034 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3036 /* Not all platformas have a scaler */
3038 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3040 pipe_config
->scaler_state
.scaler_users
,
3041 pipe_config
->scaler_state
.scaler_id
);
3043 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3044 struct intel_scaler
*sc
=
3045 &pipe_config
->scaler_state
.scalers
[i
];
3047 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3048 i
, yesno(sc
->in_use
), sc
->mode
);
3052 seq_puts(m
, "\tNo scalers available on this platform\n");
3056 static int i915_display_info(struct seq_file
*m
, void *unused
)
3058 struct drm_info_node
*node
= m
->private;
3059 struct drm_device
*dev
= node
->minor
->dev
;
3060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 struct intel_crtc
*crtc
;
3062 struct drm_connector
*connector
;
3064 intel_runtime_pm_get(dev_priv
);
3065 drm_modeset_lock_all(dev
);
3066 seq_printf(m
, "CRTC info\n");
3067 seq_printf(m
, "---------\n");
3068 for_each_intel_crtc(dev
, crtc
) {
3070 struct intel_crtc_state
*pipe_config
;
3073 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3075 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3076 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3077 yesno(pipe_config
->base
.active
),
3078 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3079 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3081 if (pipe_config
->base
.active
) {
3082 intel_crtc_info(m
, crtc
);
3084 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3085 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3086 yesno(crtc
->cursor_base
),
3087 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3088 crtc
->base
.cursor
->state
->crtc_h
,
3089 crtc
->cursor_addr
, yesno(active
));
3090 intel_scaler_info(m
, crtc
);
3091 intel_plane_info(m
, crtc
);
3094 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3095 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3096 yesno(!crtc
->pch_fifo_underrun_disabled
));
3099 seq_printf(m
, "\n");
3100 seq_printf(m
, "Connector info\n");
3101 seq_printf(m
, "--------------\n");
3102 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3103 intel_connector_info(m
, connector
);
3105 drm_modeset_unlock_all(dev
);
3106 intel_runtime_pm_put(dev_priv
);
3111 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3113 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3114 struct drm_device
*dev
= node
->minor
->dev
;
3115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 struct intel_engine_cs
*ring
;
3117 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3120 if (!i915_semaphore_is_enabled(dev
)) {
3121 seq_puts(m
, "Semaphores are disabled\n");
3125 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3128 intel_runtime_pm_get(dev_priv
);
3130 if (IS_BROADWELL(dev
)) {
3134 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3136 seqno
= (uint64_t *)kmap_atomic(page
);
3137 for_each_ring(ring
, dev_priv
, i
) {
3140 seq_printf(m
, "%s\n", ring
->name
);
3142 seq_puts(m
, " Last signal:");
3143 for (j
= 0; j
< num_rings
; j
++) {
3144 offset
= i
* I915_NUM_RINGS
+ j
;
3145 seq_printf(m
, "0x%08llx (0x%02llx) ",
3146 seqno
[offset
], offset
* 8);
3150 seq_puts(m
, " Last wait: ");
3151 for (j
= 0; j
< num_rings
; j
++) {
3152 offset
= i
+ (j
* I915_NUM_RINGS
);
3153 seq_printf(m
, "0x%08llx (0x%02llx) ",
3154 seqno
[offset
], offset
* 8);
3159 kunmap_atomic(seqno
);
3161 seq_puts(m
, " Last signal:");
3162 for_each_ring(ring
, dev_priv
, i
)
3163 for (j
= 0; j
< num_rings
; j
++)
3164 seq_printf(m
, "0x%08x\n",
3165 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
3169 seq_puts(m
, "\nSync seqno:\n");
3170 for_each_ring(ring
, dev_priv
, i
) {
3171 for (j
= 0; j
< num_rings
; j
++) {
3172 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
3178 intel_runtime_pm_put(dev_priv
);
3179 mutex_unlock(&dev
->struct_mutex
);
3183 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3185 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3186 struct drm_device
*dev
= node
->minor
->dev
;
3187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3190 drm_modeset_lock_all(dev
);
3191 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3192 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3194 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3195 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3196 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
3197 seq_printf(m
, " tracked hardware state:\n");
3198 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3199 seq_printf(m
, " dpll_md: 0x%08x\n",
3200 pll
->config
.hw_state
.dpll_md
);
3201 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3202 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3203 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3205 drm_modeset_unlock_all(dev
);
3210 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3214 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3215 struct drm_device
*dev
= node
->minor
->dev
;
3216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3218 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3222 intel_runtime_pm_get(dev_priv
);
3224 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
3225 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
3227 u32 mask
, value
, read
;
3230 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
3231 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
3232 value
= dev_priv
->workarounds
.reg
[i
].value
;
3233 read
= I915_READ(addr
);
3234 ok
= (value
& mask
) == (read
& mask
);
3235 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3236 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3239 intel_runtime_pm_put(dev_priv
);
3240 mutex_unlock(&dev
->struct_mutex
);
3245 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3247 struct drm_info_node
*node
= m
->private;
3248 struct drm_device
*dev
= node
->minor
->dev
;
3249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3250 struct skl_ddb_allocation
*ddb
;
3251 struct skl_ddb_entry
*entry
;
3255 if (INTEL_INFO(dev
)->gen
< 9)
3258 drm_modeset_lock_all(dev
);
3260 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3262 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3264 for_each_pipe(dev_priv
, pipe
) {
3265 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3267 for_each_plane(dev_priv
, pipe
, plane
) {
3268 entry
= &ddb
->plane
[pipe
][plane
];
3269 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3270 entry
->start
, entry
->end
,
3271 skl_ddb_entry_size(entry
));
3274 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3275 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3276 entry
->end
, skl_ddb_entry_size(entry
));
3279 drm_modeset_unlock_all(dev
);
3284 static void drrs_status_per_crtc(struct seq_file
*m
,
3285 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3287 struct intel_encoder
*intel_encoder
;
3288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3289 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3292 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3293 /* Encoder connected on this CRTC */
3294 switch (intel_encoder
->type
) {
3295 case INTEL_OUTPUT_EDP
:
3296 seq_puts(m
, "eDP:\n");
3298 case INTEL_OUTPUT_DSI
:
3299 seq_puts(m
, "DSI:\n");
3301 case INTEL_OUTPUT_HDMI
:
3302 seq_puts(m
, "HDMI:\n");
3304 case INTEL_OUTPUT_DISPLAYPORT
:
3305 seq_puts(m
, "DP:\n");
3308 seq_printf(m
, "Other encoder (id=%d).\n",
3309 intel_encoder
->type
);
3314 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3315 seq_puts(m
, "\tVBT: DRRS_type: Static");
3316 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3317 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3318 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3319 seq_puts(m
, "\tVBT: DRRS_type: None");
3321 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3323 seq_puts(m
, "\n\n");
3325 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3326 struct intel_panel
*panel
;
3328 mutex_lock(&drrs
->mutex
);
3329 /* DRRS Supported */
3330 seq_puts(m
, "\tDRRS Supported: Yes\n");
3332 /* disable_drrs() will make drrs->dp NULL */
3334 seq_puts(m
, "Idleness DRRS: Disabled");
3335 mutex_unlock(&drrs
->mutex
);
3339 panel
= &drrs
->dp
->attached_connector
->panel
;
3340 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3341 drrs
->busy_frontbuffer_bits
);
3343 seq_puts(m
, "\n\t\t");
3344 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3345 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3346 vrefresh
= panel
->fixed_mode
->vrefresh
;
3347 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3348 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3349 vrefresh
= panel
->downclock_mode
->vrefresh
;
3351 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3352 drrs
->refresh_rate_type
);
3353 mutex_unlock(&drrs
->mutex
);
3356 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3358 seq_puts(m
, "\n\t\t");
3359 mutex_unlock(&drrs
->mutex
);
3361 /* DRRS not supported. Print the VBT parameter*/
3362 seq_puts(m
, "\tDRRS Supported : No");
3367 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3369 struct drm_info_node
*node
= m
->private;
3370 struct drm_device
*dev
= node
->minor
->dev
;
3371 struct intel_crtc
*intel_crtc
;
3372 int active_crtc_cnt
= 0;
3374 for_each_intel_crtc(dev
, intel_crtc
) {
3375 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3377 if (intel_crtc
->base
.state
->active
) {
3379 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3381 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3384 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3387 if (!active_crtc_cnt
)
3388 seq_puts(m
, "No active crtc found\n");
3393 struct pipe_crc_info
{
3395 struct drm_device
*dev
;
3399 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3401 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3402 struct drm_device
*dev
= node
->minor
->dev
;
3403 struct drm_encoder
*encoder
;
3404 struct intel_encoder
*intel_encoder
;
3405 struct intel_digital_port
*intel_dig_port
;
3406 drm_modeset_lock_all(dev
);
3407 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3408 intel_encoder
= to_intel_encoder(encoder
);
3409 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3411 intel_dig_port
= enc_to_dig_port(encoder
);
3412 if (!intel_dig_port
->dp
.can_mst
)
3415 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3417 drm_modeset_unlock_all(dev
);
3421 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3423 struct pipe_crc_info
*info
= inode
->i_private
;
3424 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3425 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3427 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3430 spin_lock_irq(&pipe_crc
->lock
);
3432 if (pipe_crc
->opened
) {
3433 spin_unlock_irq(&pipe_crc
->lock
);
3434 return -EBUSY
; /* already open */
3437 pipe_crc
->opened
= true;
3438 filep
->private_data
= inode
->i_private
;
3440 spin_unlock_irq(&pipe_crc
->lock
);
3445 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3447 struct pipe_crc_info
*info
= inode
->i_private
;
3448 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3449 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3451 spin_lock_irq(&pipe_crc
->lock
);
3452 pipe_crc
->opened
= false;
3453 spin_unlock_irq(&pipe_crc
->lock
);
3458 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3459 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3460 /* account for \'0' */
3461 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3463 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3465 assert_spin_locked(&pipe_crc
->lock
);
3466 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3467 INTEL_PIPE_CRC_ENTRIES_NR
);
3471 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3474 struct pipe_crc_info
*info
= filep
->private_data
;
3475 struct drm_device
*dev
= info
->dev
;
3476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3477 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3478 char buf
[PIPE_CRC_BUFFER_LEN
];
3483 * Don't allow user space to provide buffers not big enough to hold
3486 if (count
< PIPE_CRC_LINE_LEN
)
3489 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3492 /* nothing to read */
3493 spin_lock_irq(&pipe_crc
->lock
);
3494 while (pipe_crc_data_count(pipe_crc
) == 0) {
3497 if (filep
->f_flags
& O_NONBLOCK
) {
3498 spin_unlock_irq(&pipe_crc
->lock
);
3502 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3503 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3505 spin_unlock_irq(&pipe_crc
->lock
);
3510 /* We now have one or more entries to read */
3511 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3514 while (n_entries
> 0) {
3515 struct intel_pipe_crc_entry
*entry
=
3516 &pipe_crc
->entries
[pipe_crc
->tail
];
3519 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3520 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3523 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3524 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3526 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3527 "%8u %8x %8x %8x %8x %8x\n",
3528 entry
->frame
, entry
->crc
[0],
3529 entry
->crc
[1], entry
->crc
[2],
3530 entry
->crc
[3], entry
->crc
[4]);
3532 spin_unlock_irq(&pipe_crc
->lock
);
3534 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3535 if (ret
== PIPE_CRC_LINE_LEN
)
3538 user_buf
+= PIPE_CRC_LINE_LEN
;
3541 spin_lock_irq(&pipe_crc
->lock
);
3544 spin_unlock_irq(&pipe_crc
->lock
);
3549 static const struct file_operations i915_pipe_crc_fops
= {
3550 .owner
= THIS_MODULE
,
3551 .open
= i915_pipe_crc_open
,
3552 .read
= i915_pipe_crc_read
,
3553 .release
= i915_pipe_crc_release
,
3556 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3558 .name
= "i915_pipe_A_crc",
3562 .name
= "i915_pipe_B_crc",
3566 .name
= "i915_pipe_C_crc",
3571 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3574 struct drm_device
*dev
= minor
->dev
;
3576 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3579 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3580 &i915_pipe_crc_fops
);
3584 return drm_add_fake_info_node(minor
, ent
, info
);
3587 static const char * const pipe_crc_sources
[] = {
3600 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3602 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3603 return pipe_crc_sources
[source
];
3606 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3608 struct drm_device
*dev
= m
->private;
3609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3612 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3613 seq_printf(m
, "%c %s\n", pipe_name(i
),
3614 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3619 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3621 struct drm_device
*dev
= inode
->i_private
;
3623 return single_open(file
, display_crc_ctl_show
, dev
);
3626 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3629 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3630 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3633 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3634 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3636 case INTEL_PIPE_CRC_SOURCE_NONE
:
3646 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3647 enum intel_pipe_crc_source
*source
)
3649 struct intel_encoder
*encoder
;
3650 struct intel_crtc
*crtc
;
3651 struct intel_digital_port
*dig_port
;
3654 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3656 drm_modeset_lock_all(dev
);
3657 for_each_intel_encoder(dev
, encoder
) {
3658 if (!encoder
->base
.crtc
)
3661 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3663 if (crtc
->pipe
!= pipe
)
3666 switch (encoder
->type
) {
3667 case INTEL_OUTPUT_TVOUT
:
3668 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3670 case INTEL_OUTPUT_DISPLAYPORT
:
3671 case INTEL_OUTPUT_EDP
:
3672 dig_port
= enc_to_dig_port(&encoder
->base
);
3673 switch (dig_port
->port
) {
3675 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3678 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3681 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3684 WARN(1, "nonexisting DP port %c\n",
3685 port_name(dig_port
->port
));
3693 drm_modeset_unlock_all(dev
);
3698 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3700 enum intel_pipe_crc_source
*source
,
3703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3704 bool need_stable_symbols
= false;
3706 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3707 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3713 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3714 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3716 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3717 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3718 need_stable_symbols
= true;
3720 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3721 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3722 need_stable_symbols
= true;
3724 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3725 if (!IS_CHERRYVIEW(dev
))
3727 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3728 need_stable_symbols
= true;
3730 case INTEL_PIPE_CRC_SOURCE_NONE
:
3738 * When the pipe CRC tap point is after the transcoders we need
3739 * to tweak symbol-level features to produce a deterministic series of
3740 * symbols for a given frame. We need to reset those features only once
3741 * a frame (instead of every nth symbol):
3742 * - DC-balance: used to ensure a better clock recovery from the data
3744 * - DisplayPort scrambling: used for EMI reduction
3746 if (need_stable_symbols
) {
3747 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3749 tmp
|= DC_BALANCE_RESET_VLV
;
3752 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3755 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3758 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3763 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3769 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3771 enum intel_pipe_crc_source
*source
,
3774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3775 bool need_stable_symbols
= false;
3777 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3778 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3784 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3785 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3787 case INTEL_PIPE_CRC_SOURCE_TV
:
3788 if (!SUPPORTS_TV(dev
))
3790 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3792 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3795 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3796 need_stable_symbols
= true;
3798 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3801 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3802 need_stable_symbols
= true;
3804 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3807 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3808 need_stable_symbols
= true;
3810 case INTEL_PIPE_CRC_SOURCE_NONE
:
3818 * When the pipe CRC tap point is after the transcoders we need
3819 * to tweak symbol-level features to produce a deterministic series of
3820 * symbols for a given frame. We need to reset those features only once
3821 * a frame (instead of every nth symbol):
3822 * - DC-balance: used to ensure a better clock recovery from the data
3824 * - DisplayPort scrambling: used for EMI reduction
3826 if (need_stable_symbols
) {
3827 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3829 WARN_ON(!IS_G4X(dev
));
3831 I915_WRITE(PORT_DFT_I9XX
,
3832 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3835 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3837 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3839 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3845 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3849 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3853 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3856 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3859 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3864 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3865 tmp
&= ~DC_BALANCE_RESET_VLV
;
3866 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3870 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3874 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3877 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3879 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3880 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3882 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3883 I915_WRITE(PORT_DFT_I9XX
,
3884 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3888 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3891 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3892 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3895 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3896 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3898 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3899 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3901 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3902 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3904 case INTEL_PIPE_CRC_SOURCE_NONE
:
3914 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3917 struct intel_crtc
*crtc
=
3918 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3919 struct intel_crtc_state
*pipe_config
;
3920 struct drm_atomic_state
*state
;
3923 drm_modeset_lock_all(dev
);
3924 state
= drm_atomic_state_alloc(dev
);
3930 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3931 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3932 if (IS_ERR(pipe_config
)) {
3933 ret
= PTR_ERR(pipe_config
);
3937 pipe_config
->pch_pfit
.force_thru
= enable
;
3938 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3939 pipe_config
->pch_pfit
.enabled
!= enable
)
3940 pipe_config
->base
.connectors_changed
= true;
3942 ret
= drm_atomic_commit(state
);
3944 drm_modeset_unlock_all(dev
);
3945 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3947 drm_atomic_state_free(state
);
3950 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3952 enum intel_pipe_crc_source
*source
,
3955 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3956 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3959 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3960 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3962 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3963 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3965 case INTEL_PIPE_CRC_SOURCE_PF
:
3966 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3967 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
3969 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3971 case INTEL_PIPE_CRC_SOURCE_NONE
:
3981 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3982 enum intel_pipe_crc_source source
)
3984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3985 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3986 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3988 u32 val
= 0; /* shut up gcc */
3991 if (pipe_crc
->source
== source
)
3994 /* forbid changing the source without going back to 'none' */
3995 if (pipe_crc
->source
&& source
)
3998 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3999 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4004 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4005 else if (INTEL_INFO(dev
)->gen
< 5)
4006 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4007 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4008 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4009 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4010 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4012 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4017 /* none -> real source transition */
4019 struct intel_pipe_crc_entry
*entries
;
4021 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4022 pipe_name(pipe
), pipe_crc_source_name(source
));
4024 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4025 sizeof(pipe_crc
->entries
[0]),
4031 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4032 * enabled and disabled dynamically based on package C states,
4033 * user space can't make reliable use of the CRCs, so let's just
4034 * completely disable it.
4036 hsw_disable_ips(crtc
);
4038 spin_lock_irq(&pipe_crc
->lock
);
4039 kfree(pipe_crc
->entries
);
4040 pipe_crc
->entries
= entries
;
4043 spin_unlock_irq(&pipe_crc
->lock
);
4046 pipe_crc
->source
= source
;
4048 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4049 POSTING_READ(PIPE_CRC_CTL(pipe
));
4051 /* real source -> none transition */
4052 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4053 struct intel_pipe_crc_entry
*entries
;
4054 struct intel_crtc
*crtc
=
4055 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4057 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4060 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4061 if (crtc
->base
.state
->active
)
4062 intel_wait_for_vblank(dev
, pipe
);
4063 drm_modeset_unlock(&crtc
->base
.mutex
);
4065 spin_lock_irq(&pipe_crc
->lock
);
4066 entries
= pipe_crc
->entries
;
4067 pipe_crc
->entries
= NULL
;
4070 spin_unlock_irq(&pipe_crc
->lock
);
4075 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4076 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4077 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4078 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4079 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4081 hsw_enable_ips(crtc
);
4088 * Parse pipe CRC command strings:
4089 * command: wsp* object wsp+ name wsp+ source wsp*
4092 * source: (none | plane1 | plane2 | pf)
4093 * wsp: (#0x20 | #0x9 | #0xA)+
4096 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4097 * "pipe A none" -> Stop CRC
4099 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4106 /* skip leading white space */
4107 buf
= skip_spaces(buf
);
4109 break; /* end of buffer */
4111 /* find end of word */
4112 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4115 if (n_words
== max_words
) {
4116 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4118 return -EINVAL
; /* ran out of words[] before bytes */
4123 words
[n_words
++] = buf
;
4130 enum intel_pipe_crc_object
{
4131 PIPE_CRC_OBJECT_PIPE
,
4134 static const char * const pipe_crc_objects
[] = {
4139 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4143 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4144 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4152 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4154 const char name
= buf
[0];
4156 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4165 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4169 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4170 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4178 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4182 char *words
[N_WORDS
];
4184 enum intel_pipe_crc_object object
;
4185 enum intel_pipe_crc_source source
;
4187 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4188 if (n_words
!= N_WORDS
) {
4189 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4194 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4195 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4199 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4200 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4204 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4205 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4209 return pipe_crc_set_source(dev
, pipe
, source
);
4212 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4213 size_t len
, loff_t
*offp
)
4215 struct seq_file
*m
= file
->private_data
;
4216 struct drm_device
*dev
= m
->private;
4223 if (len
> PAGE_SIZE
- 1) {
4224 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4229 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4233 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4239 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4250 static const struct file_operations i915_display_crc_ctl_fops
= {
4251 .owner
= THIS_MODULE
,
4252 .open
= display_crc_ctl_open
,
4254 .llseek
= seq_lseek
,
4255 .release
= single_release
,
4256 .write
= display_crc_ctl_write
4259 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4260 const char __user
*ubuf
,
4261 size_t len
, loff_t
*offp
)
4265 struct drm_device
*dev
;
4266 struct drm_connector
*connector
;
4267 struct list_head
*connector_list
;
4268 struct intel_dp
*intel_dp
;
4271 dev
= ((struct seq_file
*)file
->private_data
)->private;
4273 connector_list
= &dev
->mode_config
.connector_list
;
4278 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4282 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4287 input_buffer
[len
] = '\0';
4288 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4290 list_for_each_entry(connector
, connector_list
, head
) {
4292 if (connector
->connector_type
!=
4293 DRM_MODE_CONNECTOR_DisplayPort
)
4296 if (connector
->status
== connector_status_connected
&&
4297 connector
->encoder
!= NULL
) {
4298 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4299 status
= kstrtoint(input_buffer
, 10, &val
);
4302 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4303 /* To prevent erroneous activation of the compliance
4304 * testing code, only accept an actual value of 1 here
4307 intel_dp
->compliance_test_active
= 1;
4309 intel_dp
->compliance_test_active
= 0;
4313 kfree(input_buffer
);
4321 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4323 struct drm_device
*dev
= m
->private;
4324 struct drm_connector
*connector
;
4325 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4326 struct intel_dp
*intel_dp
;
4328 list_for_each_entry(connector
, connector_list
, head
) {
4330 if (connector
->connector_type
!=
4331 DRM_MODE_CONNECTOR_DisplayPort
)
4334 if (connector
->status
== connector_status_connected
&&
4335 connector
->encoder
!= NULL
) {
4336 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4337 if (intel_dp
->compliance_test_active
)
4348 static int i915_displayport_test_active_open(struct inode
*inode
,
4351 struct drm_device
*dev
= inode
->i_private
;
4353 return single_open(file
, i915_displayport_test_active_show
, dev
);
4356 static const struct file_operations i915_displayport_test_active_fops
= {
4357 .owner
= THIS_MODULE
,
4358 .open
= i915_displayport_test_active_open
,
4360 .llseek
= seq_lseek
,
4361 .release
= single_release
,
4362 .write
= i915_displayport_test_active_write
4365 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4367 struct drm_device
*dev
= m
->private;
4368 struct drm_connector
*connector
;
4369 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4370 struct intel_dp
*intel_dp
;
4372 list_for_each_entry(connector
, connector_list
, head
) {
4374 if (connector
->connector_type
!=
4375 DRM_MODE_CONNECTOR_DisplayPort
)
4378 if (connector
->status
== connector_status_connected
&&
4379 connector
->encoder
!= NULL
) {
4380 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4381 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4388 static int i915_displayport_test_data_open(struct inode
*inode
,
4391 struct drm_device
*dev
= inode
->i_private
;
4393 return single_open(file
, i915_displayport_test_data_show
, dev
);
4396 static const struct file_operations i915_displayport_test_data_fops
= {
4397 .owner
= THIS_MODULE
,
4398 .open
= i915_displayport_test_data_open
,
4400 .llseek
= seq_lseek
,
4401 .release
= single_release
4404 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4406 struct drm_device
*dev
= m
->private;
4407 struct drm_connector
*connector
;
4408 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4409 struct intel_dp
*intel_dp
;
4411 list_for_each_entry(connector
, connector_list
, head
) {
4413 if (connector
->connector_type
!=
4414 DRM_MODE_CONNECTOR_DisplayPort
)
4417 if (connector
->status
== connector_status_connected
&&
4418 connector
->encoder
!= NULL
) {
4419 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4420 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4428 static int i915_displayport_test_type_open(struct inode
*inode
,
4431 struct drm_device
*dev
= inode
->i_private
;
4433 return single_open(file
, i915_displayport_test_type_show
, dev
);
4436 static const struct file_operations i915_displayport_test_type_fops
= {
4437 .owner
= THIS_MODULE
,
4438 .open
= i915_displayport_test_type_open
,
4440 .llseek
= seq_lseek
,
4441 .release
= single_release
4444 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4446 struct drm_device
*dev
= m
->private;
4450 if (IS_CHERRYVIEW(dev
))
4452 else if (IS_VALLEYVIEW(dev
))
4455 num_levels
= ilk_wm_max_level(dev
) + 1;
4457 drm_modeset_lock_all(dev
);
4459 for (level
= 0; level
< num_levels
; level
++) {
4460 unsigned int latency
= wm
[level
];
4463 * - WM1+ latency values in 0.5us units
4464 * - latencies are in us on gen9/vlv/chv
4466 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4472 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4473 level
, wm
[level
], latency
/ 10, latency
% 10);
4476 drm_modeset_unlock_all(dev
);
4479 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4481 struct drm_device
*dev
= m
->private;
4482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4483 const uint16_t *latencies
;
4485 if (INTEL_INFO(dev
)->gen
>= 9)
4486 latencies
= dev_priv
->wm
.skl_latency
;
4488 latencies
= to_i915(dev
)->wm
.pri_latency
;
4490 wm_latency_show(m
, latencies
);
4495 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4497 struct drm_device
*dev
= m
->private;
4498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4499 const uint16_t *latencies
;
4501 if (INTEL_INFO(dev
)->gen
>= 9)
4502 latencies
= dev_priv
->wm
.skl_latency
;
4504 latencies
= to_i915(dev
)->wm
.spr_latency
;
4506 wm_latency_show(m
, latencies
);
4511 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4513 struct drm_device
*dev
= m
->private;
4514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4515 const uint16_t *latencies
;
4517 if (INTEL_INFO(dev
)->gen
>= 9)
4518 latencies
= dev_priv
->wm
.skl_latency
;
4520 latencies
= to_i915(dev
)->wm
.cur_latency
;
4522 wm_latency_show(m
, latencies
);
4527 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4529 struct drm_device
*dev
= inode
->i_private
;
4531 if (INTEL_INFO(dev
)->gen
< 5)
4534 return single_open(file
, pri_wm_latency_show
, dev
);
4537 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4539 struct drm_device
*dev
= inode
->i_private
;
4541 if (HAS_GMCH_DISPLAY(dev
))
4544 return single_open(file
, spr_wm_latency_show
, dev
);
4547 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4549 struct drm_device
*dev
= inode
->i_private
;
4551 if (HAS_GMCH_DISPLAY(dev
))
4554 return single_open(file
, cur_wm_latency_show
, dev
);
4557 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4558 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4560 struct seq_file
*m
= file
->private_data
;
4561 struct drm_device
*dev
= m
->private;
4562 uint16_t new[8] = { 0 };
4568 if (IS_CHERRYVIEW(dev
))
4570 else if (IS_VALLEYVIEW(dev
))
4573 num_levels
= ilk_wm_max_level(dev
) + 1;
4575 if (len
>= sizeof(tmp
))
4578 if (copy_from_user(tmp
, ubuf
, len
))
4583 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4584 &new[0], &new[1], &new[2], &new[3],
4585 &new[4], &new[5], &new[6], &new[7]);
4586 if (ret
!= num_levels
)
4589 drm_modeset_lock_all(dev
);
4591 for (level
= 0; level
< num_levels
; level
++)
4592 wm
[level
] = new[level
];
4594 drm_modeset_unlock_all(dev
);
4600 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4601 size_t len
, loff_t
*offp
)
4603 struct seq_file
*m
= file
->private_data
;
4604 struct drm_device
*dev
= m
->private;
4605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4606 uint16_t *latencies
;
4608 if (INTEL_INFO(dev
)->gen
>= 9)
4609 latencies
= dev_priv
->wm
.skl_latency
;
4611 latencies
= to_i915(dev
)->wm
.pri_latency
;
4613 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4616 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4617 size_t len
, loff_t
*offp
)
4619 struct seq_file
*m
= file
->private_data
;
4620 struct drm_device
*dev
= m
->private;
4621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4622 uint16_t *latencies
;
4624 if (INTEL_INFO(dev
)->gen
>= 9)
4625 latencies
= dev_priv
->wm
.skl_latency
;
4627 latencies
= to_i915(dev
)->wm
.spr_latency
;
4629 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4632 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4633 size_t len
, loff_t
*offp
)
4635 struct seq_file
*m
= file
->private_data
;
4636 struct drm_device
*dev
= m
->private;
4637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4638 uint16_t *latencies
;
4640 if (INTEL_INFO(dev
)->gen
>= 9)
4641 latencies
= dev_priv
->wm
.skl_latency
;
4643 latencies
= to_i915(dev
)->wm
.cur_latency
;
4645 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4648 static const struct file_operations i915_pri_wm_latency_fops
= {
4649 .owner
= THIS_MODULE
,
4650 .open
= pri_wm_latency_open
,
4652 .llseek
= seq_lseek
,
4653 .release
= single_release
,
4654 .write
= pri_wm_latency_write
4657 static const struct file_operations i915_spr_wm_latency_fops
= {
4658 .owner
= THIS_MODULE
,
4659 .open
= spr_wm_latency_open
,
4661 .llseek
= seq_lseek
,
4662 .release
= single_release
,
4663 .write
= spr_wm_latency_write
4666 static const struct file_operations i915_cur_wm_latency_fops
= {
4667 .owner
= THIS_MODULE
,
4668 .open
= cur_wm_latency_open
,
4670 .llseek
= seq_lseek
,
4671 .release
= single_release
,
4672 .write
= cur_wm_latency_write
4676 i915_wedged_get(void *data
, u64
*val
)
4678 struct drm_device
*dev
= data
;
4679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4681 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4687 i915_wedged_set(void *data
, u64 val
)
4689 struct drm_device
*dev
= data
;
4690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4693 * There is no safeguard against this debugfs entry colliding
4694 * with the hangcheck calling same i915_handle_error() in
4695 * parallel, causing an explosion. For now we assume that the
4696 * test harness is responsible enough not to inject gpu hangs
4697 * while it is writing to 'i915_wedged'
4700 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4703 intel_runtime_pm_get(dev_priv
);
4705 i915_handle_error(dev
, val
,
4706 "Manually setting wedged to %llu", val
);
4708 intel_runtime_pm_put(dev_priv
);
4713 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4714 i915_wedged_get
, i915_wedged_set
,
4718 i915_ring_stop_get(void *data
, u64
*val
)
4720 struct drm_device
*dev
= data
;
4721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4723 *val
= dev_priv
->gpu_error
.stop_rings
;
4729 i915_ring_stop_set(void *data
, u64 val
)
4731 struct drm_device
*dev
= data
;
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4735 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4737 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4741 dev_priv
->gpu_error
.stop_rings
= val
;
4742 mutex_unlock(&dev
->struct_mutex
);
4747 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4748 i915_ring_stop_get
, i915_ring_stop_set
,
4752 i915_ring_missed_irq_get(void *data
, u64
*val
)
4754 struct drm_device
*dev
= data
;
4755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4757 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4762 i915_ring_missed_irq_set(void *data
, u64 val
)
4764 struct drm_device
*dev
= data
;
4765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4768 /* Lock against concurrent debugfs callers */
4769 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4772 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4773 mutex_unlock(&dev
->struct_mutex
);
4778 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4779 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4783 i915_ring_test_irq_get(void *data
, u64
*val
)
4785 struct drm_device
*dev
= data
;
4786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4788 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4794 i915_ring_test_irq_set(void *data
, u64 val
)
4796 struct drm_device
*dev
= data
;
4797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4800 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4802 /* Lock against concurrent debugfs callers */
4803 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4807 dev_priv
->gpu_error
.test_irq_rings
= val
;
4808 mutex_unlock(&dev
->struct_mutex
);
4813 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4814 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4817 #define DROP_UNBOUND 0x1
4818 #define DROP_BOUND 0x2
4819 #define DROP_RETIRE 0x4
4820 #define DROP_ACTIVE 0x8
4821 #define DROP_ALL (DROP_UNBOUND | \
4826 i915_drop_caches_get(void *data
, u64
*val
)
4834 i915_drop_caches_set(void *data
, u64 val
)
4836 struct drm_device
*dev
= data
;
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4840 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4842 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4843 * on ioctls on -EAGAIN. */
4844 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4848 if (val
& DROP_ACTIVE
) {
4849 ret
= i915_gpu_idle(dev
);
4854 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4855 i915_gem_retire_requests(dev
);
4857 if (val
& DROP_BOUND
)
4858 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4860 if (val
& DROP_UNBOUND
)
4861 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4864 mutex_unlock(&dev
->struct_mutex
);
4869 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4870 i915_drop_caches_get
, i915_drop_caches_set
,
4874 i915_max_freq_get(void *data
, u64
*val
)
4876 struct drm_device
*dev
= data
;
4877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4880 if (INTEL_INFO(dev
)->gen
< 6)
4883 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4885 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4889 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4890 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4896 i915_max_freq_set(void *data
, u64 val
)
4898 struct drm_device
*dev
= data
;
4899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4903 if (INTEL_INFO(dev
)->gen
< 6)
4906 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4908 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4910 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4915 * Turbo will still be enabled, but won't go above the set value.
4917 val
= intel_freq_opcode(dev_priv
, val
);
4919 hw_max
= dev_priv
->rps
.max_freq
;
4920 hw_min
= dev_priv
->rps
.min_freq
;
4922 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4923 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4927 dev_priv
->rps
.max_freq_softlimit
= val
;
4929 intel_set_rps(dev
, val
);
4931 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4936 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4937 i915_max_freq_get
, i915_max_freq_set
,
4941 i915_min_freq_get(void *data
, u64
*val
)
4943 struct drm_device
*dev
= data
;
4944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4947 if (INTEL_INFO(dev
)->gen
< 6)
4950 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4952 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4956 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4957 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4963 i915_min_freq_set(void *data
, u64 val
)
4965 struct drm_device
*dev
= data
;
4966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4970 if (INTEL_INFO(dev
)->gen
< 6)
4973 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4975 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4977 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4982 * Turbo will still be enabled, but won't go below the set value.
4984 val
= intel_freq_opcode(dev_priv
, val
);
4986 hw_max
= dev_priv
->rps
.max_freq
;
4987 hw_min
= dev_priv
->rps
.min_freq
;
4989 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4990 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4994 dev_priv
->rps
.min_freq_softlimit
= val
;
4996 intel_set_rps(dev
, val
);
4998 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5003 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5004 i915_min_freq_get
, i915_min_freq_set
,
5008 i915_cache_sharing_get(void *data
, u64
*val
)
5010 struct drm_device
*dev
= data
;
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5015 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5018 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5021 intel_runtime_pm_get(dev_priv
);
5023 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5025 intel_runtime_pm_put(dev_priv
);
5026 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5028 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5034 i915_cache_sharing_set(void *data
, u64 val
)
5036 struct drm_device
*dev
= data
;
5037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5040 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5046 intel_runtime_pm_get(dev_priv
);
5047 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5049 /* Update the cache sharing policy here as well */
5050 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5051 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5052 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5053 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5055 intel_runtime_pm_put(dev_priv
);
5059 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5060 i915_cache_sharing_get
, i915_cache_sharing_set
,
5063 struct sseu_dev_status
{
5064 unsigned int slice_total
;
5065 unsigned int subslice_total
;
5066 unsigned int subslice_per_slice
;
5067 unsigned int eu_total
;
5068 unsigned int eu_per_subslice
;
5071 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5072 struct sseu_dev_status
*stat
)
5074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5077 u32 sig1
[ss_max
], sig2
[ss_max
];
5079 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5080 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5081 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5082 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5084 for (ss
= 0; ss
< ss_max
; ss
++) {
5085 unsigned int eu_cnt
;
5087 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5088 /* skip disabled subslice */
5091 stat
->slice_total
= 1;
5092 stat
->subslice_per_slice
++;
5093 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5094 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5095 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5096 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5097 stat
->eu_total
+= eu_cnt
;
5098 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5100 stat
->subslice_total
= stat
->subslice_per_slice
;
5103 static void gen9_sseu_device_status(struct drm_device
*dev
,
5104 struct sseu_dev_status
*stat
)
5106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5107 int s_max
= 3, ss_max
= 4;
5109 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5111 /* BXT has a single slice and at most 3 subslices. */
5112 if (IS_BROXTON(dev
)) {
5117 for (s
= 0; s
< s_max
; s
++) {
5118 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5119 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5120 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5123 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5124 GEN9_PGCTL_SSA_EU19_ACK
|
5125 GEN9_PGCTL_SSA_EU210_ACK
|
5126 GEN9_PGCTL_SSA_EU311_ACK
;
5127 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5128 GEN9_PGCTL_SSB_EU19_ACK
|
5129 GEN9_PGCTL_SSB_EU210_ACK
|
5130 GEN9_PGCTL_SSB_EU311_ACK
;
5132 for (s
= 0; s
< s_max
; s
++) {
5133 unsigned int ss_cnt
= 0;
5135 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5136 /* skip disabled slice */
5139 stat
->slice_total
++;
5141 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5142 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5144 for (ss
= 0; ss
< ss_max
; ss
++) {
5145 unsigned int eu_cnt
;
5147 if (IS_BROXTON(dev
) &&
5148 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5149 /* skip disabled subslice */
5152 if (IS_BROXTON(dev
))
5155 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5157 stat
->eu_total
+= eu_cnt
;
5158 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5162 stat
->subslice_total
+= ss_cnt
;
5163 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5168 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5169 struct sseu_dev_status
*stat
)
5171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5173 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5175 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5177 if (stat
->slice_total
) {
5178 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5179 stat
->subslice_total
= stat
->slice_total
*
5180 stat
->subslice_per_slice
;
5181 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5182 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5184 /* subtract fused off EU(s) from enabled slice(s) */
5185 for (s
= 0; s
< stat
->slice_total
; s
++) {
5186 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5188 stat
->eu_total
-= hweight8(subslice_7eu
);
5193 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5195 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5196 struct drm_device
*dev
= node
->minor
->dev
;
5197 struct sseu_dev_status stat
;
5199 if (INTEL_INFO(dev
)->gen
< 8)
5202 seq_puts(m
, "SSEU Device Info\n");
5203 seq_printf(m
, " Available Slice Total: %u\n",
5204 INTEL_INFO(dev
)->slice_total
);
5205 seq_printf(m
, " Available Subslice Total: %u\n",
5206 INTEL_INFO(dev
)->subslice_total
);
5207 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5208 INTEL_INFO(dev
)->subslice_per_slice
);
5209 seq_printf(m
, " Available EU Total: %u\n",
5210 INTEL_INFO(dev
)->eu_total
);
5211 seq_printf(m
, " Available EU Per Subslice: %u\n",
5212 INTEL_INFO(dev
)->eu_per_subslice
);
5213 seq_printf(m
, " Has Slice Power Gating: %s\n",
5214 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5215 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5216 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5217 seq_printf(m
, " Has EU Power Gating: %s\n",
5218 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5220 seq_puts(m
, "SSEU Device Status\n");
5221 memset(&stat
, 0, sizeof(stat
));
5222 if (IS_CHERRYVIEW(dev
)) {
5223 cherryview_sseu_device_status(dev
, &stat
);
5224 } else if (IS_BROADWELL(dev
)) {
5225 broadwell_sseu_device_status(dev
, &stat
);
5226 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5227 gen9_sseu_device_status(dev
, &stat
);
5229 seq_printf(m
, " Enabled Slice Total: %u\n",
5231 seq_printf(m
, " Enabled Subslice Total: %u\n",
5232 stat
.subslice_total
);
5233 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5234 stat
.subslice_per_slice
);
5235 seq_printf(m
, " Enabled EU Total: %u\n",
5237 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5238 stat
.eu_per_subslice
);
5243 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5245 struct drm_device
*dev
= inode
->i_private
;
5246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5248 if (INTEL_INFO(dev
)->gen
< 6)
5251 intel_runtime_pm_get(dev_priv
);
5252 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5257 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5259 struct drm_device
*dev
= inode
->i_private
;
5260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5262 if (INTEL_INFO(dev
)->gen
< 6)
5265 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5266 intel_runtime_pm_put(dev_priv
);
5271 static const struct file_operations i915_forcewake_fops
= {
5272 .owner
= THIS_MODULE
,
5273 .open
= i915_forcewake_open
,
5274 .release
= i915_forcewake_release
,
5277 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5279 struct drm_device
*dev
= minor
->dev
;
5282 ent
= debugfs_create_file("i915_forcewake_user",
5285 &i915_forcewake_fops
);
5289 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5292 static int i915_debugfs_create(struct dentry
*root
,
5293 struct drm_minor
*minor
,
5295 const struct file_operations
*fops
)
5297 struct drm_device
*dev
= minor
->dev
;
5300 ent
= debugfs_create_file(name
,
5307 return drm_add_fake_info_node(minor
, ent
, fops
);
5310 static const struct drm_info_list i915_debugfs_list
[] = {
5311 {"i915_capabilities", i915_capabilities
, 0},
5312 {"i915_gem_objects", i915_gem_object_info
, 0},
5313 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5314 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5315 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5316 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5317 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5318 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5319 {"i915_gem_request", i915_gem_request_info
, 0},
5320 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5321 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5322 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5323 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5324 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5325 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5326 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5327 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5328 {"i915_guc_info", i915_guc_info
, 0},
5329 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5330 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5331 {"i915_frequency_info", i915_frequency_info
, 0},
5332 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5333 {"i915_drpc_info", i915_drpc_info
, 0},
5334 {"i915_emon_status", i915_emon_status
, 0},
5335 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5336 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5337 {"i915_fbc_status", i915_fbc_status
, 0},
5338 {"i915_ips_status", i915_ips_status
, 0},
5339 {"i915_sr_status", i915_sr_status
, 0},
5340 {"i915_opregion", i915_opregion
, 0},
5341 {"i915_vbt", i915_vbt
, 0},
5342 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5343 {"i915_context_status", i915_context_status
, 0},
5344 {"i915_dump_lrc", i915_dump_lrc
, 0},
5345 {"i915_execlists", i915_execlists
, 0},
5346 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5347 {"i915_swizzle_info", i915_swizzle_info
, 0},
5348 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5349 {"i915_llc", i915_llc
, 0},
5350 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5351 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5352 {"i915_energy_uJ", i915_energy_uJ
, 0},
5353 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5354 {"i915_power_domain_info", i915_power_domain_info
, 0},
5355 {"i915_dmc_info", i915_dmc_info
, 0},
5356 {"i915_display_info", i915_display_info
, 0},
5357 {"i915_semaphore_status", i915_semaphore_status
, 0},
5358 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5359 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5360 {"i915_wa_registers", i915_wa_registers
, 0},
5361 {"i915_ddb_info", i915_ddb_info
, 0},
5362 {"i915_sseu_status", i915_sseu_status
, 0},
5363 {"i915_drrs_status", i915_drrs_status
, 0},
5364 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5366 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5368 static const struct i915_debugfs_files
{
5370 const struct file_operations
*fops
;
5371 } i915_debugfs_files
[] = {
5372 {"i915_wedged", &i915_wedged_fops
},
5373 {"i915_max_freq", &i915_max_freq_fops
},
5374 {"i915_min_freq", &i915_min_freq_fops
},
5375 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5376 {"i915_ring_stop", &i915_ring_stop_fops
},
5377 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5378 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5379 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5380 {"i915_error_state", &i915_error_state_fops
},
5381 {"i915_next_seqno", &i915_next_seqno_fops
},
5382 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5383 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5384 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5385 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5386 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5387 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5388 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5389 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5392 void intel_display_crc_init(struct drm_device
*dev
)
5394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5397 for_each_pipe(dev_priv
, pipe
) {
5398 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5400 pipe_crc
->opened
= false;
5401 spin_lock_init(&pipe_crc
->lock
);
5402 init_waitqueue_head(&pipe_crc
->wq
);
5406 int i915_debugfs_init(struct drm_minor
*minor
)
5410 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5414 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5415 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5420 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5421 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5422 i915_debugfs_files
[i
].name
,
5423 i915_debugfs_files
[i
].fops
);
5428 return drm_debugfs_create_files(i915_debugfs_list
,
5429 I915_DEBUGFS_ENTRIES
,
5430 minor
->debugfs_root
, minor
);
5433 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5437 drm_debugfs_remove_files(i915_debugfs_list
,
5438 I915_DEBUGFS_ENTRIES
, minor
);
5440 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5443 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5444 struct drm_info_list
*info_list
=
5445 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5447 drm_debugfs_remove_files(info_list
, 1, minor
);
5450 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5451 struct drm_info_list
*info_list
=
5452 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5454 drm_debugfs_remove_files(info_list
, 1, minor
);
5459 /* DPCD dump start address. */
5460 unsigned int offset
;
5461 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5463 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5465 /* Only valid for eDP. */
5469 static const struct dpcd_block i915_dpcd_debug
[] = {
5470 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5471 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5472 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5473 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5474 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5475 { .offset
= DP_SET_POWER
},
5476 { .offset
= DP_EDP_DPCD_REV
},
5477 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5478 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5479 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5482 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5484 struct drm_connector
*connector
= m
->private;
5485 struct intel_dp
*intel_dp
=
5486 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5491 if (connector
->status
!= connector_status_connected
)
5494 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5495 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5496 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5499 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5502 /* low tech for now */
5503 if (WARN_ON(size
> sizeof(buf
)))
5506 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5508 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5509 size
, b
->offset
, err
);
5513 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5519 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5521 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5524 static const struct file_operations i915_dpcd_fops
= {
5525 .owner
= THIS_MODULE
,
5526 .open
= i915_dpcd_open
,
5528 .llseek
= seq_lseek
,
5529 .release
= single_release
,
5533 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5534 * @connector: pointer to a registered drm_connector
5536 * Cleanup will be done by drm_connector_unregister() through a call to
5537 * drm_debugfs_connector_remove().
5539 * Returns 0 on success, negative error codes on error.
5541 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5543 struct dentry
*root
= connector
->debugfs_entry
;
5545 /* The connector must have been registered beforehands. */
5549 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5550 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5551 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,