1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
46 #include <linux/pm_runtime.h>
48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
50 #define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
54 intel_ring_emit(LP_RING(dev_priv), x)
56 #define ADVANCE_LP_RING() \
57 __intel_ring_advance(LP_RING(dev_priv))
60 * Lock test for when it's just for synchronization of ring access.
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
71 intel_read_legacy_status_page(struct drm_i915_private
*dev_priv
, int reg
)
73 if (I915_NEED_GFX_HWS(dev_priv
->dev
))
74 return ioread32(dev_priv
->dri1
.gfx_hws_cpu_addr
+ reg
);
76 return intel_read_status_page(LP_RING(dev_priv
), reg
);
79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81 #define I915_BREADCRUMB_INDEX 0x21
83 void i915_update_dri1_breadcrumb(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 struct drm_i915_master_private
*master_priv
;
89 * The dri breadcrumb update races against the drm master disappearing.
90 * Instead of trying to fix this (this is by far not the only ums issue)
91 * just don't do the update in kms mode.
93 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
96 if (dev
->primary
->master
) {
97 master_priv
= dev
->primary
->master
->driver_priv
;
98 if (master_priv
->sarea_priv
)
99 master_priv
->sarea_priv
->last_dispatch
=
100 READ_BREADCRUMB(dev_priv
);
104 static void i915_write_hws_pga(struct drm_device
*dev
)
106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
109 addr
= dev_priv
->status_page_dmah
->busaddr
;
110 if (INTEL_INFO(dev
)->gen
>= 4)
111 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
112 I915_WRITE(HWS_PGA
, addr
);
116 * Frees the hardware status page, whether it's a physical address or a virtual
117 * address set up by the X Server.
119 static void i915_free_hws(struct drm_device
*dev
)
121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
122 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
124 if (dev_priv
->status_page_dmah
) {
125 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
126 dev_priv
->status_page_dmah
= NULL
;
129 if (ring
->status_page
.gfx_addr
) {
130 ring
->status_page
.gfx_addr
= 0;
131 iounmap(dev_priv
->dri1
.gfx_hws_cpu_addr
);
134 /* Need to rewrite hardware status page */
135 I915_WRITE(HWS_PGA
, 0x1ffff000);
138 void i915_kernel_lost_context(struct drm_device
* dev
)
140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 struct drm_i915_master_private
*master_priv
;
142 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
145 * We should never lose context on the ring with modesetting
146 * as we don't expose it to userspace
148 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
151 ring
->head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
152 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
153 ring
->space
= ring
->head
- (ring
->tail
+ I915_RING_FREE_SPACE
);
155 ring
->space
+= ring
->size
;
157 if (!dev
->primary
->master
)
160 master_priv
= dev
->primary
->master
->driver_priv
;
161 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
162 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
165 static int i915_dma_cleanup(struct drm_device
* dev
)
167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 /* Make sure interrupts are disabled here because the uninstall ioctl
171 * may not have been called from userspace and after dev_private
172 * is freed, it's too late.
174 if (dev
->irq_enabled
)
175 drm_irq_uninstall(dev
);
177 mutex_lock(&dev
->struct_mutex
);
178 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
179 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
180 mutex_unlock(&dev
->struct_mutex
);
182 /* Clear the HWS virtual address at teardown */
183 if (I915_NEED_GFX_HWS(dev
))
189 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
195 master_priv
->sarea
= drm_getsarea(dev
);
196 if (master_priv
->sarea
) {
197 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
198 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
200 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
203 if (init
->ring_size
!= 0) {
204 if (LP_RING(dev_priv
)->obj
!= NULL
) {
205 i915_dma_cleanup(dev
);
206 DRM_ERROR("Client tried to initialize ringbuffer in "
211 ret
= intel_render_ring_init_dri(dev
,
215 i915_dma_cleanup(dev
);
220 dev_priv
->dri1
.cpp
= init
->cpp
;
221 dev_priv
->dri1
.back_offset
= init
->back_offset
;
222 dev_priv
->dri1
.front_offset
= init
->front_offset
;
223 dev_priv
->dri1
.current_page
= 0;
224 if (master_priv
->sarea_priv
)
225 master_priv
->sarea_priv
->pf_current_page
= 0;
227 /* Allow hardware batchbuffers unless told otherwise.
229 dev_priv
->dri1
.allow_batchbuffer
= 1;
234 static int i915_dma_resume(struct drm_device
* dev
)
236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
237 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
239 DRM_DEBUG_DRIVER("%s\n", __func__
);
241 if (ring
->virtual_start
== NULL
) {
242 DRM_ERROR("can not ioremap virtual address for"
247 /* Program Hardware Status Page */
248 if (!ring
->status_page
.page_addr
) {
249 DRM_ERROR("Can not find hardware status page\n");
252 DRM_DEBUG_DRIVER("hw status page @ %p\n",
253 ring
->status_page
.page_addr
);
254 if (ring
->status_page
.gfx_addr
!= 0)
255 intel_ring_setup_status_page(ring
);
257 i915_write_hws_pga(dev
);
259 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
264 static int i915_dma_init(struct drm_device
*dev
, void *data
,
265 struct drm_file
*file_priv
)
267 drm_i915_init_t
*init
= data
;
270 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
273 switch (init
->func
) {
275 retcode
= i915_initialize(dev
, init
);
277 case I915_CLEANUP_DMA
:
278 retcode
= i915_dma_cleanup(dev
);
280 case I915_RESUME_DMA
:
281 retcode
= i915_dma_resume(dev
);
291 /* Implement basically the same security restrictions as hardware does
292 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
294 * Most of the calculations below involve calculating the size of a
295 * particular instruction. It's important to get the size right as
296 * that tells us where the next instruction to check is. Any illegal
297 * instruction detected will be given a size of zero, which is a
298 * signal to abort the rest of the buffer.
300 static int validate_cmd(int cmd
)
302 switch (((cmd
>> 29) & 0x7)) {
304 switch ((cmd
>> 23) & 0x3f) {
306 return 1; /* MI_NOOP */
308 return 1; /* MI_FLUSH */
310 return 0; /* disallow everything else */
314 return 0; /* reserved */
316 return (cmd
& 0xff) + 2; /* 2d commands */
318 if (((cmd
>> 24) & 0x1f) <= 0x18)
321 switch ((cmd
>> 24) & 0x1f) {
325 switch ((cmd
>> 16) & 0xff) {
327 return (cmd
& 0x1f) + 2;
329 return (cmd
& 0xf) + 2;
331 return (cmd
& 0xffff) + 2;
335 return (cmd
& 0xffff) + 1;
339 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
340 return (cmd
& 0x1ffff) + 2;
341 else if (cmd
& (1 << 17)) /* indirect random */
342 if ((cmd
& 0xffff) == 0)
343 return 0; /* unknown length, too hard */
345 return (((cmd
& 0xffff) + 1) / 2) + 1;
347 return 2; /* indirect sequential */
358 static int i915_emit_cmds(struct drm_device
* dev
, int *buffer
, int dwords
)
360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
363 if ((dwords
+1) * sizeof(int) >= LP_RING(dev_priv
)->size
- 8)
366 for (i
= 0; i
< dwords
;) {
367 int sz
= validate_cmd(buffer
[i
]);
368 if (sz
== 0 || i
+ sz
> dwords
)
373 ret
= BEGIN_LP_RING((dwords
+1)&~1);
377 for (i
= 0; i
< dwords
; i
++)
388 i915_emit_box(struct drm_device
*dev
,
389 struct drm_clip_rect
*box
,
392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
395 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
396 box
->y2
<= 0 || box
->x2
<= 0) {
397 DRM_ERROR("Bad box %d,%d..%d,%d\n",
398 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
402 if (INTEL_INFO(dev
)->gen
>= 4) {
403 ret
= BEGIN_LP_RING(4);
407 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
408 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
409 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
412 ret
= BEGIN_LP_RING(6);
416 OUT_RING(GFX_OP_DRAWRECT_INFO
);
418 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
419 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
428 /* XXX: Emitting the counter should really be moved to part of the IRQ
429 * emit. For now, do it in both places:
432 static void i915_emit_breadcrumb(struct drm_device
*dev
)
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
435 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
437 dev_priv
->dri1
.counter
++;
438 if (dev_priv
->dri1
.counter
> 0x7FFFFFFFUL
)
439 dev_priv
->dri1
.counter
= 0;
440 if (master_priv
->sarea_priv
)
441 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->dri1
.counter
;
443 if (BEGIN_LP_RING(4) == 0) {
444 OUT_RING(MI_STORE_DWORD_INDEX
);
445 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
446 OUT_RING(dev_priv
->dri1
.counter
);
452 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
453 drm_i915_cmdbuffer_t
*cmd
,
454 struct drm_clip_rect
*cliprects
,
457 int nbox
= cmd
->num_cliprects
;
458 int i
= 0, count
, ret
;
461 DRM_ERROR("alignment");
465 i915_kernel_lost_context(dev
);
467 count
= nbox
? nbox
: 1;
469 for (i
= 0; i
< count
; i
++) {
471 ret
= i915_emit_box(dev
, &cliprects
[i
],
477 ret
= i915_emit_cmds(dev
, cmdbuf
, cmd
->sz
/ 4);
482 i915_emit_breadcrumb(dev
);
486 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
487 drm_i915_batchbuffer_t
* batch
,
488 struct drm_clip_rect
*cliprects
)
490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
491 int nbox
= batch
->num_cliprects
;
494 if ((batch
->start
| batch
->used
) & 0x7) {
495 DRM_ERROR("alignment");
499 i915_kernel_lost_context(dev
);
501 count
= nbox
? nbox
: 1;
502 for (i
= 0; i
< count
; i
++) {
504 ret
= i915_emit_box(dev
, &cliprects
[i
],
505 batch
->DR1
, batch
->DR4
);
510 if (!IS_I830(dev
) && !IS_845G(dev
)) {
511 ret
= BEGIN_LP_RING(2);
515 if (INTEL_INFO(dev
)->gen
>= 4) {
516 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
517 OUT_RING(batch
->start
);
519 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
520 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
523 ret
= BEGIN_LP_RING(4);
527 OUT_RING(MI_BATCH_BUFFER
);
528 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
529 OUT_RING(batch
->start
+ batch
->used
- 4);
536 if (IS_G4X(dev
) || IS_GEN5(dev
)) {
537 if (BEGIN_LP_RING(2) == 0) {
538 OUT_RING(MI_FLUSH
| MI_NO_WRITE_FLUSH
| MI_INVALIDATE_ISP
);
544 i915_emit_breadcrumb(dev
);
548 static int i915_dispatch_flip(struct drm_device
* dev
)
550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
551 struct drm_i915_master_private
*master_priv
=
552 dev
->primary
->master
->driver_priv
;
555 if (!master_priv
->sarea_priv
)
558 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
560 dev_priv
->dri1
.current_page
,
561 master_priv
->sarea_priv
->pf_current_page
);
563 i915_kernel_lost_context(dev
);
565 ret
= BEGIN_LP_RING(10);
569 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
572 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
574 if (dev_priv
->dri1
.current_page
== 0) {
575 OUT_RING(dev_priv
->dri1
.back_offset
);
576 dev_priv
->dri1
.current_page
= 1;
578 OUT_RING(dev_priv
->dri1
.front_offset
);
579 dev_priv
->dri1
.current_page
= 0;
583 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
588 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->dri1
.counter
++;
590 if (BEGIN_LP_RING(4) == 0) {
591 OUT_RING(MI_STORE_DWORD_INDEX
);
592 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
593 OUT_RING(dev_priv
->dri1
.counter
);
598 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->dri1
.current_page
;
602 static int i915_quiescent(struct drm_device
*dev
)
604 i915_kernel_lost_context(dev
);
605 return intel_ring_idle(LP_RING(dev
->dev_private
));
608 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
609 struct drm_file
*file_priv
)
613 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
616 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
618 mutex_lock(&dev
->struct_mutex
);
619 ret
= i915_quiescent(dev
);
620 mutex_unlock(&dev
->struct_mutex
);
625 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
626 struct drm_file
*file_priv
)
628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
629 struct drm_i915_master_private
*master_priv
;
630 drm_i915_sarea_t
*sarea_priv
;
631 drm_i915_batchbuffer_t
*batch
= data
;
633 struct drm_clip_rect
*cliprects
= NULL
;
635 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
638 master_priv
= dev
->primary
->master
->driver_priv
;
639 sarea_priv
= (drm_i915_sarea_t
*) master_priv
->sarea_priv
;
641 if (!dev_priv
->dri1
.allow_batchbuffer
) {
642 DRM_ERROR("Batchbuffer ioctl disabled\n");
646 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
647 batch
->start
, batch
->used
, batch
->num_cliprects
);
649 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
651 if (batch
->num_cliprects
< 0)
654 if (batch
->num_cliprects
) {
655 cliprects
= kcalloc(batch
->num_cliprects
,
658 if (cliprects
== NULL
)
661 ret
= copy_from_user(cliprects
, batch
->cliprects
,
662 batch
->num_cliprects
*
663 sizeof(struct drm_clip_rect
));
670 mutex_lock(&dev
->struct_mutex
);
671 ret
= i915_dispatch_batchbuffer(dev
, batch
, cliprects
);
672 mutex_unlock(&dev
->struct_mutex
);
675 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
683 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
684 struct drm_file
*file_priv
)
686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
687 struct drm_i915_master_private
*master_priv
;
688 drm_i915_sarea_t
*sarea_priv
;
689 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
690 struct drm_clip_rect
*cliprects
= NULL
;
694 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
695 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
697 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
700 master_priv
= dev
->primary
->master
->driver_priv
;
701 sarea_priv
= (drm_i915_sarea_t
*) master_priv
->sarea_priv
;
703 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
705 if (cmdbuf
->num_cliprects
< 0)
708 batch_data
= kmalloc(cmdbuf
->sz
, GFP_KERNEL
);
709 if (batch_data
== NULL
)
712 ret
= copy_from_user(batch_data
, cmdbuf
->buf
, cmdbuf
->sz
);
715 goto fail_batch_free
;
718 if (cmdbuf
->num_cliprects
) {
719 cliprects
= kcalloc(cmdbuf
->num_cliprects
,
720 sizeof(*cliprects
), GFP_KERNEL
);
721 if (cliprects
== NULL
) {
723 goto fail_batch_free
;
726 ret
= copy_from_user(cliprects
, cmdbuf
->cliprects
,
727 cmdbuf
->num_cliprects
*
728 sizeof(struct drm_clip_rect
));
735 mutex_lock(&dev
->struct_mutex
);
736 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
, cliprects
, batch_data
);
737 mutex_unlock(&dev
->struct_mutex
);
739 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
744 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
754 static int i915_emit_irq(struct drm_device
* dev
)
756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
757 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
759 i915_kernel_lost_context(dev
);
761 DRM_DEBUG_DRIVER("\n");
763 dev_priv
->dri1
.counter
++;
764 if (dev_priv
->dri1
.counter
> 0x7FFFFFFFUL
)
765 dev_priv
->dri1
.counter
= 1;
766 if (master_priv
->sarea_priv
)
767 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->dri1
.counter
;
769 if (BEGIN_LP_RING(4) == 0) {
770 OUT_RING(MI_STORE_DWORD_INDEX
);
771 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
772 OUT_RING(dev_priv
->dri1
.counter
);
773 OUT_RING(MI_USER_INTERRUPT
);
777 return dev_priv
->dri1
.counter
;
780 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
783 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
785 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
787 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr
,
788 READ_BREADCRUMB(dev_priv
));
790 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
791 if (master_priv
->sarea_priv
)
792 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
796 if (master_priv
->sarea_priv
)
797 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
799 if (ring
->irq_get(ring
)) {
800 DRM_WAIT_ON(ret
, ring
->irq_queue
, 3 * HZ
,
801 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
803 } else if (wait_for(READ_BREADCRUMB(dev_priv
) >= irq_nr
, 3000))
807 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
808 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->dri1
.counter
);
814 /* Needs the lock as it touches the ring.
816 static int i915_irq_emit(struct drm_device
*dev
, void *data
,
817 struct drm_file
*file_priv
)
819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 drm_i915_irq_emit_t
*emit
= data
;
823 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
826 if (!dev_priv
|| !LP_RING(dev_priv
)->virtual_start
) {
827 DRM_ERROR("called with no initialization\n");
831 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
833 mutex_lock(&dev
->struct_mutex
);
834 result
= i915_emit_irq(dev
);
835 mutex_unlock(&dev
->struct_mutex
);
837 if (copy_to_user(emit
->irq_seq
, &result
, sizeof(int))) {
838 DRM_ERROR("copy_to_user\n");
845 /* Doesn't need the hardware lock.
847 static int i915_irq_wait(struct drm_device
*dev
, void *data
,
848 struct drm_file
*file_priv
)
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
851 drm_i915_irq_wait_t
*irqwait
= data
;
853 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
857 DRM_ERROR("called with no initialization\n");
861 return i915_wait_irq(dev
, irqwait
->irq_seq
);
864 static int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
865 struct drm_file
*file_priv
)
867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
868 drm_i915_vblank_pipe_t
*pipe
= data
;
870 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
874 DRM_ERROR("called with no initialization\n");
878 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
884 * Schedule buffer swap at given vertical blank.
886 static int i915_vblank_swap(struct drm_device
*dev
, void *data
,
887 struct drm_file
*file_priv
)
889 /* The delayed swap mechanism was fundamentally racy, and has been
890 * removed. The model was that the client requested a delayed flip/swap
891 * from the kernel, then waited for vblank before continuing to perform
892 * rendering. The problem was that the kernel might wake the client
893 * up before it dispatched the vblank swap (since the lock has to be
894 * held while touching the ringbuffer), in which case the client would
895 * clear and start the next frame before the swap occurred, and
896 * flicker would occur in addition to likely missing the vblank.
898 * In the absence of this ioctl, userland falls back to a correct path
899 * of waiting for a vblank, then dispatching the swap on its own.
900 * Context switching to userland and back is plenty fast enough for
901 * meeting the requirements of vblank swapping.
906 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
907 struct drm_file
*file_priv
)
911 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
914 DRM_DEBUG_DRIVER("%s\n", __func__
);
916 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
918 mutex_lock(&dev
->struct_mutex
);
919 ret
= i915_dispatch_flip(dev
);
920 mutex_unlock(&dev
->struct_mutex
);
925 static int i915_getparam(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file_priv
)
928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
929 drm_i915_getparam_t
*param
= data
;
933 DRM_ERROR("called with no initialization\n");
937 switch (param
->param
) {
938 case I915_PARAM_IRQ_ACTIVE
:
939 value
= dev
->pdev
->irq
? 1 : 0;
941 case I915_PARAM_ALLOW_BATCHBUFFER
:
942 value
= dev_priv
->dri1
.allow_batchbuffer
? 1 : 0;
944 case I915_PARAM_LAST_DISPATCH
:
945 value
= READ_BREADCRUMB(dev_priv
);
947 case I915_PARAM_CHIPSET_ID
:
948 value
= dev
->pdev
->device
;
950 case I915_PARAM_HAS_GEM
:
953 case I915_PARAM_NUM_FENCES_AVAIL
:
954 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
956 case I915_PARAM_HAS_OVERLAY
:
957 value
= dev_priv
->overlay
? 1 : 0;
959 case I915_PARAM_HAS_PAGEFLIPPING
:
962 case I915_PARAM_HAS_EXECBUF2
:
966 case I915_PARAM_HAS_BSD
:
967 value
= intel_ring_initialized(&dev_priv
->ring
[VCS
]);
969 case I915_PARAM_HAS_BLT
:
970 value
= intel_ring_initialized(&dev_priv
->ring
[BCS
]);
972 case I915_PARAM_HAS_VEBOX
:
973 value
= intel_ring_initialized(&dev_priv
->ring
[VECS
]);
975 case I915_PARAM_HAS_RELAXED_FENCING
:
978 case I915_PARAM_HAS_COHERENT_RINGS
:
981 case I915_PARAM_HAS_EXEC_CONSTANTS
:
982 value
= INTEL_INFO(dev
)->gen
>= 4;
984 case I915_PARAM_HAS_RELAXED_DELTA
:
987 case I915_PARAM_HAS_GEN7_SOL_RESET
:
990 case I915_PARAM_HAS_LLC
:
991 value
= HAS_LLC(dev
);
993 case I915_PARAM_HAS_WT
:
996 case I915_PARAM_HAS_ALIASING_PPGTT
:
997 value
= dev_priv
->mm
.aliasing_ppgtt
|| USES_FULL_PPGTT(dev
);
999 case I915_PARAM_HAS_WAIT_TIMEOUT
:
1002 case I915_PARAM_HAS_SEMAPHORES
:
1003 value
= i915_semaphore_is_enabled(dev
);
1005 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
1008 case I915_PARAM_HAS_SECURE_BATCHES
:
1009 value
= capable(CAP_SYS_ADMIN
);
1011 case I915_PARAM_HAS_PINNED_BATCHES
:
1014 case I915_PARAM_HAS_EXEC_NO_RELOC
:
1017 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
1020 case I915_PARAM_CMD_PARSER_VERSION
:
1021 value
= i915_cmd_parser_get_version();
1024 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
1028 if (copy_to_user(param
->value
, &value
, sizeof(int))) {
1029 DRM_ERROR("copy_to_user failed\n");
1036 static int i915_setparam(struct drm_device
*dev
, void *data
,
1037 struct drm_file
*file_priv
)
1039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 drm_i915_setparam_t
*param
= data
;
1043 DRM_ERROR("called with no initialization\n");
1047 switch (param
->param
) {
1048 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
1050 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
1052 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
1053 dev_priv
->dri1
.allow_batchbuffer
= param
->value
? 1 : 0;
1055 case I915_SETPARAM_NUM_USED_FENCES
:
1056 if (param
->value
> dev_priv
->num_fence_regs
||
1059 /* Userspace can use first N regs */
1060 dev_priv
->fence_reg_start
= param
->value
;
1063 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1071 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
1072 struct drm_file
*file_priv
)
1074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1075 drm_i915_hws_addr_t
*hws
= data
;
1076 struct intel_ring_buffer
*ring
;
1078 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1081 if (!I915_NEED_GFX_HWS(dev
))
1085 DRM_ERROR("called with no initialization\n");
1089 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1090 WARN(1, "tried to set status page when mode setting active\n");
1094 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32
)hws
->addr
);
1096 ring
= LP_RING(dev_priv
);
1097 ring
->status_page
.gfx_addr
= hws
->addr
& (0x1ffff<<12);
1099 dev_priv
->dri1
.gfx_hws_cpu_addr
=
1100 ioremap_wc(dev_priv
->gtt
.mappable_base
+ hws
->addr
, 4096);
1101 if (dev_priv
->dri1
.gfx_hws_cpu_addr
== NULL
) {
1102 i915_dma_cleanup(dev
);
1103 ring
->status_page
.gfx_addr
= 0;
1104 DRM_ERROR("can not ioremap virtual address for"
1105 " G33 hw status page\n");
1109 memset_io(dev_priv
->dri1
.gfx_hws_cpu_addr
, 0, PAGE_SIZE
);
1110 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
1112 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1113 ring
->status_page
.gfx_addr
);
1114 DRM_DEBUG_DRIVER("load hws at %p\n",
1115 ring
->status_page
.page_addr
);
1119 static int i915_get_bridge_dev(struct drm_device
*dev
)
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1123 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1124 if (!dev_priv
->bridge_dev
) {
1125 DRM_ERROR("bridge device not found\n");
1131 #define MCHBAR_I915 0x44
1132 #define MCHBAR_I965 0x48
1133 #define MCHBAR_SIZE (4*4096)
1135 #define DEVEN_REG 0x54
1136 #define DEVEN_MCHBAR_EN (1 << 28)
1138 /* Allocate space for the MCH regs if needed, return nonzero on error */
1140 intel_alloc_mchbar_resource(struct drm_device
*dev
)
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1143 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1144 u32 temp_lo
, temp_hi
= 0;
1148 if (INTEL_INFO(dev
)->gen
>= 4)
1149 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
1150 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
1151 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
1153 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1156 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
1160 /* Get some space for it */
1161 dev_priv
->mch_res
.name
= "i915 MCHBAR";
1162 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
1163 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
1165 MCHBAR_SIZE
, MCHBAR_SIZE
,
1167 0, pcibios_align_resource
,
1168 dev_priv
->bridge_dev
);
1170 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
1171 dev_priv
->mch_res
.start
= 0;
1175 if (INTEL_INFO(dev
)->gen
>= 4)
1176 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
1177 upper_32_bits(dev_priv
->mch_res
.start
));
1179 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
1180 lower_32_bits(dev_priv
->mch_res
.start
));
1184 /* Setup MCHBAR if possible, return true if we should disable it again */
1186 intel_setup_mchbar(struct drm_device
*dev
)
1188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1189 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1193 if (IS_VALLEYVIEW(dev
))
1196 dev_priv
->mchbar_need_disable
= false;
1198 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1199 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1200 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
1202 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1206 /* If it's already enabled, don't have to do anything */
1210 if (intel_alloc_mchbar_resource(dev
))
1213 dev_priv
->mchbar_need_disable
= true;
1215 /* Space is allocated or reserved, so enable it. */
1216 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1217 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
1218 temp
| DEVEN_MCHBAR_EN
);
1220 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1221 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
1226 intel_teardown_mchbar(struct drm_device
*dev
)
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1229 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1232 if (dev_priv
->mchbar_need_disable
) {
1233 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1234 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1235 temp
&= ~DEVEN_MCHBAR_EN
;
1236 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
1238 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1240 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
1244 if (dev_priv
->mch_res
.start
)
1245 release_resource(&dev_priv
->mch_res
);
1248 /* true = enable decode, false = disable decoder */
1249 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
1251 struct drm_device
*dev
= cookie
;
1253 intel_modeset_vga_set_state(dev
, state
);
1255 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1256 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1258 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1261 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1263 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1264 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
1265 if (state
== VGA_SWITCHEROO_ON
) {
1266 pr_info("switched on\n");
1267 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1268 /* i915 resume handler doesn't set to D0 */
1269 pci_set_power_state(dev
->pdev
, PCI_D0
);
1271 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1273 pr_err("switched off\n");
1274 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1275 i915_suspend(dev
, pmm
);
1276 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1280 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
1282 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1285 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1286 * locking inversion with the driver load path. And the access here is
1287 * completely racy anyway. So don't bother with locking for now.
1289 return dev
->open_count
== 0;
1292 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
1293 .set_gpu_state
= i915_switcheroo_set_state
,
1295 .can_switch
= i915_switcheroo_can_switch
,
1298 static int i915_load_modeset_init(struct drm_device
*dev
)
1300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1303 ret
= intel_parse_bios(dev
);
1305 DRM_INFO("failed to find VBIOS tables\n");
1307 /* If we have > 1 VGA cards, then we need to arbitrate access
1308 * to the common VGA resources.
1310 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1311 * then we do not take part in VGA arbitration and the
1312 * vga_client_register() fails with -ENODEV.
1314 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
1315 if (ret
&& ret
!= -ENODEV
)
1318 intel_register_dsm_handler();
1320 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
, false);
1322 goto cleanup_vga_client
;
1324 /* Initialise stolen first so that we may reserve preallocated
1325 * objects for the BIOS to KMS transition.
1327 ret
= i915_gem_init_stolen(dev
);
1329 goto cleanup_vga_switcheroo
;
1331 intel_power_domains_init_hw(dev_priv
);
1333 ret
= drm_irq_install(dev
, dev
->pdev
->irq
);
1335 goto cleanup_gem_stolen
;
1337 /* Important: The output setup functions called by modeset_init need
1338 * working irqs for e.g. gmbus and dp aux transfers. */
1339 intel_modeset_init(dev
);
1341 ret
= i915_gem_init(dev
);
1345 INIT_WORK(&dev_priv
->console_resume_work
, intel_console_resume
);
1347 intel_modeset_gem_init(dev
);
1349 /* Always safe in the mode setting case. */
1350 /* FIXME: do pre/post-mode set stuff in core KMS code */
1351 dev
->vblank_disable_allowed
= true;
1352 if (INTEL_INFO(dev
)->num_pipes
== 0) {
1353 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
1357 ret
= intel_fbdev_init(dev
);
1361 /* Only enable hotplug handling once the fbdev is fully set up. */
1362 intel_hpd_init(dev
);
1365 * Some ports require correctly set-up hpd registers for detection to
1366 * work properly (leading to ghost connected connector status), e.g. VGA
1367 * on gm45. Hence we can only set up the initial fbdev config after hpd
1368 * irqs are fully enabled. Now we should scan for the initial config
1369 * only once hotplug handling is enabled, but due to screwed-up locking
1370 * around kms/fbdev init we can't protect the fdbev initial config
1371 * scanning against hotplug events. Hence do this first and ignore the
1372 * tiny window where we will loose hotplug notifactions.
1374 intel_fbdev_initial_config(dev
);
1376 /* Only enable hotplug handling once the fbdev is fully set up. */
1377 dev_priv
->enable_hotplug_processing
= true;
1379 drm_kms_helper_poll_init(dev
);
1384 mutex_lock(&dev
->struct_mutex
);
1385 i915_gem_cleanup_ringbuffer(dev
);
1386 i915_gem_context_fini(dev
);
1387 mutex_unlock(&dev
->struct_mutex
);
1388 WARN_ON(dev_priv
->mm
.aliasing_ppgtt
);
1389 drm_mm_takedown(&dev_priv
->gtt
.base
.mm
);
1391 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
1392 drm_irq_uninstall(dev
);
1394 i915_gem_cleanup_stolen(dev
);
1395 cleanup_vga_switcheroo
:
1396 vga_switcheroo_unregister_client(dev
->pdev
);
1398 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1403 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1405 struct drm_i915_master_private
*master_priv
;
1407 master_priv
= kzalloc(sizeof(*master_priv
), GFP_KERNEL
);
1411 master
->driver_priv
= master_priv
;
1415 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1417 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1424 master
->driver_priv
= NULL
;
1427 #if IS_ENABLED(CONFIG_FB)
1428 static void i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
1430 struct apertures_struct
*ap
;
1431 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
1434 ap
= alloc_apertures(1);
1438 ap
->ranges
[0].base
= dev_priv
->gtt
.mappable_base
;
1439 ap
->ranges
[0].size
= dev_priv
->gtt
.mappable_end
;
1442 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
1444 remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
1449 static void i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
1454 static void i915_dump_device_info(struct drm_i915_private
*dev_priv
)
1456 const struct intel_device_info
*info
= &dev_priv
->info
;
1458 #define PRINT_S(name) "%s"
1460 #define PRINT_FLAG(name) info->name ? #name "," : ""
1462 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1463 DEV_INFO_FOR_EACH_FLAG(PRINT_S
, SEP_EMPTY
),
1465 dev_priv
->dev
->pdev
->device
,
1466 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_COMMA
));
1474 * Determine various intel_device_info fields at runtime.
1476 * Use it when either:
1477 * - it's judged too laborious to fill n static structures with the limit
1478 * when a simple if statement does the job,
1479 * - run-time checks (eg read fuse/strap registers) are needed.
1481 * This function needs to be called:
1482 * - after the MMIO has been setup as we are reading registers,
1483 * - after the PCH has been detected,
1484 * - before the first usage of the fields it can tweak.
1486 static void intel_device_info_runtime_init(struct drm_device
*dev
)
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 struct intel_device_info
*info
;
1492 info
= (struct intel_device_info
*)&dev_priv
->info
;
1494 if (IS_VALLEYVIEW(dev
))
1496 info
->num_sprites
[pipe
] = 2;
1499 info
->num_sprites
[pipe
] = 1;
1501 if (i915
.disable_display
) {
1502 DRM_INFO("Display disabled (module parameter)\n");
1503 info
->num_pipes
= 0;
1504 } else if (info
->num_pipes
> 0 &&
1505 (INTEL_INFO(dev
)->gen
== 7 || INTEL_INFO(dev
)->gen
== 8) &&
1506 !IS_VALLEYVIEW(dev
)) {
1507 u32 fuse_strap
= I915_READ(FUSE_STRAP
);
1508 u32 sfuse_strap
= I915_READ(SFUSE_STRAP
);
1511 * SFUSE_STRAP is supposed to have a bit signalling the display
1512 * is fused off. Unfortunately it seems that, at least in
1513 * certain cases, fused off display means that PCH display
1514 * reads don't land anywhere. In that case, we read 0s.
1516 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1517 * should be set when taking over after the firmware.
1519 if (fuse_strap
& ILK_INTERNAL_DISPLAY_DISABLE
||
1520 sfuse_strap
& SFUSE_STRAP_DISPLAY_DISABLED
||
1521 (dev_priv
->pch_type
== PCH_CPT
&&
1522 !(sfuse_strap
& SFUSE_STRAP_FUSE_LOCK
))) {
1523 DRM_INFO("Display fused off, disabling\n");
1524 info
->num_pipes
= 0;
1530 * i915_driver_load - setup chip and create an initial config
1532 * @flags: startup flags
1534 * The driver load routine has to do several things:
1535 * - drive output discovery via intel_modeset_init()
1536 * - initialize the memory manager
1537 * - allocate initial config memory
1538 * - setup the DRM framebuffer with the allocated memory
1540 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
1542 struct drm_i915_private
*dev_priv
;
1543 struct intel_device_info
*info
, *device_info
;
1544 int ret
= 0, mmio_bar
, mmio_size
;
1545 uint32_t aperture_size
;
1547 info
= (struct intel_device_info
*) flags
;
1549 /* Refuse to load on gen6+ without kms enabled. */
1550 if (info
->gen
>= 6 && !drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1551 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1552 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1556 /* UMS needs agp support. */
1557 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && !dev
->agp
)
1560 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1561 if (dev_priv
== NULL
)
1564 dev
->dev_private
= (void *)dev_priv
;
1565 dev_priv
->dev
= dev
;
1567 /* copy initial configuration to dev_priv->info */
1568 device_info
= (struct intel_device_info
*)&dev_priv
->info
;
1569 *device_info
= *info
;
1571 spin_lock_init(&dev_priv
->irq_lock
);
1572 spin_lock_init(&dev_priv
->gpu_error
.lock
);
1573 spin_lock_init(&dev_priv
->backlight_lock
);
1574 spin_lock_init(&dev_priv
->uncore
.lock
);
1575 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
1576 mutex_init(&dev_priv
->dpio_lock
);
1577 mutex_init(&dev_priv
->modeset_restore_lock
);
1579 intel_pm_setup(dev
);
1581 intel_display_crc_init(dev
);
1583 i915_dump_device_info(dev_priv
);
1585 /* Not all pre-production machines fall into this category, only the
1586 * very first ones. Almost everything should work, except for maybe
1587 * suspend/resume. And we don't implement workarounds that affect only
1588 * pre-production machines. */
1589 if (IS_HSW_EARLY_SDV(dev
))
1590 DRM_INFO("This is an early pre-production Haswell machine. "
1591 "It may not be fully functional.\n");
1593 if (i915_get_bridge_dev(dev
)) {
1598 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
1599 /* Before gen4, the registers and the GTT are behind different BARs.
1600 * However, from gen4 onwards, the registers and the GTT are shared
1601 * in the same BAR, so we want to restrict this ioremap from
1602 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1603 * the register BAR remains the same size for all the earlier
1604 * generations up to Ironlake.
1607 mmio_size
= 512*1024;
1609 mmio_size
= 2*1024*1024;
1611 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, mmio_size
);
1612 if (!dev_priv
->regs
) {
1613 DRM_ERROR("failed to map registers\n");
1618 /* This must be called before any calls to HAS_PCH_* */
1619 intel_detect_pch(dev
);
1621 intel_uncore_init(dev
);
1623 ret
= i915_gem_gtt_init(dev
);
1627 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1628 i915_kick_out_firmware_fb(dev_priv
);
1630 pci_set_master(dev
->pdev
);
1632 /* overlay on gen2 is broken and can't address above 1G */
1634 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
1636 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1637 * using 32bit addressing, overwriting memory if HWS is located
1640 * The documentation also mentions an issue with undefined
1641 * behaviour if any general state is accessed within a page above 4GB,
1642 * which also needs to be handled carefully.
1644 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1645 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
1647 aperture_size
= dev_priv
->gtt
.mappable_end
;
1649 dev_priv
->gtt
.mappable
=
1650 io_mapping_create_wc(dev_priv
->gtt
.mappable_base
,
1652 if (dev_priv
->gtt
.mappable
== NULL
) {
1657 dev_priv
->gtt
.mtrr
= arch_phys_wc_add(dev_priv
->gtt
.mappable_base
,
1660 /* The i915 workqueue is primarily used for batched retirement of
1661 * requests (and thus managing bo) once the task has been completed
1662 * by the GPU. i915_gem_retire_requests() is called directly when we
1663 * need high-priority retirement, such as waiting for an explicit
1666 * It is also used for periodic low-priority events, such as
1667 * idle-timers and recording error state.
1669 * All tasks on the workqueue are expected to acquire the dev mutex
1670 * so there is no point in running more than one instance of the
1671 * workqueue at any time. Use an ordered one.
1673 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
1674 if (dev_priv
->wq
== NULL
) {
1675 DRM_ERROR("Failed to create our workqueue.\n");
1680 intel_irq_init(dev
);
1681 intel_uncore_sanitize(dev
);
1683 /* Try to make sure MCHBAR is enabled before poking at it */
1684 intel_setup_mchbar(dev
);
1685 intel_setup_gmbus(dev
);
1686 intel_opregion_setup(dev
);
1688 intel_setup_bios(dev
);
1692 /* On the 945G/GM, the chipset reports the MSI capability on the
1693 * integrated graphics even though the support isn't actually there
1694 * according to the published specs. It doesn't appear to function
1695 * correctly in testing on 945G.
1696 * This may be a side effect of MSI having been made available for PEG
1697 * and the registers being closely associated.
1699 * According to chipset errata, on the 965GM, MSI interrupts may
1700 * be lost or delayed, but we use them anyways to avoid
1701 * stuck interrupts on some machines.
1703 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1704 pci_enable_msi(dev
->pdev
);
1706 intel_device_info_runtime_init(dev
);
1708 if (INTEL_INFO(dev
)->num_pipes
) {
1709 ret
= drm_vblank_init(dev
, INTEL_INFO(dev
)->num_pipes
);
1711 goto out_gem_unload
;
1714 intel_power_domains_init(dev_priv
);
1716 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1717 ret
= i915_load_modeset_init(dev
);
1719 DRM_ERROR("failed to init modeset\n");
1720 goto out_power_well
;
1723 /* Start out suspended in ums mode. */
1724 dev_priv
->ums
.mm_suspended
= 1;
1727 i915_setup_sysfs(dev
);
1729 if (INTEL_INFO(dev
)->num_pipes
) {
1730 /* Must be done after probing outputs */
1731 intel_opregion_init(dev
);
1732 acpi_video_register();
1736 intel_gpu_ips_init(dev_priv
);
1738 intel_init_runtime_pm(dev_priv
);
1743 intel_power_domains_remove(dev_priv
);
1744 drm_vblank_cleanup(dev
);
1746 if (dev_priv
->mm
.inactive_shrinker
.scan_objects
)
1747 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1749 if (dev
->pdev
->msi_enabled
)
1750 pci_disable_msi(dev
->pdev
);
1752 intel_teardown_gmbus(dev
);
1753 intel_teardown_mchbar(dev
);
1754 pm_qos_remove_request(&dev_priv
->pm_qos
);
1755 destroy_workqueue(dev_priv
->wq
);
1757 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
1758 io_mapping_free(dev_priv
->gtt
.mappable
);
1760 list_del(&dev_priv
->gtt
.base
.global_link
);
1761 drm_mm_takedown(&dev_priv
->gtt
.base
.mm
);
1762 dev_priv
->gtt
.base
.cleanup(&dev_priv
->gtt
.base
);
1764 intel_uncore_fini(dev
);
1765 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1767 pci_dev_put(dev_priv
->bridge_dev
);
1770 kmem_cache_destroy(dev_priv
->slab
);
1775 int i915_driver_unload(struct drm_device
*dev
)
1777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1780 ret
= i915_gem_suspend(dev
);
1782 DRM_ERROR("failed to idle hardware: %d\n", ret
);
1786 intel_fini_runtime_pm(dev_priv
);
1788 intel_gpu_ips_teardown();
1790 /* The i915.ko module is still not prepared to be loaded when
1791 * the power well is not enabled, so just enable it in case
1792 * we're going to unload/reload. */
1793 intel_display_set_init_power(dev_priv
, true);
1794 intel_power_domains_remove(dev_priv
);
1796 i915_teardown_sysfs(dev
);
1798 if (dev_priv
->mm
.inactive_shrinker
.scan_objects
)
1799 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1801 io_mapping_free(dev_priv
->gtt
.mappable
);
1802 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
1804 acpi_video_unregister();
1806 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1807 intel_fbdev_fini(dev
);
1808 intel_modeset_cleanup(dev
);
1809 cancel_work_sync(&dev_priv
->console_resume_work
);
1812 * free the memory space allocated for the child device
1813 * config parsed from VBT
1815 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1816 kfree(dev_priv
->vbt
.child_dev
);
1817 dev_priv
->vbt
.child_dev
= NULL
;
1818 dev_priv
->vbt
.child_dev_num
= 0;
1821 vga_switcheroo_unregister_client(dev
->pdev
);
1822 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1825 /* Free error state after interrupts are fully disabled. */
1826 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
1827 cancel_work_sync(&dev_priv
->gpu_error
.work
);
1828 i915_destroy_error_state(dev
);
1830 if (dev
->pdev
->msi_enabled
)
1831 pci_disable_msi(dev
->pdev
);
1833 intel_opregion_fini(dev
);
1835 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1836 /* Flush any outstanding unpin_work. */
1837 flush_workqueue(dev_priv
->wq
);
1839 mutex_lock(&dev
->struct_mutex
);
1840 i915_gem_free_all_phys_object(dev
);
1841 i915_gem_cleanup_ringbuffer(dev
);
1842 i915_gem_context_fini(dev
);
1843 WARN_ON(dev_priv
->mm
.aliasing_ppgtt
);
1844 mutex_unlock(&dev
->struct_mutex
);
1845 i915_gem_cleanup_stolen(dev
);
1847 if (!I915_NEED_GFX_HWS(dev
))
1851 list_del(&dev_priv
->gtt
.base
.global_link
);
1852 WARN_ON(!list_empty(&dev_priv
->vm_list
));
1854 drm_vblank_cleanup(dev
);
1856 intel_teardown_gmbus(dev
);
1857 intel_teardown_mchbar(dev
);
1859 destroy_workqueue(dev_priv
->wq
);
1860 pm_qos_remove_request(&dev_priv
->pm_qos
);
1862 dev_priv
->gtt
.base
.cleanup(&dev_priv
->gtt
.base
);
1864 intel_uncore_fini(dev
);
1865 if (dev_priv
->regs
!= NULL
)
1866 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1869 kmem_cache_destroy(dev_priv
->slab
);
1871 pci_dev_put(dev_priv
->bridge_dev
);
1872 kfree(dev
->dev_private
);
1877 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1881 ret
= i915_gem_open(dev
, file
);
1889 * i915_driver_lastclose - clean up after all DRM clients have exited
1892 * Take care of cleaning up after all DRM clients have exited. In the
1893 * mode setting case, we want to restore the kernel's initial mode (just
1894 * in case the last client left us in a bad state).
1896 * Additionally, in the non-mode setting case, we'll tear down the GTT
1897 * and DMA structures, since the kernel won't be using them, and clea
1900 void i915_driver_lastclose(struct drm_device
* dev
)
1902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1904 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1905 * goes right around and calls lastclose. Check for this and don't clean
1910 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1911 intel_fbdev_restore_mode(dev
);
1912 vga_switcheroo_process_delayed_switch();
1916 i915_gem_lastclose(dev
);
1918 i915_dma_cleanup(dev
);
1921 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
1923 mutex_lock(&dev
->struct_mutex
);
1924 i915_gem_context_close(dev
, file_priv
);
1925 i915_gem_release(dev
, file_priv
);
1926 mutex_unlock(&dev
->struct_mutex
);
1929 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1931 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1936 const struct drm_ioctl_desc i915_ioctls
[] = {
1937 DRM_IOCTL_DEF_DRV(I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1938 DRM_IOCTL_DEF_DRV(I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
1939 DRM_IOCTL_DEF_DRV(I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
1940 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
1941 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
1942 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
1943 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1944 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1945 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1946 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1947 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1948 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
1949 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1950 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1951 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
1952 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
1953 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1954 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1955 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1956 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1957 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1958 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1959 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1960 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1961 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1962 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1963 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1964 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1965 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1966 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1967 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1968 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1969 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1970 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1971 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1972 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1973 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1974 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1975 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1976 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1977 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1978 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1979 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1980 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, intel_sprite_get_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1981 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1982 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1983 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1984 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1985 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_get_reset_stats_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1988 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
1991 * This is really ugly: Because old userspace abused the linux agp interface to
1992 * manage the gtt, we need to claim that all intel devices are agp. For
1993 * otherwise the drm core refuses to initialize the agp support code.
1995 int i915_driver_device_is_agp(struct drm_device
* dev
)