drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static struct drm_driver driver;
  42
  43 #define GEN_DEFAULT_PIPEOFFSETS \
  44         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  45                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  46         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  47                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  48         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
  49         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52
  53 static const struct intel_device_info intel_i830_info = {
  54         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  55         .has_overlay = 1, .overlay_needs_physical = 1,
  56         .ring_mask = RENDER_RING,
  57         GEN_DEFAULT_PIPEOFFSETS,
  58 };
  59
  60 static const struct intel_device_info intel_845g_info = {
  61         .gen = 2, .num_pipes = 1,
  62         .has_overlay = 1, .overlay_needs_physical = 1,
  63         .ring_mask = RENDER_RING,
  64         GEN_DEFAULT_PIPEOFFSETS,
  65 };
  66
  67 static const struct intel_device_info intel_i85x_info = {
  68         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  69         .cursor_needs_physical = 1,
  70         .has_overlay = 1, .overlay_needs_physical = 1,
  71         .has_fbc = 1,
  72         .ring_mask = RENDER_RING,
  73         GEN_DEFAULT_PIPEOFFSETS,
  74 };
  75
  76 static const struct intel_device_info intel_i865g_info = {
  77         .gen = 2, .num_pipes = 1,
  78         .has_overlay = 1, .overlay_needs_physical = 1,
  79         .ring_mask = RENDER_RING,
  80         GEN_DEFAULT_PIPEOFFSETS,
  81 };
  82
  83 static const struct intel_device_info intel_i915g_info = {
  84         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .ring_mask = RENDER_RING,
  87         GEN_DEFAULT_PIPEOFFSETS,
  88 };
  89 static const struct intel_device_info intel_i915gm_info = {
  90         .gen = 3, .is_mobile = 1, .num_pipes = 2,
  91         .cursor_needs_physical = 1,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93         .supports_tv = 1,
  94         .has_fbc = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97 };
  98 static const struct intel_device_info intel_i945g_info = {
  99         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101         .ring_mask = RENDER_RING,
 102         GEN_DEFAULT_PIPEOFFSETS,
 103 };
 104 static const struct intel_device_info intel_i945gm_info = {
 105         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 106         .has_hotplug = 1, .cursor_needs_physical = 1,
 107         .has_overlay = 1, .overlay_needs_physical = 1,
 108         .supports_tv = 1,
 109         .has_fbc = 1,
 110         .ring_mask = RENDER_RING,
 111         GEN_DEFAULT_PIPEOFFSETS,
 112 };
 113
 114 static const struct intel_device_info intel_i965g_info = {
 115         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 116         .has_hotplug = 1,
 117         .has_overlay = 1,
 118         .ring_mask = RENDER_RING,
 119         GEN_DEFAULT_PIPEOFFSETS,
 120 };
 121
 122 static const struct intel_device_info intel_i965gm_info = {
 123         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 124         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 125         .has_overlay = 1,
 126         .supports_tv = 1,
 127         .ring_mask = RENDER_RING,
 128         GEN_DEFAULT_PIPEOFFSETS,
 129 };
 130
 131 static const struct intel_device_info intel_g33_info = {
 132         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 133         .need_gfx_hws = 1, .has_hotplug = 1,
 134         .has_overlay = 1,
 135         .ring_mask = RENDER_RING,
 136         GEN_DEFAULT_PIPEOFFSETS,
 137 };
 138
 139 static const struct intel_device_info intel_g45_info = {
 140         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 141         .has_pipe_cxsr = 1, .has_hotplug = 1,
 142         .ring_mask = RENDER_RING | BSD_RING,
 143         GEN_DEFAULT_PIPEOFFSETS,
 144 };
 145
 146 static const struct intel_device_info intel_gm45_info = {
 147         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 148         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 149         .has_pipe_cxsr = 1, .has_hotplug = 1,
 150         .supports_tv = 1,
 151         .ring_mask = RENDER_RING | BSD_RING,
 152         GEN_DEFAULT_PIPEOFFSETS,
 153 };
 154
 155 static const struct intel_device_info intel_pineview_info = {
 156         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 157         .need_gfx_hws = 1, .has_hotplug = 1,
 158         .has_overlay = 1,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160 };
 161
 162 static const struct intel_device_info intel_ironlake_d_info = {
 163         .gen = 5, .num_pipes = 2,
 164         .need_gfx_hws = 1, .has_hotplug = 1,
 165         .ring_mask = RENDER_RING | BSD_RING,
 166         GEN_DEFAULT_PIPEOFFSETS,
 167 };
 168
 169 static const struct intel_device_info intel_ironlake_m_info = {
 170         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 171         .need_gfx_hws = 1, .has_hotplug = 1,
 172         .has_fbc = 1,
 173         .ring_mask = RENDER_RING | BSD_RING,
 174         GEN_DEFAULT_PIPEOFFSETS,
 175 };
 176
 177 static const struct intel_device_info intel_sandybridge_d_info = {
 178         .gen = 6, .num_pipes = 2,
 179         .need_gfx_hws = 1, .has_hotplug = 1,
 180         .has_fbc = 1,
 181         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 182         .has_llc = 1,
 183         GEN_DEFAULT_PIPEOFFSETS,
 184 };
 185
 186 static const struct intel_device_info intel_sandybridge_m_info = {
 187         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 188         .need_gfx_hws = 1, .has_hotplug = 1,
 189         .has_fbc = 1,
 190         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 191         .has_llc = 1,
 192         GEN_DEFAULT_PIPEOFFSETS,
 193 };
 194
 195 #define GEN7_FEATURES  \
 196         .gen = 7, .num_pipes = 3, \
 197         .need_gfx_hws = 1, .has_hotplug = 1, \
 198         .has_fbc = 1, \
 199         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 200         .has_llc = 1
 201
 202 static const struct intel_device_info intel_ivybridge_d_info = {
 203         GEN7_FEATURES,
 204         .is_ivybridge = 1,
 205         GEN_DEFAULT_PIPEOFFSETS,
 206 };
 207
 208 static const struct intel_device_info intel_ivybridge_m_info = {
 209         GEN7_FEATURES,
 210         .is_ivybridge = 1,
 211         .is_mobile = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213 };
 214
 215 static const struct intel_device_info intel_ivybridge_q_info = {
 216         GEN7_FEATURES,
 217         .is_ivybridge = 1,
 218         .num_pipes = 0, /* legal, last one wins */
 219         GEN_DEFAULT_PIPEOFFSETS,
 220 };
 221
 222 static const struct intel_device_info intel_valleyview_m_info = {
 223         GEN7_FEATURES,
 224         .is_mobile = 1,
 225         .num_pipes = 2,
 226         .is_valleyview = 1,
 227         .display_mmio_offset = VLV_DISPLAY_BASE,
 228         .has_fbc = 0, /* legal, last one wins */
 229         .has_llc = 0, /* legal, last one wins */
 230         GEN_DEFAULT_PIPEOFFSETS,
 231 };
 232
 233 static const struct intel_device_info intel_valleyview_d_info = {
 234         GEN7_FEATURES,
 235         .num_pipes = 2,
 236         .is_valleyview = 1,
 237         .display_mmio_offset = VLV_DISPLAY_BASE,
 238         .has_fbc = 0, /* legal, last one wins */
 239         .has_llc = 0, /* legal, last one wins */
 240         GEN_DEFAULT_PIPEOFFSETS,
 241 };
 242
 243 static const struct intel_device_info intel_haswell_d_info = {
 244         GEN7_FEATURES,
 245         .is_haswell = 1,
 246         .has_ddi = 1,
 247         .has_fpga_dbg = 1,
 248         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 249         GEN_DEFAULT_PIPEOFFSETS,
 250 };
 251
 252 static const struct intel_device_info intel_haswell_m_info = {
 253         GEN7_FEATURES,
 254         .is_haswell = 1,
 255         .is_mobile = 1,
 256         .has_ddi = 1,
 257         .has_fpga_dbg = 1,
 258         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 259         GEN_DEFAULT_PIPEOFFSETS,
 260 };
 261
 262 static const struct intel_device_info intel_broadwell_d_info = {
 263         .gen = 8, .num_pipes = 3,
 264         .need_gfx_hws = 1, .has_hotplug = 1,
 265         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 266         .has_llc = 1,
 267         .has_ddi = 1,
 268         .has_fbc = 1,
 269         GEN_DEFAULT_PIPEOFFSETS,
 270 };
 271
 272 static const struct intel_device_info intel_broadwell_m_info = {
 273         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 276         .has_llc = 1,
 277         .has_ddi = 1,
 278         .has_fbc = 1,
 279         GEN_DEFAULT_PIPEOFFSETS,
 280 };
 281
 282 /*
 283  * Make sure any device matches here are from most specific to most
 284  * general.  For example, since the Quanta match is based on the subsystem
 285  * and subvendor IDs, we need it to come before the more general IVB
 286  * PCI ID matches, otherwise we'll use the wrong info struct above.
 287  */
 288 #define INTEL_PCI_IDS \
 289         INTEL_I830_IDS(&intel_i830_info),       \
 290         INTEL_I845G_IDS(&intel_845g_info),      \
 291         INTEL_I85X_IDS(&intel_i85x_info),       \
 292         INTEL_I865G_IDS(&intel_i865g_info),     \
 293         INTEL_I915G_IDS(&intel_i915g_info),     \
 294         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 295         INTEL_I945G_IDS(&intel_i945g_info),     \
 296         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 297         INTEL_I965G_IDS(&intel_i965g_info),     \
 298         INTEL_G33_IDS(&intel_g33_info),         \
 299         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 300         INTEL_GM45_IDS(&intel_gm45_info),       \
 301         INTEL_G45_IDS(&intel_g45_info),         \
 302         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 303         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 304         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 305         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 306         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 307         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 308         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 309         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 310         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 311         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 312         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 313         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 314         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 315         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 316
 317 static const struct pci_device_id pciidlist[] = {               /* aka */
 318         INTEL_PCI_IDS,
 319         {0, 0, 0}
 320 };
 321
 322 #if defined(CONFIG_DRM_I915_KMS)
 323 MODULE_DEVICE_TABLE(pci, pciidlist);
 324 #endif
 325
 326 void intel_detect_pch(struct drm_device *dev)
 327 {
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct pci_dev *pch = NULL;
 330
 331         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 332          * (which really amounts to a PCH but no South Display).
 333          */
 334         if (INTEL_INFO(dev)->num_pipes == 0) {
 335                 dev_priv->pch_type = PCH_NOP;
 336                 return;
 337         }
 338
 339         /*
 340          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 341          * make graphics device passthrough work easy for VMM, that only
 342          * need to expose ISA bridge to let driver know the real hardware
 343          * underneath. This is a requirement from virtualization team.
 344          *
 345          * In some virtualized environments (e.g. XEN), there is irrelevant
 346          * ISA bridge in the system. To work reliably, we should scan trhough
 347          * all the ISA bridge devices and check for the first match, instead
 348          * of only checking the first one.
 349          */
 350         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 351                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 352                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 353                         dev_priv->pch_id = id;
 354
 355                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 356                                 dev_priv->pch_type = PCH_IBX;
 357                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 358                                 WARN_ON(!IS_GEN5(dev));
 359                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 360                                 dev_priv->pch_type = PCH_CPT;
 361                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 362                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 363                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 364                                 /* PantherPoint is CPT compatible */
 365                                 dev_priv->pch_type = PCH_CPT;
 366                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 367                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 368                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 369                                 dev_priv->pch_type = PCH_LPT;
 370                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 371                                 WARN_ON(!IS_HASWELL(dev));
 372                                 WARN_ON(IS_ULT(dev));
 373                         } else if (IS_BROADWELL(dev)) {
 374                                 dev_priv->pch_type = PCH_LPT;
 375                                 dev_priv->pch_id =
 376                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 377                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 378                                               "LynxPoint LP PCH\n");
 379                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 380                                 dev_priv->pch_type = PCH_LPT;
 381                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 382                                 WARN_ON(!IS_HASWELL(dev));
 383                                 WARN_ON(!IS_ULT(dev));
 384                         } else
 385                                 continue;
 386
 387                         break;
 388                 }
 389         }
 390         if (!pch)
 391                 DRM_DEBUG_KMS("No PCH found.\n");
 392
 393         pci_dev_put(pch);
 394 }
 395
 396 bool i915_semaphore_is_enabled(struct drm_device *dev)
 397 {
 398         if (INTEL_INFO(dev)->gen < 6)
 399                 return false;
 400
 401         if (i915.semaphores >= 0)
 402                 return i915.semaphores;
 403
 404         /* Until we get further testing... */
 405         if (IS_GEN8(dev))
 406                 return false;
 407
 408 #ifdef CONFIG_INTEL_IOMMU
 409         /* Enable semaphores on SNB when IO remapping is off */
 410         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 411                 return false;
 412 #endif
 413
 414         return true;
 415 }
 416
 417 static int i915_drm_freeze(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420         struct drm_crtc *crtc;
 421
 422         intel_runtime_pm_get(dev_priv);
 423
 424         /* ignore lid events during suspend */
 425         mutex_lock(&dev_priv->modeset_restore_lock);
 426         dev_priv->modeset_restore = MODESET_SUSPENDED;
 427         mutex_unlock(&dev_priv->modeset_restore_lock);
 428
 429         /* We do a lot of poking in a lot of registers, make sure they work
 430          * properly. */
 431         intel_display_set_init_power(dev_priv, true);
 432
 433         drm_kms_helper_poll_disable(dev);
 434
 435         pci_save_state(dev->pdev);
 436
 437         /* If KMS is active, we do the leavevt stuff here */
 438         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 439                 int error;
 440
 441                 error = i915_gem_suspend(dev);
 442                 if (error) {
 443                         dev_err(&dev->pdev->dev,
 444                                 "GEM idle failed, resume might fail\n");
 445                         return error;
 446                 }
 447
 448                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 449
 450                 drm_irq_uninstall(dev);
 451                 dev_priv->enable_hotplug_processing = false;
 452                 /*
 453                  * Disable CRTCs directly since we want to preserve sw state
 454                  * for _thaw.
 455                  */
 456                 mutex_lock(&dev->mode_config.mutex);
 457                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 458                         dev_priv->display.crtc_disable(crtc);
 459                 mutex_unlock(&dev->mode_config.mutex);
 460
 461                 intel_modeset_suspend_hw(dev);
 462         }
 463
 464         i915_gem_suspend_gtt_mappings(dev);
 465
 466         i915_save_state(dev);
 467
 468         intel_opregion_fini(dev);
 469         intel_uncore_fini(dev);
 470
 471         console_lock();
 472         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 473         console_unlock();
 474
 475         dev_priv->suspend_count++;
 476
 477         return 0;
 478 }
 479
 480 int i915_suspend(struct drm_device *dev, pm_message_t state)
 481 {
 482         int error;
 483
 484         if (!dev || !dev->dev_private) {
 485                 DRM_ERROR("dev: %p\n", dev);
 486                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 487                 return -ENODEV;
 488         }
 489
 490         if (state.event == PM_EVENT_PRETHAW)
 491                 return 0;
 492
 493
 494         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 495                 return 0;
 496
 497         error = i915_drm_freeze(dev);
 498         if (error)
 499                 return error;
 500
 501         if (state.event == PM_EVENT_SUSPEND) {
 502                 /* Shut down the device */
 503                 pci_disable_device(dev->pdev);
 504                 pci_set_power_state(dev->pdev, PCI_D3hot);
 505         }
 506
 507         return 0;
 508 }
 509
 510 void intel_console_resume(struct work_struct *work)
 511 {
 512         struct drm_i915_private *dev_priv =
 513                 container_of(work, struct drm_i915_private,
 514                              console_resume_work);
 515         struct drm_device *dev = dev_priv->dev;
 516
 517         console_lock();
 518         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 519         console_unlock();
 520 }
 521
 522 static void intel_resume_hotplug(struct drm_device *dev)
 523 {
 524         struct drm_mode_config *mode_config = &dev->mode_config;
 525         struct intel_encoder *encoder;
 526
 527         mutex_lock(&mode_config->mutex);
 528         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 529
 530         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 531                 if (encoder->hot_plug)
 532                         encoder->hot_plug(encoder);
 533
 534         mutex_unlock(&mode_config->mutex);
 535
 536         /* Just fire off a uevent and let userspace tell us what to do */
 537         drm_helper_hpd_irq_event(dev);
 538 }
 539
 540 static int i915_drm_thaw_early(struct drm_device *dev)
 541 {
 542         struct drm_i915_private *dev_priv = dev->dev_private;
 543
 544         intel_uncore_early_sanitize(dev);
 545         intel_uncore_sanitize(dev);
 546         intel_power_domains_init_hw(dev_priv);
 547
 548         return 0;
 549 }
 550
 551 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 552 {
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         int error = 0;
 555
 556         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 557             restore_gtt_mappings) {
 558                 mutex_lock(&dev->struct_mutex);
 559                 i915_gem_restore_gtt_mappings(dev);
 560                 mutex_unlock(&dev->struct_mutex);
 561         }
 562
 563         i915_restore_state(dev);
 564         intel_opregion_setup(dev);
 565
 566         /* KMS EnterVT equivalent */
 567         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 568                 intel_init_pch_refclk(dev);
 569                 drm_mode_config_reset(dev);
 570
 571                 mutex_lock(&dev->struct_mutex);
 572
 573                 error = i915_gem_init_hw(dev);
 574                 mutex_unlock(&dev->struct_mutex);
 575
 576                 /* We need working interrupts for modeset enabling ... */
 577                 drm_irq_install(dev, dev->pdev->irq);
 578
 579                 intel_modeset_init_hw(dev);
 580
 581                 drm_modeset_lock_all(dev);
 582                 intel_modeset_setup_hw_state(dev, true);
 583                 drm_modeset_unlock_all(dev);
 584
 585                 /*
 586                  * ... but also need to make sure that hotplug processing
 587                  * doesn't cause havoc. Like in the driver load code we don't
 588                  * bother with the tiny race here where we might loose hotplug
 589                  * notifications.
 590                  * */
 591                 intel_hpd_init(dev);
 592                 dev_priv->enable_hotplug_processing = true;
 593                 /* Config may have changed between suspend and resume */
 594                 intel_resume_hotplug(dev);
 595         }
 596
 597         intel_opregion_init(dev);
 598
 599         /*
 600          * The console lock can be pretty contented on resume due
 601          * to all the printk activity.  Try to keep it out of the hot
 602          * path of resume if possible.
 603          */
 604         if (console_trylock()) {
 605                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 606                 console_unlock();
 607         } else {
 608                 schedule_work(&dev_priv->console_resume_work);
 609         }
 610
 611         mutex_lock(&dev_priv->modeset_restore_lock);
 612         dev_priv->modeset_restore = MODESET_DONE;
 613         mutex_unlock(&dev_priv->modeset_restore_lock);
 614
 615         intel_runtime_pm_put(dev_priv);
 616         return error;
 617 }
 618
 619 static int i915_drm_thaw(struct drm_device *dev)
 620 {
 621         if (drm_core_check_feature(dev, DRIVER_MODESET))
 622                 i915_check_and_clear_faults(dev);
 623
 624         return __i915_drm_thaw(dev, true);
 625 }
 626
 627 static int i915_resume_early(struct drm_device *dev)
 628 {
 629         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 630                 return 0;
 631
 632         /*
 633          * We have a resume ordering issue with the snd-hda driver also
 634          * requiring our device to be power up. Due to the lack of a
 635          * parent/child relationship we currently solve this with an early
 636          * resume hook.
 637          *
 638          * FIXME: This should be solved with a special hdmi sink device or
 639          * similar so that power domains can be employed.
 640          */
 641         if (pci_enable_device(dev->pdev))
 642                 return -EIO;
 643
 644         pci_set_master(dev->pdev);
 645
 646         return i915_drm_thaw_early(dev);
 647 }
 648
 649 int i915_resume(struct drm_device *dev)
 650 {
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         int ret;
 653
 654         /*
 655          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 656          * earlier) need to restore the GTT mappings since the BIOS might clear
 657          * all our scratch PTEs.
 658          */
 659         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 660         if (ret)
 661                 return ret;
 662
 663         drm_kms_helper_poll_enable(dev);
 664         return 0;
 665 }
 666
 667 static int i915_resume_legacy(struct drm_device *dev)
 668 {
 669         i915_resume_early(dev);
 670         i915_resume(dev);
 671
 672         return 0;
 673 }
 674
 675 /**
 676  * i915_reset - reset chip after a hang
 677  * @dev: drm device to reset
 678  *
 679  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 680  * reset or otherwise an error code.
 681  *
 682  * Procedure is fairly simple:
 683  *   - reset the chip using the reset reg
 684  *   - re-init context state
 685  *   - re-init hardware status page
 686  *   - re-init ring buffer
 687  *   - re-init interrupt state
 688  *   - re-init display
 689  */
 690 int i915_reset(struct drm_device *dev)
 691 {
 692         struct drm_i915_private *dev_priv = dev->dev_private;
 693         bool simulated;
 694         int ret;
 695
 696         if (!i915.reset)
 697                 return 0;
 698
 699         mutex_lock(&dev->struct_mutex);
 700
 701         i915_gem_reset(dev);
 702
 703         simulated = dev_priv->gpu_error.stop_rings != 0;
 704
 705         ret = intel_gpu_reset(dev);
 706
 707         /* Also reset the gpu hangman. */
 708         if (simulated) {
 709                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 710                 dev_priv->gpu_error.stop_rings = 0;
 711                 if (ret == -ENODEV) {
 712                         DRM_INFO("Reset not implemented, but ignoring "
 713                                  "error for simulated gpu hangs\n");
 714                         ret = 0;
 715                 }
 716         }
 717
 718         if (ret) {
 719                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 720                 mutex_unlock(&dev->struct_mutex);
 721                 return ret;
 722         }
 723
 724         /* Ok, now get things going again... */
 725
 726         /*
 727          * Everything depends on having the GTT running, so we need to start
 728          * there.  Fortunately we don't need to do this unless we reset the
 729          * chip at a PCI level.
 730          *
 731          * Next we need to restore the context, but we don't use those
 732          * yet either...
 733          *
 734          * Ring buffer needs to be re-initialized in the KMS case, or if X
 735          * was running at the time of the reset (i.e. we weren't VT
 736          * switched away).
 737          */
 738         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 739                         !dev_priv->ums.mm_suspended) {
 740                 dev_priv->ums.mm_suspended = 0;
 741
 742                 ret = i915_gem_init_hw(dev);
 743                 mutex_unlock(&dev->struct_mutex);
 744                 if (ret) {
 745                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 746                         return ret;
 747                 }
 748
 749                 /*
 750                  * FIXME: This is horribly race against concurrent pageflip and
 751                  * vblank wait ioctls since they can observe dev->irqs_disabled
 752                  * being false when they shouldn't be able to.
 753                  */
 754                 drm_irq_uninstall(dev);
 755                 drm_irq_install(dev, dev->pdev->irq);
 756
 757                 /* rps/rc6 re-init is necessary to restore state lost after the
 758                  * reset and the re-install of drm irq. Skip for ironlake per
 759                  * previous concerns that it doesn't respond well to some forms
 760                  * of re-init after reset. */
 761                 if (INTEL_INFO(dev)->gen > 5) {
 762                         mutex_lock(&dev->struct_mutex);
 763                         intel_enable_gt_powersave(dev);
 764                         mutex_unlock(&dev->struct_mutex);
 765                 }
 766
 767                 intel_hpd_init(dev);
 768         } else {
 769                 mutex_unlock(&dev->struct_mutex);
 770         }
 771
 772         return 0;
 773 }
 774
 775 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 776 {
 777         struct intel_device_info *intel_info =
 778                 (struct intel_device_info *) ent->driver_data;
 779
 780         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 781                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 782                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 783                 return -ENODEV;
 784         }
 785
 786         /* Only bind to function 0 of the device. Early generations
 787          * used function 1 as a placeholder for multi-head. This causes
 788          * us confusion instead, especially on the systems where both
 789          * functions have the same PCI-ID!
 790          */
 791         if (PCI_FUNC(pdev->devfn))
 792                 return -ENODEV;
 793
 794         driver.driver_features &= ~(DRIVER_USE_AGP);
 795
 796         return drm_get_pci_dev(pdev, ent, &driver);
 797 }
 798
 799 static void
 800 i915_pci_remove(struct pci_dev *pdev)
 801 {
 802         struct drm_device *dev = pci_get_drvdata(pdev);
 803
 804         drm_put_dev(dev);
 805 }
 806
 807 static int i915_pm_suspend(struct device *dev)
 808 {
 809         struct pci_dev *pdev = to_pci_dev(dev);
 810         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 811
 812         if (!drm_dev || !drm_dev->dev_private) {
 813                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 814                 return -ENODEV;
 815         }
 816
 817         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 818                 return 0;
 819
 820         return i915_drm_freeze(drm_dev);
 821 }
 822
 823 static int i915_pm_suspend_late(struct device *dev)
 824 {
 825         struct pci_dev *pdev = to_pci_dev(dev);
 826         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 827
 828         /*
 829          * We have a suspedn ordering issue with the snd-hda driver also
 830          * requiring our device to be power up. Due to the lack of a
 831          * parent/child relationship we currently solve this with an late
 832          * suspend hook.
 833          *
 834          * FIXME: This should be solved with a special hdmi sink device or
 835          * similar so that power domains can be employed.
 836          */
 837         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 838                 return 0;
 839
 840         pci_disable_device(pdev);
 841         pci_set_power_state(pdev, PCI_D3hot);
 842
 843         return 0;
 844 }
 845
 846 static int i915_pm_resume_early(struct device *dev)
 847 {
 848         struct pci_dev *pdev = to_pci_dev(dev);
 849         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 850
 851         return i915_resume_early(drm_dev);
 852 }
 853
 854 static int i915_pm_resume(struct device *dev)
 855 {
 856         struct pci_dev *pdev = to_pci_dev(dev);
 857         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 858
 859         return i915_resume(drm_dev);
 860 }
 861
 862 static int i915_pm_freeze(struct device *dev)
 863 {
 864         struct pci_dev *pdev = to_pci_dev(dev);
 865         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 866
 867         if (!drm_dev || !drm_dev->dev_private) {
 868                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 869                 return -ENODEV;
 870         }
 871
 872         return i915_drm_freeze(drm_dev);
 873 }
 874
 875 static int i915_pm_thaw_early(struct device *dev)
 876 {
 877         struct pci_dev *pdev = to_pci_dev(dev);
 878         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 879
 880         return i915_drm_thaw_early(drm_dev);
 881 }
 882
 883 static int i915_pm_thaw(struct device *dev)
 884 {
 885         struct pci_dev *pdev = to_pci_dev(dev);
 886         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 887
 888         return i915_drm_thaw(drm_dev);
 889 }
 890
 891 static int i915_pm_poweroff(struct device *dev)
 892 {
 893         struct pci_dev *pdev = to_pci_dev(dev);
 894         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 895
 896         return i915_drm_freeze(drm_dev);
 897 }
 898
 899 static void snb_runtime_suspend(struct drm_i915_private *dev_priv)
 900 {
 901         struct drm_device *dev = dev_priv->dev;
 902
 903         intel_runtime_pm_disable_interrupts(dev);
 904 }
 905
 906 static void hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 907 {
 908         hsw_enable_pc8(dev_priv);
 909 }
 910
 911 static void snb_runtime_resume(struct drm_i915_private *dev_priv)
 912 {
 913         struct drm_device *dev = dev_priv->dev;
 914
 915         intel_runtime_pm_restore_interrupts(dev);
 916         intel_init_pch_refclk(dev);
 917         i915_gem_init_swizzling(dev);
 918         mutex_lock(&dev_priv->rps.hw_lock);
 919         gen6_update_ring_freq(dev);
 920         mutex_unlock(&dev_priv->rps.hw_lock);
 921 }
 922
 923 static void hsw_runtime_resume(struct drm_i915_private *dev_priv)
 924 {
 925         hsw_disable_pc8(dev_priv);
 926 }
 927
 928 static int intel_runtime_suspend(struct device *device)
 929 {
 930         struct pci_dev *pdev = to_pci_dev(device);
 931         struct drm_device *dev = pci_get_drvdata(pdev);
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933
 934         WARN_ON(!HAS_RUNTIME_PM(dev));
 935         assert_force_wake_inactive(dev_priv);
 936
 937         DRM_DEBUG_KMS("Suspending device\n");
 938
 939         if (IS_GEN6(dev))
 940                 snb_runtime_suspend(dev_priv);
 941         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 942                 hsw_runtime_suspend(dev_priv);
 943         else
 944                 WARN_ON(1);
 945
 946         i915_gem_release_all_mmaps(dev_priv);
 947
 948         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 949         dev_priv->pm.suspended = true;
 950
 951         /*
 952          * current versions of firmware which depend on this opregion
 953          * notification have repurposed the D1 definition to mean
 954          * "runtime suspended" vs. what you would normally expect (D3)
 955          * to distinguish it from notifications that might be sent
 956          * via the suspend path.
 957          */
 958         intel_opregion_notify_adapter(dev, PCI_D1);
 959
 960         DRM_DEBUG_KMS("Device suspended\n");
 961         return 0;
 962 }
 963
 964 static int intel_runtime_resume(struct device *device)
 965 {
 966         struct pci_dev *pdev = to_pci_dev(device);
 967         struct drm_device *dev = pci_get_drvdata(pdev);
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969
 970         WARN_ON(!HAS_RUNTIME_PM(dev));
 971
 972         DRM_DEBUG_KMS("Resuming device\n");
 973
 974         intel_opregion_notify_adapter(dev, PCI_D0);
 975         dev_priv->pm.suspended = false;
 976
 977         if (IS_GEN6(dev))
 978                 snb_runtime_resume(dev_priv);
 979         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 980                 hsw_runtime_resume(dev_priv);
 981         else
 982                 WARN_ON(1);
 983
 984         DRM_DEBUG_KMS("Device resumed\n");
 985         return 0;
 986 }
 987
 988 static const struct dev_pm_ops i915_pm_ops = {
 989         .suspend = i915_pm_suspend,
 990         .suspend_late = i915_pm_suspend_late,
 991         .resume_early = i915_pm_resume_early,
 992         .resume = i915_pm_resume,
 993         .freeze = i915_pm_freeze,
 994         .thaw_early = i915_pm_thaw_early,
 995         .thaw = i915_pm_thaw,
 996         .poweroff = i915_pm_poweroff,
 997         .restore_early = i915_pm_resume_early,
 998         .restore = i915_pm_resume,
 999         .runtime_suspend = intel_runtime_suspend,
1000         .runtime_resume = intel_runtime_resume,
1001 };
1002
1003 static const struct vm_operations_struct i915_gem_vm_ops = {
1004         .fault = i915_gem_fault,
1005         .open = drm_gem_vm_open,
1006         .close = drm_gem_vm_close,
1007 };
1008
1009 static const struct file_operations i915_driver_fops = {
1010         .owner = THIS_MODULE,
1011         .open = drm_open,
1012         .release = drm_release,
1013         .unlocked_ioctl = drm_ioctl,
1014         .mmap = drm_gem_mmap,
1015         .poll = drm_poll,
1016         .read = drm_read,
1017 #ifdef CONFIG_COMPAT
1018         .compat_ioctl = i915_compat_ioctl,
1019 #endif
1020         .llseek = noop_llseek,
1021 };
1022
1023 static struct drm_driver driver = {
1024         /* Don't use MTRRs here; the Xserver or userspace app should
1025          * deal with them for Intel hardware.
1026          */
1027         .driver_features =
1028             DRIVER_USE_AGP |
1029             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1030             DRIVER_RENDER,
1031         .load = i915_driver_load,
1032         .unload = i915_driver_unload,
1033         .open = i915_driver_open,
1034         .lastclose = i915_driver_lastclose,
1035         .preclose = i915_driver_preclose,
1036         .postclose = i915_driver_postclose,
1037
1038         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1039         .suspend = i915_suspend,
1040         .resume = i915_resume_legacy,
1041
1042         .device_is_agp = i915_driver_device_is_agp,
1043         .master_create = i915_master_create,
1044         .master_destroy = i915_master_destroy,
1045 #if defined(CONFIG_DEBUG_FS)
1046         .debugfs_init = i915_debugfs_init,
1047         .debugfs_cleanup = i915_debugfs_cleanup,
1048 #endif
1049         .gem_free_object = i915_gem_free_object,
1050         .gem_vm_ops = &i915_gem_vm_ops,
1051
1052         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1053         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1054         .gem_prime_export = i915_gem_prime_export,
1055         .gem_prime_import = i915_gem_prime_import,
1056
1057         .dumb_create = i915_gem_dumb_create,
1058         .dumb_map_offset = i915_gem_mmap_gtt,
1059         .dumb_destroy = drm_gem_dumb_destroy,
1060         .ioctls = i915_ioctls,
1061         .fops = &i915_driver_fops,
1062         .name = DRIVER_NAME,
1063         .desc = DRIVER_DESC,
1064         .date = DRIVER_DATE,
1065         .major = DRIVER_MAJOR,
1066         .minor = DRIVER_MINOR,
1067         .patchlevel = DRIVER_PATCHLEVEL,
1068 };
1069
1070 static struct pci_driver i915_pci_driver = {
1071         .name = DRIVER_NAME,
1072         .id_table = pciidlist,
1073         .probe = i915_pci_probe,
1074         .remove = i915_pci_remove,
1075         .driver.pm = &i915_pm_ops,
1076 };
1077
1078 static int __init i915_init(void)
1079 {
1080         driver.num_ioctls = i915_max_ioctl;
1081
1082         /*
1083          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1084          * explicitly disabled with the module pararmeter.
1085          *
1086          * Otherwise, just follow the parameter (defaulting to off).
1087          *
1088          * Allow optional vga_text_mode_force boot option to override
1089          * the default behavior.
1090          */
1091 #if defined(CONFIG_DRM_I915_KMS)
1092         if (i915.modeset != 0)
1093                 driver.driver_features |= DRIVER_MODESET;
1094 #endif
1095         if (i915.modeset == 1)
1096                 driver.driver_features |= DRIVER_MODESET;
1097
1098 #ifdef CONFIG_VGA_CONSOLE
1099         if (vgacon_text_force() && i915.modeset == -1)
1100                 driver.driver_features &= ~DRIVER_MODESET;
1101 #endif
1102
1103         if (!(driver.driver_features & DRIVER_MODESET)) {
1104                 driver.get_vblank_timestamp = NULL;
1105 #ifndef CONFIG_DRM_I915_UMS
1106                 /* Silently fail loading to not upset userspace. */
1107                 return 0;
1108 #endif
1109         }
1110
1111         return drm_pci_init(&driver, &i915_pci_driver);
1112 }
1113
1114 static void __exit i915_exit(void)
1115 {
1116 #ifndef CONFIG_DRM_I915_UMS
1117         if (!(driver.driver_features & DRIVER_MODESET))
1118                 return; /* Never loaded a driver. */
1119 #endif
1120
1121         drm_pci_exit(&driver, &i915_pci_driver);
1122 }
1123
1124 module_init(i915_init);
1125 module_exit(i915_exit);
1126
1127 MODULE_AUTHOR(DRIVER_AUTHOR);
1128 MODULE_DESCRIPTION(DRIVER_DESC);
1129 MODULE_LICENSE("GPL and additional rights");