1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
56 #define pipe_name(p) ((p) + 'A')
63 #define plane_name(p) ((p) + 'A')
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
83 #define WATCH_COHERENCY 0
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91 struct drm_i915_gem_phys_object
{
93 struct page
**page_list
;
94 drm_dma_handle_t
*handle
;
95 struct drm_i915_gem_object
*cur_obj
;
99 struct mem_block
*next
;
100 struct mem_block
*prev
;
103 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header
;
107 struct opregion_acpi
;
108 struct opregion_swsci
;
109 struct opregion_asle
;
110 struct drm_i915_private
;
112 struct intel_opregion
{
113 struct opregion_header
*header
;
114 struct opregion_acpi
*acpi
;
115 struct opregion_swsci
*swsci
;
116 struct opregion_asle
*asle
;
118 u32 __iomem
*lid_state
;
120 #define OPREGION_SIZE (8*1024)
122 struct intel_overlay
;
123 struct intel_overlay_error_state
;
125 struct drm_i915_master_private
{
126 drm_local_map_t
*sarea
;
127 struct _drm_i915_sarea
*sarea_priv
;
129 #define I915_FENCE_REG_NONE -1
130 #define I915_MAX_NUM_FENCES 16
131 /* 16 fences + sign bit for FENCE_REG_NONE */
132 #define I915_MAX_NUM_FENCE_BITS 5
134 struct drm_i915_fence_reg
{
135 struct list_head lru_list
;
136 struct drm_i915_gem_object
*obj
;
137 uint32_t setup_seqno
;
141 struct sdvo_device_mapping
{
150 struct intel_display_error_state
;
152 struct drm_i915_error_state
{
155 u32 pipestat
[I915_MAX_PIPES
];
156 u32 tail
[I915_NUM_RINGS
];
157 u32 head
[I915_NUM_RINGS
];
158 u32 ipeir
[I915_NUM_RINGS
];
159 u32 ipehr
[I915_NUM_RINGS
];
160 u32 instdone
[I915_NUM_RINGS
];
161 u32 acthd
[I915_NUM_RINGS
];
162 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
163 /* our own tracking of ring head and tail */
164 u32 cpu_ring_head
[I915_NUM_RINGS
];
165 u32 cpu_ring_tail
[I915_NUM_RINGS
];
166 u32 error
; /* gen6+ */
167 u32 instpm
[I915_NUM_RINGS
];
168 u32 instps
[I915_NUM_RINGS
];
170 u32 seqno
[I915_NUM_RINGS
];
172 u32 fault_reg
[I915_NUM_RINGS
];
174 u32 faddr
[I915_NUM_RINGS
];
175 u64 fence
[I915_MAX_NUM_FENCES
];
177 struct drm_i915_error_object
{
181 } *ringbuffer
[I915_NUM_RINGS
], *batchbuffer
[I915_NUM_RINGS
];
182 struct drm_i915_error_buffer
{
189 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
196 } *active_bo
, *pinned_bo
;
197 u32 active_bo_count
, pinned_bo_count
;
198 struct intel_overlay_error_state
*overlay
;
199 struct intel_display_error_state
*display
;
202 struct drm_i915_display_funcs
{
203 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
204 bool (*fbc_enabled
)(struct drm_device
*dev
);
205 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
206 void (*disable_fbc
)(struct drm_device
*dev
);
207 int (*get_display_clock_speed
)(struct drm_device
*dev
);
208 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
209 void (*update_wm
)(struct drm_device
*dev
);
210 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
211 uint32_t sprite_width
, int pixel_size
);
212 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
213 struct drm_display_mode
*mode
,
214 struct drm_display_mode
*adjusted_mode
,
216 struct drm_framebuffer
*old_fb
);
217 void (*write_eld
)(struct drm_connector
*connector
,
218 struct drm_crtc
*crtc
);
219 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
220 void (*init_clock_gating
)(struct drm_device
*dev
);
221 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
222 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
223 struct drm_framebuffer
*fb
,
224 struct drm_i915_gem_object
*obj
);
225 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
227 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
228 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
229 /* clock updates for mode set */
231 /* render clock increase/decrease */
232 /* display clock increase/decrease */
233 /* pll clock increase/decrease */
236 struct intel_device_info
{
252 u8 cursor_needs_physical
:1;
254 u8 overlay_needs_physical
:1;
261 #define I915_PPGTT_PD_ENTRIES 512
262 #define I915_PPGTT_PT_ENTRIES 1024
263 struct i915_hw_ppgtt
{
264 unsigned num_pd_entries
;
265 struct page
**pt_pages
;
267 dma_addr_t
*pt_dma_addr
;
268 dma_addr_t scratch_page_dma_addr
;
272 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
273 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
274 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
275 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
276 FBC_BAD_PLANE
, /* fbc not supported on plane */
277 FBC_NOT_TILED
, /* buffer not tiled */
278 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
283 PCH_IBX
, /* Ibexpeak PCH */
284 PCH_CPT
, /* Cougarpoint PCH */
287 #define QUIRK_PIPEA_FORCE (1<<0)
288 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
291 struct intel_fbc_work
;
293 typedef struct drm_i915_private
{
294 struct drm_device
*dev
;
296 const struct intel_device_info
*info
;
299 int relative_constants_mode
;
302 /** gt_fifo_count and the subsequent register write are synchronized
303 * with dev->struct_mutex. */
304 unsigned gt_fifo_count
;
305 /** forcewake_count is protected by gt_lock */
306 unsigned forcewake_count
;
307 /** gt_lock is also taken in irq contexts. */
308 struct spinlock gt_lock
;
311 struct i2c_adapter adapter
;
312 struct i2c_adapter
*force_bit
;
316 struct pci_dev
*bridge_dev
;
317 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
320 drm_dma_handle_t
*status_page_dmah
;
322 drm_local_map_t hws_map
;
323 struct drm_i915_gem_object
*pwrctx
;
324 struct drm_i915_gem_object
*renderctx
;
326 struct resource mch_res
;
334 atomic_t irq_received
;
336 /* protects the irq masks */
338 /** Cached value of IMR to avoid reads in updating the bitfield */
344 u32 hotplug_supported_mask
;
345 struct work_struct hotplug_work
;
347 int tex_lru_log_granularity
;
348 int allow_batchbuffer
;
349 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
353 /* For hangcheck timer */
354 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
355 struct timer_list hangcheck_timer
;
358 uint32_t last_acthd_bsd
;
359 uint32_t last_acthd_blt
;
360 uint32_t last_instdone
;
361 uint32_t last_instdone1
;
363 unsigned long cfb_size
;
365 enum plane cfb_plane
;
367 struct intel_fbc_work
*fbc_work
;
369 struct intel_opregion opregion
;
372 struct intel_overlay
*overlay
;
373 bool sprite_scaling_enabled
;
376 int backlight_level
; /* restore backlight to this value */
377 bool backlight_enabled
;
378 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
379 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
381 /* Feature bits from the VBIOS */
382 unsigned int int_tv_support
:1;
383 unsigned int lvds_dither
:1;
384 unsigned int lvds_vbt
:1;
385 unsigned int int_crt_support
:1;
386 unsigned int lvds_use_ssc
:1;
387 unsigned int display_clock_mode
:1;
398 struct edp_power_seq pps
;
400 bool no_aux_handshake
;
402 struct notifier_block lid_notifier
;
405 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
406 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
407 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
409 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
411 spinlock_t error_lock
;
412 struct drm_i915_error_state
*first_error
;
413 struct work_struct error_work
;
414 struct completion error_completion
;
415 struct workqueue_struct
*wq
;
417 /* Display functions */
418 struct drm_i915_display_funcs display
;
420 /* PCH chipset type */
421 enum intel_pch pch_type
;
423 unsigned long quirks
;
448 u32 saveTRANS_HTOTAL_A
;
449 u32 saveTRANS_HBLANK_A
;
450 u32 saveTRANS_HSYNC_A
;
451 u32 saveTRANS_VTOTAL_A
;
452 u32 saveTRANS_VBLANK_A
;
453 u32 saveTRANS_VSYNC_A
;
461 u32 savePFIT_PGM_RATIOS
;
462 u32 saveBLC_HIST_CTL
;
464 u32 saveBLC_PWM_CTL2
;
465 u32 saveBLC_CPU_PWM_CTL
;
466 u32 saveBLC_CPU_PWM_CTL2
;
479 u32 saveTRANS_HTOTAL_B
;
480 u32 saveTRANS_HBLANK_B
;
481 u32 saveTRANS_HSYNC_B
;
482 u32 saveTRANS_VTOTAL_B
;
483 u32 saveTRANS_VBLANK_B
;
484 u32 saveTRANS_VSYNC_B
;
498 u32 savePP_ON_DELAYS
;
499 u32 savePP_OFF_DELAYS
;
507 u32 savePFIT_CONTROL
;
508 u32 save_palette_a
[256];
509 u32 save_palette_b
[256];
510 u32 saveDPFC_CB_BASE
;
511 u32 saveFBC_CFB_BASE
;
514 u32 saveFBC_CONTROL2
;
524 u32 saveCACHE_MODE_0
;
525 u32 saveMI_ARB_STATE
;
536 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
547 u32 savePIPEA_GMCH_DATA_M
;
548 u32 savePIPEB_GMCH_DATA_M
;
549 u32 savePIPEA_GMCH_DATA_N
;
550 u32 savePIPEB_GMCH_DATA_N
;
551 u32 savePIPEA_DP_LINK_M
;
552 u32 savePIPEB_DP_LINK_M
;
553 u32 savePIPEA_DP_LINK_N
;
554 u32 savePIPEB_DP_LINK_N
;
565 u32 savePCH_DREF_CONTROL
;
566 u32 saveDISP_ARB_CTL
;
567 u32 savePIPEA_DATA_M1
;
568 u32 savePIPEA_DATA_N1
;
569 u32 savePIPEA_LINK_M1
;
570 u32 savePIPEA_LINK_N1
;
571 u32 savePIPEB_DATA_M1
;
572 u32 savePIPEB_DATA_N1
;
573 u32 savePIPEB_LINK_M1
;
574 u32 savePIPEB_LINK_N1
;
575 u32 saveMCHBAR_RENDER_STANDBY
;
576 u32 savePCH_PORT_HOTPLUG
;
579 /** Bridge to intel-gtt-ko */
580 const struct intel_gtt
*gtt
;
581 /** Memory allocator for GTT stolen memory */
582 struct drm_mm stolen
;
583 /** Memory allocator for GTT */
584 struct drm_mm gtt_space
;
585 /** List of all objects in gtt_space. Used to restore gtt
586 * mappings on resume */
587 struct list_head gtt_list
;
589 /** Usable portion of the GTT for GEM */
590 unsigned long gtt_start
;
591 unsigned long gtt_mappable_end
;
592 unsigned long gtt_end
;
594 struct io_mapping
*gtt_mapping
;
597 /** PPGTT used for aliasing the PPGTT with the GTT */
598 struct i915_hw_ppgtt
*aliasing_ppgtt
;
600 struct shrinker inactive_shrinker
;
603 * List of objects currently involved in rendering.
605 * Includes buffers having the contents of their GPU caches
606 * flushed, not necessarily primitives. last_rendering_seqno
607 * represents when the rendering involved will be completed.
609 * A reference is held on the buffer while on this list.
611 struct list_head active_list
;
614 * List of objects which are not in the ringbuffer but which
615 * still have a write_domain which needs to be flushed before
618 * last_rendering_seqno is 0 while an object is in this list.
620 * A reference is held on the buffer while on this list.
622 struct list_head flushing_list
;
625 * LRU list of objects which are not in the ringbuffer and
626 * are ready to unbind, but are still in the GTT.
628 * last_rendering_seqno is 0 while an object is in this list.
630 * A reference is not held on the buffer while on this list,
631 * as merely being GTT-bound shouldn't prevent its being
632 * freed, and we'll pull it off the list in the free path.
634 struct list_head inactive_list
;
637 * LRU list of objects which are not in the ringbuffer but
638 * are still pinned in the GTT.
640 struct list_head pinned_list
;
642 /** LRU list of objects with fence regs on them. */
643 struct list_head fence_list
;
646 * List of objects currently pending being freed.
648 * These objects are no longer in use, but due to a signal
649 * we were prevented from freeing them at the appointed time.
651 struct list_head deferred_free_list
;
654 * We leave the user IRQ off as much as possible,
655 * but this means that requests will finish and never
656 * be retired once the system goes idle. Set a timer to
657 * fire periodically while the ring is running. When it
658 * fires, go retire requests.
660 struct delayed_work retire_work
;
663 * Are we in a non-interruptible section of code like
669 * Flag if the X Server, and thus DRM, is not currently in
670 * control of the device.
672 * This is set between LeaveVT and EnterVT. It needs to be
673 * replaced with a semaphore. It also needs to be
674 * transitioned away from for kernel modesetting.
679 * Flag if the hardware appears to be wedged.
681 * This is set when attempts to idle the device timeout.
682 * It prevents command submission from occurring and makes
683 * every pending request fail
687 /** Bit 6 swizzling required for X tiling */
688 uint32_t bit_6_swizzle_x
;
689 /** Bit 6 swizzling required for Y tiling */
690 uint32_t bit_6_swizzle_y
;
692 /* storage for physical objects */
693 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
695 /* accounting, useful for userland debugging */
697 size_t mappable_gtt_total
;
698 size_t object_memory
;
701 struct sdvo_device_mapping sdvo_mappings
[2];
702 /* indicate whether the LVDS_BORDER should be enabled or not */
703 unsigned int lvds_border_bits
;
704 /* Panel fitter placement and size for Ironlake+ */
705 u32 pch_pf_pos
, pch_pf_size
;
707 struct drm_crtc
*plane_to_crtc_mapping
[3];
708 struct drm_crtc
*pipe_to_crtc_mapping
[3];
709 wait_queue_head_t pending_flip_queue
;
710 bool flip_pending_is_done
;
712 /* Reclocking support */
713 bool render_reclock_avail
;
714 bool lvds_downclock_avail
;
715 /* indicates the reduced downclock for LVDS*/
717 struct work_struct idle_work
;
718 struct timer_list idle_timer
;
722 struct child_device_config
*child_dev
;
723 struct drm_connector
*int_lvds_connector
;
724 struct drm_connector
*int_edp_connector
;
726 bool mchbar_need_disable
;
728 struct work_struct rps_work
;
739 unsigned long last_time1
;
740 unsigned long chipset_power
;
742 struct timespec last_time2
;
743 unsigned long gfx_power
;
747 spinlock_t
*mchdev_lock
;
749 enum no_fbc_reason no_fbc_reason
;
751 struct drm_mm_node
*compressed_fb
;
752 struct drm_mm_node
*compressed_llb
;
754 unsigned long last_gpu_reset
;
756 /* list of fbdev register on this device */
757 struct intel_fbdev
*fbdev
;
759 struct backlight_device
*backlight
;
761 struct drm_property
*broadcast_rgb_property
;
762 struct drm_property
*force_audio_property
;
763 } drm_i915_private_t
;
765 enum i915_cache_level
{
768 I915_CACHE_LLC_MLC
, /* gen6+ */
771 struct drm_i915_gem_object
{
772 struct drm_gem_object base
;
774 /** Current space allocated to this object in the GTT, if any. */
775 struct drm_mm_node
*gtt_space
;
776 struct list_head gtt_list
;
778 /** This object's place on the active/flushing/inactive lists */
779 struct list_head ring_list
;
780 struct list_head mm_list
;
781 /** This object's place on GPU write list */
782 struct list_head gpu_write_list
;
783 /** This object's place in the batchbuffer or on the eviction list */
784 struct list_head exec_list
;
787 * This is set if the object is on the active or flushing lists
788 * (has pending rendering), and is not set if it's on inactive (ready
791 unsigned int active
:1;
794 * This is set if the object has been written to since last bound
797 unsigned int dirty
:1;
800 * This is set if the object has been written to since the last
803 unsigned int pending_gpu_write
:1;
806 * Fence register bits (if any) for this object. Will be set
807 * as needed when mapped into the GTT.
808 * Protected by dev->struct_mutex.
810 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
813 * Advice: are the backing pages purgeable?
818 * Current tiling mode for the object.
820 unsigned int tiling_mode
:2;
821 unsigned int tiling_changed
:1;
823 /** How many users have pinned this object in GTT space. The following
824 * users can each hold at most one reference: pwrite/pread, pin_ioctl
825 * (via user_pin_count), execbuffer (objects are not allowed multiple
826 * times for the same batchbuffer), and the framebuffer code. When
827 * switching/pageflipping, the framebuffer code has at most two buffers
830 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
831 * bits with absolutely no headroom. So use 4 bits. */
832 unsigned int pin_count
:4;
833 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
836 * Is the object at the current location in the gtt mappable and
837 * fenceable? Used to avoid costly recalculations.
839 unsigned int map_and_fenceable
:1;
842 * Whether the current gtt mapping needs to be mappable (and isn't just
843 * mappable by accident). Track pin and fault separate for a more
844 * accurate mappable working set.
846 unsigned int fault_mappable
:1;
847 unsigned int pin_mappable
:1;
850 * Is the GPU currently using a fence to access this buffer,
852 unsigned int pending_fenced_gpu_access
:1;
853 unsigned int fenced_gpu_access
:1;
855 unsigned int cache_level
:2;
857 unsigned int has_aliasing_ppgtt_mapping
:1;
864 struct scatterlist
*sg_list
;
868 * Used for performing relocations during execbuffer insertion.
870 struct hlist_node exec_node
;
871 unsigned long exec_handle
;
872 struct drm_i915_gem_exec_object2
*exec_entry
;
875 * Current offset of the object in GTT space.
877 * This is the same as gtt_space->start
881 /** Breadcrumb of last rendering to the buffer. */
882 uint32_t last_rendering_seqno
;
883 struct intel_ring_buffer
*ring
;
885 /** Breadcrumb of last fenced GPU access to the buffer. */
886 uint32_t last_fenced_seqno
;
887 struct intel_ring_buffer
*last_fenced_ring
;
889 /** Current tiling stride for the object, if it's tiled. */
892 /** Record of address bit 17 of each page at last unbind. */
893 unsigned long *bit_17
;
897 * If present, while GEM_DOMAIN_CPU is in the read domain this array
898 * flags which individual pages are valid.
900 uint8_t *page_cpu_valid
;
902 /** User space pin count and filp owning the pin */
903 uint32_t user_pin_count
;
904 struct drm_file
*pin_filp
;
906 /** for phy allocated objects */
907 struct drm_i915_gem_phys_object
*phys_obj
;
910 * Number of crtcs where this object is currently the fb, but
911 * will be page flipped away on the next vblank. When it
912 * reaches 0, dev_priv->pending_flip_queue will be woken up.
914 atomic_t pending_flip
;
917 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
920 * Request queue structure.
922 * The request queue allows us to note sequence numbers that have been emitted
923 * and may be associated with active buffers to be retired.
925 * By keeping this list, we can avoid having to do questionable
926 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
927 * an emission time with seqnos for tracking how far ahead of the GPU we are.
929 struct drm_i915_gem_request
{
930 /** On Which ring this request was generated */
931 struct intel_ring_buffer
*ring
;
933 /** GEM sequence number associated with this request. */
936 /** Time at which this request was emitted, in jiffies. */
937 unsigned long emitted_jiffies
;
939 /** global list entry for this request */
940 struct list_head list
;
942 struct drm_i915_file_private
*file_priv
;
943 /** file_priv list entry for this request */
944 struct list_head client_list
;
947 struct drm_i915_file_private
{
949 struct spinlock lock
;
950 struct list_head request_list
;
954 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
956 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
957 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
958 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
959 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
960 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
961 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
962 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
963 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
964 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
965 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
966 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
967 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
968 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
969 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
970 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
971 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
972 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
973 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
974 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
975 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
978 * The genX designation typically refers to the render engine, so render
979 * capability related checks should use IS_GEN, while display and other checks
980 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
983 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
984 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
985 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
986 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
987 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
988 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
990 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
991 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
992 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
993 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
995 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
997 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
998 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1000 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1001 * rows, which changed the alignment requirements and fence programming.
1003 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1005 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1006 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1007 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1008 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1009 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1010 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1011 /* dsparb controlled by hw only */
1012 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1014 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1015 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1016 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1018 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1019 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1021 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1022 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1023 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1025 #include "i915_trace.h"
1027 extern struct drm_ioctl_desc i915_ioctls
[];
1028 extern int i915_max_ioctl
;
1029 extern unsigned int i915_fbpercrtc __always_unused
;
1030 extern int i915_panel_ignore_lid __read_mostly
;
1031 extern unsigned int i915_powersave __read_mostly
;
1032 extern int i915_semaphores __read_mostly
;
1033 extern unsigned int i915_lvds_downclock __read_mostly
;
1034 extern int i915_panel_use_ssc __read_mostly
;
1035 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1036 extern int i915_enable_rc6 __read_mostly
;
1037 extern int i915_enable_fbc __read_mostly
;
1038 extern bool i915_enable_hangcheck __read_mostly
;
1039 extern bool i915_enable_ppgtt __read_mostly
;
1041 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1042 extern int i915_resume(struct drm_device
*dev
);
1043 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1044 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1047 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1048 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1049 extern int i915_driver_unload(struct drm_device
*);
1050 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1051 extern void i915_driver_lastclose(struct drm_device
* dev
);
1052 extern void i915_driver_preclose(struct drm_device
*dev
,
1053 struct drm_file
*file_priv
);
1054 extern void i915_driver_postclose(struct drm_device
*dev
,
1055 struct drm_file
*file_priv
);
1056 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1057 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1059 extern int i915_emit_box(struct drm_device
*dev
,
1060 struct drm_clip_rect
*box
,
1062 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
1063 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1064 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1065 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1066 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1070 void i915_hangcheck_elapsed(unsigned long data
);
1071 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1072 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
1073 struct drm_file
*file_priv
);
1074 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
1075 struct drm_file
*file_priv
);
1077 extern void intel_irq_init(struct drm_device
*dev
);
1079 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1080 struct drm_file
*file_priv
);
1081 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1082 struct drm_file
*file_priv
);
1083 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1084 struct drm_file
*file_priv
);
1087 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1090 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1092 void intel_enable_asle(struct drm_device
*dev
);
1094 #ifdef CONFIG_DEBUG_FS
1095 extern void i915_destroy_error_state(struct drm_device
*dev
);
1097 #define i915_destroy_error_state(x)
1102 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1103 struct drm_file
*file_priv
);
1104 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1105 struct drm_file
*file_priv
);
1106 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1107 struct drm_file
*file_priv
);
1108 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1109 struct drm_file
*file_priv
);
1110 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1111 struct drm_file
*file_priv
);
1112 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1113 struct drm_file
*file_priv
);
1114 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1115 struct drm_file
*file_priv
);
1116 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1117 struct drm_file
*file_priv
);
1118 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1119 struct drm_file
*file_priv
);
1120 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1121 struct drm_file
*file_priv
);
1122 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1123 struct drm_file
*file_priv
);
1124 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1125 struct drm_file
*file_priv
);
1126 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1127 struct drm_file
*file_priv
);
1128 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1129 struct drm_file
*file_priv
);
1130 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1131 struct drm_file
*file_priv
);
1132 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1133 struct drm_file
*file_priv
);
1134 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1135 struct drm_file
*file_priv
);
1136 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1137 struct drm_file
*file_priv
);
1138 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1139 struct drm_file
*file_priv
);
1140 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1141 struct drm_file
*file_priv
);
1142 void i915_gem_load(struct drm_device
*dev
);
1143 int i915_gem_init_object(struct drm_gem_object
*obj
);
1144 int __must_check
i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
1145 uint32_t invalidate_domains
,
1146 uint32_t flush_domains
);
1147 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1149 void i915_gem_free_object(struct drm_gem_object
*obj
);
1150 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1152 bool map_and_fenceable
);
1153 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1154 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1155 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1156 void i915_gem_lastclose(struct drm_device
*dev
);
1158 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1159 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
);
1160 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1161 struct intel_ring_buffer
*ring
,
1164 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1165 struct drm_device
*dev
,
1166 struct drm_mode_create_dumb
*args
);
1167 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1168 uint32_t handle
, uint64_t *offset
);
1169 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1172 * Returns true if seq1 is later than seq2.
1175 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1177 return (int32_t)(seq1
- seq2
) >= 0;
1180 u32
i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
);
1182 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
1183 struct intel_ring_buffer
*pipelined
);
1184 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1187 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1189 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1190 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1191 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1196 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1198 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1199 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1200 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1204 void i915_gem_retire_requests(struct drm_device
*dev
);
1205 void i915_gem_reset(struct drm_device
*dev
);
1206 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1207 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1208 uint32_t read_domains
,
1209 uint32_t write_domain
);
1210 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1211 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1212 void i915_gem_init_swizzling(struct drm_device
*dev
);
1213 void i915_gem_init_ppgtt(struct drm_device
*dev
);
1214 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1215 void i915_gem_do_init(struct drm_device
*dev
,
1216 unsigned long start
,
1217 unsigned long mappable_end
,
1219 int __must_check
i915_gpu_idle(struct drm_device
*dev
, bool do_retire
);
1220 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1221 int __must_check
i915_add_request(struct intel_ring_buffer
*ring
,
1222 struct drm_file
*file
,
1223 struct drm_i915_gem_request
*request
);
1224 int __must_check
i915_wait_request(struct intel_ring_buffer
*ring
,
1227 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1229 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1232 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1234 struct intel_ring_buffer
*pipelined
);
1235 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1236 struct drm_i915_gem_object
*obj
,
1239 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1240 struct drm_i915_gem_object
*obj
);
1241 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1242 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1245 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1249 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1250 enum i915_cache_level cache_level
);
1252 /* i915_gem_gtt.c */
1253 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1254 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1255 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1256 struct drm_i915_gem_object
*obj
,
1257 enum i915_cache_level cache_level
);
1258 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1259 struct drm_i915_gem_object
*obj
);
1261 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1262 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1263 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object
*obj
,
1264 enum i915_cache_level cache_level
);
1265 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1267 /* i915_gem_evict.c */
1268 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1269 unsigned alignment
, bool mappable
);
1270 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1271 bool purgeable_only
);
1272 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1273 bool purgeable_only
);
1275 /* i915_gem_tiling.c */
1276 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1277 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1278 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1280 /* i915_gem_debug.c */
1281 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1282 const char *where
, uint32_t mark
);
1284 int i915_verify_lists(struct drm_device
*dev
);
1286 #define i915_verify_lists(dev) 0
1288 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1290 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1291 const char *where
, uint32_t mark
);
1293 /* i915_debugfs.c */
1294 int i915_debugfs_init(struct drm_minor
*minor
);
1295 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1297 /* i915_suspend.c */
1298 extern int i915_save_state(struct drm_device
*dev
);
1299 extern int i915_restore_state(struct drm_device
*dev
);
1301 /* i915_suspend.c */
1302 extern int i915_save_state(struct drm_device
*dev
);
1303 extern int i915_restore_state(struct drm_device
*dev
);
1306 extern int intel_setup_gmbus(struct drm_device
*dev
);
1307 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1308 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1309 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1310 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1312 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1314 extern void intel_i2c_reset(struct drm_device
*dev
);
1316 /* intel_opregion.c */
1317 extern int intel_opregion_setup(struct drm_device
*dev
);
1319 extern void intel_opregion_init(struct drm_device
*dev
);
1320 extern void intel_opregion_fini(struct drm_device
*dev
);
1321 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1322 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1323 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1325 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1326 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1327 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1328 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1329 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1334 extern void intel_register_dsm_handler(void);
1335 extern void intel_unregister_dsm_handler(void);
1337 static inline void intel_register_dsm_handler(void) { return; }
1338 static inline void intel_unregister_dsm_handler(void) { return; }
1339 #endif /* CONFIG_ACPI */
1342 extern void intel_modeset_init(struct drm_device
*dev
);
1343 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1344 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1345 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1346 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1347 extern void intel_disable_fbc(struct drm_device
*dev
);
1348 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1349 extern void ironlake_init_pch_refclk(struct drm_device
*dev
);
1350 extern void ironlake_enable_rc6(struct drm_device
*dev
);
1351 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1352 extern void intel_detect_pch(struct drm_device
*dev
);
1353 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1355 extern void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1356 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
);
1357 extern void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1358 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
);
1361 #ifdef CONFIG_DEBUG_FS
1362 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1363 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1365 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1366 extern void intel_display_print_error_state(struct seq_file
*m
,
1367 struct drm_device
*dev
,
1368 struct intel_display_error_state
*error
);
1371 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1373 #define BEGIN_LP_RING(n) \
1374 intel_ring_begin(LP_RING(dev_priv), (n))
1376 #define OUT_RING(x) \
1377 intel_ring_emit(LP_RING(dev_priv), x)
1379 #define ADVANCE_LP_RING() \
1380 intel_ring_advance(LP_RING(dev_priv))
1383 * Lock test for when it's just for synchronization of ring access.
1385 * In that case, we don't need to do it when GEM is initialized as nobody else
1386 * has access to the ring.
1388 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1389 if (LP_RING(dev->dev_private)->obj == NULL) \
1390 LOCK_TEST_WITH_RETURN(dev, file); \
1393 /* On SNB platform, before reading ring registers forcewake bit
1394 * must be set to prevent GT core from power down and stale values being
1397 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1398 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1399 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1401 /* We give fast paths for the really cool registers */
1402 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1403 (((dev_priv)->info->gen >= 6) && \
1404 ((reg) < 0x40000) && \
1405 ((reg) != FORCEWAKE))
1407 #define __i915_read(x, y) \
1408 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1416 #define __i915_write(x, y) \
1417 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1425 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1426 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1428 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1429 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1430 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1431 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1433 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1434 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1435 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1436 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1438 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1439 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1441 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1442 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)