drivers/gpu/drm/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <linux/string.h>
  29 #include <linux/bitops.h>
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33
  34 /** @file i915_gem_tiling.c
  35  *
  36  * Support for managing tiling state of buffer objects.
  37  *
  38  * The idea behind tiling is to increase cache hit rates by rearranging
  39  * pixel data so that a group of pixel accesses are in the same cacheline.
  40  * Performance improvement from doing this on the back/depth buffer are on
  41  * the order of 30%.
  42  *
  43  * Intel architectures make this somewhat more complicated, though, by
  44  * adjustments made to addressing of data when the memory is in interleaved
  45  * mode (matched pairs of DIMMS) to improve memory bandwidth.
  46  * For interleaved memory, the CPU sends every sequential 64 bytes
  47  * to an alternate memory channel so it can get the bandwidth from both.
  48  *
  49  * The GPU also rearranges its accesses for increased bandwidth to interleaved
  50  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
  51  * it does it a little differently, since one walks addresses not just in the
  52  * X direction but also Y.  So, along with alternating channels when bit
  53  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
  54  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
  55  * are common to both the 915 and 965-class hardware.
  56  *
  57  * The CPU also sometimes XORs in higher bits as well, to improve
  58  * bandwidth doing strided access like we do so frequently in graphics.  This
  59  * is called "Channel XOR Randomization" in the MCH documentation.  The result
  60  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
  61  * decode.
  62  *
  63  * All of this bit 6 XORing has an effect on our memory management,
  64  * as we need to make sure that the 3d driver can correctly address object
  65  * contents.
  66  *
  67  * If we don't have interleaved memory, all tiling is safe and no swizzling is
  68  * required.
  69  *
  70  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
  71  * 17 is not just a page offset, so as we page an objet out and back in,
  72  * individual pages in it will have different bit 17 addresses, resulting in
  73  * each 64 bytes being swapped with its neighbor!
  74  *
  75  * Otherwise, if interleaved, we have to tell the 3d driver what the address
  76  * swizzling it needs to do is, since it's writing with the CPU to the pages
  77  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
  78  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
  79  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
  80  * to match what the GPU expects.
  81  */
  82
  83 /**
  84  * Detects bit 6 swizzling of address lookup between IGD access and CPU
  85  * access through main memory.
  86  */
  87 void
  88 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
  92         uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
  93
  94         if (INTEL_INFO(dev)->gen >= 6) {
  95                 uint32_t dimm_c0, dimm_c1;
  96                 dimm_c0 = I915_READ(MAD_DIMM_C0);
  97                 dimm_c1 = I915_READ(MAD_DIMM_C1);
  98                 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
  99                 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 100                 /* Enable swizzling when the channels are populated with
 101                  * identically sized dimms. We don't need to check the 3rd
 102                  * channel because no cpu with gpu attached ships in that
 103                  * configuration. Also, swizzling only makes sense for 2
 104                  * channels anyway. */
 105                 if (dimm_c0 == dimm_c1) {
 106                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 107                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 108                 } else {
 109                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 110                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 111                 }
 112         } else if (IS_GEN5(dev)) {
 113                 /* On Ironlake whatever DRAM config, GPU always do
 114                  * same swizzling setup.
 115                  */
 116                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 117                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 118         } else if (IS_GEN2(dev)) {
 119                 /* As far as we know, the 865 doesn't have these bit 6
 120                  * swizzling issues.
 121                  */
 122                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 123                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 124         } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
 125                 uint32_t dcc;
 126
 127                 /* On 9xx chipsets, channel interleave by the CPU is
 128                  * determined by DCC.  For single-channel, neither the CPU
 129                  * nor the GPU do swizzling.  For dual channel interleaved,
 130                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 131                  * 9 for Y tiled.  The CPU's interleave is independent, and
 132                  * can be based on either bit 11 (haven't seen this yet) or
 133                  * bit 17 (common).
 134                  */
 135                 dcc = I915_READ(DCC);
 136                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 137                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 138                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 139                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 140                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 141                         break;
 142                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 143                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 144                                 /* This is the base swizzling by the GPU for
 145                                  * tiled buffers.
 146                                  */
 147                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 148                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 149                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 150                                 /* Bit 11 swizzling by the CPU in addition. */
 151                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 152                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 153                         } else {
 154                                 /* Bit 17 swizzling by the CPU in addition. */
 155                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 156                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 157                         }
 158                         break;
 159                 }
 160                 if (dcc == 0xffffffff) {
 161                         DRM_ERROR("Couldn't read from MCHBAR.  "
 162                                   "Disabling tiling.\n");
 163                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 164                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 165                 }
 166         } else {
 167                 /* The 965, G33, and newer, have a very flexible memory
 168                  * configuration.  It will enable dual-channel mode
 169                  * (interleaving) on as much memory as it can, and the GPU
 170                  * will additionally sometimes enable different bit 6
 171                  * swizzling for tiled objects from the CPU.
 172                  *
 173                  * Here's what I found on the G965:
 174                  *    slot fill         memory size  swizzling
 175                  * 0A   0B   1A   1B    1-ch   2-ch
 176                  * 512  0    0    0     512    0     O
 177                  * 512  0    512  0     16     1008  X
 178                  * 512  0    0    512   16     1008  X
 179                  * 0    512  0    512   16     1008  X
 180                  * 1024 1024 1024 0     2048   1024  O
 181                  *
 182                  * We could probably detect this based on either the DRB
 183                  * matching, which was the case for the swizzling required in
 184                  * the table above, or from the 1-ch value being less than
 185                  * the minimum size of a rank.
 186                  */
 187                 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
 188                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 189                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 190                 } else {
 191                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 192                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 193                 }
 194         }
 195
 196         dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 197         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 198 }
 199
 200 /* Check pitch constriants for all chips & tiling formats */
 201 static bool
 202 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 203 {
 204         int tile_width;
 205
 206         /* Linear is always fine */
 207         if (tiling_mode == I915_TILING_NONE)
 208                 return true;
 209
 210         if (IS_GEN2(dev) ||
 211             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
 212                 tile_width = 128;
 213         else
 214                 tile_width = 512;
 215
 216         /* check maximum stride & object size */
 217         if (INTEL_INFO(dev)->gen >= 4) {
 218                 /* i965 stores the end address of the gtt mapping in the fence
 219                  * reg, so dont bother to check the size */
 220                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 221                         return false;
 222         } else {
 223                 if (stride > 8192)
 224                         return false;
 225
 226                 if (IS_GEN3(dev)) {
 227                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
 228                                 return false;
 229                 } else {
 230                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
 231                                 return false;
 232                 }
 233         }
 234
 235         /* 965+ just needs multiples of tile width */
 236         if (INTEL_INFO(dev)->gen >= 4) {
 237                 if (stride & (tile_width - 1))
 238                         return false;
 239                 return true;
 240         }
 241
 242         /* Pre-965 needs power of two tile widths */
 243         if (stride < tile_width)
 244                 return false;
 245
 246         if (stride & (stride - 1))
 247                 return false;
 248
 249         return true;
 250 }
 251
 252 /* Is the current GTT allocation valid for the change in tiling? */
 253 static bool
 254 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 255 {
 256         u32 size;
 257
 258         if (tiling_mode == I915_TILING_NONE)
 259                 return true;
 260
 261         if (INTEL_INFO(obj->base.dev)->gen >= 4)
 262                 return true;
 263
 264         if (INTEL_INFO(obj->base.dev)->gen == 3) {
 265                 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
 266                         return false;
 267         } else {
 268                 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
 269                         return false;
 270         }
 271
 272         /*
 273          * Previous chips need to be aligned to the size of the smallest
 274          * fence register that can contain the object.
 275          */
 276         if (INTEL_INFO(obj->base.dev)->gen == 3)
 277                 size = 1024*1024;
 278         else
 279                 size = 512*1024;
 280
 281         while (size < obj->base.size)
 282                 size <<= 1;
 283
 284         if (obj->gtt_space->size != size)
 285                 return false;
 286
 287         if (obj->gtt_offset & (size - 1))
 288                 return false;
 289
 290         return true;
 291 }
 292
 293 /**
 294  * Sets the tiling mode of an object, returning the required swizzling of
 295  * bit 6 of addresses in the object.
 296  */
 297 int
 298 i915_gem_set_tiling(struct drm_device *dev, void *data,
 299                    struct drm_file *file)
 300 {
 301         struct drm_i915_gem_set_tiling *args = data;
 302         drm_i915_private_t *dev_priv = dev->dev_private;
 303         struct drm_i915_gem_object *obj;
 304         int ret = 0;
 305
 306         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 307         if (&obj->base == NULL)
 308                 return -ENOENT;
 309
 310         if (!i915_tiling_ok(dev,
 311                             args->stride, obj->base.size, args->tiling_mode)) {
 312                 drm_gem_object_unreference_unlocked(&obj->base);
 313                 return -EINVAL;
 314         }
 315
 316         if (obj->pin_count) {
 317                 drm_gem_object_unreference_unlocked(&obj->base);
 318                 return -EBUSY;
 319         }
 320
 321         if (args->tiling_mode == I915_TILING_NONE) {
 322                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 323                 args->stride = 0;
 324         } else {
 325                 if (args->tiling_mode == I915_TILING_X)
 326                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 327                 else
 328                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 329
 330                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 331                  * from aborting the application on sw fallbacks to bit 17,
 332                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 333                  * If there was a user that was relying on the swizzle
 334                  * information for drm_intel_bo_map()ed reads/writes this would
 335                  * break it, but we don't have any of those.
 336                  */
 337                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 338                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 339                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 340                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 341
 342                 /* If we can't handle the swizzling, make it untiled. */
 343                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 344                         args->tiling_mode = I915_TILING_NONE;
 345                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 346                         args->stride = 0;
 347                 }
 348         }
 349
 350         mutex_lock(&dev->struct_mutex);
 351         if (args->tiling_mode != obj->tiling_mode ||
 352             args->stride != obj->stride) {
 353                 /* We need to rebind the object if its current allocation
 354                  * no longer meets the alignment restrictions for its new
 355                  * tiling mode. Otherwise we can just leave it alone, but
 356                  * need to ensure that any fence register is updated before
 357                  * the next fenced (either through the GTT or by the BLT unit
 358                  * on older GPUs) access.
 359                  *
 360                  * After updating the tiling parameters, we then flag whether
 361                  * we need to update an associated fence register. Note this
 362                  * has to also include the unfenced register the GPU uses
 363                  * whilst executing a fenced command for an untiled object.
 364                  */
 365
 366                 obj->map_and_fenceable =
 367                         obj->gtt_space == NULL ||
 368                         (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
 369                          i915_gem_object_fence_ok(obj, args->tiling_mode));
 370
 371                 /* Rebind if we need a change of alignment */
 372                 if (!obj->map_and_fenceable) {
 373                         u32 unfenced_alignment =
 374                                 i915_gem_get_unfenced_gtt_alignment(dev,
 375                                                                     obj->base.size,
 376                                                                     args->tiling_mode);
 377                         if (obj->gtt_offset & (unfenced_alignment - 1))
 378                                 ret = i915_gem_object_unbind(obj);
 379                 }
 380
 381                 if (ret == 0) {
 382                         obj->fence_dirty =
 383                                 obj->fenced_gpu_access ||
 384                                 obj->fence_reg != I915_FENCE_REG_NONE;
 385
 386                         obj->tiling_mode = args->tiling_mode;
 387                         obj->stride = args->stride;
 388
 389                         /* Force the fence to be reacquired for GTT access */
 390                         i915_gem_release_mmap(obj);
 391                 }
 392         }
 393         /* we have to maintain this existing ABI... */
 394         args->stride = obj->stride;
 395         args->tiling_mode = obj->tiling_mode;
 396         drm_gem_object_unreference(&obj->base);
 397         mutex_unlock(&dev->struct_mutex);
 398
 399         return ret;
 400 }
 401
 402 /**
 403  * Returns the current tiling mode and required bit 6 swizzling for the object.
 404  */
 405 int
 406 i915_gem_get_tiling(struct drm_device *dev, void *data,
 407                    struct drm_file *file)
 408 {
 409         struct drm_i915_gem_get_tiling *args = data;
 410         drm_i915_private_t *dev_priv = dev->dev_private;
 411         struct drm_i915_gem_object *obj;
 412
 413         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 414         if (&obj->base == NULL)
 415                 return -ENOENT;
 416
 417         mutex_lock(&dev->struct_mutex);
 418
 419         args->tiling_mode = obj->tiling_mode;
 420         switch (obj->tiling_mode) {
 421         case I915_TILING_X:
 422                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 423                 break;
 424         case I915_TILING_Y:
 425                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 426                 break;
 427         case I915_TILING_NONE:
 428                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 429                 break;
 430         default:
 431                 DRM_ERROR("unknown tiling mode\n");
 432         }
 433
 434         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 435         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 436                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 437         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 438                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 439
 440         drm_gem_object_unreference(&obj->base);
 441         mutex_unlock(&dev->struct_mutex);
 442
 443         return 0;
 444 }
 445
 446 /**
 447  * Swap every 64 bytes of this page around, to account for it having a new
 448  * bit 17 of its physical address and therefore being interpreted differently
 449  * by the GPU.
 450  */
 451 static void
 452 i915_gem_swizzle_page(struct page *page)
 453 {
 454         char temp[64];
 455         char *vaddr;
 456         int i;
 457
 458         vaddr = kmap(page);
 459
 460         for (i = 0; i < PAGE_SIZE; i += 128) {
 461                 memcpy(temp, &vaddr[i], 64);
 462                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 463                 memcpy(&vaddr[i + 64], temp, 64);
 464         }
 465
 466         kunmap(page);
 467 }
 468
 469 void
 470 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
 471 {
 472         int page_count = obj->base.size >> PAGE_SHIFT;
 473         int i;
 474
 475         if (obj->bit_17 == NULL)
 476                 return;
 477
 478         for (i = 0; i < page_count; i++) {
 479                 char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
 480                 if ((new_bit_17 & 0x1) !=
 481                     (test_bit(i, obj->bit_17) != 0)) {
 482                         i915_gem_swizzle_page(obj->pages[i]);
 483                         set_page_dirty(obj->pages[i]);
 484                 }
 485         }
 486 }
 487
 488 void
 489 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
 490 {
 491         int page_count = obj->base.size >> PAGE_SHIFT;
 492         int i;
 493
 494         if (obj->bit_17 == NULL) {
 495                 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
 496                                            sizeof(long), GFP_KERNEL);
 497                 if (obj->bit_17 == NULL) {
 498                         DRM_ERROR("Failed to allocate memory for bit 17 "
 499                                   "record\n");
 500                         return;
 501                 }
 502         }
 503
 504         for (i = 0; i < page_count; i++) {
 505                 if (page_to_phys(obj->pages[i]) & (1 << 17))
 506                         __set_bit(i, obj->bit_17);
 507                 else
 508                         __clear_bit(i, obj->bit_17);
 509         }
 510 }