1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
, pixel
, vbl_start
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
538 struct intel_crtc
*intel_crtc
=
539 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
540 const struct drm_display_mode
*mode
=
541 &intel_crtc
->config
.adjusted_mode
;
543 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
545 enum transcoder cpu_transcoder
=
546 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
549 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
550 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
555 high_frame
= PIPEFRAME(pipe
);
556 low_frame
= PIPEFRAMEPIXEL(pipe
);
559 * High & low register fields aren't synchronized, so make sure
560 * we get a low value that's stable across two reads of the high
564 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
565 low
= I915_READ(low_frame
);
566 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
567 } while (high1
!= high2
);
569 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
570 pixel
= low
& PIPE_PIXEL_MASK
;
571 low
>>= PIPE_FRAME_LOW_SHIFT
;
574 * The frame counter increments at beginning of active.
575 * Cook up a vblank counter by also checking the pixel
576 * counter against vblank start.
578 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
581 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
583 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
584 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
586 if (!i915_pipe_enabled(dev
, pipe
)) {
587 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
588 "pipe %c\n", pipe_name(pipe
));
592 return I915_READ(reg
);
595 static bool intel_pipe_in_vblank(struct drm_device
*dev
, enum pipe pipe
)
597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 if (IS_VALLEYVIEW(dev
)) {
601 status
= pipe
== PIPE_A
?
602 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
603 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
605 return I915_READ(VLV_ISR
) & status
;
606 } else if (IS_GEN2(dev
)) {
607 status
= pipe
== PIPE_A
?
608 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
609 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
611 return I915_READ16(ISR
) & status
;
612 } else if (INTEL_INFO(dev
)->gen
< 5) {
613 status
= pipe
== PIPE_A
?
614 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
615 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
617 return I915_READ(ISR
) & status
;
618 } else if (INTEL_INFO(dev
)->gen
< 7) {
619 status
= pipe
== PIPE_A
?
623 return I915_READ(DEISR
) & status
;
628 status
= DE_PIPEA_VBLANK_IVB
;
631 status
= DE_PIPEB_VBLANK_IVB
;
634 status
= DE_PIPEC_VBLANK_IVB
;
638 return I915_READ(DEISR
) & status
;
642 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
643 int *vpos
, int *hpos
)
645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
646 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
647 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
648 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
650 int vbl_start
, vbl_end
, htotal
, vtotal
;
654 if (!intel_crtc
->active
) {
655 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
656 "pipe %c\n", pipe_name(pipe
));
660 htotal
= mode
->crtc_htotal
;
661 vtotal
= mode
->crtc_vtotal
;
662 vbl_start
= mode
->crtc_vblank_start
;
663 vbl_end
= mode
->crtc_vblank_end
;
665 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
667 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
668 /* No obvious pixelcount register. Only query vertical
669 * scanout position from Display scan line register.
672 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
674 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
677 * The scanline counter increments at the leading edge
678 * of hsync, ie. it completely misses the active portion
679 * of the line. Fix up the counter at both edges of vblank
680 * to get a more accurate picture whether we're in vblank
683 in_vbl
= intel_pipe_in_vblank(dev
, pipe
);
684 if ((in_vbl
&& position
== vbl_start
- 1) ||
685 (!in_vbl
&& position
== vbl_end
- 1))
686 position
= (position
+ 1) % vtotal
;
688 /* Have access to pixelcount since start of frame.
689 * We can split this into vertical and horizontal
692 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
694 /* convert to pixel counts */
700 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
703 * While in vblank, position will be negative
704 * counting up towards 0 at vbl_end. And outside
705 * vblank, position will be positive counting
708 if (position
>= vbl_start
)
711 position
+= vtotal
- vbl_end
;
713 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
717 *vpos
= position
/ htotal
;
718 *hpos
= position
- (*vpos
* htotal
);
723 ret
|= DRM_SCANOUTPOS_INVBL
;
728 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
730 struct timeval
*vblank_time
,
733 struct drm_crtc
*crtc
;
735 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
736 DRM_ERROR("Invalid crtc %d\n", pipe
);
740 /* Get drm_crtc to timestamp: */
741 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
743 DRM_ERROR("Invalid crtc %d\n", pipe
);
747 if (!crtc
->enabled
) {
748 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
752 /* Helper routine in DRM core does all the work: */
753 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
758 static bool intel_hpd_irq_event(struct drm_device
*dev
,
759 struct drm_connector
*connector
)
761 enum drm_connector_status old_status
;
763 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
764 old_status
= connector
->status
;
766 connector
->status
= connector
->funcs
->detect(connector
, false);
767 if (old_status
== connector
->status
)
770 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
772 drm_get_connector_name(connector
),
773 drm_get_connector_status_name(old_status
),
774 drm_get_connector_status_name(connector
->status
));
780 * Handle hotplug events outside the interrupt handler proper.
782 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
784 static void i915_hotplug_work_func(struct work_struct
*work
)
786 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
788 struct drm_device
*dev
= dev_priv
->dev
;
789 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
790 struct intel_connector
*intel_connector
;
791 struct intel_encoder
*intel_encoder
;
792 struct drm_connector
*connector
;
793 unsigned long irqflags
;
794 bool hpd_disabled
= false;
795 bool changed
= false;
798 /* HPD irq before everything is fully set up. */
799 if (!dev_priv
->enable_hotplug_processing
)
802 mutex_lock(&mode_config
->mutex
);
803 DRM_DEBUG_KMS("running encoder hotplug functions\n");
805 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
807 hpd_event_bits
= dev_priv
->hpd_event_bits
;
808 dev_priv
->hpd_event_bits
= 0;
809 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
810 intel_connector
= to_intel_connector(connector
);
811 intel_encoder
= intel_connector
->encoder
;
812 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
813 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
814 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
815 DRM_INFO("HPD interrupt storm detected on connector %s: "
816 "switching from hotplug detection to polling\n",
817 drm_get_connector_name(connector
));
818 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
819 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
820 | DRM_CONNECTOR_POLL_DISCONNECT
;
823 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
824 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
825 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
828 /* if there were no outputs to poll, poll was disabled,
829 * therefore make sure it's enabled when disabling HPD on
832 drm_kms_helper_poll_enable(dev
);
833 mod_timer(&dev_priv
->hotplug_reenable_timer
,
834 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
837 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
839 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
840 intel_connector
= to_intel_connector(connector
);
841 intel_encoder
= intel_connector
->encoder
;
842 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
843 if (intel_encoder
->hot_plug
)
844 intel_encoder
->hot_plug(intel_encoder
);
845 if (intel_hpd_irq_event(dev
, connector
))
849 mutex_unlock(&mode_config
->mutex
);
852 drm_kms_helper_hotplug_event(dev
);
855 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
857 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
858 u32 busy_up
, busy_down
, max_avg
, min_avg
;
861 spin_lock(&mchdev_lock
);
863 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
865 new_delay
= dev_priv
->ips
.cur_delay
;
867 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
868 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
869 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
870 max_avg
= I915_READ(RCBMAXAVG
);
871 min_avg
= I915_READ(RCBMINAVG
);
873 /* Handle RCS change request from hw */
874 if (busy_up
> max_avg
) {
875 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
876 new_delay
= dev_priv
->ips
.cur_delay
- 1;
877 if (new_delay
< dev_priv
->ips
.max_delay
)
878 new_delay
= dev_priv
->ips
.max_delay
;
879 } else if (busy_down
< min_avg
) {
880 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
881 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
882 if (new_delay
> dev_priv
->ips
.min_delay
)
883 new_delay
= dev_priv
->ips
.min_delay
;
886 if (ironlake_set_drps(dev
, new_delay
))
887 dev_priv
->ips
.cur_delay
= new_delay
;
889 spin_unlock(&mchdev_lock
);
894 static void notify_ring(struct drm_device
*dev
,
895 struct intel_ring_buffer
*ring
)
897 if (ring
->obj
== NULL
)
900 trace_i915_gem_request_complete(ring
);
902 wake_up_all(&ring
->irq_queue
);
903 i915_queue_hangcheck(dev
);
906 static void gen6_pm_rps_work(struct work_struct
*work
)
908 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
913 spin_lock_irq(&dev_priv
->irq_lock
);
914 pm_iir
= dev_priv
->rps
.pm_iir
;
915 dev_priv
->rps
.pm_iir
= 0;
916 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
917 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
918 spin_unlock_irq(&dev_priv
->irq_lock
);
920 /* Make sure we didn't queue anything we're not going to process. */
921 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
923 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
926 mutex_lock(&dev_priv
->rps
.hw_lock
);
928 adj
= dev_priv
->rps
.last_adj
;
929 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
934 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
937 * For better performance, jump directly
938 * to RPe if we're below it.
940 if (new_delay
< dev_priv
->rps
.rpe_delay
)
941 new_delay
= dev_priv
->rps
.rpe_delay
;
942 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
943 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
944 new_delay
= dev_priv
->rps
.rpe_delay
;
946 new_delay
= dev_priv
->rps
.min_delay
;
948 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
953 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
954 } else { /* unknown event */
955 new_delay
= dev_priv
->rps
.cur_delay
;
958 /* sysfs frequency interfaces may have snuck in while servicing the
961 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
962 new_delay
= dev_priv
->rps
.min_delay
;
963 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
964 new_delay
= dev_priv
->rps
.max_delay
;
965 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
967 if (IS_VALLEYVIEW(dev_priv
->dev
))
968 valleyview_set_rps(dev_priv
->dev
, new_delay
);
970 gen6_set_rps(dev_priv
->dev
, new_delay
);
972 mutex_unlock(&dev_priv
->rps
.hw_lock
);
977 * ivybridge_parity_work - Workqueue called when a parity error interrupt
979 * @work: workqueue struct
981 * Doesn't actually do anything except notify userspace. As a consequence of
982 * this event, userspace should try to remap the bad rows since statistically
983 * it is likely the same row is more likely to go bad again.
985 static void ivybridge_parity_work(struct work_struct
*work
)
987 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
988 l3_parity
.error_work
);
989 u32 error_status
, row
, bank
, subbank
;
990 char *parity_event
[6];
995 /* We must turn off DOP level clock gating to access the L3 registers.
996 * In order to prevent a get/put style interface, acquire struct mutex
997 * any time we access those registers.
999 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1001 /* If we've screwed up tracking, just let the interrupt fire again */
1002 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1005 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1006 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1007 POSTING_READ(GEN7_MISCCPCTL
);
1009 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1013 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1016 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1018 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1020 error_status
= I915_READ(reg
);
1021 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1022 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1023 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1025 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1028 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1029 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1030 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1031 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1032 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1033 parity_event
[5] = NULL
;
1035 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
1036 KOBJ_CHANGE
, parity_event
);
1038 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1039 slice
, row
, bank
, subbank
);
1041 kfree(parity_event
[4]);
1042 kfree(parity_event
[3]);
1043 kfree(parity_event
[2]);
1044 kfree(parity_event
[1]);
1047 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1050 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1051 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1052 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1053 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1055 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1058 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1060 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1062 if (!HAS_L3_DPF(dev
))
1065 spin_lock(&dev_priv
->irq_lock
);
1066 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1067 spin_unlock(&dev_priv
->irq_lock
);
1069 iir
&= GT_PARITY_ERROR(dev
);
1070 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1071 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1073 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1074 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1076 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1079 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1080 struct drm_i915_private
*dev_priv
,
1084 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1085 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1086 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1087 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1090 static void snb_gt_irq_handler(struct drm_device
*dev
,
1091 struct drm_i915_private
*dev_priv
,
1096 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1097 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1098 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1099 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1100 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1101 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1103 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1104 GT_BSD_CS_ERROR_INTERRUPT
|
1105 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1106 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1107 i915_handle_error(dev
, false);
1110 if (gt_iir
& GT_PARITY_ERROR(dev
))
1111 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1114 #define HPD_STORM_DETECT_PERIOD 1000
1115 #define HPD_STORM_THRESHOLD 5
1117 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1118 u32 hotplug_trigger
,
1121 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1123 bool storm_detected
= false;
1125 if (!hotplug_trigger
)
1128 spin_lock(&dev_priv
->irq_lock
);
1129 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1131 WARN(((hpd
[i
] & hotplug_trigger
) &&
1132 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1133 "Received HPD interrupt although disabled\n");
1135 if (!(hpd
[i
] & hotplug_trigger
) ||
1136 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1139 dev_priv
->hpd_event_bits
|= (1 << i
);
1140 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1141 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1142 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1143 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1144 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1145 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1146 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1147 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1148 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1149 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1150 storm_detected
= true;
1152 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1153 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1154 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1159 dev_priv
->display
.hpd_irq_setup(dev
);
1160 spin_unlock(&dev_priv
->irq_lock
);
1163 * Our hotplug handler can grab modeset locks (by calling down into the
1164 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1165 * queue for otherwise the flush_work in the pageflip code will
1168 schedule_work(&dev_priv
->hotplug_work
);
1171 static void gmbus_irq_handler(struct drm_device
*dev
)
1173 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1175 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1178 static void dp_aux_irq_handler(struct drm_device
*dev
)
1180 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1182 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1185 /* The RPS events need forcewake, so we add them to a work queue and mask their
1186 * IMR bits until the work is done. Other interrupts can be processed without
1187 * the work queue. */
1188 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1190 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1191 spin_lock(&dev_priv
->irq_lock
);
1192 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1193 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1194 spin_unlock(&dev_priv
->irq_lock
);
1196 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1199 if (HAS_VEBOX(dev_priv
->dev
)) {
1200 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1201 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1203 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1204 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1205 i915_handle_error(dev_priv
->dev
, false);
1210 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1212 struct drm_device
*dev
= (struct drm_device
*) arg
;
1213 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1214 u32 iir
, gt_iir
, pm_iir
;
1215 irqreturn_t ret
= IRQ_NONE
;
1216 unsigned long irqflags
;
1218 u32 pipe_stats
[I915_MAX_PIPES
];
1220 atomic_inc(&dev_priv
->irq_received
);
1223 iir
= I915_READ(VLV_IIR
);
1224 gt_iir
= I915_READ(GTIIR
);
1225 pm_iir
= I915_READ(GEN6_PMIIR
);
1227 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1232 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1234 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1235 for_each_pipe(pipe
) {
1236 int reg
= PIPESTAT(pipe
);
1237 pipe_stats
[pipe
] = I915_READ(reg
);
1240 * Clear the PIPE*STAT regs before the IIR
1242 if (pipe_stats
[pipe
] & 0x8000ffff) {
1243 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1244 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1246 I915_WRITE(reg
, pipe_stats
[pipe
]);
1249 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1251 for_each_pipe(pipe
) {
1252 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1253 drm_handle_vblank(dev
, pipe
);
1255 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1256 intel_prepare_page_flip(dev
, pipe
);
1257 intel_finish_page_flip(dev
, pipe
);
1261 /* Consume port. Then clear IIR or we'll miss events */
1262 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1263 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1264 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1266 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1269 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1271 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1272 I915_READ(PORT_HOTPLUG_STAT
);
1275 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1276 gmbus_irq_handler(dev
);
1279 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1281 I915_WRITE(GTIIR
, gt_iir
);
1282 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1283 I915_WRITE(VLV_IIR
, iir
);
1290 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1292 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1294 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1296 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1298 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1299 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1300 SDE_AUDIO_POWER_SHIFT
);
1301 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1305 if (pch_iir
& SDE_AUX_MASK
)
1306 dp_aux_irq_handler(dev
);
1308 if (pch_iir
& SDE_GMBUS
)
1309 gmbus_irq_handler(dev
);
1311 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1312 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1314 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1315 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1317 if (pch_iir
& SDE_POISON
)
1318 DRM_ERROR("PCH poison interrupt\n");
1320 if (pch_iir
& SDE_FDI_MASK
)
1322 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1324 I915_READ(FDI_RX_IIR(pipe
)));
1326 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1327 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1329 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1330 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1332 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1333 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1335 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1337 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1338 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1340 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1343 static void ivb_err_int_handler(struct drm_device
*dev
)
1345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1348 if (err_int
& ERR_INT_POISON
)
1349 DRM_ERROR("Poison interrupt\n");
1351 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1352 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1353 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1355 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1356 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1357 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1359 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1360 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1361 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1363 I915_WRITE(GEN7_ERR_INT
, err_int
);
1366 static void cpt_serr_int_handler(struct drm_device
*dev
)
1368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1369 u32 serr_int
= I915_READ(SERR_INT
);
1371 if (serr_int
& SERR_INT_POISON
)
1372 DRM_ERROR("PCH poison interrupt\n");
1374 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1375 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1377 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1379 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1380 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1382 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1384 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1385 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1387 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1389 I915_WRITE(SERR_INT
, serr_int
);
1392 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1394 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1396 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1398 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1400 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1401 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1402 SDE_AUDIO_POWER_SHIFT_CPT
);
1403 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1407 if (pch_iir
& SDE_AUX_MASK_CPT
)
1408 dp_aux_irq_handler(dev
);
1410 if (pch_iir
& SDE_GMBUS_CPT
)
1411 gmbus_irq_handler(dev
);
1413 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1414 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1416 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1417 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1419 if (pch_iir
& SDE_FDI_MASK_CPT
)
1421 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1423 I915_READ(FDI_RX_IIR(pipe
)));
1425 if (pch_iir
& SDE_ERROR_CPT
)
1426 cpt_serr_int_handler(dev
);
1429 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1433 if (de_iir
& DE_AUX_CHANNEL_A
)
1434 dp_aux_irq_handler(dev
);
1436 if (de_iir
& DE_GSE
)
1437 intel_opregion_asle_intr(dev
);
1439 if (de_iir
& DE_PIPEA_VBLANK
)
1440 drm_handle_vblank(dev
, 0);
1442 if (de_iir
& DE_PIPEB_VBLANK
)
1443 drm_handle_vblank(dev
, 1);
1445 if (de_iir
& DE_POISON
)
1446 DRM_ERROR("Poison interrupt\n");
1448 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1449 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1450 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1452 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1453 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1454 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1456 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1457 intel_prepare_page_flip(dev
, 0);
1458 intel_finish_page_flip_plane(dev
, 0);
1461 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1462 intel_prepare_page_flip(dev
, 1);
1463 intel_finish_page_flip_plane(dev
, 1);
1466 /* check event from PCH */
1467 if (de_iir
& DE_PCH_EVENT
) {
1468 u32 pch_iir
= I915_READ(SDEIIR
);
1470 if (HAS_PCH_CPT(dev
))
1471 cpt_irq_handler(dev
, pch_iir
);
1473 ibx_irq_handler(dev
, pch_iir
);
1475 /* should clear PCH hotplug event before clear CPU irq */
1476 I915_WRITE(SDEIIR
, pch_iir
);
1479 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1480 ironlake_rps_change_irq_handler(dev
);
1483 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1488 if (de_iir
& DE_ERR_INT_IVB
)
1489 ivb_err_int_handler(dev
);
1491 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1492 dp_aux_irq_handler(dev
);
1494 if (de_iir
& DE_GSE_IVB
)
1495 intel_opregion_asle_intr(dev
);
1497 for (i
= 0; i
< 3; i
++) {
1498 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1499 drm_handle_vblank(dev
, i
);
1500 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1501 intel_prepare_page_flip(dev
, i
);
1502 intel_finish_page_flip_plane(dev
, i
);
1506 /* check event from PCH */
1507 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1508 u32 pch_iir
= I915_READ(SDEIIR
);
1510 cpt_irq_handler(dev
, pch_iir
);
1512 /* clear PCH hotplug event before clear CPU irq */
1513 I915_WRITE(SDEIIR
, pch_iir
);
1517 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1519 struct drm_device
*dev
= (struct drm_device
*) arg
;
1520 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1521 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1522 irqreturn_t ret
= IRQ_NONE
;
1524 atomic_inc(&dev_priv
->irq_received
);
1526 /* We get interrupts on unclaimed registers, so check for this before we
1527 * do any I915_{READ,WRITE}. */
1528 intel_uncore_check_errors(dev
);
1530 /* disable master interrupt before clearing iir */
1531 de_ier
= I915_READ(DEIER
);
1532 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1533 POSTING_READ(DEIER
);
1535 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1536 * interrupts will will be stored on its back queue, and then we'll be
1537 * able to process them after we restore SDEIER (as soon as we restore
1538 * it, we'll get an interrupt if SDEIIR still has something to process
1539 * due to its back queue). */
1540 if (!HAS_PCH_NOP(dev
)) {
1541 sde_ier
= I915_READ(SDEIER
);
1542 I915_WRITE(SDEIER
, 0);
1543 POSTING_READ(SDEIER
);
1546 gt_iir
= I915_READ(GTIIR
);
1548 if (INTEL_INFO(dev
)->gen
>= 6)
1549 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1551 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1552 I915_WRITE(GTIIR
, gt_iir
);
1556 de_iir
= I915_READ(DEIIR
);
1558 if (INTEL_INFO(dev
)->gen
>= 7)
1559 ivb_display_irq_handler(dev
, de_iir
);
1561 ilk_display_irq_handler(dev
, de_iir
);
1562 I915_WRITE(DEIIR
, de_iir
);
1566 if (INTEL_INFO(dev
)->gen
>= 6) {
1567 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1569 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1570 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1575 I915_WRITE(DEIER
, de_ier
);
1576 POSTING_READ(DEIER
);
1577 if (!HAS_PCH_NOP(dev
)) {
1578 I915_WRITE(SDEIER
, sde_ier
);
1579 POSTING_READ(SDEIER
);
1585 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1586 bool reset_completed
)
1588 struct intel_ring_buffer
*ring
;
1592 * Notify all waiters for GPU completion events that reset state has
1593 * been changed, and that they need to restart their wait after
1594 * checking for potential errors (and bail out to drop locks if there is
1595 * a gpu reset pending so that i915_error_work_func can acquire them).
1598 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1599 for_each_ring(ring
, dev_priv
, i
)
1600 wake_up_all(&ring
->irq_queue
);
1602 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1603 wake_up_all(&dev_priv
->pending_flip_queue
);
1606 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1607 * reset state is cleared.
1609 if (reset_completed
)
1610 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1614 * i915_error_work_func - do process context error handling work
1615 * @work: work struct
1617 * Fire an error uevent so userspace can see that a hang or error
1620 static void i915_error_work_func(struct work_struct
*work
)
1622 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1624 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1626 struct drm_device
*dev
= dev_priv
->dev
;
1627 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1628 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1629 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1632 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1635 * Note that there's only one work item which does gpu resets, so we
1636 * need not worry about concurrent gpu resets potentially incrementing
1637 * error->reset_counter twice. We only need to take care of another
1638 * racing irq/hangcheck declaring the gpu dead for a second time. A
1639 * quick check for that is good enough: schedule_work ensures the
1640 * correct ordering between hang detection and this work item, and since
1641 * the reset in-progress bit is only ever set by code outside of this
1642 * work we don't need to worry about any other races.
1644 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1645 DRM_DEBUG_DRIVER("resetting chip\n");
1646 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1650 * All state reset _must_ be completed before we update the
1651 * reset counter, for otherwise waiters might miss the reset
1652 * pending state and not properly drop locks, resulting in
1653 * deadlocks with the reset work.
1655 ret
= i915_reset(dev
);
1657 intel_display_handle_reset(dev
);
1661 * After all the gem state is reset, increment the reset
1662 * counter and wake up everyone waiting for the reset to
1665 * Since unlock operations are a one-sided barrier only,
1666 * we need to insert a barrier here to order any seqno
1668 * the counter increment.
1670 smp_mb__before_atomic_inc();
1671 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1673 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1674 KOBJ_CHANGE
, reset_done_event
);
1676 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1680 * Note: The wake_up also serves as a memory barrier so that
1681 * waiters see the update value of the reset counter atomic_t.
1683 i915_error_wake_up(dev_priv
, true);
1687 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1691 u32 eir
= I915_READ(EIR
);
1697 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1699 i915_get_extra_instdone(dev
, instdone
);
1702 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1703 u32 ipeir
= I915_READ(IPEIR_I965
);
1705 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1706 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1707 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1708 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1709 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1710 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1711 I915_WRITE(IPEIR_I965
, ipeir
);
1712 POSTING_READ(IPEIR_I965
);
1714 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1715 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1716 pr_err("page table error\n");
1717 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1718 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1719 POSTING_READ(PGTBL_ER
);
1723 if (!IS_GEN2(dev
)) {
1724 if (eir
& I915_ERROR_PAGE_TABLE
) {
1725 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1726 pr_err("page table error\n");
1727 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1728 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1729 POSTING_READ(PGTBL_ER
);
1733 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1734 pr_err("memory refresh error:\n");
1736 pr_err("pipe %c stat: 0x%08x\n",
1737 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1738 /* pipestat has already been acked */
1740 if (eir
& I915_ERROR_INSTRUCTION
) {
1741 pr_err("instruction error\n");
1742 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1743 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1744 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1745 if (INTEL_INFO(dev
)->gen
< 4) {
1746 u32 ipeir
= I915_READ(IPEIR
);
1748 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1749 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1750 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1751 I915_WRITE(IPEIR
, ipeir
);
1752 POSTING_READ(IPEIR
);
1754 u32 ipeir
= I915_READ(IPEIR_I965
);
1756 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1757 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1758 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1759 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1760 I915_WRITE(IPEIR_I965
, ipeir
);
1761 POSTING_READ(IPEIR_I965
);
1765 I915_WRITE(EIR
, eir
);
1767 eir
= I915_READ(EIR
);
1770 * some errors might have become stuck,
1773 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1774 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1775 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1780 * i915_handle_error - handle an error interrupt
1783 * Do some basic checking of regsiter state at error interrupt time and
1784 * dump it to the syslog. Also call i915_capture_error_state() to make
1785 * sure we get a record and make it available in debugfs. Fire a uevent
1786 * so userspace knows something bad happened (should trigger collection
1787 * of a ring dump etc.).
1789 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1793 i915_capture_error_state(dev
);
1794 i915_report_and_clear_eir(dev
);
1797 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1798 &dev_priv
->gpu_error
.reset_counter
);
1801 * Wakeup waiting processes so that the reset work function
1802 * i915_error_work_func doesn't deadlock trying to grab various
1803 * locks. By bumping the reset counter first, the woken
1804 * processes will see a reset in progress and back off,
1805 * releasing their locks and then wait for the reset completion.
1806 * We must do this for _all_ gpu waiters that might hold locks
1807 * that the reset work needs to acquire.
1809 * Note: The wake_up serves as the required memory barrier to
1810 * ensure that the waiters see the updated value of the reset
1813 i915_error_wake_up(dev_priv
, false);
1817 * Our reset work can grab modeset locks (since it needs to reset the
1818 * state of outstanding pagelips). Hence it must not be run on our own
1819 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1820 * code will deadlock.
1822 schedule_work(&dev_priv
->gpu_error
.work
);
1825 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1827 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1828 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1830 struct drm_i915_gem_object
*obj
;
1831 struct intel_unpin_work
*work
;
1832 unsigned long flags
;
1833 bool stall_detected
;
1835 /* Ignore early vblank irqs */
1836 if (intel_crtc
== NULL
)
1839 spin_lock_irqsave(&dev
->event_lock
, flags
);
1840 work
= intel_crtc
->unpin_work
;
1843 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1844 !work
->enable_stall_check
) {
1845 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1846 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1850 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1851 obj
= work
->pending_flip_obj
;
1852 if (INTEL_INFO(dev
)->gen
>= 4) {
1853 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1854 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1855 i915_gem_obj_ggtt_offset(obj
);
1857 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1858 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1859 crtc
->y
* crtc
->fb
->pitches
[0] +
1860 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1863 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1865 if (stall_detected
) {
1866 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1867 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1871 /* Called from drm generic code, passed 'crtc' which
1872 * we use as a pipe index
1874 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1876 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1877 unsigned long irqflags
;
1879 if (!i915_pipe_enabled(dev
, pipe
))
1882 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1883 if (INTEL_INFO(dev
)->gen
>= 4)
1884 i915_enable_pipestat(dev_priv
, pipe
,
1885 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1887 i915_enable_pipestat(dev_priv
, pipe
,
1888 PIPE_VBLANK_INTERRUPT_ENABLE
);
1890 /* maintain vblank delivery even in deep C-states */
1891 if (dev_priv
->info
->gen
== 3)
1892 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1893 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1898 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1900 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1901 unsigned long irqflags
;
1902 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1903 DE_PIPE_VBLANK_ILK(pipe
);
1905 if (!i915_pipe_enabled(dev
, pipe
))
1908 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1909 ironlake_enable_display_irq(dev_priv
, bit
);
1910 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1915 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1917 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1918 unsigned long irqflags
;
1921 if (!i915_pipe_enabled(dev
, pipe
))
1924 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1925 imr
= I915_READ(VLV_IMR
);
1927 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1929 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1930 I915_WRITE(VLV_IMR
, imr
);
1931 i915_enable_pipestat(dev_priv
, pipe
,
1932 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1933 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1938 /* Called from drm generic code, passed 'crtc' which
1939 * we use as a pipe index
1941 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1943 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1944 unsigned long irqflags
;
1946 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1947 if (dev_priv
->info
->gen
== 3)
1948 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1950 i915_disable_pipestat(dev_priv
, pipe
,
1951 PIPE_VBLANK_INTERRUPT_ENABLE
|
1952 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1953 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1956 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1958 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1959 unsigned long irqflags
;
1960 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1961 DE_PIPE_VBLANK_ILK(pipe
);
1963 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1964 ironlake_disable_display_irq(dev_priv
, bit
);
1965 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1968 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1970 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1971 unsigned long irqflags
;
1974 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1975 i915_disable_pipestat(dev_priv
, pipe
,
1976 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1977 imr
= I915_READ(VLV_IMR
);
1979 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1981 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1982 I915_WRITE(VLV_IMR
, imr
);
1983 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1987 ring_last_seqno(struct intel_ring_buffer
*ring
)
1989 return list_entry(ring
->request_list
.prev
,
1990 struct drm_i915_gem_request
, list
)->seqno
;
1994 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1996 return (list_empty(&ring
->request_list
) ||
1997 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2000 static struct intel_ring_buffer
*
2001 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2003 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2004 u32 cmd
, ipehr
, acthd
, acthd_min
;
2006 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2007 if ((ipehr
& ~(0x3 << 16)) !=
2008 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2011 /* ACTHD is likely pointing to the dword after the actual command,
2012 * so scan backwards until we find the MBOX.
2014 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2015 acthd_min
= max((int)acthd
- 3 * 4, 0);
2017 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2022 if (acthd
< acthd_min
)
2026 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2027 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2030 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2032 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2033 struct intel_ring_buffer
*signaller
;
2036 ring
->hangcheck
.deadlock
= true;
2038 signaller
= semaphore_waits_for(ring
, &seqno
);
2039 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2042 /* cursory check for an unkickable deadlock */
2043 ctl
= I915_READ_CTL(signaller
);
2044 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2047 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2050 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2052 struct intel_ring_buffer
*ring
;
2055 for_each_ring(ring
, dev_priv
, i
)
2056 ring
->hangcheck
.deadlock
= false;
2059 static enum intel_ring_hangcheck_action
2060 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2062 struct drm_device
*dev
= ring
->dev
;
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2066 if (ring
->hangcheck
.acthd
!= acthd
)
2067 return HANGCHECK_ACTIVE
;
2070 return HANGCHECK_HUNG
;
2072 /* Is the chip hanging on a WAIT_FOR_EVENT?
2073 * If so we can simply poke the RB_WAIT bit
2074 * and break the hang. This should work on
2075 * all but the second generation chipsets.
2077 tmp
= I915_READ_CTL(ring
);
2078 if (tmp
& RING_WAIT
) {
2079 DRM_ERROR("Kicking stuck wait on %s\n",
2081 i915_handle_error(dev
, false);
2082 I915_WRITE_CTL(ring
, tmp
);
2083 return HANGCHECK_KICK
;
2086 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2087 switch (semaphore_passed(ring
)) {
2089 return HANGCHECK_HUNG
;
2091 DRM_ERROR("Kicking stuck semaphore on %s\n",
2093 i915_handle_error(dev
, false);
2094 I915_WRITE_CTL(ring
, tmp
);
2095 return HANGCHECK_KICK
;
2097 return HANGCHECK_WAIT
;
2101 return HANGCHECK_HUNG
;
2105 * This is called when the chip hasn't reported back with completed
2106 * batchbuffers in a long time. We keep track per ring seqno progress and
2107 * if there are no progress, hangcheck score for that ring is increased.
2108 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2109 * we kick the ring. If we see no progress on three subsequent calls
2110 * we assume chip is wedged and try to fix it by resetting the chip.
2112 static void i915_hangcheck_elapsed(unsigned long data
)
2114 struct drm_device
*dev
= (struct drm_device
*)data
;
2115 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2116 struct intel_ring_buffer
*ring
;
2118 int busy_count
= 0, rings_hung
= 0;
2119 bool stuck
[I915_NUM_RINGS
] = { 0 };
2125 if (!i915_enable_hangcheck
)
2128 for_each_ring(ring
, dev_priv
, i
) {
2132 semaphore_clear_deadlocks(dev_priv
);
2134 seqno
= ring
->get_seqno(ring
, false);
2135 acthd
= intel_ring_get_active_head(ring
);
2137 if (ring
->hangcheck
.seqno
== seqno
) {
2138 if (ring_idle(ring
, seqno
)) {
2139 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2141 if (waitqueue_active(&ring
->irq_queue
)) {
2142 /* Issue a wake-up to catch stuck h/w. */
2143 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2144 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2146 wake_up_all(&ring
->irq_queue
);
2148 /* Safeguard against driver failure */
2149 ring
->hangcheck
.score
+= BUSY
;
2153 /* We always increment the hangcheck score
2154 * if the ring is busy and still processing
2155 * the same request, so that no single request
2156 * can run indefinitely (such as a chain of
2157 * batches). The only time we do not increment
2158 * the hangcheck score on this ring, if this
2159 * ring is in a legitimate wait for another
2160 * ring. In that case the waiting ring is a
2161 * victim and we want to be sure we catch the
2162 * right culprit. Then every time we do kick
2163 * the ring, add a small increment to the
2164 * score so that we can catch a batch that is
2165 * being repeatedly kicked and so responsible
2166 * for stalling the machine.
2168 ring
->hangcheck
.action
= ring_stuck(ring
,
2171 switch (ring
->hangcheck
.action
) {
2172 case HANGCHECK_IDLE
:
2173 case HANGCHECK_WAIT
:
2175 case HANGCHECK_ACTIVE
:
2176 ring
->hangcheck
.score
+= BUSY
;
2178 case HANGCHECK_KICK
:
2179 ring
->hangcheck
.score
+= KICK
;
2181 case HANGCHECK_HUNG
:
2182 ring
->hangcheck
.score
+= HUNG
;
2188 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2190 /* Gradually reduce the count so that we catch DoS
2191 * attempts across multiple batches.
2193 if (ring
->hangcheck
.score
> 0)
2194 ring
->hangcheck
.score
--;
2197 ring
->hangcheck
.seqno
= seqno
;
2198 ring
->hangcheck
.acthd
= acthd
;
2202 for_each_ring(ring
, dev_priv
, i
) {
2203 if (ring
->hangcheck
.score
> FIRE
) {
2204 DRM_INFO("%s on %s\n",
2205 stuck
[i
] ? "stuck" : "no progress",
2212 return i915_handle_error(dev
, true);
2215 /* Reset timer case chip hangs without another request
2217 i915_queue_hangcheck(dev
);
2220 void i915_queue_hangcheck(struct drm_device
*dev
)
2222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 if (!i915_enable_hangcheck
)
2226 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2227 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2230 static void ibx_irq_preinstall(struct drm_device
*dev
)
2232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 if (HAS_PCH_NOP(dev
))
2237 /* south display irq */
2238 I915_WRITE(SDEIMR
, 0xffffffff);
2240 * SDEIER is also touched by the interrupt handler to work around missed
2241 * PCH interrupts. Hence we can't update it after the interrupt handler
2242 * is enabled - instead we unconditionally enable all PCH interrupt
2243 * sources here, but then only unmask them as needed with SDEIMR.
2245 I915_WRITE(SDEIER
, 0xffffffff);
2246 POSTING_READ(SDEIER
);
2249 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2254 I915_WRITE(GTIMR
, 0xffffffff);
2255 I915_WRITE(GTIER
, 0x0);
2256 POSTING_READ(GTIER
);
2258 if (INTEL_INFO(dev
)->gen
>= 6) {
2260 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2261 I915_WRITE(GEN6_PMIER
, 0x0);
2262 POSTING_READ(GEN6_PMIER
);
2268 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2270 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2272 atomic_set(&dev_priv
->irq_received
, 0);
2274 I915_WRITE(HWSTAM
, 0xeffe);
2276 I915_WRITE(DEIMR
, 0xffffffff);
2277 I915_WRITE(DEIER
, 0x0);
2278 POSTING_READ(DEIER
);
2280 gen5_gt_irq_preinstall(dev
);
2282 ibx_irq_preinstall(dev
);
2285 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2287 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2290 atomic_set(&dev_priv
->irq_received
, 0);
2293 I915_WRITE(VLV_IMR
, 0);
2294 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2295 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2296 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2299 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2300 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2302 gen5_gt_irq_preinstall(dev
);
2304 I915_WRITE(DPINVGTT
, 0xff);
2306 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2307 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2309 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2310 I915_WRITE(VLV_IIR
, 0xffffffff);
2311 I915_WRITE(VLV_IMR
, 0xffffffff);
2312 I915_WRITE(VLV_IER
, 0x0);
2313 POSTING_READ(VLV_IER
);
2316 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2318 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2319 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2320 struct intel_encoder
*intel_encoder
;
2321 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2323 if (HAS_PCH_IBX(dev
)) {
2324 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2325 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2326 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2327 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2329 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2330 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2331 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2332 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2335 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2338 * Enable digital hotplug on the PCH, and configure the DP short pulse
2339 * duration to 2ms (which is the minimum in the Display Port spec)
2341 * This register is the same on all known PCH chips.
2343 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2344 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2345 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2346 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2347 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2348 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2351 static void ibx_irq_postinstall(struct drm_device
*dev
)
2353 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2356 if (HAS_PCH_NOP(dev
))
2359 if (HAS_PCH_IBX(dev
)) {
2360 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2361 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2363 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2365 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2368 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2369 I915_WRITE(SDEIMR
, ~mask
);
2372 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2375 u32 pm_irqs
, gt_irqs
;
2377 pm_irqs
= gt_irqs
= 0;
2379 dev_priv
->gt_irq_mask
= ~0;
2380 if (HAS_L3_DPF(dev
)) {
2381 /* L3 parity interrupt is always unmasked. */
2382 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2383 gt_irqs
|= GT_PARITY_ERROR(dev
);
2386 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2388 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2389 ILK_BSD_USER_INTERRUPT
;
2391 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2394 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2395 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2396 I915_WRITE(GTIER
, gt_irqs
);
2397 POSTING_READ(GTIER
);
2399 if (INTEL_INFO(dev
)->gen
>= 6) {
2400 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2403 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2405 dev_priv
->pm_irq_mask
= 0xffffffff;
2406 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2407 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2408 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2409 POSTING_READ(GEN6_PMIER
);
2413 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2415 unsigned long irqflags
;
2416 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2417 u32 display_mask
, extra_mask
;
2419 if (INTEL_INFO(dev
)->gen
>= 7) {
2420 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2421 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2422 DE_PLANEB_FLIP_DONE_IVB
|
2423 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2425 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2426 DE_PIPEA_VBLANK_IVB
);
2428 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2430 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2431 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2432 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2433 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2434 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2437 dev_priv
->irq_mask
= ~display_mask
;
2439 /* should always can generate irq */
2440 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2441 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2442 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2443 POSTING_READ(DEIER
);
2445 gen5_gt_irq_postinstall(dev
);
2447 ibx_irq_postinstall(dev
);
2449 if (IS_IRONLAKE_M(dev
)) {
2450 /* Enable PCU event interrupts
2452 * spinlocking not required here for correctness since interrupt
2453 * setup is guaranteed to run in single-threaded context. But we
2454 * need it to make the assert_spin_locked happy. */
2455 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2456 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2457 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2463 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2465 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2467 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2468 unsigned long irqflags
;
2470 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2471 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2472 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2473 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2474 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2477 *Leave vblank interrupts masked initially. enable/disable will
2478 * toggle them based on usage.
2480 dev_priv
->irq_mask
= (~enable_mask
) |
2481 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2482 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2484 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2485 POSTING_READ(PORT_HOTPLUG_EN
);
2487 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2488 I915_WRITE(VLV_IER
, enable_mask
);
2489 I915_WRITE(VLV_IIR
, 0xffffffff);
2490 I915_WRITE(PIPESTAT(0), 0xffff);
2491 I915_WRITE(PIPESTAT(1), 0xffff);
2492 POSTING_READ(VLV_IER
);
2494 /* Interrupt setup is already guaranteed to be single-threaded, this is
2495 * just to make the assert_spin_locked check happy. */
2496 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2497 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2498 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2499 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2500 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2502 I915_WRITE(VLV_IIR
, 0xffffffff);
2503 I915_WRITE(VLV_IIR
, 0xffffffff);
2505 gen5_gt_irq_postinstall(dev
);
2507 /* ack & enable invalid PTE error interrupts */
2508 #if 0 /* FIXME: add support to irq handler for checking these bits */
2509 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2510 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2513 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2518 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2520 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2526 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2529 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2531 I915_WRITE(HWSTAM
, 0xffffffff);
2532 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2533 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2535 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2536 I915_WRITE(VLV_IIR
, 0xffffffff);
2537 I915_WRITE(VLV_IMR
, 0xffffffff);
2538 I915_WRITE(VLV_IER
, 0x0);
2539 POSTING_READ(VLV_IER
);
2542 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2544 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2549 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2551 I915_WRITE(HWSTAM
, 0xffffffff);
2553 I915_WRITE(DEIMR
, 0xffffffff);
2554 I915_WRITE(DEIER
, 0x0);
2555 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2557 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2559 I915_WRITE(GTIMR
, 0xffffffff);
2560 I915_WRITE(GTIER
, 0x0);
2561 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2563 if (HAS_PCH_NOP(dev
))
2566 I915_WRITE(SDEIMR
, 0xffffffff);
2567 I915_WRITE(SDEIER
, 0x0);
2568 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2569 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2570 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2573 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2575 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2578 atomic_set(&dev_priv
->irq_received
, 0);
2581 I915_WRITE(PIPESTAT(pipe
), 0);
2582 I915_WRITE16(IMR
, 0xffff);
2583 I915_WRITE16(IER
, 0x0);
2584 POSTING_READ16(IER
);
2587 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2589 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2592 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2594 /* Unmask the interrupts that we always want on. */
2595 dev_priv
->irq_mask
=
2596 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2597 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2598 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2599 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2600 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2601 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2604 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2605 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2606 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2607 I915_USER_INTERRUPT
);
2608 POSTING_READ16(IER
);
2614 * Returns true when a page flip has completed.
2616 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2619 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2620 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2622 if (!drm_handle_vblank(dev
, pipe
))
2625 if ((iir
& flip_pending
) == 0)
2628 intel_prepare_page_flip(dev
, pipe
);
2630 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2631 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2632 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2633 * the flip is completed (no longer pending). Since this doesn't raise
2634 * an interrupt per se, we watch for the change at vblank.
2636 if (I915_READ16(ISR
) & flip_pending
)
2639 intel_finish_page_flip(dev
, pipe
);
2644 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2646 struct drm_device
*dev
= (struct drm_device
*) arg
;
2647 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2650 unsigned long irqflags
;
2653 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2654 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2656 atomic_inc(&dev_priv
->irq_received
);
2658 iir
= I915_READ16(IIR
);
2662 while (iir
& ~flip_mask
) {
2663 /* Can't rely on pipestat interrupt bit in iir as it might
2664 * have been cleared after the pipestat interrupt was received.
2665 * It doesn't set the bit in iir again, but it still produces
2666 * interrupts (for non-MSI).
2668 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2669 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2670 i915_handle_error(dev
, false);
2672 for_each_pipe(pipe
) {
2673 int reg
= PIPESTAT(pipe
);
2674 pipe_stats
[pipe
] = I915_READ(reg
);
2677 * Clear the PIPE*STAT regs before the IIR
2679 if (pipe_stats
[pipe
] & 0x8000ffff) {
2680 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2681 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2683 I915_WRITE(reg
, pipe_stats
[pipe
]);
2686 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2688 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2689 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2691 i915_update_dri1_breadcrumb(dev
);
2693 if (iir
& I915_USER_INTERRUPT
)
2694 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2696 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2697 i8xx_handle_vblank(dev
, 0, iir
))
2698 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2700 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2701 i8xx_handle_vblank(dev
, 1, iir
))
2702 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2710 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2712 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2715 for_each_pipe(pipe
) {
2716 /* Clear enable bits; then clear status bits */
2717 I915_WRITE(PIPESTAT(pipe
), 0);
2718 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2720 I915_WRITE16(IMR
, 0xffff);
2721 I915_WRITE16(IER
, 0x0);
2722 I915_WRITE16(IIR
, I915_READ16(IIR
));
2725 static void i915_irq_preinstall(struct drm_device
* dev
)
2727 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2730 atomic_set(&dev_priv
->irq_received
, 0);
2732 if (I915_HAS_HOTPLUG(dev
)) {
2733 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2734 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2737 I915_WRITE16(HWSTAM
, 0xeffe);
2739 I915_WRITE(PIPESTAT(pipe
), 0);
2740 I915_WRITE(IMR
, 0xffffffff);
2741 I915_WRITE(IER
, 0x0);
2745 static int i915_irq_postinstall(struct drm_device
*dev
)
2747 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2750 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2752 /* Unmask the interrupts that we always want on. */
2753 dev_priv
->irq_mask
=
2754 ~(I915_ASLE_INTERRUPT
|
2755 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2756 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2757 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2758 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2759 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2762 I915_ASLE_INTERRUPT
|
2763 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2764 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2765 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2766 I915_USER_INTERRUPT
;
2768 if (I915_HAS_HOTPLUG(dev
)) {
2769 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2770 POSTING_READ(PORT_HOTPLUG_EN
);
2772 /* Enable in IER... */
2773 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2774 /* and unmask in IMR */
2775 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2778 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2779 I915_WRITE(IER
, enable_mask
);
2782 i915_enable_asle_pipestat(dev
);
2788 * Returns true when a page flip has completed.
2790 static bool i915_handle_vblank(struct drm_device
*dev
,
2791 int plane
, int pipe
, u32 iir
)
2793 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2794 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2796 if (!drm_handle_vblank(dev
, pipe
))
2799 if ((iir
& flip_pending
) == 0)
2802 intel_prepare_page_flip(dev
, plane
);
2804 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2805 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2806 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2807 * the flip is completed (no longer pending). Since this doesn't raise
2808 * an interrupt per se, we watch for the change at vblank.
2810 if (I915_READ(ISR
) & flip_pending
)
2813 intel_finish_page_flip(dev
, pipe
);
2818 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2820 struct drm_device
*dev
= (struct drm_device
*) arg
;
2821 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2822 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2823 unsigned long irqflags
;
2825 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2826 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2827 int pipe
, ret
= IRQ_NONE
;
2829 atomic_inc(&dev_priv
->irq_received
);
2831 iir
= I915_READ(IIR
);
2833 bool irq_received
= (iir
& ~flip_mask
) != 0;
2834 bool blc_event
= false;
2836 /* Can't rely on pipestat interrupt bit in iir as it might
2837 * have been cleared after the pipestat interrupt was received.
2838 * It doesn't set the bit in iir again, but it still produces
2839 * interrupts (for non-MSI).
2841 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2842 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2843 i915_handle_error(dev
, false);
2845 for_each_pipe(pipe
) {
2846 int reg
= PIPESTAT(pipe
);
2847 pipe_stats
[pipe
] = I915_READ(reg
);
2849 /* Clear the PIPE*STAT regs before the IIR */
2850 if (pipe_stats
[pipe
] & 0x8000ffff) {
2851 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2852 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2854 I915_WRITE(reg
, pipe_stats
[pipe
]);
2855 irq_received
= true;
2858 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2863 /* Consume port. Then clear IIR or we'll miss events */
2864 if ((I915_HAS_HOTPLUG(dev
)) &&
2865 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2866 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2867 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2869 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2872 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2874 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2875 POSTING_READ(PORT_HOTPLUG_STAT
);
2878 I915_WRITE(IIR
, iir
& ~flip_mask
);
2879 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2881 if (iir
& I915_USER_INTERRUPT
)
2882 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2884 for_each_pipe(pipe
) {
2889 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2890 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2891 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2893 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2897 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2898 intel_opregion_asle_intr(dev
);
2900 /* With MSI, interrupts are only generated when iir
2901 * transitions from zero to nonzero. If another bit got
2902 * set while we were handling the existing iir bits, then
2903 * we would never get another interrupt.
2905 * This is fine on non-MSI as well, as if we hit this path
2906 * we avoid exiting the interrupt handler only to generate
2909 * Note that for MSI this could cause a stray interrupt report
2910 * if an interrupt landed in the time between writing IIR and
2911 * the posting read. This should be rare enough to never
2912 * trigger the 99% of 100,000 interrupts test for disabling
2917 } while (iir
& ~flip_mask
);
2919 i915_update_dri1_breadcrumb(dev
);
2924 static void i915_irq_uninstall(struct drm_device
* dev
)
2926 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2929 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2931 if (I915_HAS_HOTPLUG(dev
)) {
2932 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2933 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2936 I915_WRITE16(HWSTAM
, 0xffff);
2937 for_each_pipe(pipe
) {
2938 /* Clear enable bits; then clear status bits */
2939 I915_WRITE(PIPESTAT(pipe
), 0);
2940 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2942 I915_WRITE(IMR
, 0xffffffff);
2943 I915_WRITE(IER
, 0x0);
2945 I915_WRITE(IIR
, I915_READ(IIR
));
2948 static void i965_irq_preinstall(struct drm_device
* dev
)
2950 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2953 atomic_set(&dev_priv
->irq_received
, 0);
2955 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2956 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2958 I915_WRITE(HWSTAM
, 0xeffe);
2960 I915_WRITE(PIPESTAT(pipe
), 0);
2961 I915_WRITE(IMR
, 0xffffffff);
2962 I915_WRITE(IER
, 0x0);
2966 static int i965_irq_postinstall(struct drm_device
*dev
)
2968 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2971 unsigned long irqflags
;
2973 /* Unmask the interrupts that we always want on. */
2974 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2975 I915_DISPLAY_PORT_INTERRUPT
|
2976 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2977 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2978 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2979 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2980 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2982 enable_mask
= ~dev_priv
->irq_mask
;
2983 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2984 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2985 enable_mask
|= I915_USER_INTERRUPT
;
2988 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2990 /* Interrupt setup is already guaranteed to be single-threaded, this is
2991 * just to make the assert_spin_locked check happy. */
2992 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2993 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2994 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2997 * Enable some error detection, note the instruction error mask
2998 * bit is reserved, so we leave it masked.
3001 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3002 GM45_ERROR_MEM_PRIV
|
3003 GM45_ERROR_CP_PRIV
|
3004 I915_ERROR_MEMORY_REFRESH
);
3006 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3007 I915_ERROR_MEMORY_REFRESH
);
3009 I915_WRITE(EMR
, error_mask
);
3011 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3012 I915_WRITE(IER
, enable_mask
);
3015 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3016 POSTING_READ(PORT_HOTPLUG_EN
);
3018 i915_enable_asle_pipestat(dev
);
3023 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3025 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3026 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3027 struct intel_encoder
*intel_encoder
;
3030 assert_spin_locked(&dev_priv
->irq_lock
);
3032 if (I915_HAS_HOTPLUG(dev
)) {
3033 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3034 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3035 /* Note HDMI and DP share hotplug bits */
3036 /* enable bits are the same for all generations */
3037 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3038 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3039 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3040 /* Programming the CRT detection parameters tends
3041 to generate a spurious hotplug event about three
3042 seconds later. So just do it once.
3045 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3046 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3047 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3049 /* Ignore TV since it's buggy */
3050 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3054 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3056 struct drm_device
*dev
= (struct drm_device
*) arg
;
3057 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3059 u32 pipe_stats
[I915_MAX_PIPES
];
3060 unsigned long irqflags
;
3062 int ret
= IRQ_NONE
, pipe
;
3064 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3065 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3067 atomic_inc(&dev_priv
->irq_received
);
3069 iir
= I915_READ(IIR
);
3072 bool blc_event
= false;
3074 irq_received
= (iir
& ~flip_mask
) != 0;
3076 /* Can't rely on pipestat interrupt bit in iir as it might
3077 * have been cleared after the pipestat interrupt was received.
3078 * It doesn't set the bit in iir again, but it still produces
3079 * interrupts (for non-MSI).
3081 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3082 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3083 i915_handle_error(dev
, false);
3085 for_each_pipe(pipe
) {
3086 int reg
= PIPESTAT(pipe
);
3087 pipe_stats
[pipe
] = I915_READ(reg
);
3090 * Clear the PIPE*STAT regs before the IIR
3092 if (pipe_stats
[pipe
] & 0x8000ffff) {
3093 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3094 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3096 I915_WRITE(reg
, pipe_stats
[pipe
]);
3100 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3107 /* Consume port. Then clear IIR or we'll miss events */
3108 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3109 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3110 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3111 HOTPLUG_INT_STATUS_G4X
:
3112 HOTPLUG_INT_STATUS_I915
);
3114 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3117 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3118 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3120 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3121 I915_READ(PORT_HOTPLUG_STAT
);
3124 I915_WRITE(IIR
, iir
& ~flip_mask
);
3125 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3127 if (iir
& I915_USER_INTERRUPT
)
3128 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3129 if (iir
& I915_BSD_USER_INTERRUPT
)
3130 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3132 for_each_pipe(pipe
) {
3133 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3134 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3135 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3137 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3142 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3143 intel_opregion_asle_intr(dev
);
3145 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3146 gmbus_irq_handler(dev
);
3148 /* With MSI, interrupts are only generated when iir
3149 * transitions from zero to nonzero. If another bit got
3150 * set while we were handling the existing iir bits, then
3151 * we would never get another interrupt.
3153 * This is fine on non-MSI as well, as if we hit this path
3154 * we avoid exiting the interrupt handler only to generate
3157 * Note that for MSI this could cause a stray interrupt report
3158 * if an interrupt landed in the time between writing IIR and
3159 * the posting read. This should be rare enough to never
3160 * trigger the 99% of 100,000 interrupts test for disabling
3166 i915_update_dri1_breadcrumb(dev
);
3171 static void i965_irq_uninstall(struct drm_device
* dev
)
3173 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3179 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3181 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3182 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3184 I915_WRITE(HWSTAM
, 0xffffffff);
3186 I915_WRITE(PIPESTAT(pipe
), 0);
3187 I915_WRITE(IMR
, 0xffffffff);
3188 I915_WRITE(IER
, 0x0);
3191 I915_WRITE(PIPESTAT(pipe
),
3192 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3193 I915_WRITE(IIR
, I915_READ(IIR
));
3196 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3198 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3199 struct drm_device
*dev
= dev_priv
->dev
;
3200 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3201 unsigned long irqflags
;
3204 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3205 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3206 struct drm_connector
*connector
;
3208 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3211 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3213 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3214 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3216 if (intel_connector
->encoder
->hpd_pin
== i
) {
3217 if (connector
->polled
!= intel_connector
->polled
)
3218 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3219 drm_get_connector_name(connector
));
3220 connector
->polled
= intel_connector
->polled
;
3221 if (!connector
->polled
)
3222 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3226 if (dev_priv
->display
.hpd_irq_setup
)
3227 dev_priv
->display
.hpd_irq_setup(dev
);
3228 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3231 void intel_irq_init(struct drm_device
*dev
)
3233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3235 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3236 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3237 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3238 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3240 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3241 i915_hangcheck_elapsed
,
3242 (unsigned long) dev
);
3243 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3244 (unsigned long) dev_priv
);
3246 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3248 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3249 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3250 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3252 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3253 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3256 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3257 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3258 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3261 if (IS_VALLEYVIEW(dev
)) {
3262 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3263 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3264 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3265 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3266 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3267 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3268 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3269 } else if (HAS_PCH_SPLIT(dev
)) {
3270 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3271 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3272 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3273 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3274 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3275 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3276 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3278 if (INTEL_INFO(dev
)->gen
== 2) {
3279 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3280 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3281 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3282 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3283 } else if (INTEL_INFO(dev
)->gen
== 3) {
3284 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3285 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3286 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3287 dev
->driver
->irq_handler
= i915_irq_handler
;
3288 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3290 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3291 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3292 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3293 dev
->driver
->irq_handler
= i965_irq_handler
;
3294 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3296 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3297 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3301 void intel_hpd_init(struct drm_device
*dev
)
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3304 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3305 struct drm_connector
*connector
;
3306 unsigned long irqflags
;
3309 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3310 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3311 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3313 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3314 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3315 connector
->polled
= intel_connector
->polled
;
3316 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3317 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3320 /* Interrupt setup is already guaranteed to be single-threaded, this is
3321 * just to make the assert_spin_locked checks happy. */
3322 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3323 if (dev_priv
->display
.hpd_irq_setup
)
3324 dev_priv
->display
.hpd_irq_setup(dev
);
3325 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3328 /* Disable interrupts so we can allow Package C8+. */
3329 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3332 unsigned long irqflags
;
3334 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3336 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3337 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3338 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3339 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3340 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3342 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3343 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3344 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3345 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3347 dev_priv
->pc8
.irqs_disabled
= true;
3349 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3352 /* Restore interrupts so we can recover from Package C8+. */
3353 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3356 unsigned long irqflags
;
3357 uint32_t val
, expected
;
3359 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3361 val
= I915_READ(DEIMR
);
3362 expected
= ~DE_PCH_EVENT_IVB
;
3363 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3365 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3366 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3367 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3370 val
= I915_READ(GTIMR
);
3371 expected
= 0xffffffff;
3372 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3374 val
= I915_READ(GEN6_PMIMR
);
3375 expected
= 0xffffffff;
3376 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3379 dev_priv
->pc8
.irqs_disabled
= false;
3381 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3382 ibx_enable_display_interrupt(dev_priv
,
3383 ~dev_priv
->pc8
.regsave
.sdeimr
&
3384 ~SDE_HOTPLUG_MASK_CPT
);
3385 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3386 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3387 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3389 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);