1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
112 I915_WRITE((reg), 0xffffffff); \
114 I915_WRITE((reg), 0xffffffff); \
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
133 /* For display hotplug interrupt */
135 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
137 assert_spin_locked(&dev_priv
->irq_lock
);
139 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
142 if ((dev_priv
->irq_mask
& mask
) != 0) {
143 dev_priv
->irq_mask
&= ~mask
;
144 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
150 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
152 assert_spin_locked(&dev_priv
->irq_lock
);
154 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
157 if ((dev_priv
->irq_mask
& mask
) != mask
) {
158 dev_priv
->irq_mask
|= mask
;
159 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
170 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
171 uint32_t interrupt_mask
,
172 uint32_t enabled_irq_mask
)
174 assert_spin_locked(&dev_priv
->irq_lock
);
176 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
179 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
180 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
181 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
185 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
187 ilk_update_gt_irq(dev_priv
, mask
, mask
);
190 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
192 ilk_update_gt_irq(dev_priv
, mask
, 0);
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
201 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
202 uint32_t interrupt_mask
,
203 uint32_t enabled_irq_mask
)
207 assert_spin_locked(&dev_priv
->irq_lock
);
209 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
212 new_val
= dev_priv
->pm_irq_mask
;
213 new_val
&= ~interrupt_mask
;
214 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
216 if (new_val
!= dev_priv
->pm_irq_mask
) {
217 dev_priv
->pm_irq_mask
= new_val
;
218 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
219 POSTING_READ(GEN6_PMIMR
);
223 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
225 snb_update_pm_irq(dev_priv
, mask
, mask
);
228 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
230 snb_update_pm_irq(dev_priv
, mask
, 0);
233 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
236 struct intel_crtc
*crtc
;
239 assert_spin_locked(&dev_priv
->irq_lock
);
241 for_each_pipe(pipe
) {
242 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
244 if (crtc
->cpu_fifo_underrun_disabled
)
251 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 struct intel_crtc
*crtc
;
257 assert_spin_locked(&dev_priv
->irq_lock
);
259 for_each_pipe(pipe
) {
260 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
262 if (crtc
->pch_fifo_underrun_disabled
)
269 static void i9xx_clear_fifo_underrun(struct drm_device
*dev
, enum pipe pipe
)
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 u32 reg
= PIPESTAT(pipe
);
273 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
275 assert_spin_locked(&dev_priv
->irq_lock
);
277 I915_WRITE(reg
, pipestat
| PIPE_FIFO_UNDERRUN_STATUS
);
281 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
282 enum pipe pipe
, bool enable
)
284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
285 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
286 DE_PIPEB_FIFO_UNDERRUN
;
289 ironlake_enable_display_irq(dev_priv
, bit
);
291 ironlake_disable_display_irq(dev_priv
, bit
);
294 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
295 enum pipe pipe
, bool enable
)
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
301 if (!ivb_can_enable_err_int(dev
))
304 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
306 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
308 /* Change the state _after_ we've read out the current one. */
309 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
312 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
313 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
319 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum pipe pipe
, bool enable
)
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 assert_spin_locked(&dev_priv
->irq_lock
);
327 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_FIFO_UNDERRUN
;
329 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_FIFO_UNDERRUN
;
330 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
331 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
335 * ibx_display_interrupt_update - update SDEIMR
336 * @dev_priv: driver private
337 * @interrupt_mask: mask of interrupt bits to update
338 * @enabled_irq_mask: mask of interrupt bits to enable
340 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
341 uint32_t interrupt_mask
,
342 uint32_t enabled_irq_mask
)
344 uint32_t sdeimr
= I915_READ(SDEIMR
);
345 sdeimr
&= ~interrupt_mask
;
346 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
348 assert_spin_locked(&dev_priv
->irq_lock
);
350 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
353 I915_WRITE(SDEIMR
, sdeimr
);
354 POSTING_READ(SDEIMR
);
356 #define ibx_enable_display_interrupt(dev_priv, bits) \
357 ibx_display_interrupt_update((dev_priv), (bits), (bits))
358 #define ibx_disable_display_interrupt(dev_priv, bits) \
359 ibx_display_interrupt_update((dev_priv), (bits), 0)
361 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
362 enum transcoder pch_transcoder
,
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
367 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
370 ibx_enable_display_interrupt(dev_priv
, bit
);
372 ibx_disable_display_interrupt(dev_priv
, bit
);
375 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
376 enum transcoder pch_transcoder
,
379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
385 if (!cpt_can_enable_serr_int(dev
))
388 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
390 uint32_t tmp
= I915_READ(SERR_INT
);
391 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
393 /* Change the state _after_ we've read out the current one. */
394 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
397 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
398 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
399 transcoder_name(pch_transcoder
));
405 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
408 * @enable: true if we want to report FIFO underrun errors, false otherwise
410 * This function makes us disable or enable CPU fifo underruns for a specific
411 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
412 * reporting for one pipe may also disable all the other CPU error interruts for
413 * the other pipes, due to the fact that there's just one interrupt mask/enable
414 * bit for all the pipes.
416 * Returns the previous state of underrun reporting.
418 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
419 enum pipe pipe
, bool enable
)
421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
422 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
426 assert_spin_locked(&dev_priv
->irq_lock
);
428 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
433 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
435 if (enable
&& (INTEL_INFO(dev
)->gen
< 5 || IS_VALLEYVIEW(dev
)))
436 i9xx_clear_fifo_underrun(dev
, pipe
);
437 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
438 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
439 else if (IS_GEN7(dev
))
440 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
441 else if (IS_GEN8(dev
))
442 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
448 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
449 enum pipe pipe
, bool enable
)
451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
455 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
456 ret
= __intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, enable
);
457 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
462 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device
*dev
,
465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
466 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
467 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
469 return !intel_crtc
->cpu_fifo_underrun_disabled
;
473 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
476 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 * This function makes us disable or enable PCH fifo underruns for a specific
479 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
480 * underrun reporting for one transcoder may also disable all the other PCH
481 * error interruts for the other transcoders, due to the fact that there's just
482 * one interrupt mask/enable bit for all the transcoders.
484 * Returns the previous state of underrun reporting.
486 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
487 enum transcoder pch_transcoder
,
490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
491 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
497 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
498 * has only one pch transcoder A that all pipes can use. To avoid racy
499 * pch transcoder -> pipe lookups from interrupt code simply store the
500 * underrun statistics in crtc A. Since we never expose this anywhere
501 * nor use it outside of the fifo underrun code here using the "wrong"
502 * crtc on LPT won't cause issues.
505 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
507 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
512 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
514 if (HAS_PCH_IBX(dev
))
515 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
517 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
520 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
526 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
527 u32 enable_mask
, u32 status_mask
)
529 u32 reg
= PIPESTAT(pipe
);
530 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
532 assert_spin_locked(&dev_priv
->irq_lock
);
534 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
535 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe
), enable_mask
, status_mask
))
540 if ((pipestat
& enable_mask
) == enable_mask
)
543 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
545 /* Enable the interrupt, clear any pending status */
546 pipestat
|= enable_mask
| status_mask
;
547 I915_WRITE(reg
, pipestat
);
552 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
553 u32 enable_mask
, u32 status_mask
)
555 u32 reg
= PIPESTAT(pipe
);
556 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
558 assert_spin_locked(&dev_priv
->irq_lock
);
560 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
561 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
562 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
563 pipe_name(pipe
), enable_mask
, status_mask
))
566 if ((pipestat
& enable_mask
) == 0)
569 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
571 pipestat
&= ~enable_mask
;
572 I915_WRITE(reg
, pipestat
);
576 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
578 u32 enable_mask
= status_mask
<< 16;
581 * On pipe A we don't support the PSR interrupt yet, on pipe B the
584 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
587 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
588 SPRITE0_FLIP_DONE_INT_EN_VLV
|
589 SPRITE1_FLIP_DONE_INT_EN_VLV
);
590 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
591 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
592 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
593 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
599 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
604 if (IS_VALLEYVIEW(dev_priv
->dev
))
605 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
608 enable_mask
= status_mask
<< 16;
609 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
613 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
618 if (IS_VALLEYVIEW(dev_priv
->dev
))
619 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
622 enable_mask
= status_mask
<< 16;
623 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
627 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
629 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
632 unsigned long irqflags
;
634 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
637 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
639 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
640 if (INTEL_INFO(dev
)->gen
>= 4)
641 i915_enable_pipestat(dev_priv
, PIPE_A
,
642 PIPE_LEGACY_BLC_EVENT_STATUS
);
644 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
648 * i915_pipe_enabled - check if a pipe is enabled
650 * @pipe: pipe to check
652 * Reading certain registers when the pipe is disabled can hang the chip.
653 * Use this routine to make sure the PLL is running and the pipe is active
654 * before reading such registers if unsure.
657 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
661 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
662 /* Locking is horribly broken here, but whatever. */
663 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
664 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
666 return intel_crtc
->active
;
668 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
672 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
674 /* Gen2 doesn't have a hardware frame counter */
678 /* Called from drm generic code, passed a 'crtc', which
679 * we use as a pipe index
681 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
684 unsigned long high_frame
;
685 unsigned long low_frame
;
686 u32 high1
, high2
, low
, pixel
, vbl_start
;
688 if (!i915_pipe_enabled(dev
, pipe
)) {
689 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
690 "pipe %c\n", pipe_name(pipe
));
694 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
695 struct intel_crtc
*intel_crtc
=
696 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
697 const struct drm_display_mode
*mode
=
698 &intel_crtc
->config
.adjusted_mode
;
700 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
702 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
705 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
706 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
711 high_frame
= PIPEFRAME(pipe
);
712 low_frame
= PIPEFRAMEPIXEL(pipe
);
715 * High & low register fields aren't synchronized, so make sure
716 * we get a low value that's stable across two reads of the high
720 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
721 low
= I915_READ(low_frame
);
722 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
723 } while (high1
!= high2
);
725 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
726 pixel
= low
& PIPE_PIXEL_MASK
;
727 low
>>= PIPE_FRAME_LOW_SHIFT
;
730 * The frame counter increments at beginning of active.
731 * Cook up a vblank counter by also checking the pixel
732 * counter against vblank start.
734 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
737 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
740 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
742 if (!i915_pipe_enabled(dev
, pipe
)) {
743 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
744 "pipe %c\n", pipe_name(pipe
));
748 return I915_READ(reg
);
751 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
752 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
754 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
755 unsigned int flags
, int *vpos
, int *hpos
,
756 ktime_t
*stime
, ktime_t
*etime
)
758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
759 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
761 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
763 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
766 unsigned long irqflags
;
768 if (!intel_crtc
->active
) {
769 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
770 "pipe %c\n", pipe_name(pipe
));
774 htotal
= mode
->crtc_htotal
;
775 hsync_start
= mode
->crtc_hsync_start
;
776 vtotal
= mode
->crtc_vtotal
;
777 vbl_start
= mode
->crtc_vblank_start
;
778 vbl_end
= mode
->crtc_vblank_end
;
780 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
781 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
786 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
789 * Lock uncore.lock, as we will do multiple timing critical raw
790 * register reads, potentially with preemption disabled, so the
791 * following code must not block on uncore.lock.
793 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
795 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
797 /* Get optional system timestamp before query. */
799 *stime
= ktime_get();
801 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
802 /* No obvious pixelcount register. Only query vertical
803 * scanout position from Display scan line register.
806 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
808 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
811 * Scanline counter increments at leading edge of hsync, and
812 * it starts counting from vtotal-1 on the first active line.
813 * That means the scanline counter value is always one less
814 * than what we would expect. Ie. just after start of vblank,
815 * which also occurs at start of hsync (on the last active line),
816 * the scanline counter will read vblank_start-1.
818 position
= (position
+ 1) % vtotal
;
820 /* Have access to pixelcount since start of frame.
821 * We can split this into vertical and horizontal
824 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
826 /* convert to pixel counts */
832 * Start of vblank interrupt is triggered at start of hsync,
833 * just prior to the first active line of vblank. However we
834 * consider lines to start at the leading edge of horizontal
835 * active. So, should we get here before we've crossed into
836 * the horizontal active of the first line in vblank, we would
837 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
838 * always add htotal-hsync_start to the current pixel position.
840 position
= (position
+ htotal
- hsync_start
) % vtotal
;
843 /* Get optional system timestamp after query. */
845 *etime
= ktime_get();
847 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
849 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
851 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
854 * While in vblank, position will be negative
855 * counting up towards 0 at vbl_end. And outside
856 * vblank, position will be positive counting
859 if (position
>= vbl_start
)
862 position
+= vtotal
- vbl_end
;
864 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
868 *vpos
= position
/ htotal
;
869 *hpos
= position
- (*vpos
* htotal
);
874 ret
|= DRM_SCANOUTPOS_INVBL
;
879 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
881 struct timeval
*vblank_time
,
884 struct drm_crtc
*crtc
;
886 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
887 DRM_ERROR("Invalid crtc %d\n", pipe
);
891 /* Get drm_crtc to timestamp: */
892 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
894 DRM_ERROR("Invalid crtc %d\n", pipe
);
898 if (!crtc
->enabled
) {
899 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
903 /* Helper routine in DRM core does all the work: */
904 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
907 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
910 static bool intel_hpd_irq_event(struct drm_device
*dev
,
911 struct drm_connector
*connector
)
913 enum drm_connector_status old_status
;
915 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
916 old_status
= connector
->status
;
918 connector
->status
= connector
->funcs
->detect(connector
, false);
919 if (old_status
== connector
->status
)
922 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
924 drm_get_connector_name(connector
),
925 drm_get_connector_status_name(old_status
),
926 drm_get_connector_status_name(connector
->status
));
932 * Handle hotplug events outside the interrupt handler proper.
934 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
936 static void i915_hotplug_work_func(struct work_struct
*work
)
938 struct drm_i915_private
*dev_priv
=
939 container_of(work
, struct drm_i915_private
, hotplug_work
);
940 struct drm_device
*dev
= dev_priv
->dev
;
941 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
942 struct intel_connector
*intel_connector
;
943 struct intel_encoder
*intel_encoder
;
944 struct drm_connector
*connector
;
945 unsigned long irqflags
;
946 bool hpd_disabled
= false;
947 bool changed
= false;
950 /* HPD irq before everything is fully set up. */
951 if (!dev_priv
->enable_hotplug_processing
)
954 mutex_lock(&mode_config
->mutex
);
955 DRM_DEBUG_KMS("running encoder hotplug functions\n");
957 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
959 hpd_event_bits
= dev_priv
->hpd_event_bits
;
960 dev_priv
->hpd_event_bits
= 0;
961 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
962 intel_connector
= to_intel_connector(connector
);
963 intel_encoder
= intel_connector
->encoder
;
964 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
965 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
966 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
967 DRM_INFO("HPD interrupt storm detected on connector %s: "
968 "switching from hotplug detection to polling\n",
969 drm_get_connector_name(connector
));
970 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
971 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
972 | DRM_CONNECTOR_POLL_DISCONNECT
;
975 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
976 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
977 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
980 /* if there were no outputs to poll, poll was disabled,
981 * therefore make sure it's enabled when disabling HPD on
984 drm_kms_helper_poll_enable(dev
);
985 mod_timer(&dev_priv
->hotplug_reenable_timer
,
986 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
989 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
991 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
992 intel_connector
= to_intel_connector(connector
);
993 intel_encoder
= intel_connector
->encoder
;
994 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
995 if (intel_encoder
->hot_plug
)
996 intel_encoder
->hot_plug(intel_encoder
);
997 if (intel_hpd_irq_event(dev
, connector
))
1001 mutex_unlock(&mode_config
->mutex
);
1004 drm_kms_helper_hotplug_event(dev
);
1007 static void intel_hpd_irq_uninstall(struct drm_i915_private
*dev_priv
)
1009 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
1012 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 u32 busy_up
, busy_down
, max_avg
, min_avg
;
1018 spin_lock(&mchdev_lock
);
1020 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
1022 new_delay
= dev_priv
->ips
.cur_delay
;
1024 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
1025 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
1026 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
1027 max_avg
= I915_READ(RCBMAXAVG
);
1028 min_avg
= I915_READ(RCBMINAVG
);
1030 /* Handle RCS change request from hw */
1031 if (busy_up
> max_avg
) {
1032 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
1033 new_delay
= dev_priv
->ips
.cur_delay
- 1;
1034 if (new_delay
< dev_priv
->ips
.max_delay
)
1035 new_delay
= dev_priv
->ips
.max_delay
;
1036 } else if (busy_down
< min_avg
) {
1037 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
1038 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
1039 if (new_delay
> dev_priv
->ips
.min_delay
)
1040 new_delay
= dev_priv
->ips
.min_delay
;
1043 if (ironlake_set_drps(dev
, new_delay
))
1044 dev_priv
->ips
.cur_delay
= new_delay
;
1046 spin_unlock(&mchdev_lock
);
1051 static void notify_ring(struct drm_device
*dev
,
1052 struct intel_ring_buffer
*ring
)
1054 if (ring
->obj
== NULL
)
1057 trace_i915_gem_request_complete(ring
);
1059 wake_up_all(&ring
->irq_queue
);
1060 i915_queue_hangcheck(dev
);
1063 static void gen6_pm_rps_work(struct work_struct
*work
)
1065 struct drm_i915_private
*dev_priv
=
1066 container_of(work
, struct drm_i915_private
, rps
.work
);
1070 spin_lock_irq(&dev_priv
->irq_lock
);
1071 pm_iir
= dev_priv
->rps
.pm_iir
;
1072 dev_priv
->rps
.pm_iir
= 0;
1073 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1074 snb_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1075 spin_unlock_irq(&dev_priv
->irq_lock
);
1077 /* Make sure we didn't queue anything we're not going to process. */
1078 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1080 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1083 mutex_lock(&dev_priv
->rps
.hw_lock
);
1085 adj
= dev_priv
->rps
.last_adj
;
1086 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1091 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1094 * For better performance, jump directly
1095 * to RPe if we're below it.
1097 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1098 new_delay
= dev_priv
->rps
.efficient_freq
;
1099 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1100 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1101 new_delay
= dev_priv
->rps
.efficient_freq
;
1103 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1105 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1110 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1111 } else { /* unknown event */
1112 new_delay
= dev_priv
->rps
.cur_freq
;
1115 /* sysfs frequency interfaces may have snuck in while servicing the
1118 new_delay
= clamp_t(int, new_delay
,
1119 dev_priv
->rps
.min_freq_softlimit
,
1120 dev_priv
->rps
.max_freq_softlimit
);
1122 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1124 if (IS_VALLEYVIEW(dev_priv
->dev
))
1125 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1127 gen6_set_rps(dev_priv
->dev
, new_delay
);
1129 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1134 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1136 * @work: workqueue struct
1138 * Doesn't actually do anything except notify userspace. As a consequence of
1139 * this event, userspace should try to remap the bad rows since statistically
1140 * it is likely the same row is more likely to go bad again.
1142 static void ivybridge_parity_work(struct work_struct
*work
)
1144 struct drm_i915_private
*dev_priv
=
1145 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1146 u32 error_status
, row
, bank
, subbank
;
1147 char *parity_event
[6];
1149 unsigned long flags
;
1152 /* We must turn off DOP level clock gating to access the L3 registers.
1153 * In order to prevent a get/put style interface, acquire struct mutex
1154 * any time we access those registers.
1156 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1158 /* If we've screwed up tracking, just let the interrupt fire again */
1159 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1162 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1163 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1164 POSTING_READ(GEN7_MISCCPCTL
);
1166 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1170 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1173 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1175 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1177 error_status
= I915_READ(reg
);
1178 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1179 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1180 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1182 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1185 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1186 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1187 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1188 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1189 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1190 parity_event
[5] = NULL
;
1192 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1193 KOBJ_CHANGE
, parity_event
);
1195 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1196 slice
, row
, bank
, subbank
);
1198 kfree(parity_event
[4]);
1199 kfree(parity_event
[3]);
1200 kfree(parity_event
[2]);
1201 kfree(parity_event
[1]);
1204 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1207 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1208 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1209 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1210 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1212 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1215 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1219 if (!HAS_L3_DPF(dev
))
1222 spin_lock(&dev_priv
->irq_lock
);
1223 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1224 spin_unlock(&dev_priv
->irq_lock
);
1226 iir
&= GT_PARITY_ERROR(dev
);
1227 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1228 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1230 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1231 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1233 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1236 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1237 struct drm_i915_private
*dev_priv
,
1241 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1242 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1243 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1244 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1247 static void snb_gt_irq_handler(struct drm_device
*dev
,
1248 struct drm_i915_private
*dev_priv
,
1253 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1254 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1255 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1256 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1257 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1258 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1260 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1261 GT_BSD_CS_ERROR_INTERRUPT
|
1262 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1263 i915_handle_error(dev
, false, "GT error interrupt 0x%08x",
1267 if (gt_iir
& GT_PARITY_ERROR(dev
))
1268 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1271 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1272 struct drm_i915_private
*dev_priv
,
1277 irqreturn_t ret
= IRQ_NONE
;
1279 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1280 tmp
= I915_READ(GEN8_GT_IIR(0));
1283 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1284 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1285 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1286 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1287 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1288 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1289 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1291 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1294 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1295 tmp
= I915_READ(GEN8_GT_IIR(1));
1298 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1299 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1300 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1301 vcs
= tmp
>> GEN8_VCS2_IRQ_SHIFT
;
1302 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1303 notify_ring(dev
, &dev_priv
->ring
[VCS2
]);
1304 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1306 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1309 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1310 tmp
= I915_READ(GEN8_GT_IIR(3));
1313 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1314 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1315 notify_ring(dev
, &dev_priv
->ring
[VECS
]);
1316 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1318 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1324 #define HPD_STORM_DETECT_PERIOD 1000
1325 #define HPD_STORM_THRESHOLD 5
1327 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1328 u32 hotplug_trigger
,
1331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1333 bool storm_detected
= false;
1335 if (!hotplug_trigger
)
1338 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1341 spin_lock(&dev_priv
->irq_lock
);
1342 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1344 if (hpd
[i
] & hotplug_trigger
&&
1345 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
) {
1347 * On GMCH platforms the interrupt mask bits only
1348 * prevent irq generation, not the setting of the
1349 * hotplug bits itself. So only WARN about unexpected
1350 * interrupts on saner platforms.
1352 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1353 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1354 hotplug_trigger
, i
, hpd
[i
]);
1359 if (!(hpd
[i
] & hotplug_trigger
) ||
1360 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1363 dev_priv
->hpd_event_bits
|= (1 << i
);
1364 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1365 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1366 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1367 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1368 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1369 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1370 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1371 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1372 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1373 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1374 storm_detected
= true;
1376 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1377 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1378 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1383 dev_priv
->display
.hpd_irq_setup(dev
);
1384 spin_unlock(&dev_priv
->irq_lock
);
1387 * Our hotplug handler can grab modeset locks (by calling down into the
1388 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1389 * queue for otherwise the flush_work in the pageflip code will
1392 schedule_work(&dev_priv
->hotplug_work
);
1395 static void gmbus_irq_handler(struct drm_device
*dev
)
1397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1399 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1402 static void dp_aux_irq_handler(struct drm_device
*dev
)
1404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1409 #if defined(CONFIG_DEBUG_FS)
1410 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1411 uint32_t crc0
, uint32_t crc1
,
1412 uint32_t crc2
, uint32_t crc3
,
1415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1416 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1417 struct intel_pipe_crc_entry
*entry
;
1420 spin_lock(&pipe_crc
->lock
);
1422 if (!pipe_crc
->entries
) {
1423 spin_unlock(&pipe_crc
->lock
);
1424 DRM_ERROR("spurious interrupt\n");
1428 head
= pipe_crc
->head
;
1429 tail
= pipe_crc
->tail
;
1431 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1432 spin_unlock(&pipe_crc
->lock
);
1433 DRM_ERROR("CRC buffer overflowing\n");
1437 entry
= &pipe_crc
->entries
[head
];
1439 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1440 entry
->crc
[0] = crc0
;
1441 entry
->crc
[1] = crc1
;
1442 entry
->crc
[2] = crc2
;
1443 entry
->crc
[3] = crc3
;
1444 entry
->crc
[4] = crc4
;
1446 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1447 pipe_crc
->head
= head
;
1449 spin_unlock(&pipe_crc
->lock
);
1451 wake_up_interruptible(&pipe_crc
->wq
);
1455 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1456 uint32_t crc0
, uint32_t crc1
,
1457 uint32_t crc2
, uint32_t crc3
,
1462 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1466 display_pipe_crc_irq_handler(dev
, pipe
,
1467 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1471 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1475 display_pipe_crc_irq_handler(dev
, pipe
,
1476 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1477 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1478 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1479 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1480 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1483 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 uint32_t res1
, res2
;
1488 if (INTEL_INFO(dev
)->gen
>= 3)
1489 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1493 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1494 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1498 display_pipe_crc_irq_handler(dev
, pipe
,
1499 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1500 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1501 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1505 /* The RPS events need forcewake, so we add them to a work queue and mask their
1506 * IMR bits until the work is done. Other interrupts can be processed without
1507 * the work queue. */
1508 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1510 if (pm_iir
& dev_priv
->pm_rps_events
) {
1511 spin_lock(&dev_priv
->irq_lock
);
1512 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1513 snb_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1514 spin_unlock(&dev_priv
->irq_lock
);
1516 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1519 if (HAS_VEBOX(dev_priv
->dev
)) {
1520 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1521 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1523 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1524 i915_handle_error(dev_priv
->dev
, false,
1525 "VEBOX CS error interrupt 0x%08x",
1531 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1534 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1537 spin_lock(&dev_priv
->irq_lock
);
1538 for_each_pipe(pipe
) {
1540 u32 mask
, iir_bit
= 0;
1543 * PIPESTAT bits get signalled even when the interrupt is
1544 * disabled with the mask bits, and some of the status bits do
1545 * not generate interrupts at all (like the underrun bit). Hence
1546 * we need to be careful that we only handle what we want to
1550 if (__cpu_fifo_underrun_reporting_enabled(dev
, pipe
))
1551 mask
|= PIPE_FIFO_UNDERRUN_STATUS
;
1555 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1558 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1562 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1567 reg
= PIPESTAT(pipe
);
1568 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1569 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1572 * Clear the PIPE*STAT regs before the IIR
1574 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1575 PIPESTAT_INT_STATUS_MASK
))
1576 I915_WRITE(reg
, pipe_stats
[pipe
]);
1578 spin_unlock(&dev_priv
->irq_lock
);
1580 for_each_pipe(pipe
) {
1581 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
)
1582 drm_handle_vblank(dev
, pipe
);
1584 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1585 intel_prepare_page_flip(dev
, pipe
);
1586 intel_finish_page_flip(dev
, pipe
);
1589 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1590 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1592 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
1593 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1594 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
1597 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1598 gmbus_irq_handler(dev
);
1601 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1604 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1607 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1609 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_g4x
);
1611 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1613 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1616 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1617 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1618 dp_aux_irq_handler(dev
);
1620 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1622 * Make sure hotplug status is cleared before we clear IIR, or else we
1623 * may miss hotplug events.
1625 POSTING_READ(PORT_HOTPLUG_STAT
);
1628 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1630 struct drm_device
*dev
= (struct drm_device
*) arg
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 u32 iir
, gt_iir
, pm_iir
;
1633 irqreturn_t ret
= IRQ_NONE
;
1636 iir
= I915_READ(VLV_IIR
);
1637 gt_iir
= I915_READ(GTIIR
);
1638 pm_iir
= I915_READ(GEN6_PMIIR
);
1640 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1645 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1647 valleyview_pipestat_irq_handler(dev
, iir
);
1649 /* Consume port. Then clear IIR or we'll miss events */
1650 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1651 i9xx_hpd_irq_handler(dev
);
1654 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1656 I915_WRITE(GTIIR
, gt_iir
);
1657 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1658 I915_WRITE(VLV_IIR
, iir
);
1665 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1669 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1671 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1673 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1674 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1675 SDE_AUDIO_POWER_SHIFT
);
1676 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1680 if (pch_iir
& SDE_AUX_MASK
)
1681 dp_aux_irq_handler(dev
);
1683 if (pch_iir
& SDE_GMBUS
)
1684 gmbus_irq_handler(dev
);
1686 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1687 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1689 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1690 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1692 if (pch_iir
& SDE_POISON
)
1693 DRM_ERROR("PCH poison interrupt\n");
1695 if (pch_iir
& SDE_FDI_MASK
)
1697 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1699 I915_READ(FDI_RX_IIR(pipe
)));
1701 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1702 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1704 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1705 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1707 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1708 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1710 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1712 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1713 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1715 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1718 static void ivb_err_int_handler(struct drm_device
*dev
)
1720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1721 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1724 if (err_int
& ERR_INT_POISON
)
1725 DRM_ERROR("Poison interrupt\n");
1727 for_each_pipe(pipe
) {
1728 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) {
1729 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1731 DRM_ERROR("Pipe %c FIFO underrun\n",
1735 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1736 if (IS_IVYBRIDGE(dev
))
1737 ivb_pipe_crc_irq_handler(dev
, pipe
);
1739 hsw_pipe_crc_irq_handler(dev
, pipe
);
1743 I915_WRITE(GEN7_ERR_INT
, err_int
);
1746 static void cpt_serr_int_handler(struct drm_device
*dev
)
1748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1749 u32 serr_int
= I915_READ(SERR_INT
);
1751 if (serr_int
& SERR_INT_POISON
)
1752 DRM_ERROR("PCH poison interrupt\n");
1754 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1755 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1757 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1759 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1760 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1762 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1764 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1765 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1767 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1769 I915_WRITE(SERR_INT
, serr_int
);
1772 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1776 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1778 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1780 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1781 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1782 SDE_AUDIO_POWER_SHIFT_CPT
);
1783 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1787 if (pch_iir
& SDE_AUX_MASK_CPT
)
1788 dp_aux_irq_handler(dev
);
1790 if (pch_iir
& SDE_GMBUS_CPT
)
1791 gmbus_irq_handler(dev
);
1793 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1794 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1796 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1797 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1799 if (pch_iir
& SDE_FDI_MASK_CPT
)
1801 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1803 I915_READ(FDI_RX_IIR(pipe
)));
1805 if (pch_iir
& SDE_ERROR_CPT
)
1806 cpt_serr_int_handler(dev
);
1809 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1814 if (de_iir
& DE_AUX_CHANNEL_A
)
1815 dp_aux_irq_handler(dev
);
1817 if (de_iir
& DE_GSE
)
1818 intel_opregion_asle_intr(dev
);
1820 if (de_iir
& DE_POISON
)
1821 DRM_ERROR("Poison interrupt\n");
1823 for_each_pipe(pipe
) {
1824 if (de_iir
& DE_PIPE_VBLANK(pipe
))
1825 drm_handle_vblank(dev
, pipe
);
1827 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
1828 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1829 DRM_ERROR("Pipe %c FIFO underrun\n",
1832 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
1833 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1835 /* plane/pipes map 1:1 on ilk+ */
1836 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
1837 intel_prepare_page_flip(dev
, pipe
);
1838 intel_finish_page_flip_plane(dev
, pipe
);
1842 /* check event from PCH */
1843 if (de_iir
& DE_PCH_EVENT
) {
1844 u32 pch_iir
= I915_READ(SDEIIR
);
1846 if (HAS_PCH_CPT(dev
))
1847 cpt_irq_handler(dev
, pch_iir
);
1849 ibx_irq_handler(dev
, pch_iir
);
1851 /* should clear PCH hotplug event before clear CPU irq */
1852 I915_WRITE(SDEIIR
, pch_iir
);
1855 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1856 ironlake_rps_change_irq_handler(dev
);
1859 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 if (de_iir
& DE_ERR_INT_IVB
)
1865 ivb_err_int_handler(dev
);
1867 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1868 dp_aux_irq_handler(dev
);
1870 if (de_iir
& DE_GSE_IVB
)
1871 intel_opregion_asle_intr(dev
);
1873 for_each_pipe(pipe
) {
1874 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)))
1875 drm_handle_vblank(dev
, pipe
);
1877 /* plane/pipes map 1:1 on ilk+ */
1878 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
1879 intel_prepare_page_flip(dev
, pipe
);
1880 intel_finish_page_flip_plane(dev
, pipe
);
1884 /* check event from PCH */
1885 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1886 u32 pch_iir
= I915_READ(SDEIIR
);
1888 cpt_irq_handler(dev
, pch_iir
);
1890 /* clear PCH hotplug event before clear CPU irq */
1891 I915_WRITE(SDEIIR
, pch_iir
);
1895 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1897 struct drm_device
*dev
= (struct drm_device
*) arg
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1900 irqreturn_t ret
= IRQ_NONE
;
1902 /* We get interrupts on unclaimed registers, so check for this before we
1903 * do any I915_{READ,WRITE}. */
1904 intel_uncore_check_errors(dev
);
1906 /* disable master interrupt before clearing iir */
1907 de_ier
= I915_READ(DEIER
);
1908 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1909 POSTING_READ(DEIER
);
1911 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1912 * interrupts will will be stored on its back queue, and then we'll be
1913 * able to process them after we restore SDEIER (as soon as we restore
1914 * it, we'll get an interrupt if SDEIIR still has something to process
1915 * due to its back queue). */
1916 if (!HAS_PCH_NOP(dev
)) {
1917 sde_ier
= I915_READ(SDEIER
);
1918 I915_WRITE(SDEIER
, 0);
1919 POSTING_READ(SDEIER
);
1922 gt_iir
= I915_READ(GTIIR
);
1924 if (INTEL_INFO(dev
)->gen
>= 6)
1925 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1927 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1928 I915_WRITE(GTIIR
, gt_iir
);
1932 de_iir
= I915_READ(DEIIR
);
1934 if (INTEL_INFO(dev
)->gen
>= 7)
1935 ivb_display_irq_handler(dev
, de_iir
);
1937 ilk_display_irq_handler(dev
, de_iir
);
1938 I915_WRITE(DEIIR
, de_iir
);
1942 if (INTEL_INFO(dev
)->gen
>= 6) {
1943 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1945 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1946 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1951 I915_WRITE(DEIER
, de_ier
);
1952 POSTING_READ(DEIER
);
1953 if (!HAS_PCH_NOP(dev
)) {
1954 I915_WRITE(SDEIER
, sde_ier
);
1955 POSTING_READ(SDEIER
);
1961 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
1963 struct drm_device
*dev
= arg
;
1964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 irqreturn_t ret
= IRQ_NONE
;
1970 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
1971 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
1975 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1976 POSTING_READ(GEN8_MASTER_IRQ
);
1978 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1980 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
1981 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
1982 if (tmp
& GEN8_DE_MISC_GSE
)
1983 intel_opregion_asle_intr(dev
);
1985 DRM_ERROR("Unexpected DE Misc interrupt\n");
1987 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1990 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
1995 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
1996 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
1997 if (tmp
& GEN8_AUX_CHANNEL_A
)
1998 dp_aux_irq_handler(dev
);
2000 DRM_ERROR("Unexpected DE Port interrupt\n");
2002 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2005 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2010 for_each_pipe(pipe
) {
2013 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2016 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2017 if (pipe_iir
& GEN8_PIPE_VBLANK
)
2018 drm_handle_vblank(dev
, pipe
);
2020 if (pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
) {
2021 intel_prepare_page_flip(dev
, pipe
);
2022 intel_finish_page_flip_plane(dev
, pipe
);
2025 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2026 hsw_pipe_crc_irq_handler(dev
, pipe
);
2028 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
) {
2029 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
2031 DRM_ERROR("Pipe %c FIFO underrun\n",
2035 if (pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
) {
2036 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2038 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2043 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2045 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2048 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2050 * FIXME(BDW): Assume for now that the new interrupt handling
2051 * scheme also closed the SDE interrupt handling race we've seen
2052 * on older pch-split platforms. But this needs testing.
2054 u32 pch_iir
= I915_READ(SDEIIR
);
2056 cpt_irq_handler(dev
, pch_iir
);
2059 I915_WRITE(SDEIIR
, pch_iir
);
2064 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2065 POSTING_READ(GEN8_MASTER_IRQ
);
2070 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2071 bool reset_completed
)
2073 struct intel_ring_buffer
*ring
;
2077 * Notify all waiters for GPU completion events that reset state has
2078 * been changed, and that they need to restart their wait after
2079 * checking for potential errors (and bail out to drop locks if there is
2080 * a gpu reset pending so that i915_error_work_func can acquire them).
2083 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2084 for_each_ring(ring
, dev_priv
, i
)
2085 wake_up_all(&ring
->irq_queue
);
2087 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2088 wake_up_all(&dev_priv
->pending_flip_queue
);
2091 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2092 * reset state is cleared.
2094 if (reset_completed
)
2095 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2099 * i915_error_work_func - do process context error handling work
2100 * @work: work struct
2102 * Fire an error uevent so userspace can see that a hang or error
2105 static void i915_error_work_func(struct work_struct
*work
)
2107 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2109 struct drm_i915_private
*dev_priv
=
2110 container_of(error
, struct drm_i915_private
, gpu_error
);
2111 struct drm_device
*dev
= dev_priv
->dev
;
2112 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2113 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2114 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2117 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2120 * Note that there's only one work item which does gpu resets, so we
2121 * need not worry about concurrent gpu resets potentially incrementing
2122 * error->reset_counter twice. We only need to take care of another
2123 * racing irq/hangcheck declaring the gpu dead for a second time. A
2124 * quick check for that is good enough: schedule_work ensures the
2125 * correct ordering between hang detection and this work item, and since
2126 * the reset in-progress bit is only ever set by code outside of this
2127 * work we don't need to worry about any other races.
2129 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2130 DRM_DEBUG_DRIVER("resetting chip\n");
2131 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2135 * In most cases it's guaranteed that we get here with an RPM
2136 * reference held, for example because there is a pending GPU
2137 * request that won't finish until the reset is done. This
2138 * isn't the case at least when we get here by doing a
2139 * simulated reset via debugs, so get an RPM reference.
2141 intel_runtime_pm_get(dev_priv
);
2143 * All state reset _must_ be completed before we update the
2144 * reset counter, for otherwise waiters might miss the reset
2145 * pending state and not properly drop locks, resulting in
2146 * deadlocks with the reset work.
2148 ret
= i915_reset(dev
);
2150 intel_display_handle_reset(dev
);
2152 intel_runtime_pm_put(dev_priv
);
2156 * After all the gem state is reset, increment the reset
2157 * counter and wake up everyone waiting for the reset to
2160 * Since unlock operations are a one-sided barrier only,
2161 * we need to insert a barrier here to order any seqno
2163 * the counter increment.
2165 smp_mb__before_atomic_inc();
2166 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2168 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2169 KOBJ_CHANGE
, reset_done_event
);
2171 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2175 * Note: The wake_up also serves as a memory barrier so that
2176 * waiters see the update value of the reset counter atomic_t.
2178 i915_error_wake_up(dev_priv
, true);
2182 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2185 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2186 u32 eir
= I915_READ(EIR
);
2192 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2194 i915_get_extra_instdone(dev
, instdone
);
2197 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2198 u32 ipeir
= I915_READ(IPEIR_I965
);
2200 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2201 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2202 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2203 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2204 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2205 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2206 I915_WRITE(IPEIR_I965
, ipeir
);
2207 POSTING_READ(IPEIR_I965
);
2209 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2210 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2211 pr_err("page table error\n");
2212 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2213 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2214 POSTING_READ(PGTBL_ER
);
2218 if (!IS_GEN2(dev
)) {
2219 if (eir
& I915_ERROR_PAGE_TABLE
) {
2220 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2221 pr_err("page table error\n");
2222 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2223 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2224 POSTING_READ(PGTBL_ER
);
2228 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2229 pr_err("memory refresh error:\n");
2231 pr_err("pipe %c stat: 0x%08x\n",
2232 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2233 /* pipestat has already been acked */
2235 if (eir
& I915_ERROR_INSTRUCTION
) {
2236 pr_err("instruction error\n");
2237 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2238 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2239 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2240 if (INTEL_INFO(dev
)->gen
< 4) {
2241 u32 ipeir
= I915_READ(IPEIR
);
2243 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2244 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2245 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2246 I915_WRITE(IPEIR
, ipeir
);
2247 POSTING_READ(IPEIR
);
2249 u32 ipeir
= I915_READ(IPEIR_I965
);
2251 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2252 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2253 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2254 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2255 I915_WRITE(IPEIR_I965
, ipeir
);
2256 POSTING_READ(IPEIR_I965
);
2260 I915_WRITE(EIR
, eir
);
2262 eir
= I915_READ(EIR
);
2265 * some errors might have become stuck,
2268 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2269 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2270 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2275 * i915_handle_error - handle an error interrupt
2278 * Do some basic checking of regsiter state at error interrupt time and
2279 * dump it to the syslog. Also call i915_capture_error_state() to make
2280 * sure we get a record and make it available in debugfs. Fire a uevent
2281 * so userspace knows something bad happened (should trigger collection
2282 * of a ring dump etc.).
2284 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2285 const char *fmt
, ...)
2287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2291 va_start(args
, fmt
);
2292 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2295 i915_capture_error_state(dev
, wedged
, error_msg
);
2296 i915_report_and_clear_eir(dev
);
2299 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2300 &dev_priv
->gpu_error
.reset_counter
);
2303 * Wakeup waiting processes so that the reset work function
2304 * i915_error_work_func doesn't deadlock trying to grab various
2305 * locks. By bumping the reset counter first, the woken
2306 * processes will see a reset in progress and back off,
2307 * releasing their locks and then wait for the reset completion.
2308 * We must do this for _all_ gpu waiters that might hold locks
2309 * that the reset work needs to acquire.
2311 * Note: The wake_up serves as the required memory barrier to
2312 * ensure that the waiters see the updated value of the reset
2315 i915_error_wake_up(dev_priv
, false);
2319 * Our reset work can grab modeset locks (since it needs to reset the
2320 * state of outstanding pagelips). Hence it must not be run on our own
2321 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2322 * code will deadlock.
2324 schedule_work(&dev_priv
->gpu_error
.work
);
2327 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2330 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2331 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2332 struct drm_i915_gem_object
*obj
;
2333 struct intel_unpin_work
*work
;
2334 unsigned long flags
;
2335 bool stall_detected
;
2337 /* Ignore early vblank irqs */
2338 if (intel_crtc
== NULL
)
2341 spin_lock_irqsave(&dev
->event_lock
, flags
);
2342 work
= intel_crtc
->unpin_work
;
2345 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2346 !work
->enable_stall_check
) {
2347 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2348 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2352 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2353 obj
= work
->pending_flip_obj
;
2354 if (INTEL_INFO(dev
)->gen
>= 4) {
2355 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2356 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2357 i915_gem_obj_ggtt_offset(obj
);
2359 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2360 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2361 crtc
->y
* crtc
->primary
->fb
->pitches
[0] +
2362 crtc
->x
* crtc
->primary
->fb
->bits_per_pixel
/8);
2365 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2367 if (stall_detected
) {
2368 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2369 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2373 /* Called from drm generic code, passed 'crtc' which
2374 * we use as a pipe index
2376 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2379 unsigned long irqflags
;
2381 if (!i915_pipe_enabled(dev
, pipe
))
2384 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2385 if (INTEL_INFO(dev
)->gen
>= 4)
2386 i915_enable_pipestat(dev_priv
, pipe
,
2387 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2389 i915_enable_pipestat(dev_priv
, pipe
,
2390 PIPE_VBLANK_INTERRUPT_STATUS
);
2392 /* maintain vblank delivery even in deep C-states */
2393 if (INTEL_INFO(dev
)->gen
== 3)
2394 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2395 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2400 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2403 unsigned long irqflags
;
2404 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2405 DE_PIPE_VBLANK(pipe
);
2407 if (!i915_pipe_enabled(dev
, pipe
))
2410 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2411 ironlake_enable_display_irq(dev_priv
, bit
);
2412 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2417 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2420 unsigned long irqflags
;
2422 if (!i915_pipe_enabled(dev
, pipe
))
2425 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2426 i915_enable_pipestat(dev_priv
, pipe
,
2427 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2428 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2433 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2436 unsigned long irqflags
;
2438 if (!i915_pipe_enabled(dev
, pipe
))
2441 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2442 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2443 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2444 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2445 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2449 /* Called from drm generic code, passed 'crtc' which
2450 * we use as a pipe index
2452 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2455 unsigned long irqflags
;
2457 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2458 if (INTEL_INFO(dev
)->gen
== 3)
2459 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2461 i915_disable_pipestat(dev_priv
, pipe
,
2462 PIPE_VBLANK_INTERRUPT_STATUS
|
2463 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2464 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2467 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2470 unsigned long irqflags
;
2471 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2472 DE_PIPE_VBLANK(pipe
);
2474 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2475 ironlake_disable_display_irq(dev_priv
, bit
);
2476 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2479 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2482 unsigned long irqflags
;
2484 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2485 i915_disable_pipestat(dev_priv
, pipe
,
2486 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2487 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2490 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2493 unsigned long irqflags
;
2495 if (!i915_pipe_enabled(dev
, pipe
))
2498 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2499 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2500 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2501 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2502 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2506 ring_last_seqno(struct intel_ring_buffer
*ring
)
2508 return list_entry(ring
->request_list
.prev
,
2509 struct drm_i915_gem_request
, list
)->seqno
;
2513 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2515 return (list_empty(&ring
->request_list
) ||
2516 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2520 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2522 if (INTEL_INFO(dev
)->gen
>= 8) {
2524 * FIXME: gen8 semaphore support - currently we don't emit
2525 * semaphores on bdw anyway, but this needs to be addressed when
2526 * we merge that code.
2530 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2531 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2532 MI_SEMAPHORE_REGISTER
);
2536 static struct intel_ring_buffer
*
2537 semaphore_wait_to_signaller_ring(struct intel_ring_buffer
*ring
, u32 ipehr
)
2539 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2540 struct intel_ring_buffer
*signaller
;
2543 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2545 * FIXME: gen8 semaphore support - currently we don't emit
2546 * semaphores on bdw anyway, but this needs to be addressed when
2547 * we merge that code.
2551 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2553 for_each_ring(signaller
, dev_priv
, i
) {
2554 if(ring
== signaller
)
2558 signaller
->semaphore_register
[ring
->id
])
2563 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2569 static struct intel_ring_buffer
*
2570 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2572 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2573 u32 cmd
, ipehr
, head
;
2576 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2577 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2581 * HEAD is likely pointing to the dword after the actual command,
2582 * so scan backwards until we find the MBOX. But limit it to just 3
2583 * dwords. Note that we don't care about ACTHD here since that might
2584 * point at at batch, and semaphores are always emitted into the
2585 * ringbuffer itself.
2587 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2589 for (i
= 4; i
; --i
) {
2591 * Be paranoid and presume the hw has gone off into the wild -
2592 * our ring is smaller than what the hardware (and hence
2593 * HEAD_ADDR) allows. Also handles wrap-around.
2595 head
&= ring
->size
- 1;
2597 /* This here seems to blow up */
2598 cmd
= ioread32(ring
->virtual_start
+ head
);
2608 *seqno
= ioread32(ring
->virtual_start
+ head
+ 4) + 1;
2609 return semaphore_wait_to_signaller_ring(ring
, ipehr
);
2612 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2614 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2615 struct intel_ring_buffer
*signaller
;
2618 ring
->hangcheck
.deadlock
= true;
2620 signaller
= semaphore_waits_for(ring
, &seqno
);
2621 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2624 /* cursory check for an unkickable deadlock */
2625 ctl
= I915_READ_CTL(signaller
);
2626 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2629 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2632 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2634 struct intel_ring_buffer
*ring
;
2637 for_each_ring(ring
, dev_priv
, i
)
2638 ring
->hangcheck
.deadlock
= false;
2641 static enum intel_ring_hangcheck_action
2642 ring_stuck(struct intel_ring_buffer
*ring
, u64 acthd
)
2644 struct drm_device
*dev
= ring
->dev
;
2645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2648 if (ring
->hangcheck
.acthd
!= acthd
)
2649 return HANGCHECK_ACTIVE
;
2652 return HANGCHECK_HUNG
;
2654 /* Is the chip hanging on a WAIT_FOR_EVENT?
2655 * If so we can simply poke the RB_WAIT bit
2656 * and break the hang. This should work on
2657 * all but the second generation chipsets.
2659 tmp
= I915_READ_CTL(ring
);
2660 if (tmp
& RING_WAIT
) {
2661 i915_handle_error(dev
, false,
2662 "Kicking stuck wait on %s",
2664 I915_WRITE_CTL(ring
, tmp
);
2665 return HANGCHECK_KICK
;
2668 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2669 switch (semaphore_passed(ring
)) {
2671 return HANGCHECK_HUNG
;
2673 i915_handle_error(dev
, false,
2674 "Kicking stuck semaphore on %s",
2676 I915_WRITE_CTL(ring
, tmp
);
2677 return HANGCHECK_KICK
;
2679 return HANGCHECK_WAIT
;
2683 return HANGCHECK_HUNG
;
2687 * This is called when the chip hasn't reported back with completed
2688 * batchbuffers in a long time. We keep track per ring seqno progress and
2689 * if there are no progress, hangcheck score for that ring is increased.
2690 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2691 * we kick the ring. If we see no progress on three subsequent calls
2692 * we assume chip is wedged and try to fix it by resetting the chip.
2694 static void i915_hangcheck_elapsed(unsigned long data
)
2696 struct drm_device
*dev
= (struct drm_device
*)data
;
2697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2698 struct intel_ring_buffer
*ring
;
2700 int busy_count
= 0, rings_hung
= 0;
2701 bool stuck
[I915_NUM_RINGS
] = { 0 };
2706 if (!i915
.enable_hangcheck
)
2709 for_each_ring(ring
, dev_priv
, i
) {
2714 semaphore_clear_deadlocks(dev_priv
);
2716 seqno
= ring
->get_seqno(ring
, false);
2717 acthd
= intel_ring_get_active_head(ring
);
2719 if (ring
->hangcheck
.seqno
== seqno
) {
2720 if (ring_idle(ring
, seqno
)) {
2721 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2723 if (waitqueue_active(&ring
->irq_queue
)) {
2724 /* Issue a wake-up to catch stuck h/w. */
2725 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2726 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2727 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2730 DRM_INFO("Fake missed irq on %s\n",
2732 wake_up_all(&ring
->irq_queue
);
2734 /* Safeguard against driver failure */
2735 ring
->hangcheck
.score
+= BUSY
;
2739 /* We always increment the hangcheck score
2740 * if the ring is busy and still processing
2741 * the same request, so that no single request
2742 * can run indefinitely (such as a chain of
2743 * batches). The only time we do not increment
2744 * the hangcheck score on this ring, if this
2745 * ring is in a legitimate wait for another
2746 * ring. In that case the waiting ring is a
2747 * victim and we want to be sure we catch the
2748 * right culprit. Then every time we do kick
2749 * the ring, add a small increment to the
2750 * score so that we can catch a batch that is
2751 * being repeatedly kicked and so responsible
2752 * for stalling the machine.
2754 ring
->hangcheck
.action
= ring_stuck(ring
,
2757 switch (ring
->hangcheck
.action
) {
2758 case HANGCHECK_IDLE
:
2759 case HANGCHECK_WAIT
:
2761 case HANGCHECK_ACTIVE
:
2762 ring
->hangcheck
.score
+= BUSY
;
2764 case HANGCHECK_KICK
:
2765 ring
->hangcheck
.score
+= KICK
;
2767 case HANGCHECK_HUNG
:
2768 ring
->hangcheck
.score
+= HUNG
;
2774 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2776 /* Gradually reduce the count so that we catch DoS
2777 * attempts across multiple batches.
2779 if (ring
->hangcheck
.score
> 0)
2780 ring
->hangcheck
.score
--;
2783 ring
->hangcheck
.seqno
= seqno
;
2784 ring
->hangcheck
.acthd
= acthd
;
2788 for_each_ring(ring
, dev_priv
, i
) {
2789 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
2790 DRM_INFO("%s on %s\n",
2791 stuck
[i
] ? "stuck" : "no progress",
2798 return i915_handle_error(dev
, true, "Ring hung");
2801 /* Reset timer case chip hangs without another request
2803 i915_queue_hangcheck(dev
);
2806 void i915_queue_hangcheck(struct drm_device
*dev
)
2808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2809 if (!i915
.enable_hangcheck
)
2812 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2813 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2816 static void ibx_irq_reset(struct drm_device
*dev
)
2818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 if (HAS_PCH_NOP(dev
))
2823 GEN5_IRQ_RESET(SDE
);
2825 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2826 I915_WRITE(SERR_INT
, 0xffffffff);
2830 * SDEIER is also touched by the interrupt handler to work around missed PCH
2831 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2832 * instead we unconditionally enable all PCH interrupt sources here, but then
2833 * only unmask them as needed with SDEIMR.
2835 * This function needs to be called before interrupts are enabled.
2837 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2841 if (HAS_PCH_NOP(dev
))
2844 WARN_ON(I915_READ(SDEIER
) != 0);
2845 I915_WRITE(SDEIER
, 0xffffffff);
2846 POSTING_READ(SDEIER
);
2849 static void gen5_gt_irq_reset(struct drm_device
*dev
)
2851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2854 if (INTEL_INFO(dev
)->gen
>= 6)
2855 GEN5_IRQ_RESET(GEN6_PM
);
2860 static void ironlake_irq_reset(struct drm_device
*dev
)
2862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2864 I915_WRITE(HWSTAM
, 0xffffffff);
2868 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
2870 gen5_gt_irq_reset(dev
);
2875 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2877 ironlake_irq_reset(dev
);
2880 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 I915_WRITE(VLV_IMR
, 0);
2887 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2888 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2889 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2892 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2893 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2895 gen5_gt_irq_reset(dev
);
2897 I915_WRITE(DPINVGTT
, 0xff);
2899 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2900 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2902 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2903 I915_WRITE(VLV_IIR
, 0xffffffff);
2904 I915_WRITE(VLV_IMR
, 0xffffffff);
2905 I915_WRITE(VLV_IER
, 0x0);
2906 POSTING_READ(VLV_IER
);
2909 static void gen8_irq_reset(struct drm_device
*dev
)
2911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2914 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2915 POSTING_READ(GEN8_MASTER_IRQ
);
2917 GEN8_IRQ_RESET_NDX(GT
, 0);
2918 GEN8_IRQ_RESET_NDX(GT
, 1);
2919 GEN8_IRQ_RESET_NDX(GT
, 2);
2920 GEN8_IRQ_RESET_NDX(GT
, 3);
2923 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
2925 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
2926 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
2927 GEN5_IRQ_RESET(GEN8_PCU_
);
2932 static void gen8_irq_preinstall(struct drm_device
*dev
)
2934 gen8_irq_reset(dev
);
2937 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2940 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2941 struct intel_encoder
*intel_encoder
;
2942 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2944 if (HAS_PCH_IBX(dev
)) {
2945 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2946 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2947 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2948 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2950 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2951 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2952 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2953 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2956 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2959 * Enable digital hotplug on the PCH, and configure the DP short pulse
2960 * duration to 2ms (which is the minimum in the Display Port spec)
2962 * This register is the same on all known PCH chips.
2964 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2965 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2966 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2967 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2968 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2969 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2972 static void ibx_irq_postinstall(struct drm_device
*dev
)
2974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2977 if (HAS_PCH_NOP(dev
))
2980 if (HAS_PCH_IBX(dev
))
2981 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
2983 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
2985 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
2986 I915_WRITE(SDEIMR
, ~mask
);
2989 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2992 u32 pm_irqs
, gt_irqs
;
2994 pm_irqs
= gt_irqs
= 0;
2996 dev_priv
->gt_irq_mask
= ~0;
2997 if (HAS_L3_DPF(dev
)) {
2998 /* L3 parity interrupt is always unmasked. */
2999 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3000 gt_irqs
|= GT_PARITY_ERROR(dev
);
3003 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3005 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3006 ILK_BSD_USER_INTERRUPT
;
3008 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3011 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3013 if (INTEL_INFO(dev
)->gen
>= 6) {
3014 pm_irqs
|= dev_priv
->pm_rps_events
;
3017 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3019 dev_priv
->pm_irq_mask
= 0xffffffff;
3020 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3024 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3026 unsigned long irqflags
;
3027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3028 u32 display_mask
, extra_mask
;
3030 if (INTEL_INFO(dev
)->gen
>= 7) {
3031 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3032 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3033 DE_PLANEB_FLIP_DONE_IVB
|
3034 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3035 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3036 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3038 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3039 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3041 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3043 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3044 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3047 dev_priv
->irq_mask
= ~display_mask
;
3049 I915_WRITE(HWSTAM
, 0xeffe);
3051 ibx_irq_pre_postinstall(dev
);
3053 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3055 gen5_gt_irq_postinstall(dev
);
3057 ibx_irq_postinstall(dev
);
3059 if (IS_IRONLAKE_M(dev
)) {
3060 /* Enable PCU event interrupts
3062 * spinlocking not required here for correctness since interrupt
3063 * setup is guaranteed to run in single-threaded context. But we
3064 * need it to make the assert_spin_locked happy. */
3065 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3066 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3067 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3073 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3078 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3079 PIPE_FIFO_UNDERRUN_STATUS
;
3081 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3082 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3083 POSTING_READ(PIPESTAT(PIPE_A
));
3085 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3086 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3088 i915_enable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3089 PIPE_GMBUS_INTERRUPT_STATUS
);
3090 i915_enable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3092 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3093 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3094 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3095 dev_priv
->irq_mask
&= ~iir_mask
;
3097 I915_WRITE(VLV_IIR
, iir_mask
);
3098 I915_WRITE(VLV_IIR
, iir_mask
);
3099 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3100 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3101 POSTING_READ(VLV_IER
);
3104 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3109 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3110 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3111 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3113 dev_priv
->irq_mask
|= iir_mask
;
3114 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3115 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3116 I915_WRITE(VLV_IIR
, iir_mask
);
3117 I915_WRITE(VLV_IIR
, iir_mask
);
3118 POSTING_READ(VLV_IIR
);
3120 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3121 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3123 i915_disable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3124 PIPE_GMBUS_INTERRUPT_STATUS
);
3125 i915_disable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3127 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3128 PIPE_FIFO_UNDERRUN_STATUS
;
3129 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3130 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3131 POSTING_READ(PIPESTAT(PIPE_A
));
3134 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3136 assert_spin_locked(&dev_priv
->irq_lock
);
3138 if (dev_priv
->display_irqs_enabled
)
3141 dev_priv
->display_irqs_enabled
= true;
3143 if (dev_priv
->dev
->irq_enabled
)
3144 valleyview_display_irqs_install(dev_priv
);
3147 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3149 assert_spin_locked(&dev_priv
->irq_lock
);
3151 if (!dev_priv
->display_irqs_enabled
)
3154 dev_priv
->display_irqs_enabled
= false;
3156 if (dev_priv
->dev
->irq_enabled
)
3157 valleyview_display_irqs_uninstall(dev_priv
);
3160 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3163 unsigned long irqflags
;
3165 dev_priv
->irq_mask
= ~0;
3167 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3168 POSTING_READ(PORT_HOTPLUG_EN
);
3170 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3171 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3172 I915_WRITE(VLV_IIR
, 0xffffffff);
3173 POSTING_READ(VLV_IER
);
3175 /* Interrupt setup is already guaranteed to be single-threaded, this is
3176 * just to make the assert_spin_locked check happy. */
3177 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3178 if (dev_priv
->display_irqs_enabled
)
3179 valleyview_display_irqs_install(dev_priv
);
3180 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3182 I915_WRITE(VLV_IIR
, 0xffffffff);
3183 I915_WRITE(VLV_IIR
, 0xffffffff);
3185 gen5_gt_irq_postinstall(dev
);
3187 /* ack & enable invalid PTE error interrupts */
3188 #if 0 /* FIXME: add support to irq handler for checking these bits */
3189 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3190 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3193 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3198 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3202 /* These are interrupts we'll toggle with the ring mask register */
3203 uint32_t gt_interrupts
[] = {
3204 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3205 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3206 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3207 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3208 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3210 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3213 for (i
= 0; i
< ARRAY_SIZE(gt_interrupts
); i
++)
3214 GEN8_IRQ_INIT_NDX(GT
, i
, ~gt_interrupts
[i
], gt_interrupts
[i
]);
3217 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3219 struct drm_device
*dev
= dev_priv
->dev
;
3220 uint32_t de_pipe_masked
= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3221 GEN8_PIPE_CDCLK_CRC_DONE
|
3222 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3223 uint32_t de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3224 GEN8_PIPE_FIFO_UNDERRUN
;
3226 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3227 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3228 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3231 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
, dev_priv
->de_irq_mask
[pipe
],
3234 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~GEN8_AUX_CHANNEL_A
, GEN8_AUX_CHANNEL_A
);
3237 static int gen8_irq_postinstall(struct drm_device
*dev
)
3239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 ibx_irq_pre_postinstall(dev
);
3243 gen8_gt_irq_postinstall(dev_priv
);
3244 gen8_de_irq_postinstall(dev_priv
);
3246 ibx_irq_postinstall(dev
);
3248 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3249 POSTING_READ(GEN8_MASTER_IRQ
);
3254 static void gen8_irq_uninstall(struct drm_device
*dev
)
3256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3261 intel_hpd_irq_uninstall(dev_priv
);
3263 gen8_irq_reset(dev
);
3266 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3269 unsigned long irqflags
;
3275 I915_WRITE(VLV_MASTER_IER
, 0);
3277 intel_hpd_irq_uninstall(dev_priv
);
3280 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3282 I915_WRITE(HWSTAM
, 0xffffffff);
3283 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3284 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3286 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3287 if (dev_priv
->display_irqs_enabled
)
3288 valleyview_display_irqs_uninstall(dev_priv
);
3289 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3291 dev_priv
->irq_mask
= 0;
3293 I915_WRITE(VLV_IIR
, 0xffffffff);
3294 I915_WRITE(VLV_IMR
, 0xffffffff);
3295 I915_WRITE(VLV_IER
, 0x0);
3296 POSTING_READ(VLV_IER
);
3299 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 intel_hpd_irq_uninstall(dev_priv
);
3308 ironlake_irq_reset(dev
);
3311 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3317 I915_WRITE(PIPESTAT(pipe
), 0);
3318 I915_WRITE16(IMR
, 0xffff);
3319 I915_WRITE16(IER
, 0x0);
3320 POSTING_READ16(IER
);
3323 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3326 unsigned long irqflags
;
3329 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3331 /* Unmask the interrupts that we always want on. */
3332 dev_priv
->irq_mask
=
3333 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3334 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3335 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3336 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3337 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3338 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3341 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3342 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3343 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3344 I915_USER_INTERRUPT
);
3345 POSTING_READ16(IER
);
3347 /* Interrupt setup is already guaranteed to be single-threaded, this is
3348 * just to make the assert_spin_locked check happy. */
3349 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3350 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3351 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3352 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3358 * Returns true when a page flip has completed.
3360 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3361 int plane
, int pipe
, u32 iir
)
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3366 if (!drm_handle_vblank(dev
, pipe
))
3369 if ((iir
& flip_pending
) == 0)
3372 intel_prepare_page_flip(dev
, plane
);
3374 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3375 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3376 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3377 * the flip is completed (no longer pending). Since this doesn't raise
3378 * an interrupt per se, we watch for the change at vblank.
3380 if (I915_READ16(ISR
) & flip_pending
)
3383 intel_finish_page_flip(dev
, pipe
);
3388 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3390 struct drm_device
*dev
= (struct drm_device
*) arg
;
3391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3394 unsigned long irqflags
;
3397 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3398 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3400 iir
= I915_READ16(IIR
);
3404 while (iir
& ~flip_mask
) {
3405 /* Can't rely on pipestat interrupt bit in iir as it might
3406 * have been cleared after the pipestat interrupt was received.
3407 * It doesn't set the bit in iir again, but it still produces
3408 * interrupts (for non-MSI).
3410 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3411 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3412 i915_handle_error(dev
, false,
3413 "Command parser error, iir 0x%08x",
3416 for_each_pipe(pipe
) {
3417 int reg
= PIPESTAT(pipe
);
3418 pipe_stats
[pipe
] = I915_READ(reg
);
3421 * Clear the PIPE*STAT regs before the IIR
3423 if (pipe_stats
[pipe
] & 0x8000ffff)
3424 I915_WRITE(reg
, pipe_stats
[pipe
]);
3426 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3428 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3429 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3431 i915_update_dri1_breadcrumb(dev
);
3433 if (iir
& I915_USER_INTERRUPT
)
3434 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3436 for_each_pipe(pipe
) {
3441 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3442 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3443 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3445 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3446 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3448 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3449 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3450 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3459 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3464 for_each_pipe(pipe
) {
3465 /* Clear enable bits; then clear status bits */
3466 I915_WRITE(PIPESTAT(pipe
), 0);
3467 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3469 I915_WRITE16(IMR
, 0xffff);
3470 I915_WRITE16(IER
, 0x0);
3471 I915_WRITE16(IIR
, I915_READ16(IIR
));
3474 static void i915_irq_preinstall(struct drm_device
* dev
)
3476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3479 if (I915_HAS_HOTPLUG(dev
)) {
3480 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3481 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3484 I915_WRITE16(HWSTAM
, 0xeffe);
3486 I915_WRITE(PIPESTAT(pipe
), 0);
3487 I915_WRITE(IMR
, 0xffffffff);
3488 I915_WRITE(IER
, 0x0);
3492 static int i915_irq_postinstall(struct drm_device
*dev
)
3494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3496 unsigned long irqflags
;
3498 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3500 /* Unmask the interrupts that we always want on. */
3501 dev_priv
->irq_mask
=
3502 ~(I915_ASLE_INTERRUPT
|
3503 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3504 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3505 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3506 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3507 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3510 I915_ASLE_INTERRUPT
|
3511 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3512 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3513 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3514 I915_USER_INTERRUPT
;
3516 if (I915_HAS_HOTPLUG(dev
)) {
3517 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3518 POSTING_READ(PORT_HOTPLUG_EN
);
3520 /* Enable in IER... */
3521 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3522 /* and unmask in IMR */
3523 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3526 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3527 I915_WRITE(IER
, enable_mask
);
3530 i915_enable_asle_pipestat(dev
);
3532 /* Interrupt setup is already guaranteed to be single-threaded, this is
3533 * just to make the assert_spin_locked check happy. */
3534 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3535 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3536 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3537 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3543 * Returns true when a page flip has completed.
3545 static bool i915_handle_vblank(struct drm_device
*dev
,
3546 int plane
, int pipe
, u32 iir
)
3548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3549 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3551 if (!drm_handle_vblank(dev
, pipe
))
3554 if ((iir
& flip_pending
) == 0)
3557 intel_prepare_page_flip(dev
, plane
);
3559 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3560 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3561 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3562 * the flip is completed (no longer pending). Since this doesn't raise
3563 * an interrupt per se, we watch for the change at vblank.
3565 if (I915_READ(ISR
) & flip_pending
)
3568 intel_finish_page_flip(dev
, pipe
);
3573 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3575 struct drm_device
*dev
= (struct drm_device
*) arg
;
3576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3577 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3578 unsigned long irqflags
;
3580 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3581 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3582 int pipe
, ret
= IRQ_NONE
;
3584 iir
= I915_READ(IIR
);
3586 bool irq_received
= (iir
& ~flip_mask
) != 0;
3587 bool blc_event
= false;
3589 /* Can't rely on pipestat interrupt bit in iir as it might
3590 * have been cleared after the pipestat interrupt was received.
3591 * It doesn't set the bit in iir again, but it still produces
3592 * interrupts (for non-MSI).
3594 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3595 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3596 i915_handle_error(dev
, false,
3597 "Command parser error, iir 0x%08x",
3600 for_each_pipe(pipe
) {
3601 int reg
= PIPESTAT(pipe
);
3602 pipe_stats
[pipe
] = I915_READ(reg
);
3604 /* Clear the PIPE*STAT regs before the IIR */
3605 if (pipe_stats
[pipe
] & 0x8000ffff) {
3606 I915_WRITE(reg
, pipe_stats
[pipe
]);
3607 irq_received
= true;
3610 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3615 /* Consume port. Then clear IIR or we'll miss events */
3616 if (I915_HAS_HOTPLUG(dev
) &&
3617 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3618 i9xx_hpd_irq_handler(dev
);
3620 I915_WRITE(IIR
, iir
& ~flip_mask
);
3621 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3623 if (iir
& I915_USER_INTERRUPT
)
3624 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3626 for_each_pipe(pipe
) {
3631 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3632 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3633 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3635 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3638 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3639 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3641 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3642 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3643 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3646 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3647 intel_opregion_asle_intr(dev
);
3649 /* With MSI, interrupts are only generated when iir
3650 * transitions from zero to nonzero. If another bit got
3651 * set while we were handling the existing iir bits, then
3652 * we would never get another interrupt.
3654 * This is fine on non-MSI as well, as if we hit this path
3655 * we avoid exiting the interrupt handler only to generate
3658 * Note that for MSI this could cause a stray interrupt report
3659 * if an interrupt landed in the time between writing IIR and
3660 * the posting read. This should be rare enough to never
3661 * trigger the 99% of 100,000 interrupts test for disabling
3666 } while (iir
& ~flip_mask
);
3668 i915_update_dri1_breadcrumb(dev
);
3673 static void i915_irq_uninstall(struct drm_device
* dev
)
3675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3678 intel_hpd_irq_uninstall(dev_priv
);
3680 if (I915_HAS_HOTPLUG(dev
)) {
3681 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3682 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3685 I915_WRITE16(HWSTAM
, 0xffff);
3686 for_each_pipe(pipe
) {
3687 /* Clear enable bits; then clear status bits */
3688 I915_WRITE(PIPESTAT(pipe
), 0);
3689 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3691 I915_WRITE(IMR
, 0xffffffff);
3692 I915_WRITE(IER
, 0x0);
3694 I915_WRITE(IIR
, I915_READ(IIR
));
3697 static void i965_irq_preinstall(struct drm_device
* dev
)
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3702 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3703 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3705 I915_WRITE(HWSTAM
, 0xeffe);
3707 I915_WRITE(PIPESTAT(pipe
), 0);
3708 I915_WRITE(IMR
, 0xffffffff);
3709 I915_WRITE(IER
, 0x0);
3713 static int i965_irq_postinstall(struct drm_device
*dev
)
3715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3718 unsigned long irqflags
;
3720 /* Unmask the interrupts that we always want on. */
3721 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3722 I915_DISPLAY_PORT_INTERRUPT
|
3723 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3724 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3725 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3726 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3727 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3729 enable_mask
= ~dev_priv
->irq_mask
;
3730 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3731 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3732 enable_mask
|= I915_USER_INTERRUPT
;
3735 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3737 /* Interrupt setup is already guaranteed to be single-threaded, this is
3738 * just to make the assert_spin_locked check happy. */
3739 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3740 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3741 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3742 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3743 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3746 * Enable some error detection, note the instruction error mask
3747 * bit is reserved, so we leave it masked.
3750 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3751 GM45_ERROR_MEM_PRIV
|
3752 GM45_ERROR_CP_PRIV
|
3753 I915_ERROR_MEMORY_REFRESH
);
3755 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3756 I915_ERROR_MEMORY_REFRESH
);
3758 I915_WRITE(EMR
, error_mask
);
3760 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3761 I915_WRITE(IER
, enable_mask
);
3764 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3765 POSTING_READ(PORT_HOTPLUG_EN
);
3767 i915_enable_asle_pipestat(dev
);
3772 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3775 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3776 struct intel_encoder
*intel_encoder
;
3779 assert_spin_locked(&dev_priv
->irq_lock
);
3781 if (I915_HAS_HOTPLUG(dev
)) {
3782 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3783 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3784 /* Note HDMI and DP share hotplug bits */
3785 /* enable bits are the same for all generations */
3786 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3787 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3788 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3789 /* Programming the CRT detection parameters tends
3790 to generate a spurious hotplug event about three
3791 seconds later. So just do it once.
3794 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3795 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3796 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3798 /* Ignore TV since it's buggy */
3799 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3803 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3805 struct drm_device
*dev
= (struct drm_device
*) arg
;
3806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3808 u32 pipe_stats
[I915_MAX_PIPES
];
3809 unsigned long irqflags
;
3810 int ret
= IRQ_NONE
, pipe
;
3812 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3813 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3815 iir
= I915_READ(IIR
);
3818 bool irq_received
= (iir
& ~flip_mask
) != 0;
3819 bool blc_event
= false;
3821 /* Can't rely on pipestat interrupt bit in iir as it might
3822 * have been cleared after the pipestat interrupt was received.
3823 * It doesn't set the bit in iir again, but it still produces
3824 * interrupts (for non-MSI).
3826 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3827 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3828 i915_handle_error(dev
, false,
3829 "Command parser error, iir 0x%08x",
3832 for_each_pipe(pipe
) {
3833 int reg
= PIPESTAT(pipe
);
3834 pipe_stats
[pipe
] = I915_READ(reg
);
3837 * Clear the PIPE*STAT regs before the IIR
3839 if (pipe_stats
[pipe
] & 0x8000ffff) {
3840 I915_WRITE(reg
, pipe_stats
[pipe
]);
3841 irq_received
= true;
3844 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3851 /* Consume port. Then clear IIR or we'll miss events */
3852 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
3853 i9xx_hpd_irq_handler(dev
);
3855 I915_WRITE(IIR
, iir
& ~flip_mask
);
3856 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3858 if (iir
& I915_USER_INTERRUPT
)
3859 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3860 if (iir
& I915_BSD_USER_INTERRUPT
)
3861 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3863 for_each_pipe(pipe
) {
3864 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3865 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3866 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3868 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3871 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3872 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3874 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3875 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3876 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3879 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3880 intel_opregion_asle_intr(dev
);
3882 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3883 gmbus_irq_handler(dev
);
3885 /* With MSI, interrupts are only generated when iir
3886 * transitions from zero to nonzero. If another bit got
3887 * set while we were handling the existing iir bits, then
3888 * we would never get another interrupt.
3890 * This is fine on non-MSI as well, as if we hit this path
3891 * we avoid exiting the interrupt handler only to generate
3894 * Note that for MSI this could cause a stray interrupt report
3895 * if an interrupt landed in the time between writing IIR and
3896 * the posting read. This should be rare enough to never
3897 * trigger the 99% of 100,000 interrupts test for disabling
3903 i915_update_dri1_breadcrumb(dev
);
3908 static void i965_irq_uninstall(struct drm_device
* dev
)
3910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3916 intel_hpd_irq_uninstall(dev_priv
);
3918 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3919 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3921 I915_WRITE(HWSTAM
, 0xffffffff);
3923 I915_WRITE(PIPESTAT(pipe
), 0);
3924 I915_WRITE(IMR
, 0xffffffff);
3925 I915_WRITE(IER
, 0x0);
3928 I915_WRITE(PIPESTAT(pipe
),
3929 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3930 I915_WRITE(IIR
, I915_READ(IIR
));
3933 static void intel_hpd_irq_reenable(unsigned long data
)
3935 struct drm_i915_private
*dev_priv
= (struct drm_i915_private
*)data
;
3936 struct drm_device
*dev
= dev_priv
->dev
;
3937 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3938 unsigned long irqflags
;
3941 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3942 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3943 struct drm_connector
*connector
;
3945 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3948 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3950 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3951 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3953 if (intel_connector
->encoder
->hpd_pin
== i
) {
3954 if (connector
->polled
!= intel_connector
->polled
)
3955 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3956 drm_get_connector_name(connector
));
3957 connector
->polled
= intel_connector
->polled
;
3958 if (!connector
->polled
)
3959 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3963 if (dev_priv
->display
.hpd_irq_setup
)
3964 dev_priv
->display
.hpd_irq_setup(dev
);
3965 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3968 void intel_irq_init(struct drm_device
*dev
)
3970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3972 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3973 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3974 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3975 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3977 /* Let's track the enabled rps events */
3978 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
3980 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3981 i915_hangcheck_elapsed
,
3982 (unsigned long) dev
);
3983 setup_timer(&dev_priv
->hotplug_reenable_timer
, intel_hpd_irq_reenable
,
3984 (unsigned long) dev_priv
);
3986 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3989 dev
->max_vblank_count
= 0;
3990 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
3991 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3992 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3993 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3995 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3996 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3999 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4000 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4001 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4004 if (IS_VALLEYVIEW(dev
)) {
4005 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4006 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4007 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4008 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4009 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4010 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4011 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4012 } else if (IS_GEN8(dev
)) {
4013 dev
->driver
->irq_handler
= gen8_irq_handler
;
4014 dev
->driver
->irq_preinstall
= gen8_irq_preinstall
;
4015 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4016 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4017 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4018 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4019 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4020 } else if (HAS_PCH_SPLIT(dev
)) {
4021 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4022 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
4023 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4024 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4025 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4026 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4027 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4029 if (INTEL_INFO(dev
)->gen
== 2) {
4030 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4031 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4032 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4033 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4034 } else if (INTEL_INFO(dev
)->gen
== 3) {
4035 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4036 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4037 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4038 dev
->driver
->irq_handler
= i915_irq_handler
;
4039 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4041 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4042 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4043 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4044 dev
->driver
->irq_handler
= i965_irq_handler
;
4045 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4047 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4048 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4052 void intel_hpd_init(struct drm_device
*dev
)
4054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4055 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4056 struct drm_connector
*connector
;
4057 unsigned long irqflags
;
4060 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4061 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4062 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4064 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4065 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4066 connector
->polled
= intel_connector
->polled
;
4067 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4068 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4071 /* Interrupt setup is already guaranteed to be single-threaded, this is
4072 * just to make the assert_spin_locked checks happy. */
4073 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4074 if (dev_priv
->display
.hpd_irq_setup
)
4075 dev_priv
->display
.hpd_irq_setup(dev
);
4076 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4079 /* Disable interrupts so we can allow runtime PM. */
4080 void intel_runtime_pm_disable_interrupts(struct drm_device
*dev
)
4082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 dev
->driver
->irq_uninstall(dev
);
4085 dev_priv
->pm
.irqs_disabled
= true;
4088 /* Restore interrupts so we can recover from runtime PM. */
4089 void intel_runtime_pm_restore_interrupts(struct drm_device
*dev
)
4091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4093 dev_priv
->pm
.irqs_disabled
= false;
4094 dev
->driver
->irq_preinstall(dev
);
4095 dev
->driver
->irq_postinstall(dev
);