1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
50 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
51 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
54 static const u32 hpd_mask_i915
[] = {
55 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
56 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
57 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
58 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
59 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
60 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
63 static const u32 hpd_status_gen4
[] = {
64 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
65 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
66 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
68 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
72 static const u32 hpd_status_i965
[] = {
73 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
74 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I965
,
75 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I965
,
76 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
77 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
81 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
82 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
83 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
84 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
85 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
86 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
92 /* For display hotplug interrupt */
94 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
96 if ((dev_priv
->irq_mask
& mask
) != 0) {
97 dev_priv
->irq_mask
&= ~mask
;
98 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
104 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
106 if ((dev_priv
->irq_mask
& mask
) != mask
) {
107 dev_priv
->irq_mask
|= mask
;
108 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
114 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
116 u32 reg
= PIPESTAT(pipe
);
117 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
119 if ((pipestat
& mask
) == mask
)
122 /* Enable the interrupt, clear any pending status */
123 pipestat
|= mask
| (mask
>> 16);
124 I915_WRITE(reg
, pipestat
);
129 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
131 u32 reg
= PIPESTAT(pipe
);
132 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
134 if ((pipestat
& mask
) == 0)
138 I915_WRITE(reg
, pipestat
);
143 * intel_enable_asle - enable ASLE interrupt for OpRegion
145 void intel_enable_asle(struct drm_device
*dev
)
147 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
148 unsigned long irqflags
;
150 /* FIXME: opregion/asle for VLV */
151 if (IS_VALLEYVIEW(dev
))
154 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
156 if (HAS_PCH_SPLIT(dev
))
157 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
159 i915_enable_pipestat(dev_priv
, 1,
160 PIPE_LEGACY_BLC_EVENT_ENABLE
);
161 if (INTEL_INFO(dev
)->gen
>= 4)
162 i915_enable_pipestat(dev_priv
, 0,
163 PIPE_LEGACY_BLC_EVENT_ENABLE
);
166 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
170 * i915_pipe_enabled - check if a pipe is enabled
172 * @pipe: pipe to check
174 * Reading certain registers when the pipe is disabled can hang the chip.
175 * Use this routine to make sure the PLL is running and the pipe is active
176 * before reading such registers if unsure.
179 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
181 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
182 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
185 return I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_ENABLE
;
188 /* Called from drm generic code, passed a 'crtc', which
189 * we use as a pipe index
191 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
193 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
194 unsigned long high_frame
;
195 unsigned long low_frame
;
196 u32 high1
, high2
, low
;
198 if (!i915_pipe_enabled(dev
, pipe
)) {
199 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
200 "pipe %c\n", pipe_name(pipe
));
204 high_frame
= PIPEFRAME(pipe
);
205 low_frame
= PIPEFRAMEPIXEL(pipe
);
208 * High & low register fields aren't synchronized, so make sure
209 * we get a low value that's stable across two reads of the high
213 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
214 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
215 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
216 } while (high1
!= high2
);
218 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
219 low
>>= PIPE_FRAME_LOW_SHIFT
;
220 return (high1
<< 8) | low
;
223 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
225 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
226 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
228 if (!i915_pipe_enabled(dev
, pipe
)) {
229 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
230 "pipe %c\n", pipe_name(pipe
));
234 return I915_READ(reg
);
237 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
238 int *vpos
, int *hpos
)
240 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
241 u32 vbl
= 0, position
= 0;
242 int vbl_start
, vbl_end
, htotal
, vtotal
;
245 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
248 if (!i915_pipe_enabled(dev
, pipe
)) {
249 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
250 "pipe %c\n", pipe_name(pipe
));
255 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
257 if (INTEL_INFO(dev
)->gen
>= 4) {
258 /* No obvious pixelcount register. Only query vertical
259 * scanout position from Display scan line register.
261 position
= I915_READ(PIPEDSL(pipe
));
263 /* Decode into vertical scanout position. Don't have
264 * horizontal scanout position.
266 *vpos
= position
& 0x1fff;
269 /* Have access to pixelcount since start of frame.
270 * We can split this into vertical and horizontal
273 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
275 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
276 *vpos
= position
/ htotal
;
277 *hpos
= position
- (*vpos
* htotal
);
280 /* Query vblank area. */
281 vbl
= I915_READ(VBLANK(cpu_transcoder
));
283 /* Test position against vblank region. */
284 vbl_start
= vbl
& 0x1fff;
285 vbl_end
= (vbl
>> 16) & 0x1fff;
287 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
290 /* Inside "upper part" of vblank area? Apply corrective offset: */
291 if (in_vbl
&& (*vpos
>= vbl_start
))
292 *vpos
= *vpos
- vtotal
;
294 /* Readouts valid? */
296 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
300 ret
|= DRM_SCANOUTPOS_INVBL
;
305 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
307 struct timeval
*vblank_time
,
310 struct drm_crtc
*crtc
;
312 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
313 DRM_ERROR("Invalid crtc %d\n", pipe
);
317 /* Get drm_crtc to timestamp: */
318 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
320 DRM_ERROR("Invalid crtc %d\n", pipe
);
324 if (!crtc
->enabled
) {
325 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
329 /* Helper routine in DRM core does all the work: */
330 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
336 * Handle hotplug events outside the interrupt handler proper.
338 static void i915_hotplug_work_func(struct work_struct
*work
)
340 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
342 struct drm_device
*dev
= dev_priv
->dev
;
343 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
344 struct intel_encoder
*encoder
;
346 /* HPD irq before everything is fully set up. */
347 if (!dev_priv
->enable_hotplug_processing
)
350 mutex_lock(&mode_config
->mutex
);
351 DRM_DEBUG_KMS("running encoder hotplug functions\n");
353 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
354 if (encoder
->hot_plug
)
355 encoder
->hot_plug(encoder
);
357 mutex_unlock(&mode_config
->mutex
);
359 /* Just fire off a uevent and let userspace tell us what to do */
360 drm_helper_hpd_irq_event(dev
);
363 static void ironlake_handle_rps_change(struct drm_device
*dev
)
365 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
366 u32 busy_up
, busy_down
, max_avg
, min_avg
;
370 spin_lock_irqsave(&mchdev_lock
, flags
);
372 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
374 new_delay
= dev_priv
->ips
.cur_delay
;
376 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
377 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
378 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
379 max_avg
= I915_READ(RCBMAXAVG
);
380 min_avg
= I915_READ(RCBMINAVG
);
382 /* Handle RCS change request from hw */
383 if (busy_up
> max_avg
) {
384 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
385 new_delay
= dev_priv
->ips
.cur_delay
- 1;
386 if (new_delay
< dev_priv
->ips
.max_delay
)
387 new_delay
= dev_priv
->ips
.max_delay
;
388 } else if (busy_down
< min_avg
) {
389 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
390 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
391 if (new_delay
> dev_priv
->ips
.min_delay
)
392 new_delay
= dev_priv
->ips
.min_delay
;
395 if (ironlake_set_drps(dev
, new_delay
))
396 dev_priv
->ips
.cur_delay
= new_delay
;
398 spin_unlock_irqrestore(&mchdev_lock
, flags
);
403 static void notify_ring(struct drm_device
*dev
,
404 struct intel_ring_buffer
*ring
)
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
408 if (ring
->obj
== NULL
)
411 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
413 wake_up_all(&ring
->irq_queue
);
414 if (i915_enable_hangcheck
) {
415 dev_priv
->gpu_error
.hangcheck_count
= 0;
416 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
417 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
421 static void gen6_pm_rps_work(struct work_struct
*work
)
423 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
428 spin_lock_irq(&dev_priv
->rps
.lock
);
429 pm_iir
= dev_priv
->rps
.pm_iir
;
430 dev_priv
->rps
.pm_iir
= 0;
431 pm_imr
= I915_READ(GEN6_PMIMR
);
432 I915_WRITE(GEN6_PMIMR
, 0);
433 spin_unlock_irq(&dev_priv
->rps
.lock
);
435 if ((pm_iir
& GEN6_PM_DEFERRED_EVENTS
) == 0)
438 mutex_lock(&dev_priv
->rps
.hw_lock
);
440 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
)
441 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
443 new_delay
= dev_priv
->rps
.cur_delay
- 1;
445 /* sysfs frequency interfaces may have snuck in while servicing the
448 if (!(new_delay
> dev_priv
->rps
.max_delay
||
449 new_delay
< dev_priv
->rps
.min_delay
)) {
450 gen6_set_rps(dev_priv
->dev
, new_delay
);
453 mutex_unlock(&dev_priv
->rps
.hw_lock
);
458 * ivybridge_parity_work - Workqueue called when a parity error interrupt
460 * @work: workqueue struct
462 * Doesn't actually do anything except notify userspace. As a consequence of
463 * this event, userspace should try to remap the bad rows since statistically
464 * it is likely the same row is more likely to go bad again.
466 static void ivybridge_parity_work(struct work_struct
*work
)
468 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
469 l3_parity
.error_work
);
470 u32 error_status
, row
, bank
, subbank
;
471 char *parity_event
[5];
475 /* We must turn off DOP level clock gating to access the L3 registers.
476 * In order to prevent a get/put style interface, acquire struct mutex
477 * any time we access those registers.
479 mutex_lock(&dev_priv
->dev
->struct_mutex
);
481 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
482 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
483 POSTING_READ(GEN7_MISCCPCTL
);
485 error_status
= I915_READ(GEN7_L3CDERRST1
);
486 row
= GEN7_PARITY_ERROR_ROW(error_status
);
487 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
488 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
490 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
491 GEN7_L3CDERRST1_ENABLE
);
492 POSTING_READ(GEN7_L3CDERRST1
);
494 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
496 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
497 dev_priv
->gt_irq_mask
&= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
498 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
499 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
501 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
503 parity_event
[0] = "L3_PARITY_ERROR=1";
504 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
505 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
506 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
507 parity_event
[4] = NULL
;
509 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
510 KOBJ_CHANGE
, parity_event
);
512 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
515 kfree(parity_event
[3]);
516 kfree(parity_event
[2]);
517 kfree(parity_event
[1]);
520 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
522 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
525 if (!HAS_L3_GPU_CACHE(dev
))
528 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
529 dev_priv
->gt_irq_mask
|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
530 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
531 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
533 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
536 static void snb_gt_irq_handler(struct drm_device
*dev
,
537 struct drm_i915_private
*dev_priv
,
541 if (gt_iir
& (GEN6_RENDER_USER_INTERRUPT
|
542 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
))
543 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
544 if (gt_iir
& GEN6_BSD_USER_INTERRUPT
)
545 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
546 if (gt_iir
& GEN6_BLITTER_USER_INTERRUPT
)
547 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
549 if (gt_iir
& (GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
550 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
551 GT_RENDER_CS_ERROR_INTERRUPT
)) {
552 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
553 i915_handle_error(dev
, false);
556 if (gt_iir
& GT_GEN7_L3_PARITY_ERROR_INTERRUPT
)
557 ivybridge_handle_parity_error(dev
);
560 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
566 * IIR bits should never already be set because IMR should
567 * prevent an interrupt from being shown in IIR. The warning
568 * displays a case where we've unsafely cleared
569 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
570 * type is not a problem, it displays a problem in the logic.
572 * The mask bit in IMR is cleared by dev_priv->rps.work.
575 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
576 dev_priv
->rps
.pm_iir
|= pm_iir
;
577 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
578 POSTING_READ(GEN6_PMIMR
);
579 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
581 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
584 static void gmbus_irq_handler(struct drm_device
*dev
)
586 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
588 wake_up_all(&dev_priv
->gmbus_wait_queue
);
591 static void dp_aux_irq_handler(struct drm_device
*dev
)
593 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
595 wake_up_all(&dev_priv
->gmbus_wait_queue
);
598 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
600 struct drm_device
*dev
= (struct drm_device
*) arg
;
601 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
602 u32 iir
, gt_iir
, pm_iir
;
603 irqreturn_t ret
= IRQ_NONE
;
604 unsigned long irqflags
;
606 u32 pipe_stats
[I915_MAX_PIPES
];
608 atomic_inc(&dev_priv
->irq_received
);
611 iir
= I915_READ(VLV_IIR
);
612 gt_iir
= I915_READ(GTIIR
);
613 pm_iir
= I915_READ(GEN6_PMIIR
);
615 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
620 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
622 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
623 for_each_pipe(pipe
) {
624 int reg
= PIPESTAT(pipe
);
625 pipe_stats
[pipe
] = I915_READ(reg
);
628 * Clear the PIPE*STAT regs before the IIR
630 if (pipe_stats
[pipe
] & 0x8000ffff) {
631 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
632 DRM_DEBUG_DRIVER("pipe %c underrun\n",
634 I915_WRITE(reg
, pipe_stats
[pipe
]);
637 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
639 for_each_pipe(pipe
) {
640 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
641 drm_handle_vblank(dev
, pipe
);
643 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
644 intel_prepare_page_flip(dev
, pipe
);
645 intel_finish_page_flip(dev
, pipe
);
649 /* Consume port. Then clear IIR or we'll miss events */
650 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
651 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
653 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
655 if (hotplug_status
& HOTPLUG_INT_STATUS_I915
)
656 queue_work(dev_priv
->wq
,
657 &dev_priv
->hotplug_work
);
659 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
660 I915_READ(PORT_HOTPLUG_STAT
);
663 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
664 gmbus_irq_handler(dev
);
666 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
667 gen6_queue_rps_work(dev_priv
, pm_iir
);
669 I915_WRITE(GTIIR
, gt_iir
);
670 I915_WRITE(GEN6_PMIIR
, pm_iir
);
671 I915_WRITE(VLV_IIR
, iir
);
678 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
680 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
683 if (pch_iir
& SDE_HOTPLUG_MASK
)
684 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
686 if (pch_iir
& SDE_AUDIO_POWER_MASK
)
687 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
688 (pch_iir
& SDE_AUDIO_POWER_MASK
) >>
689 SDE_AUDIO_POWER_SHIFT
);
691 if (pch_iir
& SDE_AUX_MASK
)
692 dp_aux_irq_handler(dev
);
694 if (pch_iir
& SDE_GMBUS
)
695 gmbus_irq_handler(dev
);
697 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
698 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
700 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
701 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
703 if (pch_iir
& SDE_POISON
)
704 DRM_ERROR("PCH poison interrupt\n");
706 if (pch_iir
& SDE_FDI_MASK
)
708 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
710 I915_READ(FDI_RX_IIR(pipe
)));
712 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
713 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
715 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
716 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
718 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
719 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
720 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
721 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
724 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
726 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
729 if (pch_iir
& SDE_HOTPLUG_MASK_CPT
)
730 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
732 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
)
733 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
734 (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
735 SDE_AUDIO_POWER_SHIFT_CPT
);
737 if (pch_iir
& SDE_AUX_MASK_CPT
)
738 dp_aux_irq_handler(dev
);
740 if (pch_iir
& SDE_GMBUS_CPT
)
741 gmbus_irq_handler(dev
);
743 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
744 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
746 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
747 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
749 if (pch_iir
& SDE_FDI_MASK_CPT
)
751 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
753 I915_READ(FDI_RX_IIR(pipe
)));
756 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
758 struct drm_device
*dev
= (struct drm_device
*) arg
;
759 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
760 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
761 irqreturn_t ret
= IRQ_NONE
;
764 atomic_inc(&dev_priv
->irq_received
);
766 /* disable master interrupt before clearing iir */
767 de_ier
= I915_READ(DEIER
);
768 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
770 /* Disable south interrupts. We'll only write to SDEIIR once, so further
771 * interrupts will will be stored on its back queue, and then we'll be
772 * able to process them after we restore SDEIER (as soon as we restore
773 * it, we'll get an interrupt if SDEIIR still has something to process
774 * due to its back queue). */
775 sde_ier
= I915_READ(SDEIER
);
776 I915_WRITE(SDEIER
, 0);
777 POSTING_READ(SDEIER
);
779 gt_iir
= I915_READ(GTIIR
);
781 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
782 I915_WRITE(GTIIR
, gt_iir
);
786 de_iir
= I915_READ(DEIIR
);
788 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
789 dp_aux_irq_handler(dev
);
791 if (de_iir
& DE_GSE_IVB
)
792 intel_opregion_gse_intr(dev
);
794 for (i
= 0; i
< 3; i
++) {
795 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
796 drm_handle_vblank(dev
, i
);
797 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
798 intel_prepare_page_flip(dev
, i
);
799 intel_finish_page_flip_plane(dev
, i
);
803 /* check event from PCH */
804 if (de_iir
& DE_PCH_EVENT_IVB
) {
805 u32 pch_iir
= I915_READ(SDEIIR
);
807 cpt_irq_handler(dev
, pch_iir
);
809 /* clear PCH hotplug event before clear CPU irq */
810 I915_WRITE(SDEIIR
, pch_iir
);
813 I915_WRITE(DEIIR
, de_iir
);
817 pm_iir
= I915_READ(GEN6_PMIIR
);
819 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
820 gen6_queue_rps_work(dev_priv
, pm_iir
);
821 I915_WRITE(GEN6_PMIIR
, pm_iir
);
825 I915_WRITE(DEIER
, de_ier
);
827 I915_WRITE(SDEIER
, sde_ier
);
828 POSTING_READ(SDEIER
);
833 static void ilk_gt_irq_handler(struct drm_device
*dev
,
834 struct drm_i915_private
*dev_priv
,
837 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
838 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
839 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
840 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
843 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
845 struct drm_device
*dev
= (struct drm_device
*) arg
;
846 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
848 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
850 atomic_inc(&dev_priv
->irq_received
);
852 /* disable master interrupt before clearing iir */
853 de_ier
= I915_READ(DEIER
);
854 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
857 /* Disable south interrupts. We'll only write to SDEIIR once, so further
858 * interrupts will will be stored on its back queue, and then we'll be
859 * able to process them after we restore SDEIER (as soon as we restore
860 * it, we'll get an interrupt if SDEIIR still has something to process
861 * due to its back queue). */
862 sde_ier
= I915_READ(SDEIER
);
863 I915_WRITE(SDEIER
, 0);
864 POSTING_READ(SDEIER
);
866 de_iir
= I915_READ(DEIIR
);
867 gt_iir
= I915_READ(GTIIR
);
868 pm_iir
= I915_READ(GEN6_PMIIR
);
870 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
876 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
878 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
880 if (de_iir
& DE_AUX_CHANNEL_A
)
881 dp_aux_irq_handler(dev
);
884 intel_opregion_gse_intr(dev
);
886 if (de_iir
& DE_PIPEA_VBLANK
)
887 drm_handle_vblank(dev
, 0);
889 if (de_iir
& DE_PIPEB_VBLANK
)
890 drm_handle_vblank(dev
, 1);
892 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
893 intel_prepare_page_flip(dev
, 0);
894 intel_finish_page_flip_plane(dev
, 0);
897 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
898 intel_prepare_page_flip(dev
, 1);
899 intel_finish_page_flip_plane(dev
, 1);
902 /* check event from PCH */
903 if (de_iir
& DE_PCH_EVENT
) {
904 u32 pch_iir
= I915_READ(SDEIIR
);
906 if (HAS_PCH_CPT(dev
))
907 cpt_irq_handler(dev
, pch_iir
);
909 ibx_irq_handler(dev
, pch_iir
);
911 /* should clear PCH hotplug event before clear CPU irq */
912 I915_WRITE(SDEIIR
, pch_iir
);
915 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
916 ironlake_handle_rps_change(dev
);
918 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
919 gen6_queue_rps_work(dev_priv
, pm_iir
);
921 I915_WRITE(GTIIR
, gt_iir
);
922 I915_WRITE(DEIIR
, de_iir
);
923 I915_WRITE(GEN6_PMIIR
, pm_iir
);
926 I915_WRITE(DEIER
, de_ier
);
928 I915_WRITE(SDEIER
, sde_ier
);
929 POSTING_READ(SDEIER
);
935 * i915_error_work_func - do process context error handling work
938 * Fire an error uevent so userspace can see that a hang or error
941 static void i915_error_work_func(struct work_struct
*work
)
943 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
945 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
947 struct drm_device
*dev
= dev_priv
->dev
;
948 struct intel_ring_buffer
*ring
;
949 char *error_event
[] = { "ERROR=1", NULL
};
950 char *reset_event
[] = { "RESET=1", NULL
};
951 char *reset_done_event
[] = { "ERROR=0", NULL
};
954 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
957 * Note that there's only one work item which does gpu resets, so we
958 * need not worry about concurrent gpu resets potentially incrementing
959 * error->reset_counter twice. We only need to take care of another
960 * racing irq/hangcheck declaring the gpu dead for a second time. A
961 * quick check for that is good enough: schedule_work ensures the
962 * correct ordering between hang detection and this work item, and since
963 * the reset in-progress bit is only ever set by code outside of this
964 * work we don't need to worry about any other races.
966 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
967 DRM_DEBUG_DRIVER("resetting chip\n");
968 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
971 ret
= i915_reset(dev
);
975 * After all the gem state is reset, increment the reset
976 * counter and wake up everyone waiting for the reset to
979 * Since unlock operations are a one-sided barrier only,
980 * we need to insert a barrier here to order any seqno
982 * the counter increment.
984 smp_mb__before_atomic_inc();
985 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
987 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
988 KOBJ_CHANGE
, reset_done_event
);
990 atomic_set(&error
->reset_counter
, I915_WEDGED
);
993 for_each_ring(ring
, dev_priv
, i
)
994 wake_up_all(&ring
->irq_queue
);
996 intel_display_handle_reset(dev
);
998 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1002 /* NB: please notice the memset */
1003 static void i915_get_extra_instdone(struct drm_device
*dev
,
1006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1007 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
1009 switch(INTEL_INFO(dev
)->gen
) {
1012 instdone
[0] = I915_READ(INSTDONE
);
1017 instdone
[0] = I915_READ(INSTDONE_I965
);
1018 instdone
[1] = I915_READ(INSTDONE1
);
1021 WARN_ONCE(1, "Unsupported platform\n");
1023 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
1024 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
1025 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
1026 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
1031 #ifdef CONFIG_DEBUG_FS
1032 static struct drm_i915_error_object
*
1033 i915_error_object_create_sized(struct drm_i915_private
*dev_priv
,
1034 struct drm_i915_gem_object
*src
,
1035 const int num_pages
)
1037 struct drm_i915_error_object
*dst
;
1041 if (src
== NULL
|| src
->pages
== NULL
)
1044 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), GFP_ATOMIC
);
1048 reloc_offset
= src
->gtt_offset
;
1049 for (i
= 0; i
< num_pages
; i
++) {
1050 unsigned long flags
;
1053 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
1057 local_irq_save(flags
);
1058 if (reloc_offset
< dev_priv
->gtt
.mappable_end
&&
1059 src
->has_global_gtt_mapping
) {
1062 /* Simply ignore tiling or any overlapping fence.
1063 * It's part of the error state, and this hopefully
1064 * captures what the GPU read.
1067 s
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
1069 memcpy_fromio(d
, s
, PAGE_SIZE
);
1070 io_mapping_unmap_atomic(s
);
1071 } else if (src
->stolen
) {
1072 unsigned long offset
;
1074 offset
= dev_priv
->mm
.stolen_base
;
1075 offset
+= src
->stolen
->start
;
1076 offset
+= i
<< PAGE_SHIFT
;
1078 memcpy_fromio(d
, (void __iomem
*) offset
, PAGE_SIZE
);
1083 page
= i915_gem_object_get_page(src
, i
);
1085 drm_clflush_pages(&page
, 1);
1087 s
= kmap_atomic(page
);
1088 memcpy(d
, s
, PAGE_SIZE
);
1091 drm_clflush_pages(&page
, 1);
1093 local_irq_restore(flags
);
1097 reloc_offset
+= PAGE_SIZE
;
1099 dst
->page_count
= num_pages
;
1100 dst
->gtt_offset
= src
->gtt_offset
;
1106 kfree(dst
->pages
[i
]);
1110 #define i915_error_object_create(dev_priv, src) \
1111 i915_error_object_create_sized((dev_priv), (src), \
1112 (src)->base.size>>PAGE_SHIFT)
1115 i915_error_object_free(struct drm_i915_error_object
*obj
)
1122 for (page
= 0; page
< obj
->page_count
; page
++)
1123 kfree(obj
->pages
[page
]);
1129 i915_error_state_free(struct kref
*error_ref
)
1131 struct drm_i915_error_state
*error
= container_of(error_ref
,
1132 typeof(*error
), ref
);
1135 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
1136 i915_error_object_free(error
->ring
[i
].batchbuffer
);
1137 i915_error_object_free(error
->ring
[i
].ringbuffer
);
1138 kfree(error
->ring
[i
].requests
);
1141 kfree(error
->active_bo
);
1142 kfree(error
->overlay
);
1145 static void capture_bo(struct drm_i915_error_buffer
*err
,
1146 struct drm_i915_gem_object
*obj
)
1148 err
->size
= obj
->base
.size
;
1149 err
->name
= obj
->base
.name
;
1150 err
->rseqno
= obj
->last_read_seqno
;
1151 err
->wseqno
= obj
->last_write_seqno
;
1152 err
->gtt_offset
= obj
->gtt_offset
;
1153 err
->read_domains
= obj
->base
.read_domains
;
1154 err
->write_domain
= obj
->base
.write_domain
;
1155 err
->fence_reg
= obj
->fence_reg
;
1157 if (obj
->pin_count
> 0)
1159 if (obj
->user_pin_count
> 0)
1161 err
->tiling
= obj
->tiling_mode
;
1162 err
->dirty
= obj
->dirty
;
1163 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1164 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1165 err
->cache_level
= obj
->cache_level
;
1168 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1169 int count
, struct list_head
*head
)
1171 struct drm_i915_gem_object
*obj
;
1174 list_for_each_entry(obj
, head
, mm_list
) {
1175 capture_bo(err
++, obj
);
1183 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1184 int count
, struct list_head
*head
)
1186 struct drm_i915_gem_object
*obj
;
1189 list_for_each_entry(obj
, head
, gtt_list
) {
1190 if (obj
->pin_count
== 0)
1193 capture_bo(err
++, obj
);
1201 static void i915_gem_record_fences(struct drm_device
*dev
,
1202 struct drm_i915_error_state
*error
)
1204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1208 switch (INTEL_INFO(dev
)->gen
) {
1211 for (i
= 0; i
< 16; i
++)
1212 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1216 for (i
= 0; i
< 16; i
++)
1217 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1220 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1221 for (i
= 0; i
< 8; i
++)
1222 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1224 for (i
= 0; i
< 8; i
++)
1225 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1233 static struct drm_i915_error_object
*
1234 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1235 struct intel_ring_buffer
*ring
)
1237 struct drm_i915_gem_object
*obj
;
1240 if (!ring
->get_seqno
)
1243 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1244 u32 acthd
= I915_READ(ACTHD
);
1246 if (WARN_ON(ring
->id
!= RCS
))
1249 obj
= ring
->private;
1250 if (acthd
>= obj
->gtt_offset
&&
1251 acthd
< obj
->gtt_offset
+ obj
->base
.size
)
1252 return i915_error_object_create(dev_priv
, obj
);
1255 seqno
= ring
->get_seqno(ring
, false);
1256 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1257 if (obj
->ring
!= ring
)
1260 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1263 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1266 /* We need to copy these to an anonymous buffer as the simplest
1267 * method to avoid being overwritten by userspace.
1269 return i915_error_object_create(dev_priv
, obj
);
1275 static void i915_record_ring_state(struct drm_device
*dev
,
1276 struct drm_i915_error_state
*error
,
1277 struct intel_ring_buffer
*ring
)
1279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 if (INTEL_INFO(dev
)->gen
>= 6) {
1282 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1283 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1284 error
->semaphore_mboxes
[ring
->id
][0]
1285 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1286 error
->semaphore_mboxes
[ring
->id
][1]
1287 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1288 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1289 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1292 if (INTEL_INFO(dev
)->gen
>= 4) {
1293 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1294 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1295 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1296 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1297 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1298 if (ring
->id
== RCS
)
1299 error
->bbaddr
= I915_READ64(BB_ADDR
);
1301 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1302 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1303 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1304 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1307 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1308 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1309 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1310 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1311 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1312 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1313 error
->ctl
[ring
->id
] = I915_READ_CTL(ring
);
1315 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1316 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1320 static void i915_gem_record_active_context(struct intel_ring_buffer
*ring
,
1321 struct drm_i915_error_state
*error
,
1322 struct drm_i915_error_ring
*ering
)
1324 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1325 struct drm_i915_gem_object
*obj
;
1327 /* Currently render ring is the only HW context user */
1328 if (ring
->id
!= RCS
|| !error
->ccid
)
1331 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
1332 if ((error
->ccid
& PAGE_MASK
) == obj
->gtt_offset
) {
1333 ering
->ctx
= i915_error_object_create_sized(dev_priv
,
1339 static void i915_gem_record_rings(struct drm_device
*dev
,
1340 struct drm_i915_error_state
*error
)
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1343 struct intel_ring_buffer
*ring
;
1344 struct drm_i915_gem_request
*request
;
1347 for_each_ring(ring
, dev_priv
, i
) {
1348 i915_record_ring_state(dev
, error
, ring
);
1350 error
->ring
[i
].batchbuffer
=
1351 i915_error_first_batchbuffer(dev_priv
, ring
);
1353 error
->ring
[i
].ringbuffer
=
1354 i915_error_object_create(dev_priv
, ring
->obj
);
1357 i915_gem_record_active_context(ring
, error
, &error
->ring
[i
]);
1360 list_for_each_entry(request
, &ring
->request_list
, list
)
1363 error
->ring
[i
].num_requests
= count
;
1364 error
->ring
[i
].requests
=
1365 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1367 if (error
->ring
[i
].requests
== NULL
) {
1368 error
->ring
[i
].num_requests
= 0;
1373 list_for_each_entry(request
, &ring
->request_list
, list
) {
1374 struct drm_i915_error_request
*erq
;
1376 erq
= &error
->ring
[i
].requests
[count
++];
1377 erq
->seqno
= request
->seqno
;
1378 erq
->jiffies
= request
->emitted_jiffies
;
1379 erq
->tail
= request
->tail
;
1385 * i915_capture_error_state - capture an error record for later analysis
1388 * Should be called when an error is detected (either a hang or an error
1389 * interrupt) to capture error state from the time of the error. Fills
1390 * out a structure which becomes available in debugfs for user level tools
1393 static void i915_capture_error_state(struct drm_device
*dev
)
1395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1396 struct drm_i915_gem_object
*obj
;
1397 struct drm_i915_error_state
*error
;
1398 unsigned long flags
;
1401 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1402 error
= dev_priv
->gpu_error
.first_error
;
1403 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1407 /* Account for pipe specific data like PIPE*STAT */
1408 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1410 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1414 DRM_INFO("capturing error event; look for more information in "
1415 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1416 dev
->primary
->index
);
1418 kref_init(&error
->ref
);
1419 error
->eir
= I915_READ(EIR
);
1420 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1421 if (HAS_HW_CONTEXTS(dev
))
1422 error
->ccid
= I915_READ(CCID
);
1424 if (HAS_PCH_SPLIT(dev
))
1425 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1426 else if (IS_VALLEYVIEW(dev
))
1427 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1428 else if (IS_GEN2(dev
))
1429 error
->ier
= I915_READ16(IER
);
1431 error
->ier
= I915_READ(IER
);
1433 if (INTEL_INFO(dev
)->gen
>= 6)
1434 error
->derrmr
= I915_READ(DERRMR
);
1436 if (IS_VALLEYVIEW(dev
))
1437 error
->forcewake
= I915_READ(FORCEWAKE_VLV
);
1438 else if (INTEL_INFO(dev
)->gen
>= 7)
1439 error
->forcewake
= I915_READ(FORCEWAKE_MT
);
1440 else if (INTEL_INFO(dev
)->gen
== 6)
1441 error
->forcewake
= I915_READ(FORCEWAKE
);
1443 if (!HAS_PCH_SPLIT(dev
))
1445 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1447 if (INTEL_INFO(dev
)->gen
>= 6) {
1448 error
->error
= I915_READ(ERROR_GEN6
);
1449 error
->done_reg
= I915_READ(DONE_REG
);
1452 if (INTEL_INFO(dev
)->gen
== 7)
1453 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1455 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1457 i915_gem_record_fences(dev
, error
);
1458 i915_gem_record_rings(dev
, error
);
1460 /* Record buffers on the active and pinned lists. */
1461 error
->active_bo
= NULL
;
1462 error
->pinned_bo
= NULL
;
1465 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1467 error
->active_bo_count
= i
;
1468 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
1471 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1473 error
->active_bo
= NULL
;
1474 error
->pinned_bo
= NULL
;
1476 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1478 if (error
->active_bo
)
1480 error
->active_bo
+ error
->active_bo_count
;
1483 if (error
->active_bo
)
1484 error
->active_bo_count
=
1485 capture_active_bo(error
->active_bo
,
1486 error
->active_bo_count
,
1487 &dev_priv
->mm
.active_list
);
1489 if (error
->pinned_bo
)
1490 error
->pinned_bo_count
=
1491 capture_pinned_bo(error
->pinned_bo
,
1492 error
->pinned_bo_count
,
1493 &dev_priv
->mm
.bound_list
);
1495 do_gettimeofday(&error
->time
);
1497 error
->overlay
= intel_overlay_capture_error_state(dev
);
1498 error
->display
= intel_display_capture_error_state(dev
);
1500 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1501 if (dev_priv
->gpu_error
.first_error
== NULL
) {
1502 dev_priv
->gpu_error
.first_error
= error
;
1505 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1508 i915_error_state_free(&error
->ref
);
1511 void i915_destroy_error_state(struct drm_device
*dev
)
1513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1514 struct drm_i915_error_state
*error
;
1515 unsigned long flags
;
1517 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1518 error
= dev_priv
->gpu_error
.first_error
;
1519 dev_priv
->gpu_error
.first_error
= NULL
;
1520 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1523 kref_put(&error
->ref
, i915_error_state_free
);
1526 #define i915_capture_error_state(x)
1529 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1532 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1533 u32 eir
= I915_READ(EIR
);
1539 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1541 i915_get_extra_instdone(dev
, instdone
);
1544 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1545 u32 ipeir
= I915_READ(IPEIR_I965
);
1547 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1548 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1549 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1550 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1551 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1552 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1553 I915_WRITE(IPEIR_I965
, ipeir
);
1554 POSTING_READ(IPEIR_I965
);
1556 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1557 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1558 pr_err("page table error\n");
1559 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1560 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1561 POSTING_READ(PGTBL_ER
);
1565 if (!IS_GEN2(dev
)) {
1566 if (eir
& I915_ERROR_PAGE_TABLE
) {
1567 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1568 pr_err("page table error\n");
1569 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1570 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1571 POSTING_READ(PGTBL_ER
);
1575 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1576 pr_err("memory refresh error:\n");
1578 pr_err("pipe %c stat: 0x%08x\n",
1579 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1580 /* pipestat has already been acked */
1582 if (eir
& I915_ERROR_INSTRUCTION
) {
1583 pr_err("instruction error\n");
1584 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1585 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1586 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1587 if (INTEL_INFO(dev
)->gen
< 4) {
1588 u32 ipeir
= I915_READ(IPEIR
);
1590 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1591 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1592 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1593 I915_WRITE(IPEIR
, ipeir
);
1594 POSTING_READ(IPEIR
);
1596 u32 ipeir
= I915_READ(IPEIR_I965
);
1598 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1599 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1600 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1601 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1602 I915_WRITE(IPEIR_I965
, ipeir
);
1603 POSTING_READ(IPEIR_I965
);
1607 I915_WRITE(EIR
, eir
);
1609 eir
= I915_READ(EIR
);
1612 * some errors might have become stuck,
1615 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1616 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1617 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1622 * i915_handle_error - handle an error interrupt
1625 * Do some basic checking of regsiter state at error interrupt time and
1626 * dump it to the syslog. Also call i915_capture_error_state() to make
1627 * sure we get a record and make it available in debugfs. Fire a uevent
1628 * so userspace knows something bad happened (should trigger collection
1629 * of a ring dump etc.).
1631 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1634 struct intel_ring_buffer
*ring
;
1637 i915_capture_error_state(dev
);
1638 i915_report_and_clear_eir(dev
);
1641 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1642 &dev_priv
->gpu_error
.reset_counter
);
1645 * Wakeup waiting processes so that the reset work item
1646 * doesn't deadlock trying to grab various locks.
1648 for_each_ring(ring
, dev_priv
, i
)
1649 wake_up_all(&ring
->irq_queue
);
1652 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1655 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1658 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1659 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1660 struct drm_i915_gem_object
*obj
;
1661 struct intel_unpin_work
*work
;
1662 unsigned long flags
;
1663 bool stall_detected
;
1665 /* Ignore early vblank irqs */
1666 if (intel_crtc
== NULL
)
1669 spin_lock_irqsave(&dev
->event_lock
, flags
);
1670 work
= intel_crtc
->unpin_work
;
1673 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1674 !work
->enable_stall_check
) {
1675 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1676 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1680 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1681 obj
= work
->pending_flip_obj
;
1682 if (INTEL_INFO(dev
)->gen
>= 4) {
1683 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1684 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1687 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1688 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
1689 crtc
->y
* crtc
->fb
->pitches
[0] +
1690 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1693 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1695 if (stall_detected
) {
1696 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1697 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1701 /* Called from drm generic code, passed 'crtc' which
1702 * we use as a pipe index
1704 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1706 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1707 unsigned long irqflags
;
1709 if (!i915_pipe_enabled(dev
, pipe
))
1712 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1713 if (INTEL_INFO(dev
)->gen
>= 4)
1714 i915_enable_pipestat(dev_priv
, pipe
,
1715 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1717 i915_enable_pipestat(dev_priv
, pipe
,
1718 PIPE_VBLANK_INTERRUPT_ENABLE
);
1720 /* maintain vblank delivery even in deep C-states */
1721 if (dev_priv
->info
->gen
== 3)
1722 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1723 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1728 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1730 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1731 unsigned long irqflags
;
1733 if (!i915_pipe_enabled(dev
, pipe
))
1736 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1737 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1738 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1739 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1744 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1746 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1747 unsigned long irqflags
;
1749 if (!i915_pipe_enabled(dev
, pipe
))
1752 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1753 ironlake_enable_display_irq(dev_priv
,
1754 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1755 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1760 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1762 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1763 unsigned long irqflags
;
1766 if (!i915_pipe_enabled(dev
, pipe
))
1769 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1770 imr
= I915_READ(VLV_IMR
);
1772 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1774 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1775 I915_WRITE(VLV_IMR
, imr
);
1776 i915_enable_pipestat(dev_priv
, pipe
,
1777 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1778 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1783 /* Called from drm generic code, passed 'crtc' which
1784 * we use as a pipe index
1786 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1788 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1789 unsigned long irqflags
;
1791 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1792 if (dev_priv
->info
->gen
== 3)
1793 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1795 i915_disable_pipestat(dev_priv
, pipe
,
1796 PIPE_VBLANK_INTERRUPT_ENABLE
|
1797 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1798 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1801 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1803 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1804 unsigned long irqflags
;
1806 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1807 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1808 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1809 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1812 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1814 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1815 unsigned long irqflags
;
1817 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1818 ironlake_disable_display_irq(dev_priv
,
1819 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1820 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1823 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1825 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1826 unsigned long irqflags
;
1829 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1830 i915_disable_pipestat(dev_priv
, pipe
,
1831 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1832 imr
= I915_READ(VLV_IMR
);
1834 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1836 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1837 I915_WRITE(VLV_IMR
, imr
);
1838 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1842 ring_last_seqno(struct intel_ring_buffer
*ring
)
1844 return list_entry(ring
->request_list
.prev
,
1845 struct drm_i915_gem_request
, list
)->seqno
;
1848 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
1850 if (list_empty(&ring
->request_list
) ||
1851 i915_seqno_passed(ring
->get_seqno(ring
, false),
1852 ring_last_seqno(ring
))) {
1853 /* Issue a wake-up to catch stuck h/w. */
1854 if (waitqueue_active(&ring
->irq_queue
)) {
1855 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1857 wake_up_all(&ring
->irq_queue
);
1865 static bool semaphore_passed(struct intel_ring_buffer
*ring
)
1867 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1868 u32 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1869 struct intel_ring_buffer
*signaller
;
1870 u32 cmd
, ipehr
, acthd_min
;
1872 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1873 if ((ipehr
& ~(0x3 << 16)) !=
1874 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1877 /* ACTHD is likely pointing to the dword after the actual command,
1878 * so scan backwards until we find the MBOX.
1880 acthd_min
= max((int)acthd
- 3 * 4, 0);
1882 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1887 if (acthd
< acthd_min
)
1891 signaller
= &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1892 return i915_seqno_passed(signaller
->get_seqno(signaller
, false),
1893 ioread32(ring
->virtual_start
+acthd
+4)+1);
1896 static bool kick_ring(struct intel_ring_buffer
*ring
)
1898 struct drm_device
*dev
= ring
->dev
;
1899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1900 u32 tmp
= I915_READ_CTL(ring
);
1901 if (tmp
& RING_WAIT
) {
1902 DRM_ERROR("Kicking stuck wait on %s\n",
1904 I915_WRITE_CTL(ring
, tmp
);
1908 if (INTEL_INFO(dev
)->gen
>= 6 &&
1909 tmp
& RING_WAIT_SEMAPHORE
&&
1910 semaphore_passed(ring
)) {
1911 DRM_ERROR("Kicking stuck semaphore on %s\n",
1913 I915_WRITE_CTL(ring
, tmp
);
1919 static bool i915_hangcheck_hung(struct drm_device
*dev
)
1921 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1923 if (dev_priv
->gpu_error
.hangcheck_count
++ > 1) {
1926 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1927 i915_handle_error(dev
, true);
1929 if (!IS_GEN2(dev
)) {
1930 struct intel_ring_buffer
*ring
;
1933 /* Is the chip hanging on a WAIT_FOR_EVENT?
1934 * If so we can simply poke the RB_WAIT bit
1935 * and break the hang. This should work on
1936 * all but the second generation chipsets.
1938 for_each_ring(ring
, dev_priv
, i
)
1939 hung
&= !kick_ring(ring
);
1949 * This is called when the chip hasn't reported back with completed
1950 * batchbuffers in a long time. The first time this is called we simply record
1951 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1952 * again, we assume the chip is wedged and try to fix it.
1954 void i915_hangcheck_elapsed(unsigned long data
)
1956 struct drm_device
*dev
= (struct drm_device
*)data
;
1957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1958 uint32_t acthd
[I915_NUM_RINGS
], instdone
[I915_NUM_INSTDONE_REG
];
1959 struct intel_ring_buffer
*ring
;
1960 bool err
= false, idle
;
1963 if (!i915_enable_hangcheck
)
1966 memset(acthd
, 0, sizeof(acthd
));
1968 for_each_ring(ring
, dev_priv
, i
) {
1969 idle
&= i915_hangcheck_ring_idle(ring
, &err
);
1970 acthd
[i
] = intel_ring_get_active_head(ring
);
1973 /* If all work is done then ACTHD clearly hasn't advanced. */
1976 if (i915_hangcheck_hung(dev
))
1982 dev_priv
->gpu_error
.hangcheck_count
= 0;
1986 i915_get_extra_instdone(dev
, instdone
);
1987 if (memcmp(dev_priv
->gpu_error
.last_acthd
, acthd
,
1988 sizeof(acthd
)) == 0 &&
1989 memcmp(dev_priv
->gpu_error
.prev_instdone
, instdone
,
1990 sizeof(instdone
)) == 0) {
1991 if (i915_hangcheck_hung(dev
))
1994 dev_priv
->gpu_error
.hangcheck_count
= 0;
1996 memcpy(dev_priv
->gpu_error
.last_acthd
, acthd
,
1998 memcpy(dev_priv
->gpu_error
.prev_instdone
, instdone
,
2003 /* Reset timer case chip hangs without another request being added */
2004 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2005 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2010 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2012 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2014 atomic_set(&dev_priv
->irq_received
, 0);
2016 I915_WRITE(HWSTAM
, 0xeffe);
2018 /* XXX hotplug from PCH */
2020 I915_WRITE(DEIMR
, 0xffffffff);
2021 I915_WRITE(DEIER
, 0x0);
2022 POSTING_READ(DEIER
);
2025 I915_WRITE(GTIMR
, 0xffffffff);
2026 I915_WRITE(GTIER
, 0x0);
2027 POSTING_READ(GTIER
);
2029 /* south display irq */
2030 I915_WRITE(SDEIMR
, 0xffffffff);
2032 * SDEIER is also touched by the interrupt handler to work around missed
2033 * PCH interrupts. Hence we can't update it after the interrupt handler
2034 * is enabled - instead we unconditionally enable all PCH interrupt
2035 * sources here, but then only unmask them as needed with SDEIMR.
2037 I915_WRITE(SDEIER
, 0xffffffff);
2038 POSTING_READ(SDEIER
);
2041 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2043 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2046 atomic_set(&dev_priv
->irq_received
, 0);
2049 I915_WRITE(VLV_IMR
, 0);
2050 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2051 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2052 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2055 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2056 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2057 I915_WRITE(GTIMR
, 0xffffffff);
2058 I915_WRITE(GTIER
, 0x0);
2059 POSTING_READ(GTIER
);
2061 I915_WRITE(DPINVGTT
, 0xff);
2063 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2064 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2066 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2067 I915_WRITE(VLV_IIR
, 0xffffffff);
2068 I915_WRITE(VLV_IMR
, 0xffffffff);
2069 I915_WRITE(VLV_IER
, 0x0);
2070 POSTING_READ(VLV_IER
);
2073 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2075 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2076 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2077 struct intel_encoder
*intel_encoder
;
2078 u32 mask
= ~I915_READ(SDEIMR
);
2081 if (HAS_PCH_IBX(dev
)) {
2082 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2083 mask
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2085 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2086 mask
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2089 I915_WRITE(SDEIMR
, ~mask
);
2092 * Enable digital hotplug on the PCH, and configure the DP short pulse
2093 * duration to 2ms (which is the minimum in the Display Port spec)
2095 * This register is the same on all known PCH chips.
2097 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2098 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2099 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2100 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2101 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2102 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2105 static void ibx_irq_postinstall(struct drm_device
*dev
)
2107 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2110 if (HAS_PCH_IBX(dev
))
2111 mask
= SDE_GMBUS
| SDE_AUX_MASK
;
2113 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
2114 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2115 I915_WRITE(SDEIMR
, ~mask
);
2118 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2120 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2121 /* enable kind of interrupts always enabled */
2122 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2123 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2127 dev_priv
->irq_mask
= ~display_mask
;
2129 /* should always can generate irq */
2130 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2131 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2132 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
2133 POSTING_READ(DEIER
);
2135 dev_priv
->gt_irq_mask
= ~0;
2137 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2138 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2143 GEN6_BSD_USER_INTERRUPT
|
2144 GEN6_BLITTER_USER_INTERRUPT
;
2149 GT_BSD_USER_INTERRUPT
;
2150 I915_WRITE(GTIER
, render_irqs
);
2151 POSTING_READ(GTIER
);
2153 ibx_irq_postinstall(dev
);
2155 if (IS_IRONLAKE_M(dev
)) {
2156 /* Clear & enable PCU event interrupts */
2157 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2158 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
2159 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2165 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2167 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2168 /* enable kind of interrupts always enabled */
2170 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2171 DE_PLANEC_FLIP_DONE_IVB
|
2172 DE_PLANEB_FLIP_DONE_IVB
|
2173 DE_PLANEA_FLIP_DONE_IVB
|
2174 DE_AUX_CHANNEL_A_IVB
;
2177 dev_priv
->irq_mask
= ~display_mask
;
2179 /* should always can generate irq */
2180 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2181 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2184 DE_PIPEC_VBLANK_IVB
|
2185 DE_PIPEB_VBLANK_IVB
|
2186 DE_PIPEA_VBLANK_IVB
);
2187 POSTING_READ(DEIER
);
2189 dev_priv
->gt_irq_mask
= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
2191 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2192 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2194 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
2195 GEN6_BLITTER_USER_INTERRUPT
| GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
2196 I915_WRITE(GTIER
, render_irqs
);
2197 POSTING_READ(GTIER
);
2199 ibx_irq_postinstall(dev
);
2204 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2206 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2208 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2212 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2213 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2214 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2215 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2216 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2219 *Leave vblank interrupts masked initially. enable/disable will
2220 * toggle them based on usage.
2222 dev_priv
->irq_mask
= (~enable_mask
) |
2223 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2224 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2226 /* Hack for broken MSIs on VLV */
2227 pci_write_config_dword(dev_priv
->dev
->pdev
, 0x94, 0xfee00000);
2228 pci_read_config_word(dev
->pdev
, 0x98, &msid
);
2229 msid
&= 0xff; /* mask out delivery bits */
2231 pci_write_config_word(dev_priv
->dev
->pdev
, 0x98, msid
);
2233 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2234 POSTING_READ(PORT_HOTPLUG_EN
);
2236 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2237 I915_WRITE(VLV_IER
, enable_mask
);
2238 I915_WRITE(VLV_IIR
, 0xffffffff);
2239 I915_WRITE(PIPESTAT(0), 0xffff);
2240 I915_WRITE(PIPESTAT(1), 0xffff);
2241 POSTING_READ(VLV_IER
);
2243 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2244 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2245 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2247 I915_WRITE(VLV_IIR
, 0xffffffff);
2248 I915_WRITE(VLV_IIR
, 0xffffffff);
2250 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2251 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2253 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
2254 GEN6_BLITTER_USER_INTERRUPT
;
2255 I915_WRITE(GTIER
, render_irqs
);
2256 POSTING_READ(GTIER
);
2258 /* ack & enable invalid PTE error interrupts */
2259 #if 0 /* FIXME: add support to irq handler for checking these bits */
2260 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2261 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2264 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2269 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2271 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2278 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2280 I915_WRITE(HWSTAM
, 0xffffffff);
2281 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2282 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2284 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2285 I915_WRITE(VLV_IIR
, 0xffffffff);
2286 I915_WRITE(VLV_IMR
, 0xffffffff);
2287 I915_WRITE(VLV_IER
, 0x0);
2288 POSTING_READ(VLV_IER
);
2291 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2293 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2298 I915_WRITE(HWSTAM
, 0xffffffff);
2300 I915_WRITE(DEIMR
, 0xffffffff);
2301 I915_WRITE(DEIER
, 0x0);
2302 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2304 I915_WRITE(GTIMR
, 0xffffffff);
2305 I915_WRITE(GTIER
, 0x0);
2306 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2308 I915_WRITE(SDEIMR
, 0xffffffff);
2309 I915_WRITE(SDEIER
, 0x0);
2310 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2313 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2315 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2318 atomic_set(&dev_priv
->irq_received
, 0);
2321 I915_WRITE(PIPESTAT(pipe
), 0);
2322 I915_WRITE16(IMR
, 0xffff);
2323 I915_WRITE16(IER
, 0x0);
2324 POSTING_READ16(IER
);
2327 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2329 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2332 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2334 /* Unmask the interrupts that we always want on. */
2335 dev_priv
->irq_mask
=
2336 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2337 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2338 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2339 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2340 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2341 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2344 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2345 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2346 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2347 I915_USER_INTERRUPT
);
2348 POSTING_READ16(IER
);
2354 * Returns true when a page flip has completed.
2356 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2359 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2360 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2362 if (!drm_handle_vblank(dev
, pipe
))
2365 if ((iir
& flip_pending
) == 0)
2368 intel_prepare_page_flip(dev
, pipe
);
2370 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2371 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2372 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2373 * the flip is completed (no longer pending). Since this doesn't raise
2374 * an interrupt per se, we watch for the change at vblank.
2376 if (I915_READ16(ISR
) & flip_pending
)
2379 intel_finish_page_flip(dev
, pipe
);
2384 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2386 struct drm_device
*dev
= (struct drm_device
*) arg
;
2387 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2390 unsigned long irqflags
;
2394 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2395 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2397 atomic_inc(&dev_priv
->irq_received
);
2399 iir
= I915_READ16(IIR
);
2403 while (iir
& ~flip_mask
) {
2404 /* Can't rely on pipestat interrupt bit in iir as it might
2405 * have been cleared after the pipestat interrupt was received.
2406 * It doesn't set the bit in iir again, but it still produces
2407 * interrupts (for non-MSI).
2409 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2410 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2411 i915_handle_error(dev
, false);
2413 for_each_pipe(pipe
) {
2414 int reg
= PIPESTAT(pipe
);
2415 pipe_stats
[pipe
] = I915_READ(reg
);
2418 * Clear the PIPE*STAT regs before the IIR
2420 if (pipe_stats
[pipe
] & 0x8000ffff) {
2421 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2422 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2424 I915_WRITE(reg
, pipe_stats
[pipe
]);
2428 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2430 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2431 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2433 i915_update_dri1_breadcrumb(dev
);
2435 if (iir
& I915_USER_INTERRUPT
)
2436 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2438 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2439 i8xx_handle_vblank(dev
, 0, iir
))
2440 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2442 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2443 i8xx_handle_vblank(dev
, 1, iir
))
2444 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2452 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2454 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2457 for_each_pipe(pipe
) {
2458 /* Clear enable bits; then clear status bits */
2459 I915_WRITE(PIPESTAT(pipe
), 0);
2460 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2462 I915_WRITE16(IMR
, 0xffff);
2463 I915_WRITE16(IER
, 0x0);
2464 I915_WRITE16(IIR
, I915_READ16(IIR
));
2467 static void i915_irq_preinstall(struct drm_device
* dev
)
2469 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2472 atomic_set(&dev_priv
->irq_received
, 0);
2474 if (I915_HAS_HOTPLUG(dev
)) {
2475 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2476 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2479 I915_WRITE16(HWSTAM
, 0xeffe);
2481 I915_WRITE(PIPESTAT(pipe
), 0);
2482 I915_WRITE(IMR
, 0xffffffff);
2483 I915_WRITE(IER
, 0x0);
2487 static int i915_irq_postinstall(struct drm_device
*dev
)
2489 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2492 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2494 /* Unmask the interrupts that we always want on. */
2495 dev_priv
->irq_mask
=
2496 ~(I915_ASLE_INTERRUPT
|
2497 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2498 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2499 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2500 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2501 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2504 I915_ASLE_INTERRUPT
|
2505 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2506 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2507 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2508 I915_USER_INTERRUPT
;
2510 if (I915_HAS_HOTPLUG(dev
)) {
2511 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2512 POSTING_READ(PORT_HOTPLUG_EN
);
2514 /* Enable in IER... */
2515 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2516 /* and unmask in IMR */
2517 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2520 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2521 I915_WRITE(IER
, enable_mask
);
2524 intel_opregion_enable_asle(dev
);
2529 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2531 if (I915_HAS_HOTPLUG(dev
)) {
2532 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2533 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2534 struct intel_encoder
*encoder
;
2535 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2537 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2538 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
2539 hotplug_en
|= hpd_mask_i915
[encoder
->hpd_pin
];
2540 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2542 /* Ignore TV since it's buggy */
2544 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2549 * Returns true when a page flip has completed.
2551 static bool i915_handle_vblank(struct drm_device
*dev
,
2552 int plane
, int pipe
, u32 iir
)
2554 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2555 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2557 if (!drm_handle_vblank(dev
, pipe
))
2560 if ((iir
& flip_pending
) == 0)
2563 intel_prepare_page_flip(dev
, plane
);
2565 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2566 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2567 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2568 * the flip is completed (no longer pending). Since this doesn't raise
2569 * an interrupt per se, we watch for the change at vblank.
2571 if (I915_READ(ISR
) & flip_pending
)
2574 intel_finish_page_flip(dev
, pipe
);
2579 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2581 struct drm_device
*dev
= (struct drm_device
*) arg
;
2582 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2583 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2584 unsigned long irqflags
;
2586 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2587 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2588 int pipe
, ret
= IRQ_NONE
;
2590 atomic_inc(&dev_priv
->irq_received
);
2592 iir
= I915_READ(IIR
);
2594 bool irq_received
= (iir
& ~flip_mask
) != 0;
2595 bool blc_event
= false;
2597 /* Can't rely on pipestat interrupt bit in iir as it might
2598 * have been cleared after the pipestat interrupt was received.
2599 * It doesn't set the bit in iir again, but it still produces
2600 * interrupts (for non-MSI).
2602 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2603 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2604 i915_handle_error(dev
, false);
2606 for_each_pipe(pipe
) {
2607 int reg
= PIPESTAT(pipe
);
2608 pipe_stats
[pipe
] = I915_READ(reg
);
2610 /* Clear the PIPE*STAT regs before the IIR */
2611 if (pipe_stats
[pipe
] & 0x8000ffff) {
2612 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2613 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2615 I915_WRITE(reg
, pipe_stats
[pipe
]);
2616 irq_received
= true;
2619 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2624 /* Consume port. Then clear IIR or we'll miss events */
2625 if ((I915_HAS_HOTPLUG(dev
)) &&
2626 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2627 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2629 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2631 if (hotplug_status
& HOTPLUG_INT_STATUS_I915
)
2632 queue_work(dev_priv
->wq
,
2633 &dev_priv
->hotplug_work
);
2635 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2636 POSTING_READ(PORT_HOTPLUG_STAT
);
2639 I915_WRITE(IIR
, iir
& ~flip_mask
);
2640 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2642 if (iir
& I915_USER_INTERRUPT
)
2643 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2645 for_each_pipe(pipe
) {
2650 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2651 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2652 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2654 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2658 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2659 intel_opregion_asle_intr(dev
);
2661 /* With MSI, interrupts are only generated when iir
2662 * transitions from zero to nonzero. If another bit got
2663 * set while we were handling the existing iir bits, then
2664 * we would never get another interrupt.
2666 * This is fine on non-MSI as well, as if we hit this path
2667 * we avoid exiting the interrupt handler only to generate
2670 * Note that for MSI this could cause a stray interrupt report
2671 * if an interrupt landed in the time between writing IIR and
2672 * the posting read. This should be rare enough to never
2673 * trigger the 99% of 100,000 interrupts test for disabling
2678 } while (iir
& ~flip_mask
);
2680 i915_update_dri1_breadcrumb(dev
);
2685 static void i915_irq_uninstall(struct drm_device
* dev
)
2687 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2690 if (I915_HAS_HOTPLUG(dev
)) {
2691 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2692 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2695 I915_WRITE16(HWSTAM
, 0xffff);
2696 for_each_pipe(pipe
) {
2697 /* Clear enable bits; then clear status bits */
2698 I915_WRITE(PIPESTAT(pipe
), 0);
2699 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2701 I915_WRITE(IMR
, 0xffffffff);
2702 I915_WRITE(IER
, 0x0);
2704 I915_WRITE(IIR
, I915_READ(IIR
));
2707 static void i965_irq_preinstall(struct drm_device
* dev
)
2709 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2712 atomic_set(&dev_priv
->irq_received
, 0);
2714 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2715 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2717 I915_WRITE(HWSTAM
, 0xeffe);
2719 I915_WRITE(PIPESTAT(pipe
), 0);
2720 I915_WRITE(IMR
, 0xffffffff);
2721 I915_WRITE(IER
, 0x0);
2725 static int i965_irq_postinstall(struct drm_device
*dev
)
2727 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2731 /* Unmask the interrupts that we always want on. */
2732 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2733 I915_DISPLAY_PORT_INTERRUPT
|
2734 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2735 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2736 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2737 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2738 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2740 enable_mask
= ~dev_priv
->irq_mask
;
2741 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2742 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2743 enable_mask
|= I915_USER_INTERRUPT
;
2746 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2748 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2751 * Enable some error detection, note the instruction error mask
2752 * bit is reserved, so we leave it masked.
2755 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2756 GM45_ERROR_MEM_PRIV
|
2757 GM45_ERROR_CP_PRIV
|
2758 I915_ERROR_MEMORY_REFRESH
);
2760 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2761 I915_ERROR_MEMORY_REFRESH
);
2763 I915_WRITE(EMR
, error_mask
);
2765 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2766 I915_WRITE(IER
, enable_mask
);
2769 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2770 POSTING_READ(PORT_HOTPLUG_EN
);
2772 intel_opregion_enable_asle(dev
);
2777 static void i965_hpd_irq_setup(struct drm_device
*dev
)
2779 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2780 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2781 struct intel_encoder
*encoder
;
2784 /* Note HDMI and DP share hotplug bits */
2786 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
2787 /* enable bits are the same for all generations */
2788 hotplug_en
|= hpd_mask_i915
[encoder
->hpd_pin
];
2789 /* Programming the CRT detection parameters tends
2790 to generate a spurious hotplug event about three
2791 seconds later. So just do it once.
2794 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2795 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2797 /* Ignore TV since it's buggy */
2799 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2802 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2804 struct drm_device
*dev
= (struct drm_device
*) arg
;
2805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2807 u32 pipe_stats
[I915_MAX_PIPES
];
2808 unsigned long irqflags
;
2810 int ret
= IRQ_NONE
, pipe
;
2812 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2813 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2815 atomic_inc(&dev_priv
->irq_received
);
2817 iir
= I915_READ(IIR
);
2820 bool blc_event
= false;
2822 irq_received
= (iir
& ~flip_mask
) != 0;
2824 /* Can't rely on pipestat interrupt bit in iir as it might
2825 * have been cleared after the pipestat interrupt was received.
2826 * It doesn't set the bit in iir again, but it still produces
2827 * interrupts (for non-MSI).
2829 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2830 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2831 i915_handle_error(dev
, false);
2833 for_each_pipe(pipe
) {
2834 int reg
= PIPESTAT(pipe
);
2835 pipe_stats
[pipe
] = I915_READ(reg
);
2838 * Clear the PIPE*STAT regs before the IIR
2840 if (pipe_stats
[pipe
] & 0x8000ffff) {
2841 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2842 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2844 I915_WRITE(reg
, pipe_stats
[pipe
]);
2848 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2855 /* Consume port. Then clear IIR or we'll miss events */
2856 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2857 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2859 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2861 if (hotplug_status
& (IS_G4X(dev
) ?
2862 HOTPLUG_INT_STATUS_G4X
:
2863 HOTPLUG_INT_STATUS_I965
))
2864 queue_work(dev_priv
->wq
,
2865 &dev_priv
->hotplug_work
);
2867 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2868 I915_READ(PORT_HOTPLUG_STAT
);
2871 I915_WRITE(IIR
, iir
& ~flip_mask
);
2872 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2874 if (iir
& I915_USER_INTERRUPT
)
2875 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2876 if (iir
& I915_BSD_USER_INTERRUPT
)
2877 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2879 for_each_pipe(pipe
) {
2880 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2881 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2882 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2884 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2889 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2890 intel_opregion_asle_intr(dev
);
2892 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2893 gmbus_irq_handler(dev
);
2895 /* With MSI, interrupts are only generated when iir
2896 * transitions from zero to nonzero. If another bit got
2897 * set while we were handling the existing iir bits, then
2898 * we would never get another interrupt.
2900 * This is fine on non-MSI as well, as if we hit this path
2901 * we avoid exiting the interrupt handler only to generate
2904 * Note that for MSI this could cause a stray interrupt report
2905 * if an interrupt landed in the time between writing IIR and
2906 * the posting read. This should be rare enough to never
2907 * trigger the 99% of 100,000 interrupts test for disabling
2913 i915_update_dri1_breadcrumb(dev
);
2918 static void i965_irq_uninstall(struct drm_device
* dev
)
2920 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2926 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2927 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2929 I915_WRITE(HWSTAM
, 0xffffffff);
2931 I915_WRITE(PIPESTAT(pipe
), 0);
2932 I915_WRITE(IMR
, 0xffffffff);
2933 I915_WRITE(IER
, 0x0);
2936 I915_WRITE(PIPESTAT(pipe
),
2937 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2938 I915_WRITE(IIR
, I915_READ(IIR
));
2941 void intel_irq_init(struct drm_device
*dev
)
2943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2945 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
2946 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
2947 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
2948 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
2950 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2951 i915_hangcheck_elapsed
,
2952 (unsigned long) dev
);
2954 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
2956 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2957 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2958 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
2959 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2960 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2963 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
2964 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
2966 dev
->driver
->get_vblank_timestamp
= NULL
;
2967 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
2969 if (IS_VALLEYVIEW(dev
)) {
2970 dev
->driver
->irq_handler
= valleyview_irq_handler
;
2971 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
2972 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
2973 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
2974 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
2975 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
2976 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
2977 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
2978 /* Share pre & uninstall handlers with ILK/SNB */
2979 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2980 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2981 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2982 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2983 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2984 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2985 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
2986 } else if (HAS_PCH_SPLIT(dev
)) {
2987 dev
->driver
->irq_handler
= ironlake_irq_handler
;
2988 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2989 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
2990 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2991 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
2992 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
2993 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
2995 if (INTEL_INFO(dev
)->gen
== 2) {
2996 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
2997 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
2998 dev
->driver
->irq_handler
= i8xx_irq_handler
;
2999 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3000 } else if (INTEL_INFO(dev
)->gen
== 3) {
3001 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3002 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3003 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3004 dev
->driver
->irq_handler
= i915_irq_handler
;
3005 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3007 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3008 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3009 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3010 dev
->driver
->irq_handler
= i965_irq_handler
;
3011 dev_priv
->display
.hpd_irq_setup
= i965_hpd_irq_setup
;
3013 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3014 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3018 void intel_hpd_init(struct drm_device
*dev
)
3020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 if (dev_priv
->display
.hpd_irq_setup
)
3023 dev_priv
->display
.hpd_irq_setup(dev
);