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Merge remote-tracking branch 'airlied/drm-next' into HEAD
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 static bool cpt_can_enable_serr_int(struct drm_device *dev)
252 {
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 enum pipe pipe;
255 struct intel_crtc *crtc;
256
257 assert_spin_locked(&dev_priv->irq_lock);
258
259 for_each_pipe(pipe) {
260 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
261
262 if (crtc->pch_fifo_underrun_disabled)
263 return false;
264 }
265
266 return true;
267 }
268
269 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
270 {
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 u32 reg = PIPESTAT(pipe);
273 u32 pipestat = I915_READ(reg) & 0x7fff0000;
274
275 assert_spin_locked(&dev_priv->irq_lock);
276
277 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
278 POSTING_READ(reg);
279 }
280
281 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
282 enum pipe pipe, bool enable)
283 {
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
286 DE_PIPEB_FIFO_UNDERRUN;
287
288 if (enable)
289 ironlake_enable_display_irq(dev_priv, bit);
290 else
291 ironlake_disable_display_irq(dev_priv, bit);
292 }
293
294 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
295 enum pipe pipe, bool enable)
296 {
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 if (enable) {
299 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
300
301 if (!ivb_can_enable_err_int(dev))
302 return;
303
304 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
305 } else {
306 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
307
308 /* Change the state _after_ we've read out the current one. */
309 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
310
311 if (!was_enabled &&
312 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
313 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
314 pipe_name(pipe));
315 }
316 }
317 }
318
319 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum pipe pipe, bool enable)
321 {
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 assert_spin_locked(&dev_priv->irq_lock);
325
326 if (enable)
327 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
328 else
329 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
330 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
331 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
332 }
333
334 /**
335 * ibx_display_interrupt_update - update SDEIMR
336 * @dev_priv: driver private
337 * @interrupt_mask: mask of interrupt bits to update
338 * @enabled_irq_mask: mask of interrupt bits to enable
339 */
340 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
341 uint32_t interrupt_mask,
342 uint32_t enabled_irq_mask)
343 {
344 uint32_t sdeimr = I915_READ(SDEIMR);
345 sdeimr &= ~interrupt_mask;
346 sdeimr |= (~enabled_irq_mask & interrupt_mask);
347
348 assert_spin_locked(&dev_priv->irq_lock);
349
350 if (WARN_ON(dev_priv->pm.irqs_disabled))
351 return;
352
353 I915_WRITE(SDEIMR, sdeimr);
354 POSTING_READ(SDEIMR);
355 }
356 #define ibx_enable_display_interrupt(dev_priv, bits) \
357 ibx_display_interrupt_update((dev_priv), (bits), (bits))
358 #define ibx_disable_display_interrupt(dev_priv, bits) \
359 ibx_display_interrupt_update((dev_priv), (bits), 0)
360
361 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
362 enum transcoder pch_transcoder,
363 bool enable)
364 {
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
367 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
368
369 if (enable)
370 ibx_enable_display_interrupt(dev_priv, bit);
371 else
372 ibx_disable_display_interrupt(dev_priv, bit);
373 }
374
375 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
376 enum transcoder pch_transcoder,
377 bool enable)
378 {
379 struct drm_i915_private *dev_priv = dev->dev_private;
380
381 if (enable) {
382 I915_WRITE(SERR_INT,
383 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
384
385 if (!cpt_can_enable_serr_int(dev))
386 return;
387
388 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
389 } else {
390 uint32_t tmp = I915_READ(SERR_INT);
391 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
392
393 /* Change the state _after_ we've read out the current one. */
394 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
395
396 if (!was_enabled &&
397 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
398 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
399 transcoder_name(pch_transcoder));
400 }
401 }
402 }
403
404 /**
405 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
406 * @dev: drm device
407 * @pipe: pipe
408 * @enable: true if we want to report FIFO underrun errors, false otherwise
409 *
410 * This function makes us disable or enable CPU fifo underruns for a specific
411 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
412 * reporting for one pipe may also disable all the other CPU error interruts for
413 * the other pipes, due to the fact that there's just one interrupt mask/enable
414 * bit for all the pipes.
415 *
416 * Returns the previous state of underrun reporting.
417 */
418 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
419 enum pipe pipe, bool enable)
420 {
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
424 bool ret;
425
426 assert_spin_locked(&dev_priv->irq_lock);
427
428 ret = !intel_crtc->cpu_fifo_underrun_disabled;
429
430 if (enable == ret)
431 goto done;
432
433 intel_crtc->cpu_fifo_underrun_disabled = !enable;
434
435 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
436 i9xx_clear_fifo_underrun(dev, pipe);
437 else if (IS_GEN5(dev) || IS_GEN6(dev))
438 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
439 else if (IS_GEN7(dev))
440 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
441 else if (IS_GEN8(dev))
442 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
443
444 done:
445 return ret;
446 }
447
448 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
449 enum pipe pipe, bool enable)
450 {
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 unsigned long flags;
453 bool ret;
454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
457 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
458
459 return ret;
460 }
461
462 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
463 enum pipe pipe)
464 {
465 struct drm_i915_private *dev_priv = dev->dev_private;
466 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
468
469 return !intel_crtc->cpu_fifo_underrun_disabled;
470 }
471
472 /**
473 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
474 * @dev: drm device
475 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
476 * @enable: true if we want to report FIFO underrun errors, false otherwise
477 *
478 * This function makes us disable or enable PCH fifo underruns for a specific
479 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
480 * underrun reporting for one transcoder may also disable all the other PCH
481 * error interruts for the other transcoders, due to the fact that there's just
482 * one interrupt mask/enable bit for all the transcoders.
483 *
484 * Returns the previous state of underrun reporting.
485 */
486 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
487 enum transcoder pch_transcoder,
488 bool enable)
489 {
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 unsigned long flags;
494 bool ret;
495
496 /*
497 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
498 * has only one pch transcoder A that all pipes can use. To avoid racy
499 * pch transcoder -> pipe lookups from interrupt code simply store the
500 * underrun statistics in crtc A. Since we never expose this anywhere
501 * nor use it outside of the fifo underrun code here using the "wrong"
502 * crtc on LPT won't cause issues.
503 */
504
505 spin_lock_irqsave(&dev_priv->irq_lock, flags);
506
507 ret = !intel_crtc->pch_fifo_underrun_disabled;
508
509 if (enable == ret)
510 goto done;
511
512 intel_crtc->pch_fifo_underrun_disabled = !enable;
513
514 if (HAS_PCH_IBX(dev))
515 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
516 else
517 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
518
519 done:
520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
521 return ret;
522 }
523
524
525 static void
526 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
527 u32 enable_mask, u32 status_mask)
528 {
529 u32 reg = PIPESTAT(pipe);
530 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
531
532 assert_spin_locked(&dev_priv->irq_lock);
533
534 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe), enable_mask, status_mask))
538 return;
539
540 if ((pipestat & enable_mask) == enable_mask)
541 return;
542
543 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
544
545 /* Enable the interrupt, clear any pending status */
546 pipestat |= enable_mask | status_mask;
547 I915_WRITE(reg, pipestat);
548 POSTING_READ(reg);
549 }
550
551 static void
552 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
553 u32 enable_mask, u32 status_mask)
554 {
555 u32 reg = PIPESTAT(pipe);
556 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
557
558 assert_spin_locked(&dev_priv->irq_lock);
559
560 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
561 status_mask & ~PIPESTAT_INT_STATUS_MASK,
562 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
563 pipe_name(pipe), enable_mask, status_mask))
564 return;
565
566 if ((pipestat & enable_mask) == 0)
567 return;
568
569 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
570
571 pipestat &= ~enable_mask;
572 I915_WRITE(reg, pipestat);
573 POSTING_READ(reg);
574 }
575
576 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
577 {
578 u32 enable_mask = status_mask << 16;
579
580 /*
581 * On pipe A we don't support the PSR interrupt yet, on pipe B the
582 * same bit MBZ.
583 */
584 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
585 return 0;
586
587 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
588 SPRITE0_FLIP_DONE_INT_EN_VLV |
589 SPRITE1_FLIP_DONE_INT_EN_VLV);
590 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
591 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
592 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
593 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
594
595 return enable_mask;
596 }
597
598 void
599 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
600 u32 status_mask)
601 {
602 u32 enable_mask;
603
604 if (IS_VALLEYVIEW(dev_priv->dev))
605 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
606 status_mask);
607 else
608 enable_mask = status_mask << 16;
609 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
610 }
611
612 void
613 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
614 u32 status_mask)
615 {
616 u32 enable_mask;
617
618 if (IS_VALLEYVIEW(dev_priv->dev))
619 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
620 status_mask);
621 else
622 enable_mask = status_mask << 16;
623 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
624 }
625
626 /**
627 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
628 */
629 static void i915_enable_asle_pipestat(struct drm_device *dev)
630 {
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 unsigned long irqflags;
633
634 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
635 return;
636
637 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
638
639 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
640 if (INTEL_INFO(dev)->gen >= 4)
641 i915_enable_pipestat(dev_priv, PIPE_A,
642 PIPE_LEGACY_BLC_EVENT_STATUS);
643
644 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
645 }
646
647 /**
648 * i915_pipe_enabled - check if a pipe is enabled
649 * @dev: DRM device
650 * @pipe: pipe to check
651 *
652 * Reading certain registers when the pipe is disabled can hang the chip.
653 * Use this routine to make sure the PLL is running and the pipe is active
654 * before reading such registers if unsure.
655 */
656 static int
657 i915_pipe_enabled(struct drm_device *dev, int pipe)
658 {
659 struct drm_i915_private *dev_priv = dev->dev_private;
660
661 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
662 /* Locking is horribly broken here, but whatever. */
663 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
665
666 return intel_crtc->active;
667 } else {
668 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
669 }
670 }
671
672 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
673 {
674 /* Gen2 doesn't have a hardware frame counter */
675 return 0;
676 }
677
678 /* Called from drm generic code, passed a 'crtc', which
679 * we use as a pipe index
680 */
681 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
682 {
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 unsigned long high_frame;
685 unsigned long low_frame;
686 u32 high1, high2, low, pixel, vbl_start;
687
688 if (!i915_pipe_enabled(dev, pipe)) {
689 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
690 "pipe %c\n", pipe_name(pipe));
691 return 0;
692 }
693
694 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
695 struct intel_crtc *intel_crtc =
696 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
697 const struct drm_display_mode *mode =
698 &intel_crtc->config.adjusted_mode;
699
700 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
701 } else {
702 enum transcoder cpu_transcoder = (enum transcoder) pipe;
703 u32 htotal;
704
705 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
706 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
707
708 vbl_start *= htotal;
709 }
710
711 high_frame = PIPEFRAME(pipe);
712 low_frame = PIPEFRAMEPIXEL(pipe);
713
714 /*
715 * High & low register fields aren't synchronized, so make sure
716 * we get a low value that's stable across two reads of the high
717 * register.
718 */
719 do {
720 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
721 low = I915_READ(low_frame);
722 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
723 } while (high1 != high2);
724
725 high1 >>= PIPE_FRAME_HIGH_SHIFT;
726 pixel = low & PIPE_PIXEL_MASK;
727 low >>= PIPE_FRAME_LOW_SHIFT;
728
729 /*
730 * The frame counter increments at beginning of active.
731 * Cook up a vblank counter by also checking the pixel
732 * counter against vblank start.
733 */
734 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
735 }
736
737 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
738 {
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 int reg = PIPE_FRMCOUNT_GM45(pipe);
741
742 if (!i915_pipe_enabled(dev, pipe)) {
743 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
744 "pipe %c\n", pipe_name(pipe));
745 return 0;
746 }
747
748 return I915_READ(reg);
749 }
750
751 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
752 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
753
754 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
755 {
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 uint32_t status;
758 int reg;
759
760 if (INTEL_INFO(dev)->gen >= 8) {
761 status = GEN8_PIPE_VBLANK;
762 reg = GEN8_DE_PIPE_ISR(pipe);
763 } else if (INTEL_INFO(dev)->gen >= 7) {
764 status = DE_PIPE_VBLANK_IVB(pipe);
765 reg = DEISR;
766 } else {
767 status = DE_PIPE_VBLANK(pipe);
768 reg = DEISR;
769 }
770
771 return __raw_i915_read32(dev_priv, reg) & status;
772 }
773
774 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
775 unsigned int flags, int *vpos, int *hpos,
776 ktime_t *stime, ktime_t *etime)
777 {
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
781 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
782 int position;
783 int vbl_start, vbl_end, htotal, vtotal;
784 bool in_vbl = true;
785 int ret = 0;
786 unsigned long irqflags;
787
788 if (!intel_crtc->active) {
789 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
790 "pipe %c\n", pipe_name(pipe));
791 return 0;
792 }
793
794 htotal = mode->crtc_htotal;
795 vtotal = mode->crtc_vtotal;
796 vbl_start = mode->crtc_vblank_start;
797 vbl_end = mode->crtc_vblank_end;
798
799 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
800 vbl_start = DIV_ROUND_UP(vbl_start, 2);
801 vbl_end /= 2;
802 vtotal /= 2;
803 }
804
805 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
806
807 /*
808 * Lock uncore.lock, as we will do multiple timing critical raw
809 * register reads, potentially with preemption disabled, so the
810 * following code must not block on uncore.lock.
811 */
812 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
813
814 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815
816 /* Get optional system timestamp before query. */
817 if (stime)
818 *stime = ktime_get();
819
820 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
821 /* No obvious pixelcount register. Only query vertical
822 * scanout position from Display scan line register.
823 */
824 if (IS_GEN2(dev))
825 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
826 else
827 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
828
829 if (HAS_DDI(dev)) {
830 /*
831 * On HSW HDMI outputs there seems to be a 2 line
832 * difference, whereas eDP has the normal 1 line
833 * difference that earlier platforms have. External
834 * DP is unknown. For now just check for the 2 line
835 * difference case on all output types on HSW+.
836 *
837 * This might misinterpret the scanline counter being
838 * one line too far along on eDP, but that's less
839 * dangerous than the alternative since that would lead
840 * the vblank timestamp code astray when it sees a
841 * scanline count before vblank_start during a vblank
842 * interrupt.
843 */
844 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
845 if ((in_vbl && (position == vbl_start - 2 ||
846 position == vbl_start - 1)) ||
847 (!in_vbl && (position == vbl_end - 2 ||
848 position == vbl_end - 1)))
849 position = (position + 2) % vtotal;
850 } else if (HAS_PCH_SPLIT(dev)) {
851 /*
852 * The scanline counter increments at the leading edge
853 * of hsync, ie. it completely misses the active portion
854 * of the line. Fix up the counter at both edges of vblank
855 * to get a more accurate picture whether we're in vblank
856 * or not.
857 */
858 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
859 if ((in_vbl && position == vbl_start - 1) ||
860 (!in_vbl && position == vbl_end - 1))
861 position = (position + 1) % vtotal;
862 } else {
863 /*
864 * ISR vblank status bits don't work the way we'd want
865 * them to work on non-PCH platforms (for
866 * ilk_pipe_in_vblank_locked()), and there doesn't
867 * appear any other way to determine if we're currently
868 * in vblank.
869 *
870 * Instead let's assume that we're already in vblank if
871 * we got called from the vblank interrupt and the
872 * scanline counter value indicates that we're on the
873 * line just prior to vblank start. This should result
874 * in the correct answer, unless the vblank interrupt
875 * delivery really got delayed for almost exactly one
876 * full frame/field.
877 */
878 if (flags & DRM_CALLED_FROM_VBLIRQ &&
879 position == vbl_start - 1) {
880 position = (position + 1) % vtotal;
881
882 /* Signal this correction as "applied". */
883 ret |= 0x8;
884 }
885 }
886 } else {
887 /* Have access to pixelcount since start of frame.
888 * We can split this into vertical and horizontal
889 * scanout position.
890 */
891 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
892
893 /* convert to pixel counts */
894 vbl_start *= htotal;
895 vbl_end *= htotal;
896 vtotal *= htotal;
897 }
898
899 /* Get optional system timestamp after query. */
900 if (etime)
901 *etime = ktime_get();
902
903 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
904
905 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
906
907 in_vbl = position >= vbl_start && position < vbl_end;
908
909 /*
910 * While in vblank, position will be negative
911 * counting up towards 0 at vbl_end. And outside
912 * vblank, position will be positive counting
913 * up since vbl_end.
914 */
915 if (position >= vbl_start)
916 position -= vbl_end;
917 else
918 position += vtotal - vbl_end;
919
920 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 *vpos = position;
922 *hpos = 0;
923 } else {
924 *vpos = position / htotal;
925 *hpos = position - (*vpos * htotal);
926 }
927
928 /* In vblank? */
929 if (in_vbl)
930 ret |= DRM_SCANOUTPOS_INVBL;
931
932 return ret;
933 }
934
935 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
936 int *max_error,
937 struct timeval *vblank_time,
938 unsigned flags)
939 {
940 struct drm_crtc *crtc;
941
942 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
943 DRM_ERROR("Invalid crtc %d\n", pipe);
944 return -EINVAL;
945 }
946
947 /* Get drm_crtc to timestamp: */
948 crtc = intel_get_crtc_for_pipe(dev, pipe);
949 if (crtc == NULL) {
950 DRM_ERROR("Invalid crtc %d\n", pipe);
951 return -EINVAL;
952 }
953
954 if (!crtc->enabled) {
955 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
956 return -EBUSY;
957 }
958
959 /* Helper routine in DRM core does all the work: */
960 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
961 vblank_time, flags,
962 crtc,
963 &to_intel_crtc(crtc)->config.adjusted_mode);
964 }
965
966 static bool intel_hpd_irq_event(struct drm_device *dev,
967 struct drm_connector *connector)
968 {
969 enum drm_connector_status old_status;
970
971 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
972 old_status = connector->status;
973
974 connector->status = connector->funcs->detect(connector, false);
975 if (old_status == connector->status)
976 return false;
977
978 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
979 connector->base.id,
980 drm_get_connector_name(connector),
981 drm_get_connector_status_name(old_status),
982 drm_get_connector_status_name(connector->status));
983
984 return true;
985 }
986
987 /*
988 * Handle hotplug events outside the interrupt handler proper.
989 */
990 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
991
992 static void i915_hotplug_work_func(struct work_struct *work)
993 {
994 struct drm_i915_private *dev_priv =
995 container_of(work, struct drm_i915_private, hotplug_work);
996 struct drm_device *dev = dev_priv->dev;
997 struct drm_mode_config *mode_config = &dev->mode_config;
998 struct intel_connector *intel_connector;
999 struct intel_encoder *intel_encoder;
1000 struct drm_connector *connector;
1001 unsigned long irqflags;
1002 bool hpd_disabled = false;
1003 bool changed = false;
1004 u32 hpd_event_bits;
1005
1006 /* HPD irq before everything is fully set up. */
1007 if (!dev_priv->enable_hotplug_processing)
1008 return;
1009
1010 mutex_lock(&mode_config->mutex);
1011 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1012
1013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1014
1015 hpd_event_bits = dev_priv->hpd_event_bits;
1016 dev_priv->hpd_event_bits = 0;
1017 list_for_each_entry(connector, &mode_config->connector_list, head) {
1018 intel_connector = to_intel_connector(connector);
1019 intel_encoder = intel_connector->encoder;
1020 if (intel_encoder->hpd_pin > HPD_NONE &&
1021 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1022 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1023 DRM_INFO("HPD interrupt storm detected on connector %s: "
1024 "switching from hotplug detection to polling\n",
1025 drm_get_connector_name(connector));
1026 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1027 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1028 | DRM_CONNECTOR_POLL_DISCONNECT;
1029 hpd_disabled = true;
1030 }
1031 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1032 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1033 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1034 }
1035 }
1036 /* if there were no outputs to poll, poll was disabled,
1037 * therefore make sure it's enabled when disabling HPD on
1038 * some connectors */
1039 if (hpd_disabled) {
1040 drm_kms_helper_poll_enable(dev);
1041 mod_timer(&dev_priv->hotplug_reenable_timer,
1042 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1043 }
1044
1045 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1046
1047 list_for_each_entry(connector, &mode_config->connector_list, head) {
1048 intel_connector = to_intel_connector(connector);
1049 intel_encoder = intel_connector->encoder;
1050 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1051 if (intel_encoder->hot_plug)
1052 intel_encoder->hot_plug(intel_encoder);
1053 if (intel_hpd_irq_event(dev, connector))
1054 changed = true;
1055 }
1056 }
1057 mutex_unlock(&mode_config->mutex);
1058
1059 if (changed)
1060 drm_kms_helper_hotplug_event(dev);
1061 }
1062
1063 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1064 {
1065 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1066 }
1067
1068 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1069 {
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 u32 busy_up, busy_down, max_avg, min_avg;
1072 u8 new_delay;
1073
1074 spin_lock(&mchdev_lock);
1075
1076 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1077
1078 new_delay = dev_priv->ips.cur_delay;
1079
1080 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1081 busy_up = I915_READ(RCPREVBSYTUPAVG);
1082 busy_down = I915_READ(RCPREVBSYTDNAVG);
1083 max_avg = I915_READ(RCBMAXAVG);
1084 min_avg = I915_READ(RCBMINAVG);
1085
1086 /* Handle RCS change request from hw */
1087 if (busy_up > max_avg) {
1088 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1089 new_delay = dev_priv->ips.cur_delay - 1;
1090 if (new_delay < dev_priv->ips.max_delay)
1091 new_delay = dev_priv->ips.max_delay;
1092 } else if (busy_down < min_avg) {
1093 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1094 new_delay = dev_priv->ips.cur_delay + 1;
1095 if (new_delay > dev_priv->ips.min_delay)
1096 new_delay = dev_priv->ips.min_delay;
1097 }
1098
1099 if (ironlake_set_drps(dev, new_delay))
1100 dev_priv->ips.cur_delay = new_delay;
1101
1102 spin_unlock(&mchdev_lock);
1103
1104 return;
1105 }
1106
1107 static void notify_ring(struct drm_device *dev,
1108 struct intel_ring_buffer *ring)
1109 {
1110 if (ring->obj == NULL)
1111 return;
1112
1113 trace_i915_gem_request_complete(ring);
1114
1115 wake_up_all(&ring->irq_queue);
1116 i915_queue_hangcheck(dev);
1117 }
1118
1119 static void gen6_pm_rps_work(struct work_struct *work)
1120 {
1121 struct drm_i915_private *dev_priv =
1122 container_of(work, struct drm_i915_private, rps.work);
1123 u32 pm_iir;
1124 int new_delay, adj;
1125
1126 spin_lock_irq(&dev_priv->irq_lock);
1127 pm_iir = dev_priv->rps.pm_iir;
1128 dev_priv->rps.pm_iir = 0;
1129 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1130 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1131 spin_unlock_irq(&dev_priv->irq_lock);
1132
1133 /* Make sure we didn't queue anything we're not going to process. */
1134 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1135
1136 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1137 return;
1138
1139 mutex_lock(&dev_priv->rps.hw_lock);
1140
1141 adj = dev_priv->rps.last_adj;
1142 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1143 if (adj > 0)
1144 adj *= 2;
1145 else
1146 adj = 1;
1147 new_delay = dev_priv->rps.cur_freq + adj;
1148
1149 /*
1150 * For better performance, jump directly
1151 * to RPe if we're below it.
1152 */
1153 if (new_delay < dev_priv->rps.efficient_freq)
1154 new_delay = dev_priv->rps.efficient_freq;
1155 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1156 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1157 new_delay = dev_priv->rps.efficient_freq;
1158 else
1159 new_delay = dev_priv->rps.min_freq_softlimit;
1160 adj = 0;
1161 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1162 if (adj < 0)
1163 adj *= 2;
1164 else
1165 adj = -1;
1166 new_delay = dev_priv->rps.cur_freq + adj;
1167 } else { /* unknown event */
1168 new_delay = dev_priv->rps.cur_freq;
1169 }
1170
1171 /* sysfs frequency interfaces may have snuck in while servicing the
1172 * interrupt
1173 */
1174 new_delay = clamp_t(int, new_delay,
1175 dev_priv->rps.min_freq_softlimit,
1176 dev_priv->rps.max_freq_softlimit);
1177
1178 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1179
1180 if (IS_VALLEYVIEW(dev_priv->dev))
1181 valleyview_set_rps(dev_priv->dev, new_delay);
1182 else
1183 gen6_set_rps(dev_priv->dev, new_delay);
1184
1185 mutex_unlock(&dev_priv->rps.hw_lock);
1186 }
1187
1188
1189 /**
1190 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1191 * occurred.
1192 * @work: workqueue struct
1193 *
1194 * Doesn't actually do anything except notify userspace. As a consequence of
1195 * this event, userspace should try to remap the bad rows since statistically
1196 * it is likely the same row is more likely to go bad again.
1197 */
1198 static void ivybridge_parity_work(struct work_struct *work)
1199 {
1200 struct drm_i915_private *dev_priv =
1201 container_of(work, struct drm_i915_private, l3_parity.error_work);
1202 u32 error_status, row, bank, subbank;
1203 char *parity_event[6];
1204 uint32_t misccpctl;
1205 unsigned long flags;
1206 uint8_t slice = 0;
1207
1208 /* We must turn off DOP level clock gating to access the L3 registers.
1209 * In order to prevent a get/put style interface, acquire struct mutex
1210 * any time we access those registers.
1211 */
1212 mutex_lock(&dev_priv->dev->struct_mutex);
1213
1214 /* If we've screwed up tracking, just let the interrupt fire again */
1215 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1216 goto out;
1217
1218 misccpctl = I915_READ(GEN7_MISCCPCTL);
1219 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1220 POSTING_READ(GEN7_MISCCPCTL);
1221
1222 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1223 u32 reg;
1224
1225 slice--;
1226 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1227 break;
1228
1229 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1230
1231 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1232
1233 error_status = I915_READ(reg);
1234 row = GEN7_PARITY_ERROR_ROW(error_status);
1235 bank = GEN7_PARITY_ERROR_BANK(error_status);
1236 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1237
1238 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1239 POSTING_READ(reg);
1240
1241 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1242 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1243 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1244 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1245 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1246 parity_event[5] = NULL;
1247
1248 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1249 KOBJ_CHANGE, parity_event);
1250
1251 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1252 slice, row, bank, subbank);
1253
1254 kfree(parity_event[4]);
1255 kfree(parity_event[3]);
1256 kfree(parity_event[2]);
1257 kfree(parity_event[1]);
1258 }
1259
1260 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1261
1262 out:
1263 WARN_ON(dev_priv->l3_parity.which_slice);
1264 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1265 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1266 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1267
1268 mutex_unlock(&dev_priv->dev->struct_mutex);
1269 }
1270
1271 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1272 {
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274
1275 if (!HAS_L3_DPF(dev))
1276 return;
1277
1278 spin_lock(&dev_priv->irq_lock);
1279 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1280 spin_unlock(&dev_priv->irq_lock);
1281
1282 iir &= GT_PARITY_ERROR(dev);
1283 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1284 dev_priv->l3_parity.which_slice |= 1 << 1;
1285
1286 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1287 dev_priv->l3_parity.which_slice |= 1 << 0;
1288
1289 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1290 }
1291
1292 static void ilk_gt_irq_handler(struct drm_device *dev,
1293 struct drm_i915_private *dev_priv,
1294 u32 gt_iir)
1295 {
1296 if (gt_iir &
1297 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1298 notify_ring(dev, &dev_priv->ring[RCS]);
1299 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1300 notify_ring(dev, &dev_priv->ring[VCS]);
1301 }
1302
1303 static void snb_gt_irq_handler(struct drm_device *dev,
1304 struct drm_i915_private *dev_priv,
1305 u32 gt_iir)
1306 {
1307
1308 if (gt_iir &
1309 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1310 notify_ring(dev, &dev_priv->ring[RCS]);
1311 if (gt_iir & GT_BSD_USER_INTERRUPT)
1312 notify_ring(dev, &dev_priv->ring[VCS]);
1313 if (gt_iir & GT_BLT_USER_INTERRUPT)
1314 notify_ring(dev, &dev_priv->ring[BCS]);
1315
1316 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1317 GT_BSD_CS_ERROR_INTERRUPT |
1318 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1319 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1320 gt_iir);
1321 }
1322
1323 if (gt_iir & GT_PARITY_ERROR(dev))
1324 ivybridge_parity_error_irq_handler(dev, gt_iir);
1325 }
1326
1327 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1328 struct drm_i915_private *dev_priv,
1329 u32 master_ctl)
1330 {
1331 u32 rcs, bcs, vcs;
1332 uint32_t tmp = 0;
1333 irqreturn_t ret = IRQ_NONE;
1334
1335 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1336 tmp = I915_READ(GEN8_GT_IIR(0));
1337 if (tmp) {
1338 ret = IRQ_HANDLED;
1339 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1340 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1341 if (rcs & GT_RENDER_USER_INTERRUPT)
1342 notify_ring(dev, &dev_priv->ring[RCS]);
1343 if (bcs & GT_RENDER_USER_INTERRUPT)
1344 notify_ring(dev, &dev_priv->ring[BCS]);
1345 I915_WRITE(GEN8_GT_IIR(0), tmp);
1346 } else
1347 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1348 }
1349
1350 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1351 tmp = I915_READ(GEN8_GT_IIR(1));
1352 if (tmp) {
1353 ret = IRQ_HANDLED;
1354 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1355 if (vcs & GT_RENDER_USER_INTERRUPT)
1356 notify_ring(dev, &dev_priv->ring[VCS]);
1357 I915_WRITE(GEN8_GT_IIR(1), tmp);
1358 } else
1359 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1360 }
1361
1362 if (master_ctl & GEN8_GT_VECS_IRQ) {
1363 tmp = I915_READ(GEN8_GT_IIR(3));
1364 if (tmp) {
1365 ret = IRQ_HANDLED;
1366 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1367 if (vcs & GT_RENDER_USER_INTERRUPT)
1368 notify_ring(dev, &dev_priv->ring[VECS]);
1369 I915_WRITE(GEN8_GT_IIR(3), tmp);
1370 } else
1371 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1372 }
1373
1374 return ret;
1375 }
1376
1377 #define HPD_STORM_DETECT_PERIOD 1000
1378 #define HPD_STORM_THRESHOLD 5
1379
1380 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1381 u32 hotplug_trigger,
1382 const u32 *hpd)
1383 {
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 int i;
1386 bool storm_detected = false;
1387
1388 if (!hotplug_trigger)
1389 return;
1390
1391 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1392 hotplug_trigger);
1393
1394 spin_lock(&dev_priv->irq_lock);
1395 for (i = 1; i < HPD_NUM_PINS; i++) {
1396
1397 WARN_ONCE(hpd[i] & hotplug_trigger &&
1398 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1399 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1400 hotplug_trigger, i, hpd[i]);
1401
1402 if (!(hpd[i] & hotplug_trigger) ||
1403 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1404 continue;
1405
1406 dev_priv->hpd_event_bits |= (1 << i);
1407 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1408 dev_priv->hpd_stats[i].hpd_last_jiffies
1409 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1410 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1411 dev_priv->hpd_stats[i].hpd_cnt = 0;
1412 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1413 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1414 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1415 dev_priv->hpd_event_bits &= ~(1 << i);
1416 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1417 storm_detected = true;
1418 } else {
1419 dev_priv->hpd_stats[i].hpd_cnt++;
1420 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1421 dev_priv->hpd_stats[i].hpd_cnt);
1422 }
1423 }
1424
1425 if (storm_detected)
1426 dev_priv->display.hpd_irq_setup(dev);
1427 spin_unlock(&dev_priv->irq_lock);
1428
1429 /*
1430 * Our hotplug handler can grab modeset locks (by calling down into the
1431 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1432 * queue for otherwise the flush_work in the pageflip code will
1433 * deadlock.
1434 */
1435 schedule_work(&dev_priv->hotplug_work);
1436 }
1437
1438 static void gmbus_irq_handler(struct drm_device *dev)
1439 {
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441
1442 wake_up_all(&dev_priv->gmbus_wait_queue);
1443 }
1444
1445 static void dp_aux_irq_handler(struct drm_device *dev)
1446 {
1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448
1449 wake_up_all(&dev_priv->gmbus_wait_queue);
1450 }
1451
1452 #if defined(CONFIG_DEBUG_FS)
1453 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1454 uint32_t crc0, uint32_t crc1,
1455 uint32_t crc2, uint32_t crc3,
1456 uint32_t crc4)
1457 {
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1460 struct intel_pipe_crc_entry *entry;
1461 int head, tail;
1462
1463 spin_lock(&pipe_crc->lock);
1464
1465 if (!pipe_crc->entries) {
1466 spin_unlock(&pipe_crc->lock);
1467 DRM_ERROR("spurious interrupt\n");
1468 return;
1469 }
1470
1471 head = pipe_crc->head;
1472 tail = pipe_crc->tail;
1473
1474 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1475 spin_unlock(&pipe_crc->lock);
1476 DRM_ERROR("CRC buffer overflowing\n");
1477 return;
1478 }
1479
1480 entry = &pipe_crc->entries[head];
1481
1482 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1483 entry->crc[0] = crc0;
1484 entry->crc[1] = crc1;
1485 entry->crc[2] = crc2;
1486 entry->crc[3] = crc3;
1487 entry->crc[4] = crc4;
1488
1489 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1490 pipe_crc->head = head;
1491
1492 spin_unlock(&pipe_crc->lock);
1493
1494 wake_up_interruptible(&pipe_crc->wq);
1495 }
1496 #else
1497 static inline void
1498 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1499 uint32_t crc0, uint32_t crc1,
1500 uint32_t crc2, uint32_t crc3,
1501 uint32_t crc4) {}
1502 #endif
1503
1504
1505 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1506 {
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508
1509 display_pipe_crc_irq_handler(dev, pipe,
1510 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1511 0, 0, 0, 0);
1512 }
1513
1514 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1515 {
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517
1518 display_pipe_crc_irq_handler(dev, pipe,
1519 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1520 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1521 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1522 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1523 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1524 }
1525
1526 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1527 {
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 uint32_t res1, res2;
1530
1531 if (INTEL_INFO(dev)->gen >= 3)
1532 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1533 else
1534 res1 = 0;
1535
1536 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1537 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1538 else
1539 res2 = 0;
1540
1541 display_pipe_crc_irq_handler(dev, pipe,
1542 I915_READ(PIPE_CRC_RES_RED(pipe)),
1543 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1544 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1545 res1, res2);
1546 }
1547
1548 /* The RPS events need forcewake, so we add them to a work queue and mask their
1549 * IMR bits until the work is done. Other interrupts can be processed without
1550 * the work queue. */
1551 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1552 {
1553 if (pm_iir & dev_priv->pm_rps_events) {
1554 spin_lock(&dev_priv->irq_lock);
1555 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1556 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1557 spin_unlock(&dev_priv->irq_lock);
1558
1559 queue_work(dev_priv->wq, &dev_priv->rps.work);
1560 }
1561
1562 if (HAS_VEBOX(dev_priv->dev)) {
1563 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1564 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1565
1566 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1567 i915_handle_error(dev_priv->dev, false,
1568 "VEBOX CS error interrupt 0x%08x",
1569 pm_iir);
1570 }
1571 }
1572 }
1573
1574 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1575 {
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 u32 pipe_stats[I915_MAX_PIPES] = { };
1578 int pipe;
1579
1580 spin_lock(&dev_priv->irq_lock);
1581 for_each_pipe(pipe) {
1582 int reg;
1583 u32 mask, iir_bit = 0;
1584
1585 /*
1586 * PIPESTAT bits get signalled even when the interrupt is
1587 * disabled with the mask bits, and some of the status bits do
1588 * not generate interrupts at all (like the underrun bit). Hence
1589 * we need to be careful that we only handle what we want to
1590 * handle.
1591 */
1592 mask = 0;
1593 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1594 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1595
1596 switch (pipe) {
1597 case PIPE_A:
1598 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1599 break;
1600 case PIPE_B:
1601 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1602 break;
1603 }
1604 if (iir & iir_bit)
1605 mask |= dev_priv->pipestat_irq_mask[pipe];
1606
1607 if (!mask)
1608 continue;
1609
1610 reg = PIPESTAT(pipe);
1611 mask |= PIPESTAT_INT_ENABLE_MASK;
1612 pipe_stats[pipe] = I915_READ(reg) & mask;
1613
1614 /*
1615 * Clear the PIPE*STAT regs before the IIR
1616 */
1617 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1618 PIPESTAT_INT_STATUS_MASK))
1619 I915_WRITE(reg, pipe_stats[pipe]);
1620 }
1621 spin_unlock(&dev_priv->irq_lock);
1622
1623 for_each_pipe(pipe) {
1624 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1625 drm_handle_vblank(dev, pipe);
1626
1627 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1628 intel_prepare_page_flip(dev, pipe);
1629 intel_finish_page_flip(dev, pipe);
1630 }
1631
1632 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1633 i9xx_pipe_crc_irq_handler(dev, pipe);
1634
1635 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1636 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1637 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1638 }
1639
1640 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1641 gmbus_irq_handler(dev);
1642 }
1643
1644 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1645 {
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1648
1649 if (IS_G4X(dev)) {
1650 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1651
1652 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1653 } else {
1654 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1655
1656 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1657 }
1658
1659 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1660 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1661 dp_aux_irq_handler(dev);
1662
1663 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1664 /*
1665 * Make sure hotplug status is cleared before we clear IIR, or else we
1666 * may miss hotplug events.
1667 */
1668 POSTING_READ(PORT_HOTPLUG_STAT);
1669 }
1670
1671 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1672 {
1673 struct drm_device *dev = (struct drm_device *) arg;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 u32 iir, gt_iir, pm_iir;
1676 irqreturn_t ret = IRQ_NONE;
1677
1678 while (true) {
1679 iir = I915_READ(VLV_IIR);
1680 gt_iir = I915_READ(GTIIR);
1681 pm_iir = I915_READ(GEN6_PMIIR);
1682
1683 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1684 goto out;
1685
1686 ret = IRQ_HANDLED;
1687
1688 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1689
1690 valleyview_pipestat_irq_handler(dev, iir);
1691
1692 /* Consume port. Then clear IIR or we'll miss events */
1693 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1694 i9xx_hpd_irq_handler(dev);
1695
1696 if (pm_iir)
1697 gen6_rps_irq_handler(dev_priv, pm_iir);
1698
1699 I915_WRITE(GTIIR, gt_iir);
1700 I915_WRITE(GEN6_PMIIR, pm_iir);
1701 I915_WRITE(VLV_IIR, iir);
1702 }
1703
1704 out:
1705 return ret;
1706 }
1707
1708 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1709 {
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int pipe;
1712 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1713
1714 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1715
1716 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1717 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1718 SDE_AUDIO_POWER_SHIFT);
1719 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1720 port_name(port));
1721 }
1722
1723 if (pch_iir & SDE_AUX_MASK)
1724 dp_aux_irq_handler(dev);
1725
1726 if (pch_iir & SDE_GMBUS)
1727 gmbus_irq_handler(dev);
1728
1729 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1730 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1731
1732 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1733 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1734
1735 if (pch_iir & SDE_POISON)
1736 DRM_ERROR("PCH poison interrupt\n");
1737
1738 if (pch_iir & SDE_FDI_MASK)
1739 for_each_pipe(pipe)
1740 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1741 pipe_name(pipe),
1742 I915_READ(FDI_RX_IIR(pipe)));
1743
1744 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1745 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1746
1747 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1748 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1749
1750 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1751 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1752 false))
1753 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1754
1755 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1756 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1757 false))
1758 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1759 }
1760
1761 static void ivb_err_int_handler(struct drm_device *dev)
1762 {
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 u32 err_int = I915_READ(GEN7_ERR_INT);
1765 enum pipe pipe;
1766
1767 if (err_int & ERR_INT_POISON)
1768 DRM_ERROR("Poison interrupt\n");
1769
1770 for_each_pipe(pipe) {
1771 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1772 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1773 false))
1774 DRM_ERROR("Pipe %c FIFO underrun\n",
1775 pipe_name(pipe));
1776 }
1777
1778 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1779 if (IS_IVYBRIDGE(dev))
1780 ivb_pipe_crc_irq_handler(dev, pipe);
1781 else
1782 hsw_pipe_crc_irq_handler(dev, pipe);
1783 }
1784 }
1785
1786 I915_WRITE(GEN7_ERR_INT, err_int);
1787 }
1788
1789 static void cpt_serr_int_handler(struct drm_device *dev)
1790 {
1791 struct drm_i915_private *dev_priv = dev->dev_private;
1792 u32 serr_int = I915_READ(SERR_INT);
1793
1794 if (serr_int & SERR_INT_POISON)
1795 DRM_ERROR("PCH poison interrupt\n");
1796
1797 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1798 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1799 false))
1800 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1801
1802 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1803 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1804 false))
1805 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1806
1807 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1808 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1809 false))
1810 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1811
1812 I915_WRITE(SERR_INT, serr_int);
1813 }
1814
1815 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1816 {
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818 int pipe;
1819 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1820
1821 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1822
1823 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1824 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1825 SDE_AUDIO_POWER_SHIFT_CPT);
1826 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1827 port_name(port));
1828 }
1829
1830 if (pch_iir & SDE_AUX_MASK_CPT)
1831 dp_aux_irq_handler(dev);
1832
1833 if (pch_iir & SDE_GMBUS_CPT)
1834 gmbus_irq_handler(dev);
1835
1836 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1837 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1838
1839 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1840 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1841
1842 if (pch_iir & SDE_FDI_MASK_CPT)
1843 for_each_pipe(pipe)
1844 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1845 pipe_name(pipe),
1846 I915_READ(FDI_RX_IIR(pipe)));
1847
1848 if (pch_iir & SDE_ERROR_CPT)
1849 cpt_serr_int_handler(dev);
1850 }
1851
1852 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1853 {
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 enum pipe pipe;
1856
1857 if (de_iir & DE_AUX_CHANNEL_A)
1858 dp_aux_irq_handler(dev);
1859
1860 if (de_iir & DE_GSE)
1861 intel_opregion_asle_intr(dev);
1862
1863 if (de_iir & DE_POISON)
1864 DRM_ERROR("Poison interrupt\n");
1865
1866 for_each_pipe(pipe) {
1867 if (de_iir & DE_PIPE_VBLANK(pipe))
1868 drm_handle_vblank(dev, pipe);
1869
1870 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1871 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1872 DRM_ERROR("Pipe %c FIFO underrun\n",
1873 pipe_name(pipe));
1874
1875 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1876 i9xx_pipe_crc_irq_handler(dev, pipe);
1877
1878 /* plane/pipes map 1:1 on ilk+ */
1879 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1880 intel_prepare_page_flip(dev, pipe);
1881 intel_finish_page_flip_plane(dev, pipe);
1882 }
1883 }
1884
1885 /* check event from PCH */
1886 if (de_iir & DE_PCH_EVENT) {
1887 u32 pch_iir = I915_READ(SDEIIR);
1888
1889 if (HAS_PCH_CPT(dev))
1890 cpt_irq_handler(dev, pch_iir);
1891 else
1892 ibx_irq_handler(dev, pch_iir);
1893
1894 /* should clear PCH hotplug event before clear CPU irq */
1895 I915_WRITE(SDEIIR, pch_iir);
1896 }
1897
1898 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1899 ironlake_rps_change_irq_handler(dev);
1900 }
1901
1902 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1903 {
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 enum pipe pipe;
1906
1907 if (de_iir & DE_ERR_INT_IVB)
1908 ivb_err_int_handler(dev);
1909
1910 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1911 dp_aux_irq_handler(dev);
1912
1913 if (de_iir & DE_GSE_IVB)
1914 intel_opregion_asle_intr(dev);
1915
1916 for_each_pipe(pipe) {
1917 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1918 drm_handle_vblank(dev, pipe);
1919
1920 /* plane/pipes map 1:1 on ilk+ */
1921 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1922 intel_prepare_page_flip(dev, pipe);
1923 intel_finish_page_flip_plane(dev, pipe);
1924 }
1925 }
1926
1927 /* check event from PCH */
1928 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1929 u32 pch_iir = I915_READ(SDEIIR);
1930
1931 cpt_irq_handler(dev, pch_iir);
1932
1933 /* clear PCH hotplug event before clear CPU irq */
1934 I915_WRITE(SDEIIR, pch_iir);
1935 }
1936 }
1937
1938 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1939 {
1940 struct drm_device *dev = (struct drm_device *) arg;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1943 irqreturn_t ret = IRQ_NONE;
1944
1945 /* We get interrupts on unclaimed registers, so check for this before we
1946 * do any I915_{READ,WRITE}. */
1947 intel_uncore_check_errors(dev);
1948
1949 /* disable master interrupt before clearing iir */
1950 de_ier = I915_READ(DEIER);
1951 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1952 POSTING_READ(DEIER);
1953
1954 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1955 * interrupts will will be stored on its back queue, and then we'll be
1956 * able to process them after we restore SDEIER (as soon as we restore
1957 * it, we'll get an interrupt if SDEIIR still has something to process
1958 * due to its back queue). */
1959 if (!HAS_PCH_NOP(dev)) {
1960 sde_ier = I915_READ(SDEIER);
1961 I915_WRITE(SDEIER, 0);
1962 POSTING_READ(SDEIER);
1963 }
1964
1965 gt_iir = I915_READ(GTIIR);
1966 if (gt_iir) {
1967 if (INTEL_INFO(dev)->gen >= 6)
1968 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1969 else
1970 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1971 I915_WRITE(GTIIR, gt_iir);
1972 ret = IRQ_HANDLED;
1973 }
1974
1975 de_iir = I915_READ(DEIIR);
1976 if (de_iir) {
1977 if (INTEL_INFO(dev)->gen >= 7)
1978 ivb_display_irq_handler(dev, de_iir);
1979 else
1980 ilk_display_irq_handler(dev, de_iir);
1981 I915_WRITE(DEIIR, de_iir);
1982 ret = IRQ_HANDLED;
1983 }
1984
1985 if (INTEL_INFO(dev)->gen >= 6) {
1986 u32 pm_iir = I915_READ(GEN6_PMIIR);
1987 if (pm_iir) {
1988 gen6_rps_irq_handler(dev_priv, pm_iir);
1989 I915_WRITE(GEN6_PMIIR, pm_iir);
1990 ret = IRQ_HANDLED;
1991 }
1992 }
1993
1994 I915_WRITE(DEIER, de_ier);
1995 POSTING_READ(DEIER);
1996 if (!HAS_PCH_NOP(dev)) {
1997 I915_WRITE(SDEIER, sde_ier);
1998 POSTING_READ(SDEIER);
1999 }
2000
2001 return ret;
2002 }
2003
2004 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2005 {
2006 struct drm_device *dev = arg;
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 u32 master_ctl;
2009 irqreturn_t ret = IRQ_NONE;
2010 uint32_t tmp = 0;
2011 enum pipe pipe;
2012
2013 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2014 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2015 if (!master_ctl)
2016 return IRQ_NONE;
2017
2018 I915_WRITE(GEN8_MASTER_IRQ, 0);
2019 POSTING_READ(GEN8_MASTER_IRQ);
2020
2021 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2022
2023 if (master_ctl & GEN8_DE_MISC_IRQ) {
2024 tmp = I915_READ(GEN8_DE_MISC_IIR);
2025 if (tmp & GEN8_DE_MISC_GSE)
2026 intel_opregion_asle_intr(dev);
2027 else if (tmp)
2028 DRM_ERROR("Unexpected DE Misc interrupt\n");
2029 else
2030 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2031
2032 if (tmp) {
2033 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2034 ret = IRQ_HANDLED;
2035 }
2036 }
2037
2038 if (master_ctl & GEN8_DE_PORT_IRQ) {
2039 tmp = I915_READ(GEN8_DE_PORT_IIR);
2040 if (tmp & GEN8_AUX_CHANNEL_A)
2041 dp_aux_irq_handler(dev);
2042 else if (tmp)
2043 DRM_ERROR("Unexpected DE Port interrupt\n");
2044 else
2045 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2046
2047 if (tmp) {
2048 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2049 ret = IRQ_HANDLED;
2050 }
2051 }
2052
2053 for_each_pipe(pipe) {
2054 uint32_t pipe_iir;
2055
2056 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2057 continue;
2058
2059 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2060 if (pipe_iir & GEN8_PIPE_VBLANK)
2061 drm_handle_vblank(dev, pipe);
2062
2063 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2064 intel_prepare_page_flip(dev, pipe);
2065 intel_finish_page_flip_plane(dev, pipe);
2066 }
2067
2068 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2069 hsw_pipe_crc_irq_handler(dev, pipe);
2070
2071 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2072 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2073 false))
2074 DRM_ERROR("Pipe %c FIFO underrun\n",
2075 pipe_name(pipe));
2076 }
2077
2078 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2079 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2080 pipe_name(pipe),
2081 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2082 }
2083
2084 if (pipe_iir) {
2085 ret = IRQ_HANDLED;
2086 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2087 } else
2088 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2089 }
2090
2091 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2092 /*
2093 * FIXME(BDW): Assume for now that the new interrupt handling
2094 * scheme also closed the SDE interrupt handling race we've seen
2095 * on older pch-split platforms. But this needs testing.
2096 */
2097 u32 pch_iir = I915_READ(SDEIIR);
2098
2099 cpt_irq_handler(dev, pch_iir);
2100
2101 if (pch_iir) {
2102 I915_WRITE(SDEIIR, pch_iir);
2103 ret = IRQ_HANDLED;
2104 }
2105 }
2106
2107 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2108 POSTING_READ(GEN8_MASTER_IRQ);
2109
2110 return ret;
2111 }
2112
2113 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2114 bool reset_completed)
2115 {
2116 struct intel_ring_buffer *ring;
2117 int i;
2118
2119 /*
2120 * Notify all waiters for GPU completion events that reset state has
2121 * been changed, and that they need to restart their wait after
2122 * checking for potential errors (and bail out to drop locks if there is
2123 * a gpu reset pending so that i915_error_work_func can acquire them).
2124 */
2125
2126 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2127 for_each_ring(ring, dev_priv, i)
2128 wake_up_all(&ring->irq_queue);
2129
2130 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2131 wake_up_all(&dev_priv->pending_flip_queue);
2132
2133 /*
2134 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2135 * reset state is cleared.
2136 */
2137 if (reset_completed)
2138 wake_up_all(&dev_priv->gpu_error.reset_queue);
2139 }
2140
2141 /**
2142 * i915_error_work_func - do process context error handling work
2143 * @work: work struct
2144 *
2145 * Fire an error uevent so userspace can see that a hang or error
2146 * was detected.
2147 */
2148 static void i915_error_work_func(struct work_struct *work)
2149 {
2150 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2151 work);
2152 struct drm_i915_private *dev_priv =
2153 container_of(error, struct drm_i915_private, gpu_error);
2154 struct drm_device *dev = dev_priv->dev;
2155 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2156 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2157 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2158 int ret;
2159
2160 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2161
2162 /*
2163 * Note that there's only one work item which does gpu resets, so we
2164 * need not worry about concurrent gpu resets potentially incrementing
2165 * error->reset_counter twice. We only need to take care of another
2166 * racing irq/hangcheck declaring the gpu dead for a second time. A
2167 * quick check for that is good enough: schedule_work ensures the
2168 * correct ordering between hang detection and this work item, and since
2169 * the reset in-progress bit is only ever set by code outside of this
2170 * work we don't need to worry about any other races.
2171 */
2172 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2173 DRM_DEBUG_DRIVER("resetting chip\n");
2174 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2175 reset_event);
2176
2177 /*
2178 * All state reset _must_ be completed before we update the
2179 * reset counter, for otherwise waiters might miss the reset
2180 * pending state and not properly drop locks, resulting in
2181 * deadlocks with the reset work.
2182 */
2183 ret = i915_reset(dev);
2184
2185 intel_display_handle_reset(dev);
2186
2187 if (ret == 0) {
2188 /*
2189 * After all the gem state is reset, increment the reset
2190 * counter and wake up everyone waiting for the reset to
2191 * complete.
2192 *
2193 * Since unlock operations are a one-sided barrier only,
2194 * we need to insert a barrier here to order any seqno
2195 * updates before
2196 * the counter increment.
2197 */
2198 smp_mb__before_atomic_inc();
2199 atomic_inc(&dev_priv->gpu_error.reset_counter);
2200
2201 kobject_uevent_env(&dev->primary->kdev->kobj,
2202 KOBJ_CHANGE, reset_done_event);
2203 } else {
2204 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2205 }
2206
2207 /*
2208 * Note: The wake_up also serves as a memory barrier so that
2209 * waiters see the update value of the reset counter atomic_t.
2210 */
2211 i915_error_wake_up(dev_priv, true);
2212 }
2213 }
2214
2215 static void i915_report_and_clear_eir(struct drm_device *dev)
2216 {
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 uint32_t instdone[I915_NUM_INSTDONE_REG];
2219 u32 eir = I915_READ(EIR);
2220 int pipe, i;
2221
2222 if (!eir)
2223 return;
2224
2225 pr_err("render error detected, EIR: 0x%08x\n", eir);
2226
2227 i915_get_extra_instdone(dev, instdone);
2228
2229 if (IS_G4X(dev)) {
2230 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2231 u32 ipeir = I915_READ(IPEIR_I965);
2232
2233 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2234 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2235 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2236 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2237 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2238 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2239 I915_WRITE(IPEIR_I965, ipeir);
2240 POSTING_READ(IPEIR_I965);
2241 }
2242 if (eir & GM45_ERROR_PAGE_TABLE) {
2243 u32 pgtbl_err = I915_READ(PGTBL_ER);
2244 pr_err("page table error\n");
2245 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2246 I915_WRITE(PGTBL_ER, pgtbl_err);
2247 POSTING_READ(PGTBL_ER);
2248 }
2249 }
2250
2251 if (!IS_GEN2(dev)) {
2252 if (eir & I915_ERROR_PAGE_TABLE) {
2253 u32 pgtbl_err = I915_READ(PGTBL_ER);
2254 pr_err("page table error\n");
2255 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2256 I915_WRITE(PGTBL_ER, pgtbl_err);
2257 POSTING_READ(PGTBL_ER);
2258 }
2259 }
2260
2261 if (eir & I915_ERROR_MEMORY_REFRESH) {
2262 pr_err("memory refresh error:\n");
2263 for_each_pipe(pipe)
2264 pr_err("pipe %c stat: 0x%08x\n",
2265 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2266 /* pipestat has already been acked */
2267 }
2268 if (eir & I915_ERROR_INSTRUCTION) {
2269 pr_err("instruction error\n");
2270 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2271 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2272 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2273 if (INTEL_INFO(dev)->gen < 4) {
2274 u32 ipeir = I915_READ(IPEIR);
2275
2276 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2277 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2278 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2279 I915_WRITE(IPEIR, ipeir);
2280 POSTING_READ(IPEIR);
2281 } else {
2282 u32 ipeir = I915_READ(IPEIR_I965);
2283
2284 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2285 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2286 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2287 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2288 I915_WRITE(IPEIR_I965, ipeir);
2289 POSTING_READ(IPEIR_I965);
2290 }
2291 }
2292
2293 I915_WRITE(EIR, eir);
2294 POSTING_READ(EIR);
2295 eir = I915_READ(EIR);
2296 if (eir) {
2297 /*
2298 * some errors might have become stuck,
2299 * mask them.
2300 */
2301 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2302 I915_WRITE(EMR, I915_READ(EMR) | eir);
2303 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2304 }
2305 }
2306
2307 /**
2308 * i915_handle_error - handle an error interrupt
2309 * @dev: drm device
2310 *
2311 * Do some basic checking of regsiter state at error interrupt time and
2312 * dump it to the syslog. Also call i915_capture_error_state() to make
2313 * sure we get a record and make it available in debugfs. Fire a uevent
2314 * so userspace knows something bad happened (should trigger collection
2315 * of a ring dump etc.).
2316 */
2317 void i915_handle_error(struct drm_device *dev, bool wedged,
2318 const char *fmt, ...)
2319 {
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 va_list args;
2322 char error_msg[80];
2323
2324 va_start(args, fmt);
2325 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2326 va_end(args);
2327
2328 i915_capture_error_state(dev, wedged, error_msg);
2329 i915_report_and_clear_eir(dev);
2330
2331 if (wedged) {
2332 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2333 &dev_priv->gpu_error.reset_counter);
2334
2335 /*
2336 * Wakeup waiting processes so that the reset work function
2337 * i915_error_work_func doesn't deadlock trying to grab various
2338 * locks. By bumping the reset counter first, the woken
2339 * processes will see a reset in progress and back off,
2340 * releasing their locks and then wait for the reset completion.
2341 * We must do this for _all_ gpu waiters that might hold locks
2342 * that the reset work needs to acquire.
2343 *
2344 * Note: The wake_up serves as the required memory barrier to
2345 * ensure that the waiters see the updated value of the reset
2346 * counter atomic_t.
2347 */
2348 i915_error_wake_up(dev_priv, false);
2349 }
2350
2351 /*
2352 * Our reset work can grab modeset locks (since it needs to reset the
2353 * state of outstanding pagelips). Hence it must not be run on our own
2354 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2355 * code will deadlock.
2356 */
2357 schedule_work(&dev_priv->gpu_error.work);
2358 }
2359
2360 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2361 {
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 struct drm_i915_gem_object *obj;
2366 struct intel_unpin_work *work;
2367 unsigned long flags;
2368 bool stall_detected;
2369
2370 /* Ignore early vblank irqs */
2371 if (intel_crtc == NULL)
2372 return;
2373
2374 spin_lock_irqsave(&dev->event_lock, flags);
2375 work = intel_crtc->unpin_work;
2376
2377 if (work == NULL ||
2378 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2379 !work->enable_stall_check) {
2380 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2381 spin_unlock_irqrestore(&dev->event_lock, flags);
2382 return;
2383 }
2384
2385 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2386 obj = work->pending_flip_obj;
2387 if (INTEL_INFO(dev)->gen >= 4) {
2388 int dspsurf = DSPSURF(intel_crtc->plane);
2389 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2390 i915_gem_obj_ggtt_offset(obj);
2391 } else {
2392 int dspaddr = DSPADDR(intel_crtc->plane);
2393 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2394 crtc->y * crtc->primary->fb->pitches[0] +
2395 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2396 }
2397
2398 spin_unlock_irqrestore(&dev->event_lock, flags);
2399
2400 if (stall_detected) {
2401 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2402 intel_prepare_page_flip(dev, intel_crtc->plane);
2403 }
2404 }
2405
2406 /* Called from drm generic code, passed 'crtc' which
2407 * we use as a pipe index
2408 */
2409 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2410 {
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 unsigned long irqflags;
2413
2414 if (!i915_pipe_enabled(dev, pipe))
2415 return -EINVAL;
2416
2417 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2418 if (INTEL_INFO(dev)->gen >= 4)
2419 i915_enable_pipestat(dev_priv, pipe,
2420 PIPE_START_VBLANK_INTERRUPT_STATUS);
2421 else
2422 i915_enable_pipestat(dev_priv, pipe,
2423 PIPE_VBLANK_INTERRUPT_STATUS);
2424
2425 /* maintain vblank delivery even in deep C-states */
2426 if (INTEL_INFO(dev)->gen == 3)
2427 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2429
2430 return 0;
2431 }
2432
2433 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2434 {
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 unsigned long irqflags;
2437 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2438 DE_PIPE_VBLANK(pipe);
2439
2440 if (!i915_pipe_enabled(dev, pipe))
2441 return -EINVAL;
2442
2443 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2444 ironlake_enable_display_irq(dev_priv, bit);
2445 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2446
2447 return 0;
2448 }
2449
2450 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2451 {
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 unsigned long irqflags;
2454
2455 if (!i915_pipe_enabled(dev, pipe))
2456 return -EINVAL;
2457
2458 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2459 i915_enable_pipestat(dev_priv, pipe,
2460 PIPE_START_VBLANK_INTERRUPT_STATUS);
2461 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2462
2463 return 0;
2464 }
2465
2466 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2467 {
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 unsigned long irqflags;
2470
2471 if (!i915_pipe_enabled(dev, pipe))
2472 return -EINVAL;
2473
2474 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2475 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2476 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2477 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2478 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2479 return 0;
2480 }
2481
2482 /* Called from drm generic code, passed 'crtc' which
2483 * we use as a pipe index
2484 */
2485 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2486 {
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 unsigned long irqflags;
2489
2490 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2491 if (INTEL_INFO(dev)->gen == 3)
2492 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2493
2494 i915_disable_pipestat(dev_priv, pipe,
2495 PIPE_VBLANK_INTERRUPT_STATUS |
2496 PIPE_START_VBLANK_INTERRUPT_STATUS);
2497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2498 }
2499
2500 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2501 {
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 unsigned long irqflags;
2504 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2505 DE_PIPE_VBLANK(pipe);
2506
2507 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2508 ironlake_disable_display_irq(dev_priv, bit);
2509 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2510 }
2511
2512 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2513 {
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 unsigned long irqflags;
2516
2517 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2518 i915_disable_pipestat(dev_priv, pipe,
2519 PIPE_START_VBLANK_INTERRUPT_STATUS);
2520 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2521 }
2522
2523 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2524 {
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 unsigned long irqflags;
2527
2528 if (!i915_pipe_enabled(dev, pipe))
2529 return;
2530
2531 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2532 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2533 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2534 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2535 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2536 }
2537
2538 static u32
2539 ring_last_seqno(struct intel_ring_buffer *ring)
2540 {
2541 return list_entry(ring->request_list.prev,
2542 struct drm_i915_gem_request, list)->seqno;
2543 }
2544
2545 static bool
2546 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2547 {
2548 return (list_empty(&ring->request_list) ||
2549 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2550 }
2551
2552 static bool
2553 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2554 {
2555 if (INTEL_INFO(dev)->gen >= 8) {
2556 /*
2557 * FIXME: gen8 semaphore support - currently we don't emit
2558 * semaphores on bdw anyway, but this needs to be addressed when
2559 * we merge that code.
2560 */
2561 return false;
2562 } else {
2563 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2564 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2565 MI_SEMAPHORE_REGISTER);
2566 }
2567 }
2568
2569 static struct intel_ring_buffer *
2570 semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2571 {
2572 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2573 struct intel_ring_buffer *signaller;
2574 int i;
2575
2576 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2577 /*
2578 * FIXME: gen8 semaphore support - currently we don't emit
2579 * semaphores on bdw anyway, but this needs to be addressed when
2580 * we merge that code.
2581 */
2582 return NULL;
2583 } else {
2584 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2585
2586 for_each_ring(signaller, dev_priv, i) {
2587 if(ring == signaller)
2588 continue;
2589
2590 if (sync_bits ==
2591 signaller->semaphore_register[ring->id])
2592 return signaller;
2593 }
2594 }
2595
2596 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2597 ring->id, ipehr);
2598
2599 return NULL;
2600 }
2601
2602 static struct intel_ring_buffer *
2603 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2604 {
2605 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2606 u32 cmd, ipehr, head;
2607 int i;
2608
2609 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2610 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2611 return NULL;
2612
2613 /*
2614 * HEAD is likely pointing to the dword after the actual command,
2615 * so scan backwards until we find the MBOX. But limit it to just 3
2616 * dwords. Note that we don't care about ACTHD here since that might
2617 * point at at batch, and semaphores are always emitted into the
2618 * ringbuffer itself.
2619 */
2620 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2621
2622 for (i = 4; i; --i) {
2623 /*
2624 * Be paranoid and presume the hw has gone off into the wild -
2625 * our ring is smaller than what the hardware (and hence
2626 * HEAD_ADDR) allows. Also handles wrap-around.
2627 */
2628 head &= ring->size - 1;
2629
2630 /* This here seems to blow up */
2631 cmd = ioread32(ring->virtual_start + head);
2632 if (cmd == ipehr)
2633 break;
2634
2635 head -= 4;
2636 }
2637
2638 if (!i)
2639 return NULL;
2640
2641 *seqno = ioread32(ring->virtual_start + head + 4) + 1;
2642 return semaphore_wait_to_signaller_ring(ring, ipehr);
2643 }
2644
2645 static int semaphore_passed(struct intel_ring_buffer *ring)
2646 {
2647 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2648 struct intel_ring_buffer *signaller;
2649 u32 seqno, ctl;
2650
2651 ring->hangcheck.deadlock = true;
2652
2653 signaller = semaphore_waits_for(ring, &seqno);
2654 if (signaller == NULL || signaller->hangcheck.deadlock)
2655 return -1;
2656
2657 /* cursory check for an unkickable deadlock */
2658 ctl = I915_READ_CTL(signaller);
2659 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2660 return -1;
2661
2662 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2663 }
2664
2665 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2666 {
2667 struct intel_ring_buffer *ring;
2668 int i;
2669
2670 for_each_ring(ring, dev_priv, i)
2671 ring->hangcheck.deadlock = false;
2672 }
2673
2674 static enum intel_ring_hangcheck_action
2675 ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2676 {
2677 struct drm_device *dev = ring->dev;
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 u32 tmp;
2680
2681 if (ring->hangcheck.acthd != acthd)
2682 return HANGCHECK_ACTIVE;
2683
2684 if (IS_GEN2(dev))
2685 return HANGCHECK_HUNG;
2686
2687 /* Is the chip hanging on a WAIT_FOR_EVENT?
2688 * If so we can simply poke the RB_WAIT bit
2689 * and break the hang. This should work on
2690 * all but the second generation chipsets.
2691 */
2692 tmp = I915_READ_CTL(ring);
2693 if (tmp & RING_WAIT) {
2694 i915_handle_error(dev, false,
2695 "Kicking stuck wait on %s",
2696 ring->name);
2697 I915_WRITE_CTL(ring, tmp);
2698 return HANGCHECK_KICK;
2699 }
2700
2701 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2702 switch (semaphore_passed(ring)) {
2703 default:
2704 return HANGCHECK_HUNG;
2705 case 1:
2706 i915_handle_error(dev, false,
2707 "Kicking stuck semaphore on %s",
2708 ring->name);
2709 I915_WRITE_CTL(ring, tmp);
2710 return HANGCHECK_KICK;
2711 case 0:
2712 return HANGCHECK_WAIT;
2713 }
2714 }
2715
2716 return HANGCHECK_HUNG;
2717 }
2718
2719 /**
2720 * This is called when the chip hasn't reported back with completed
2721 * batchbuffers in a long time. We keep track per ring seqno progress and
2722 * if there are no progress, hangcheck score for that ring is increased.
2723 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2724 * we kick the ring. If we see no progress on three subsequent calls
2725 * we assume chip is wedged and try to fix it by resetting the chip.
2726 */
2727 static void i915_hangcheck_elapsed(unsigned long data)
2728 {
2729 struct drm_device *dev = (struct drm_device *)data;
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 struct intel_ring_buffer *ring;
2732 int i;
2733 int busy_count = 0, rings_hung = 0;
2734 bool stuck[I915_NUM_RINGS] = { 0 };
2735 #define BUSY 1
2736 #define KICK 5
2737 #define HUNG 20
2738
2739 if (!i915.enable_hangcheck)
2740 return;
2741
2742 for_each_ring(ring, dev_priv, i) {
2743 u64 acthd;
2744 u32 seqno;
2745 bool busy = true;
2746
2747 semaphore_clear_deadlocks(dev_priv);
2748
2749 seqno = ring->get_seqno(ring, false);
2750 acthd = intel_ring_get_active_head(ring);
2751
2752 if (ring->hangcheck.seqno == seqno) {
2753 if (ring_idle(ring, seqno)) {
2754 ring->hangcheck.action = HANGCHECK_IDLE;
2755
2756 if (waitqueue_active(&ring->irq_queue)) {
2757 /* Issue a wake-up to catch stuck h/w. */
2758 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2759 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2760 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2761 ring->name);
2762 else
2763 DRM_INFO("Fake missed irq on %s\n",
2764 ring->name);
2765 wake_up_all(&ring->irq_queue);
2766 }
2767 /* Safeguard against driver failure */
2768 ring->hangcheck.score += BUSY;
2769 } else
2770 busy = false;
2771 } else {
2772 /* We always increment the hangcheck score
2773 * if the ring is busy and still processing
2774 * the same request, so that no single request
2775 * can run indefinitely (such as a chain of
2776 * batches). The only time we do not increment
2777 * the hangcheck score on this ring, if this
2778 * ring is in a legitimate wait for another
2779 * ring. In that case the waiting ring is a
2780 * victim and we want to be sure we catch the
2781 * right culprit. Then every time we do kick
2782 * the ring, add a small increment to the
2783 * score so that we can catch a batch that is
2784 * being repeatedly kicked and so responsible
2785 * for stalling the machine.
2786 */
2787 ring->hangcheck.action = ring_stuck(ring,
2788 acthd);
2789
2790 switch (ring->hangcheck.action) {
2791 case HANGCHECK_IDLE:
2792 case HANGCHECK_WAIT:
2793 break;
2794 case HANGCHECK_ACTIVE:
2795 ring->hangcheck.score += BUSY;
2796 break;
2797 case HANGCHECK_KICK:
2798 ring->hangcheck.score += KICK;
2799 break;
2800 case HANGCHECK_HUNG:
2801 ring->hangcheck.score += HUNG;
2802 stuck[i] = true;
2803 break;
2804 }
2805 }
2806 } else {
2807 ring->hangcheck.action = HANGCHECK_ACTIVE;
2808
2809 /* Gradually reduce the count so that we catch DoS
2810 * attempts across multiple batches.
2811 */
2812 if (ring->hangcheck.score > 0)
2813 ring->hangcheck.score--;
2814 }
2815
2816 ring->hangcheck.seqno = seqno;
2817 ring->hangcheck.acthd = acthd;
2818 busy_count += busy;
2819 }
2820
2821 for_each_ring(ring, dev_priv, i) {
2822 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2823 DRM_INFO("%s on %s\n",
2824 stuck[i] ? "stuck" : "no progress",
2825 ring->name);
2826 rings_hung++;
2827 }
2828 }
2829
2830 if (rings_hung)
2831 return i915_handle_error(dev, true, "Ring hung");
2832
2833 if (busy_count)
2834 /* Reset timer case chip hangs without another request
2835 * being added */
2836 i915_queue_hangcheck(dev);
2837 }
2838
2839 void i915_queue_hangcheck(struct drm_device *dev)
2840 {
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 if (!i915.enable_hangcheck)
2843 return;
2844
2845 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2846 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2847 }
2848
2849 static void ibx_irq_reset(struct drm_device *dev)
2850 {
2851 struct drm_i915_private *dev_priv = dev->dev_private;
2852
2853 if (HAS_PCH_NOP(dev))
2854 return;
2855
2856 GEN5_IRQ_RESET(SDE);
2857
2858 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2859 I915_WRITE(SERR_INT, 0xffffffff);
2860 }
2861
2862 /*
2863 * SDEIER is also touched by the interrupt handler to work around missed PCH
2864 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2865 * instead we unconditionally enable all PCH interrupt sources here, but then
2866 * only unmask them as needed with SDEIMR.
2867 *
2868 * This function needs to be called before interrupts are enabled.
2869 */
2870 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2871 {
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873
2874 if (HAS_PCH_NOP(dev))
2875 return;
2876
2877 WARN_ON(I915_READ(SDEIER) != 0);
2878 I915_WRITE(SDEIER, 0xffffffff);
2879 POSTING_READ(SDEIER);
2880 }
2881
2882 static void gen5_gt_irq_reset(struct drm_device *dev)
2883 {
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885
2886 GEN5_IRQ_RESET(GT);
2887 if (INTEL_INFO(dev)->gen >= 6)
2888 GEN5_IRQ_RESET(GEN6_PM);
2889 }
2890
2891 /* drm_dma.h hooks
2892 */
2893 static void ironlake_irq_reset(struct drm_device *dev)
2894 {
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897 I915_WRITE(HWSTAM, 0xffffffff);
2898
2899 GEN5_IRQ_RESET(DE);
2900 if (IS_GEN7(dev))
2901 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2902
2903 gen5_gt_irq_reset(dev);
2904
2905 ibx_irq_reset(dev);
2906 }
2907
2908 static void ironlake_irq_preinstall(struct drm_device *dev)
2909 {
2910 ironlake_irq_reset(dev);
2911 }
2912
2913 static void valleyview_irq_preinstall(struct drm_device *dev)
2914 {
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 int pipe;
2917
2918 /* VLV magic */
2919 I915_WRITE(VLV_IMR, 0);
2920 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2921 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2922 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2923
2924 /* and GT */
2925 I915_WRITE(GTIIR, I915_READ(GTIIR));
2926 I915_WRITE(GTIIR, I915_READ(GTIIR));
2927
2928 gen5_gt_irq_reset(dev);
2929
2930 I915_WRITE(DPINVGTT, 0xff);
2931
2932 I915_WRITE(PORT_HOTPLUG_EN, 0);
2933 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2934 for_each_pipe(pipe)
2935 I915_WRITE(PIPESTAT(pipe), 0xffff);
2936 I915_WRITE(VLV_IIR, 0xffffffff);
2937 I915_WRITE(VLV_IMR, 0xffffffff);
2938 I915_WRITE(VLV_IER, 0x0);
2939 POSTING_READ(VLV_IER);
2940 }
2941
2942 static void gen8_irq_reset(struct drm_device *dev)
2943 {
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 int pipe;
2946
2947 I915_WRITE(GEN8_MASTER_IRQ, 0);
2948 POSTING_READ(GEN8_MASTER_IRQ);
2949
2950 GEN8_IRQ_RESET_NDX(GT, 0);
2951 GEN8_IRQ_RESET_NDX(GT, 1);
2952 GEN8_IRQ_RESET_NDX(GT, 2);
2953 GEN8_IRQ_RESET_NDX(GT, 3);
2954
2955 for_each_pipe(pipe)
2956 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
2957
2958 GEN5_IRQ_RESET(GEN8_DE_PORT_);
2959 GEN5_IRQ_RESET(GEN8_DE_MISC_);
2960 GEN5_IRQ_RESET(GEN8_PCU_);
2961
2962 ibx_irq_reset(dev);
2963 }
2964
2965 static void gen8_irq_preinstall(struct drm_device *dev)
2966 {
2967 gen8_irq_reset(dev);
2968 }
2969
2970 static void ibx_hpd_irq_setup(struct drm_device *dev)
2971 {
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2973 struct drm_mode_config *mode_config = &dev->mode_config;
2974 struct intel_encoder *intel_encoder;
2975 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2976
2977 if (HAS_PCH_IBX(dev)) {
2978 hotplug_irqs = SDE_HOTPLUG_MASK;
2979 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2980 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2981 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2982 } else {
2983 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2984 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2985 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2986 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2987 }
2988
2989 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2990
2991 /*
2992 * Enable digital hotplug on the PCH, and configure the DP short pulse
2993 * duration to 2ms (which is the minimum in the Display Port spec)
2994 *
2995 * This register is the same on all known PCH chips.
2996 */
2997 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2998 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2999 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3000 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3001 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3002 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3003 }
3004
3005 static void ibx_irq_postinstall(struct drm_device *dev)
3006 {
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 mask;
3009
3010 if (HAS_PCH_NOP(dev))
3011 return;
3012
3013 if (HAS_PCH_IBX(dev))
3014 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3015 else
3016 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3017
3018 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3019 I915_WRITE(SDEIMR, ~mask);
3020 }
3021
3022 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3023 {
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 u32 pm_irqs, gt_irqs;
3026
3027 pm_irqs = gt_irqs = 0;
3028
3029 dev_priv->gt_irq_mask = ~0;
3030 if (HAS_L3_DPF(dev)) {
3031 /* L3 parity interrupt is always unmasked. */
3032 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3033 gt_irqs |= GT_PARITY_ERROR(dev);
3034 }
3035
3036 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3037 if (IS_GEN5(dev)) {
3038 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3039 ILK_BSD_USER_INTERRUPT;
3040 } else {
3041 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3042 }
3043
3044 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3045
3046 if (INTEL_INFO(dev)->gen >= 6) {
3047 pm_irqs |= dev_priv->pm_rps_events;
3048
3049 if (HAS_VEBOX(dev))
3050 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3051
3052 dev_priv->pm_irq_mask = 0xffffffff;
3053 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3054 }
3055 }
3056
3057 static int ironlake_irq_postinstall(struct drm_device *dev)
3058 {
3059 unsigned long irqflags;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 u32 display_mask, extra_mask;
3062
3063 if (INTEL_INFO(dev)->gen >= 7) {
3064 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3065 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3066 DE_PLANEB_FLIP_DONE_IVB |
3067 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3068 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3069 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3070 } else {
3071 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3072 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3073 DE_AUX_CHANNEL_A |
3074 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3075 DE_POISON);
3076 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3077 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3078 }
3079
3080 dev_priv->irq_mask = ~display_mask;
3081
3082 I915_WRITE(HWSTAM, 0xeffe);
3083
3084 ibx_irq_pre_postinstall(dev);
3085
3086 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3087
3088 gen5_gt_irq_postinstall(dev);
3089
3090 ibx_irq_postinstall(dev);
3091
3092 if (IS_IRONLAKE_M(dev)) {
3093 /* Enable PCU event interrupts
3094 *
3095 * spinlocking not required here for correctness since interrupt
3096 * setup is guaranteed to run in single-threaded context. But we
3097 * need it to make the assert_spin_locked happy. */
3098 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3099 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3100 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3101 }
3102
3103 return 0;
3104 }
3105
3106 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3107 {
3108 u32 pipestat_mask;
3109 u32 iir_mask;
3110
3111 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3112 PIPE_FIFO_UNDERRUN_STATUS;
3113
3114 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3115 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3116 POSTING_READ(PIPESTAT(PIPE_A));
3117
3118 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3119 PIPE_CRC_DONE_INTERRUPT_STATUS;
3120
3121 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3122 PIPE_GMBUS_INTERRUPT_STATUS);
3123 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3124
3125 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3126 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3127 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3128 dev_priv->irq_mask &= ~iir_mask;
3129
3130 I915_WRITE(VLV_IIR, iir_mask);
3131 I915_WRITE(VLV_IIR, iir_mask);
3132 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3133 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3134 POSTING_READ(VLV_IER);
3135 }
3136
3137 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3138 {
3139 u32 pipestat_mask;
3140 u32 iir_mask;
3141
3142 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3143 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3144 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3145
3146 dev_priv->irq_mask |= iir_mask;
3147 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3148 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3149 I915_WRITE(VLV_IIR, iir_mask);
3150 I915_WRITE(VLV_IIR, iir_mask);
3151 POSTING_READ(VLV_IIR);
3152
3153 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3154 PIPE_CRC_DONE_INTERRUPT_STATUS;
3155
3156 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3157 PIPE_GMBUS_INTERRUPT_STATUS);
3158 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3159
3160 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3161 PIPE_FIFO_UNDERRUN_STATUS;
3162 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3163 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3164 POSTING_READ(PIPESTAT(PIPE_A));
3165 }
3166
3167 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3168 {
3169 assert_spin_locked(&dev_priv->irq_lock);
3170
3171 if (dev_priv->display_irqs_enabled)
3172 return;
3173
3174 dev_priv->display_irqs_enabled = true;
3175
3176 if (dev_priv->dev->irq_enabled)
3177 valleyview_display_irqs_install(dev_priv);
3178 }
3179
3180 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3181 {
3182 assert_spin_locked(&dev_priv->irq_lock);
3183
3184 if (!dev_priv->display_irqs_enabled)
3185 return;
3186
3187 dev_priv->display_irqs_enabled = false;
3188
3189 if (dev_priv->dev->irq_enabled)
3190 valleyview_display_irqs_uninstall(dev_priv);
3191 }
3192
3193 static int valleyview_irq_postinstall(struct drm_device *dev)
3194 {
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 unsigned long irqflags;
3197
3198 dev_priv->irq_mask = ~0;
3199
3200 I915_WRITE(PORT_HOTPLUG_EN, 0);
3201 POSTING_READ(PORT_HOTPLUG_EN);
3202
3203 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3204 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3205 I915_WRITE(VLV_IIR, 0xffffffff);
3206 POSTING_READ(VLV_IER);
3207
3208 /* Interrupt setup is already guaranteed to be single-threaded, this is
3209 * just to make the assert_spin_locked check happy. */
3210 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3211 if (dev_priv->display_irqs_enabled)
3212 valleyview_display_irqs_install(dev_priv);
3213 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3214
3215 I915_WRITE(VLV_IIR, 0xffffffff);
3216 I915_WRITE(VLV_IIR, 0xffffffff);
3217
3218 gen5_gt_irq_postinstall(dev);
3219
3220 /* ack & enable invalid PTE error interrupts */
3221 #if 0 /* FIXME: add support to irq handler for checking these bits */
3222 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3223 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3224 #endif
3225
3226 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3227
3228 return 0;
3229 }
3230
3231 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3232 {
3233 int i;
3234
3235 /* These are interrupts we'll toggle with the ring mask register */
3236 uint32_t gt_interrupts[] = {
3237 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3238 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3239 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3240 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3241 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3242 0,
3243 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3244 };
3245
3246 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3247 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3248 }
3249
3250 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3251 {
3252 struct drm_device *dev = dev_priv->dev;
3253 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3254 GEN8_PIPE_CDCLK_CRC_DONE |
3255 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3256 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3257 GEN8_PIPE_FIFO_UNDERRUN;
3258 int pipe;
3259 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3260 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3261 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3262
3263 for_each_pipe(pipe)
3264 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3265 de_pipe_enables);
3266
3267 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3268 }
3269
3270 static int gen8_irq_postinstall(struct drm_device *dev)
3271 {
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274 ibx_irq_pre_postinstall(dev);
3275
3276 gen8_gt_irq_postinstall(dev_priv);
3277 gen8_de_irq_postinstall(dev_priv);
3278
3279 ibx_irq_postinstall(dev);
3280
3281 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3282 POSTING_READ(GEN8_MASTER_IRQ);
3283
3284 return 0;
3285 }
3286
3287 static void gen8_irq_uninstall(struct drm_device *dev)
3288 {
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290
3291 if (!dev_priv)
3292 return;
3293
3294 intel_hpd_irq_uninstall(dev_priv);
3295
3296 gen8_irq_reset(dev);
3297 }
3298
3299 static void valleyview_irq_uninstall(struct drm_device *dev)
3300 {
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 unsigned long irqflags;
3303 int pipe;
3304
3305 if (!dev_priv)
3306 return;
3307
3308 intel_hpd_irq_uninstall(dev_priv);
3309
3310 for_each_pipe(pipe)
3311 I915_WRITE(PIPESTAT(pipe), 0xffff);
3312
3313 I915_WRITE(HWSTAM, 0xffffffff);
3314 I915_WRITE(PORT_HOTPLUG_EN, 0);
3315 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3316
3317 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3318 if (dev_priv->display_irqs_enabled)
3319 valleyview_display_irqs_uninstall(dev_priv);
3320 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3321
3322 dev_priv->irq_mask = 0;
3323
3324 I915_WRITE(VLV_IIR, 0xffffffff);
3325 I915_WRITE(VLV_IMR, 0xffffffff);
3326 I915_WRITE(VLV_IER, 0x0);
3327 POSTING_READ(VLV_IER);
3328 }
3329
3330 static void ironlake_irq_uninstall(struct drm_device *dev)
3331 {
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333
3334 if (!dev_priv)
3335 return;
3336
3337 intel_hpd_irq_uninstall(dev_priv);
3338
3339 ironlake_irq_reset(dev);
3340 }
3341
3342 static void i8xx_irq_preinstall(struct drm_device * dev)
3343 {
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe;
3346
3347 for_each_pipe(pipe)
3348 I915_WRITE(PIPESTAT(pipe), 0);
3349 I915_WRITE16(IMR, 0xffff);
3350 I915_WRITE16(IER, 0x0);
3351 POSTING_READ16(IER);
3352 }
3353
3354 static int i8xx_irq_postinstall(struct drm_device *dev)
3355 {
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357 unsigned long irqflags;
3358
3359 I915_WRITE16(EMR,
3360 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3361
3362 /* Unmask the interrupts that we always want on. */
3363 dev_priv->irq_mask =
3364 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3365 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3366 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3367 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3368 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3369 I915_WRITE16(IMR, dev_priv->irq_mask);
3370
3371 I915_WRITE16(IER,
3372 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3373 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3374 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3375 I915_USER_INTERRUPT);
3376 POSTING_READ16(IER);
3377
3378 /* Interrupt setup is already guaranteed to be single-threaded, this is
3379 * just to make the assert_spin_locked check happy. */
3380 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3381 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3382 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3383 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3384
3385 return 0;
3386 }
3387
3388 /*
3389 * Returns true when a page flip has completed.
3390 */
3391 static bool i8xx_handle_vblank(struct drm_device *dev,
3392 int plane, int pipe, u32 iir)
3393 {
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3396
3397 if (!drm_handle_vblank(dev, pipe))
3398 return false;
3399
3400 if ((iir & flip_pending) == 0)
3401 return false;
3402
3403 intel_prepare_page_flip(dev, plane);
3404
3405 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3406 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3407 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3408 * the flip is completed (no longer pending). Since this doesn't raise
3409 * an interrupt per se, we watch for the change at vblank.
3410 */
3411 if (I915_READ16(ISR) & flip_pending)
3412 return false;
3413
3414 intel_finish_page_flip(dev, pipe);
3415
3416 return true;
3417 }
3418
3419 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3420 {
3421 struct drm_device *dev = (struct drm_device *) arg;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 u16 iir, new_iir;
3424 u32 pipe_stats[2];
3425 unsigned long irqflags;
3426 int pipe;
3427 u16 flip_mask =
3428 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3429 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3430
3431 iir = I915_READ16(IIR);
3432 if (iir == 0)
3433 return IRQ_NONE;
3434
3435 while (iir & ~flip_mask) {
3436 /* Can't rely on pipestat interrupt bit in iir as it might
3437 * have been cleared after the pipestat interrupt was received.
3438 * It doesn't set the bit in iir again, but it still produces
3439 * interrupts (for non-MSI).
3440 */
3441 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3442 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3443 i915_handle_error(dev, false,
3444 "Command parser error, iir 0x%08x",
3445 iir);
3446
3447 for_each_pipe(pipe) {
3448 int reg = PIPESTAT(pipe);
3449 pipe_stats[pipe] = I915_READ(reg);
3450
3451 /*
3452 * Clear the PIPE*STAT regs before the IIR
3453 */
3454 if (pipe_stats[pipe] & 0x8000ffff)
3455 I915_WRITE(reg, pipe_stats[pipe]);
3456 }
3457 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3458
3459 I915_WRITE16(IIR, iir & ~flip_mask);
3460 new_iir = I915_READ16(IIR); /* Flush posted writes */
3461
3462 i915_update_dri1_breadcrumb(dev);
3463
3464 if (iir & I915_USER_INTERRUPT)
3465 notify_ring(dev, &dev_priv->ring[RCS]);
3466
3467 for_each_pipe(pipe) {
3468 int plane = pipe;
3469 if (HAS_FBC(dev))
3470 plane = !plane;
3471
3472 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3473 i8xx_handle_vblank(dev, plane, pipe, iir))
3474 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3475
3476 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3477 i9xx_pipe_crc_irq_handler(dev, pipe);
3478
3479 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3480 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3481 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3482 }
3483
3484 iir = new_iir;
3485 }
3486
3487 return IRQ_HANDLED;
3488 }
3489
3490 static void i8xx_irq_uninstall(struct drm_device * dev)
3491 {
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 int pipe;
3494
3495 for_each_pipe(pipe) {
3496 /* Clear enable bits; then clear status bits */
3497 I915_WRITE(PIPESTAT(pipe), 0);
3498 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3499 }
3500 I915_WRITE16(IMR, 0xffff);
3501 I915_WRITE16(IER, 0x0);
3502 I915_WRITE16(IIR, I915_READ16(IIR));
3503 }
3504
3505 static void i915_irq_preinstall(struct drm_device * dev)
3506 {
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 int pipe;
3509
3510 if (I915_HAS_HOTPLUG(dev)) {
3511 I915_WRITE(PORT_HOTPLUG_EN, 0);
3512 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3513 }
3514
3515 I915_WRITE16(HWSTAM, 0xeffe);
3516 for_each_pipe(pipe)
3517 I915_WRITE(PIPESTAT(pipe), 0);
3518 I915_WRITE(IMR, 0xffffffff);
3519 I915_WRITE(IER, 0x0);
3520 POSTING_READ(IER);
3521 }
3522
3523 static int i915_irq_postinstall(struct drm_device *dev)
3524 {
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526 u32 enable_mask;
3527 unsigned long irqflags;
3528
3529 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3530
3531 /* Unmask the interrupts that we always want on. */
3532 dev_priv->irq_mask =
3533 ~(I915_ASLE_INTERRUPT |
3534 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3535 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3536 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3537 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3538 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3539
3540 enable_mask =
3541 I915_ASLE_INTERRUPT |
3542 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3543 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3544 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3545 I915_USER_INTERRUPT;
3546
3547 if (I915_HAS_HOTPLUG(dev)) {
3548 I915_WRITE(PORT_HOTPLUG_EN, 0);
3549 POSTING_READ(PORT_HOTPLUG_EN);
3550
3551 /* Enable in IER... */
3552 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3553 /* and unmask in IMR */
3554 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3555 }
3556
3557 I915_WRITE(IMR, dev_priv->irq_mask);
3558 I915_WRITE(IER, enable_mask);
3559 POSTING_READ(IER);
3560
3561 i915_enable_asle_pipestat(dev);
3562
3563 /* Interrupt setup is already guaranteed to be single-threaded, this is
3564 * just to make the assert_spin_locked check happy. */
3565 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3566 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3567 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3568 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3569
3570 return 0;
3571 }
3572
3573 /*
3574 * Returns true when a page flip has completed.
3575 */
3576 static bool i915_handle_vblank(struct drm_device *dev,
3577 int plane, int pipe, u32 iir)
3578 {
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3581
3582 if (!drm_handle_vblank(dev, pipe))
3583 return false;
3584
3585 if ((iir & flip_pending) == 0)
3586 return false;
3587
3588 intel_prepare_page_flip(dev, plane);
3589
3590 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3591 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3592 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3593 * the flip is completed (no longer pending). Since this doesn't raise
3594 * an interrupt per se, we watch for the change at vblank.
3595 */
3596 if (I915_READ(ISR) & flip_pending)
3597 return false;
3598
3599 intel_finish_page_flip(dev, pipe);
3600
3601 return true;
3602 }
3603
3604 static irqreturn_t i915_irq_handler(int irq, void *arg)
3605 {
3606 struct drm_device *dev = (struct drm_device *) arg;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3609 unsigned long irqflags;
3610 u32 flip_mask =
3611 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3612 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3613 int pipe, ret = IRQ_NONE;
3614
3615 iir = I915_READ(IIR);
3616 do {
3617 bool irq_received = (iir & ~flip_mask) != 0;
3618 bool blc_event = false;
3619
3620 /* Can't rely on pipestat interrupt bit in iir as it might
3621 * have been cleared after the pipestat interrupt was received.
3622 * It doesn't set the bit in iir again, but it still produces
3623 * interrupts (for non-MSI).
3624 */
3625 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3626 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3627 i915_handle_error(dev, false,
3628 "Command parser error, iir 0x%08x",
3629 iir);
3630
3631 for_each_pipe(pipe) {
3632 int reg = PIPESTAT(pipe);
3633 pipe_stats[pipe] = I915_READ(reg);
3634
3635 /* Clear the PIPE*STAT regs before the IIR */
3636 if (pipe_stats[pipe] & 0x8000ffff) {
3637 I915_WRITE(reg, pipe_stats[pipe]);
3638 irq_received = true;
3639 }
3640 }
3641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3642
3643 if (!irq_received)
3644 break;
3645
3646 /* Consume port. Then clear IIR or we'll miss events */
3647 if (I915_HAS_HOTPLUG(dev) &&
3648 iir & I915_DISPLAY_PORT_INTERRUPT)
3649 i9xx_hpd_irq_handler(dev);
3650
3651 I915_WRITE(IIR, iir & ~flip_mask);
3652 new_iir = I915_READ(IIR); /* Flush posted writes */
3653
3654 if (iir & I915_USER_INTERRUPT)
3655 notify_ring(dev, &dev_priv->ring[RCS]);
3656
3657 for_each_pipe(pipe) {
3658 int plane = pipe;
3659 if (HAS_FBC(dev))
3660 plane = !plane;
3661
3662 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3663 i915_handle_vblank(dev, plane, pipe, iir))
3664 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3665
3666 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3667 blc_event = true;
3668
3669 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3670 i9xx_pipe_crc_irq_handler(dev, pipe);
3671
3672 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3673 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3674 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3675 }
3676
3677 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3678 intel_opregion_asle_intr(dev);
3679
3680 /* With MSI, interrupts are only generated when iir
3681 * transitions from zero to nonzero. If another bit got
3682 * set while we were handling the existing iir bits, then
3683 * we would never get another interrupt.
3684 *
3685 * This is fine on non-MSI as well, as if we hit this path
3686 * we avoid exiting the interrupt handler only to generate
3687 * another one.
3688 *
3689 * Note that for MSI this could cause a stray interrupt report
3690 * if an interrupt landed in the time between writing IIR and
3691 * the posting read. This should be rare enough to never
3692 * trigger the 99% of 100,000 interrupts test for disabling
3693 * stray interrupts.
3694 */
3695 ret = IRQ_HANDLED;
3696 iir = new_iir;
3697 } while (iir & ~flip_mask);
3698
3699 i915_update_dri1_breadcrumb(dev);
3700
3701 return ret;
3702 }
3703
3704 static void i915_irq_uninstall(struct drm_device * dev)
3705 {
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 int pipe;
3708
3709 intel_hpd_irq_uninstall(dev_priv);
3710
3711 if (I915_HAS_HOTPLUG(dev)) {
3712 I915_WRITE(PORT_HOTPLUG_EN, 0);
3713 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3714 }
3715
3716 I915_WRITE16(HWSTAM, 0xffff);
3717 for_each_pipe(pipe) {
3718 /* Clear enable bits; then clear status bits */
3719 I915_WRITE(PIPESTAT(pipe), 0);
3720 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3721 }
3722 I915_WRITE(IMR, 0xffffffff);
3723 I915_WRITE(IER, 0x0);
3724
3725 I915_WRITE(IIR, I915_READ(IIR));
3726 }
3727
3728 static void i965_irq_preinstall(struct drm_device * dev)
3729 {
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 int pipe;
3732
3733 I915_WRITE(PORT_HOTPLUG_EN, 0);
3734 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3735
3736 I915_WRITE(HWSTAM, 0xeffe);
3737 for_each_pipe(pipe)
3738 I915_WRITE(PIPESTAT(pipe), 0);
3739 I915_WRITE(IMR, 0xffffffff);
3740 I915_WRITE(IER, 0x0);
3741 POSTING_READ(IER);
3742 }
3743
3744 static int i965_irq_postinstall(struct drm_device *dev)
3745 {
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 u32 enable_mask;
3748 u32 error_mask;
3749 unsigned long irqflags;
3750
3751 /* Unmask the interrupts that we always want on. */
3752 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3753 I915_DISPLAY_PORT_INTERRUPT |
3754 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3755 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3756 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3757 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3758 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3759
3760 enable_mask = ~dev_priv->irq_mask;
3761 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3762 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3763 enable_mask |= I915_USER_INTERRUPT;
3764
3765 if (IS_G4X(dev))
3766 enable_mask |= I915_BSD_USER_INTERRUPT;
3767
3768 /* Interrupt setup is already guaranteed to be single-threaded, this is
3769 * just to make the assert_spin_locked check happy. */
3770 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3771 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3772 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3773 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3774 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775
3776 /*
3777 * Enable some error detection, note the instruction error mask
3778 * bit is reserved, so we leave it masked.
3779 */
3780 if (IS_G4X(dev)) {
3781 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3782 GM45_ERROR_MEM_PRIV |
3783 GM45_ERROR_CP_PRIV |
3784 I915_ERROR_MEMORY_REFRESH);
3785 } else {
3786 error_mask = ~(I915_ERROR_PAGE_TABLE |
3787 I915_ERROR_MEMORY_REFRESH);
3788 }
3789 I915_WRITE(EMR, error_mask);
3790
3791 I915_WRITE(IMR, dev_priv->irq_mask);
3792 I915_WRITE(IER, enable_mask);
3793 POSTING_READ(IER);
3794
3795 I915_WRITE(PORT_HOTPLUG_EN, 0);
3796 POSTING_READ(PORT_HOTPLUG_EN);
3797
3798 i915_enable_asle_pipestat(dev);
3799
3800 return 0;
3801 }
3802
3803 static void i915_hpd_irq_setup(struct drm_device *dev)
3804 {
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct drm_mode_config *mode_config = &dev->mode_config;
3807 struct intel_encoder *intel_encoder;
3808 u32 hotplug_en;
3809
3810 assert_spin_locked(&dev_priv->irq_lock);
3811
3812 if (I915_HAS_HOTPLUG(dev)) {
3813 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3814 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3815 /* Note HDMI and DP share hotplug bits */
3816 /* enable bits are the same for all generations */
3817 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3818 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3819 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3820 /* Programming the CRT detection parameters tends
3821 to generate a spurious hotplug event about three
3822 seconds later. So just do it once.
3823 */
3824 if (IS_G4X(dev))
3825 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3826 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3827 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3828
3829 /* Ignore TV since it's buggy */
3830 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3831 }
3832 }
3833
3834 static irqreturn_t i965_irq_handler(int irq, void *arg)
3835 {
3836 struct drm_device *dev = (struct drm_device *) arg;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 u32 iir, new_iir;
3839 u32 pipe_stats[I915_MAX_PIPES];
3840 unsigned long irqflags;
3841 int ret = IRQ_NONE, pipe;
3842 u32 flip_mask =
3843 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3844 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3845
3846 iir = I915_READ(IIR);
3847
3848 for (;;) {
3849 bool irq_received = (iir & ~flip_mask) != 0;
3850 bool blc_event = false;
3851
3852 /* Can't rely on pipestat interrupt bit in iir as it might
3853 * have been cleared after the pipestat interrupt was received.
3854 * It doesn't set the bit in iir again, but it still produces
3855 * interrupts (for non-MSI).
3856 */
3857 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3858 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3859 i915_handle_error(dev, false,
3860 "Command parser error, iir 0x%08x",
3861 iir);
3862
3863 for_each_pipe(pipe) {
3864 int reg = PIPESTAT(pipe);
3865 pipe_stats[pipe] = I915_READ(reg);
3866
3867 /*
3868 * Clear the PIPE*STAT regs before the IIR
3869 */
3870 if (pipe_stats[pipe] & 0x8000ffff) {
3871 I915_WRITE(reg, pipe_stats[pipe]);
3872 irq_received = true;
3873 }
3874 }
3875 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3876
3877 if (!irq_received)
3878 break;
3879
3880 ret = IRQ_HANDLED;
3881
3882 /* Consume port. Then clear IIR or we'll miss events */
3883 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3884 i9xx_hpd_irq_handler(dev);
3885
3886 I915_WRITE(IIR, iir & ~flip_mask);
3887 new_iir = I915_READ(IIR); /* Flush posted writes */
3888
3889 if (iir & I915_USER_INTERRUPT)
3890 notify_ring(dev, &dev_priv->ring[RCS]);
3891 if (iir & I915_BSD_USER_INTERRUPT)
3892 notify_ring(dev, &dev_priv->ring[VCS]);
3893
3894 for_each_pipe(pipe) {
3895 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3896 i915_handle_vblank(dev, pipe, pipe, iir))
3897 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3898
3899 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3900 blc_event = true;
3901
3902 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3903 i9xx_pipe_crc_irq_handler(dev, pipe);
3904
3905 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3906 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3907 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3908 }
3909
3910 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3911 intel_opregion_asle_intr(dev);
3912
3913 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3914 gmbus_irq_handler(dev);
3915
3916 /* With MSI, interrupts are only generated when iir
3917 * transitions from zero to nonzero. If another bit got
3918 * set while we were handling the existing iir bits, then
3919 * we would never get another interrupt.
3920 *
3921 * This is fine on non-MSI as well, as if we hit this path
3922 * we avoid exiting the interrupt handler only to generate
3923 * another one.
3924 *
3925 * Note that for MSI this could cause a stray interrupt report
3926 * if an interrupt landed in the time between writing IIR and
3927 * the posting read. This should be rare enough to never
3928 * trigger the 99% of 100,000 interrupts test for disabling
3929 * stray interrupts.
3930 */
3931 iir = new_iir;
3932 }
3933
3934 i915_update_dri1_breadcrumb(dev);
3935
3936 return ret;
3937 }
3938
3939 static void i965_irq_uninstall(struct drm_device * dev)
3940 {
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942 int pipe;
3943
3944 if (!dev_priv)
3945 return;
3946
3947 intel_hpd_irq_uninstall(dev_priv);
3948
3949 I915_WRITE(PORT_HOTPLUG_EN, 0);
3950 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3951
3952 I915_WRITE(HWSTAM, 0xffffffff);
3953 for_each_pipe(pipe)
3954 I915_WRITE(PIPESTAT(pipe), 0);
3955 I915_WRITE(IMR, 0xffffffff);
3956 I915_WRITE(IER, 0x0);
3957
3958 for_each_pipe(pipe)
3959 I915_WRITE(PIPESTAT(pipe),
3960 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3961 I915_WRITE(IIR, I915_READ(IIR));
3962 }
3963
3964 static void intel_hpd_irq_reenable(unsigned long data)
3965 {
3966 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
3967 struct drm_device *dev = dev_priv->dev;
3968 struct drm_mode_config *mode_config = &dev->mode_config;
3969 unsigned long irqflags;
3970 int i;
3971
3972 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3973 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3974 struct drm_connector *connector;
3975
3976 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3977 continue;
3978
3979 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3980
3981 list_for_each_entry(connector, &mode_config->connector_list, head) {
3982 struct intel_connector *intel_connector = to_intel_connector(connector);
3983
3984 if (intel_connector->encoder->hpd_pin == i) {
3985 if (connector->polled != intel_connector->polled)
3986 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3987 drm_get_connector_name(connector));
3988 connector->polled = intel_connector->polled;
3989 if (!connector->polled)
3990 connector->polled = DRM_CONNECTOR_POLL_HPD;
3991 }
3992 }
3993 }
3994 if (dev_priv->display.hpd_irq_setup)
3995 dev_priv->display.hpd_irq_setup(dev);
3996 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3997 }
3998
3999 void intel_irq_init(struct drm_device *dev)
4000 {
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002
4003 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4004 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4005 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4006 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4007
4008 /* Let's track the enabled rps events */
4009 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4010
4011 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4012 i915_hangcheck_elapsed,
4013 (unsigned long) dev);
4014 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4015 (unsigned long) dev_priv);
4016
4017 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4018
4019 if (IS_GEN2(dev)) {
4020 dev->max_vblank_count = 0;
4021 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4022 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4025 } else {
4026 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4027 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4028 }
4029
4030 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4031 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4032 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4033 }
4034
4035 if (IS_VALLEYVIEW(dev)) {
4036 dev->driver->irq_handler = valleyview_irq_handler;
4037 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4038 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4039 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4040 dev->driver->enable_vblank = valleyview_enable_vblank;
4041 dev->driver->disable_vblank = valleyview_disable_vblank;
4042 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4043 } else if (IS_GEN8(dev)) {
4044 dev->driver->irq_handler = gen8_irq_handler;
4045 dev->driver->irq_preinstall = gen8_irq_preinstall;
4046 dev->driver->irq_postinstall = gen8_irq_postinstall;
4047 dev->driver->irq_uninstall = gen8_irq_uninstall;
4048 dev->driver->enable_vblank = gen8_enable_vblank;
4049 dev->driver->disable_vblank = gen8_disable_vblank;
4050 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4051 } else if (HAS_PCH_SPLIT(dev)) {
4052 dev->driver->irq_handler = ironlake_irq_handler;
4053 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4054 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4055 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4056 dev->driver->enable_vblank = ironlake_enable_vblank;
4057 dev->driver->disable_vblank = ironlake_disable_vblank;
4058 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4059 } else {
4060 if (INTEL_INFO(dev)->gen == 2) {
4061 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4062 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4063 dev->driver->irq_handler = i8xx_irq_handler;
4064 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4065 } else if (INTEL_INFO(dev)->gen == 3) {
4066 dev->driver->irq_preinstall = i915_irq_preinstall;
4067 dev->driver->irq_postinstall = i915_irq_postinstall;
4068 dev->driver->irq_uninstall = i915_irq_uninstall;
4069 dev->driver->irq_handler = i915_irq_handler;
4070 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4071 } else {
4072 dev->driver->irq_preinstall = i965_irq_preinstall;
4073 dev->driver->irq_postinstall = i965_irq_postinstall;
4074 dev->driver->irq_uninstall = i965_irq_uninstall;
4075 dev->driver->irq_handler = i965_irq_handler;
4076 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4077 }
4078 dev->driver->enable_vblank = i915_enable_vblank;
4079 dev->driver->disable_vblank = i915_disable_vblank;
4080 }
4081 }
4082
4083 void intel_hpd_init(struct drm_device *dev)
4084 {
4085 struct drm_i915_private *dev_priv = dev->dev_private;
4086 struct drm_mode_config *mode_config = &dev->mode_config;
4087 struct drm_connector *connector;
4088 unsigned long irqflags;
4089 int i;
4090
4091 for (i = 1; i < HPD_NUM_PINS; i++) {
4092 dev_priv->hpd_stats[i].hpd_cnt = 0;
4093 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4094 }
4095 list_for_each_entry(connector, &mode_config->connector_list, head) {
4096 struct intel_connector *intel_connector = to_intel_connector(connector);
4097 connector->polled = intel_connector->polled;
4098 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4099 connector->polled = DRM_CONNECTOR_POLL_HPD;
4100 }
4101
4102 /* Interrupt setup is already guaranteed to be single-threaded, this is
4103 * just to make the assert_spin_locked checks happy. */
4104 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4105 if (dev_priv->display.hpd_irq_setup)
4106 dev_priv->display.hpd_irq_setup(dev);
4107 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4108 }
4109
4110 /* Disable interrupts so we can allow runtime PM. */
4111 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4112 {
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114
4115 dev->driver->irq_uninstall(dev);
4116 dev_priv->pm.irqs_disabled = true;
4117 }
4118
4119 /* Restore interrupts so we can recover from runtime PM. */
4120 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4121 {
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123
4124 dev_priv->pm.irqs_disabled = false;
4125 dev->driver->irq_preinstall(dev);
4126 dev->driver->irq_postinstall(dev);
4127 }
Linux kernel - Deliverables
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