1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
344 spin_lock_irq(&dev_priv
->irq_lock
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
346 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
348 dev_priv
->rps
.pm_iir
= 0;
349 spin_unlock_irq(&dev_priv
->irq_lock
);
352 void gen6_enable_rps_interrupts(struct drm_device
*dev
)
354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
356 spin_lock_irq(&dev_priv
->irq_lock
);
358 WARN_ON(dev_priv
->rps
.pm_iir
);
359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
360 dev_priv
->rps
.interrupts_enabled
= true;
361 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
362 dev_priv
->pm_rps_events
);
363 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
365 spin_unlock_irq(&dev_priv
->irq_lock
);
368 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
372 * if GEN6_PM_UP_EI_EXPIRED is masked.
374 * TODO: verify if this can be reproduced on VLV,CHV.
376 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
377 mask
&= ~GEN6_PM_RP_UP_EI_EXPIRED
;
379 if (INTEL_INFO(dev_priv
)->gen
>= 8)
380 mask
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
385 void gen6_disable_rps_interrupts(struct drm_device
*dev
)
387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
389 spin_lock_irq(&dev_priv
->irq_lock
);
390 dev_priv
->rps
.interrupts_enabled
= false;
391 spin_unlock_irq(&dev_priv
->irq_lock
);
393 cancel_work_sync(&dev_priv
->rps
.work
);
395 spin_lock_irq(&dev_priv
->irq_lock
);
397 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
399 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
400 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
401 ~dev_priv
->pm_rps_events
);
403 spin_unlock_irq(&dev_priv
->irq_lock
);
405 synchronize_irq(dev
->irq
);
409 * bdw_update_port_irq - update DE port interrupt
410 * @dev_priv: driver private
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
414 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
415 uint32_t interrupt_mask
,
416 uint32_t enabled_irq_mask
)
421 assert_spin_locked(&dev_priv
->irq_lock
);
423 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
425 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
428 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
431 new_val
&= ~interrupt_mask
;
432 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
434 if (new_val
!= old_val
) {
435 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
436 POSTING_READ(GEN8_DE_PORT_IMR
);
441 * bdw_update_pipe_irq - update DE pipe interrupt
442 * @dev_priv: driver private
443 * @pipe: pipe whose interrupt to update
444 * @interrupt_mask: mask of interrupt bits to update
445 * @enabled_irq_mask: mask of interrupt bits to enable
447 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
449 uint32_t interrupt_mask
,
450 uint32_t enabled_irq_mask
)
454 assert_spin_locked(&dev_priv
->irq_lock
);
456 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
458 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
461 new_val
= dev_priv
->de_irq_mask
[pipe
];
462 new_val
&= ~interrupt_mask
;
463 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
465 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
466 dev_priv
->de_irq_mask
[pipe
] = new_val
;
467 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
468 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
473 * ibx_display_interrupt_update - update SDEIMR
474 * @dev_priv: driver private
475 * @interrupt_mask: mask of interrupt bits to update
476 * @enabled_irq_mask: mask of interrupt bits to enable
478 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
479 uint32_t interrupt_mask
,
480 uint32_t enabled_irq_mask
)
482 uint32_t sdeimr
= I915_READ(SDEIMR
);
483 sdeimr
&= ~interrupt_mask
;
484 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
486 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
488 assert_spin_locked(&dev_priv
->irq_lock
);
490 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
493 I915_WRITE(SDEIMR
, sdeimr
);
494 POSTING_READ(SDEIMR
);
498 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
499 u32 enable_mask
, u32 status_mask
)
501 i915_reg_t reg
= PIPESTAT(pipe
);
502 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
504 assert_spin_locked(&dev_priv
->irq_lock
);
505 WARN_ON(!intel_irqs_enabled(dev_priv
));
507 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
508 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
509 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
510 pipe_name(pipe
), enable_mask
, status_mask
))
513 if ((pipestat
& enable_mask
) == enable_mask
)
516 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
518 /* Enable the interrupt, clear any pending status */
519 pipestat
|= enable_mask
| status_mask
;
520 I915_WRITE(reg
, pipestat
);
525 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
526 u32 enable_mask
, u32 status_mask
)
528 i915_reg_t reg
= PIPESTAT(pipe
);
529 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
531 assert_spin_locked(&dev_priv
->irq_lock
);
532 WARN_ON(!intel_irqs_enabled(dev_priv
));
534 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
535 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe
), enable_mask
, status_mask
))
540 if ((pipestat
& enable_mask
) == 0)
543 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
545 pipestat
&= ~enable_mask
;
546 I915_WRITE(reg
, pipestat
);
550 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
552 u32 enable_mask
= status_mask
<< 16;
555 * On pipe A we don't support the PSR interrupt yet,
556 * on pipe B and C the same bit MBZ.
558 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
561 * On pipe B and C we don't support the PSR interrupt yet, on pipe
562 * A the same bit is for perf counters which we don't use either.
564 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
567 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
568 SPRITE0_FLIP_DONE_INT_EN_VLV
|
569 SPRITE1_FLIP_DONE_INT_EN_VLV
);
570 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
571 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
572 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
573 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
579 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
584 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
585 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
588 enable_mask
= status_mask
<< 16;
589 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
593 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
598 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
599 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
602 enable_mask
= status_mask
<< 16;
603 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
610 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
617 spin_lock_irq(&dev_priv
->irq_lock
);
619 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
620 if (INTEL_INFO(dev
)->gen
>= 4)
621 i915_enable_pipestat(dev_priv
, PIPE_A
,
622 PIPE_LEGACY_BLC_EVENT_STATUS
);
624 spin_unlock_irq(&dev_priv
->irq_lock
);
628 * This timing diagram depicts the video signal in and
629 * around the vertical blanking period.
631 * Assumptions about the fictitious mode used in this example:
633 * vsync_start = vblank_start + 1
634 * vsync_end = vblank_start + 2
635 * vtotal = vblank_start + 3
638 * latch double buffered registers
639 * increment frame counter (ctg+)
640 * generate start of vblank interrupt (gen4+)
643 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
644 * | may be shifted forward 1-3 extra lines via PIPECONF
646 * | | start of vsync:
647 * | | generate vsync interrupt
649 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
650 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
651 * ----va---> <-----------------vb--------------------> <--------va-------------
652 * | | <----vs-----> |
653 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
654 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
655 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
657 * last visible pixel first visible pixel
658 * | increment frame counter (gen3/4)
659 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
661 * x = horizontal active
662 * _ = horizontal blanking
663 * hs = horizontal sync
664 * va = vertical active
665 * vb = vertical blanking
667 * vbs = vblank_start (number)
670 * - most events happen at the start of horizontal sync
671 * - frame start happens at the start of horizontal blank, 1-4 lines
672 * (depending on PIPECONF settings) after the start of vblank
673 * - gen3/4 pixel and frame counter are synchronized with the start
674 * of horizontal active on the first line of vertical active
677 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
679 /* Gen2 doesn't have a hardware frame counter */
683 /* Called from drm generic code, passed a 'crtc', which
684 * we use as a pipe index
686 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 i915_reg_t high_frame
, low_frame
;
690 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
691 struct intel_crtc
*intel_crtc
=
692 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
693 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
695 htotal
= mode
->crtc_htotal
;
696 hsync_start
= mode
->crtc_hsync_start
;
697 vbl_start
= mode
->crtc_vblank_start
;
698 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
699 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
701 /* Convert to pixel count */
704 /* Start of vblank event occurs at start of hsync */
705 vbl_start
-= htotal
- hsync_start
;
707 high_frame
= PIPEFRAME(pipe
);
708 low_frame
= PIPEFRAMEPIXEL(pipe
);
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
716 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
717 low
= I915_READ(low_frame
);
718 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
719 } while (high1
!= high2
);
721 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
722 pixel
= low
& PIPE_PIXEL_MASK
;
723 low
>>= PIPE_FRAME_LOW_SHIFT
;
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
730 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
733 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
740 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
741 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
743 struct drm_device
*dev
= crtc
->base
.dev
;
744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
746 enum pipe pipe
= crtc
->pipe
;
747 int position
, vtotal
;
749 vtotal
= mode
->crtc_vtotal
;
750 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
754 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
756 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
759 * On HSW, the DSL reg (0x70000) appears to return 0 if we
760 * read it just before the start of vblank. So try it again
761 * so we don't accidentally end up spanning a vblank frame
762 * increment, causing the pipe_update_end() code to squak at us.
764 * The nature of this problem means we can't simply check the ISR
765 * bit and return the vblank start value; nor can we use the scanline
766 * debug register in the transcoder as it appears to have the same
767 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW.
770 if (HAS_DDI(dev
) && !position
) {
773 for (i
= 0; i
< 100; i
++) {
775 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
777 if (temp
!= position
) {
785 * See update_scanline_offset() for the details on the
786 * scanline_offset adjustment.
788 return (position
+ crtc
->scanline_offset
) % vtotal
;
791 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
792 unsigned int flags
, int *vpos
, int *hpos
,
793 ktime_t
*stime
, ktime_t
*etime
,
794 const struct drm_display_mode
*mode
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
800 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
803 unsigned long irqflags
;
805 if (WARN_ON(!mode
->crtc_clock
)) {
806 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
807 "pipe %c\n", pipe_name(pipe
));
811 htotal
= mode
->crtc_htotal
;
812 hsync_start
= mode
->crtc_hsync_start
;
813 vtotal
= mode
->crtc_vtotal
;
814 vbl_start
= mode
->crtc_vblank_start
;
815 vbl_end
= mode
->crtc_vblank_end
;
817 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
818 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
823 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
830 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
834 /* Get optional system timestamp before query. */
836 *stime
= ktime_get();
838 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
842 position
= __intel_get_crtc_scanline(intel_crtc
);
844 /* Have access to pixelcount since start of frame.
845 * We can split this into vertical and horizontal
848 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
850 /* convert to pixel counts */
856 * In interlaced modes, the pixel counter counts all pixels,
857 * so one field will have htotal more pixels. In order to avoid
858 * the reported position from jumping backwards when the pixel
859 * counter is beyond the length of the shorter field, just
860 * clamp the position the length of the shorter field. This
861 * matches how the scanline counter based position works since
862 * the scanline counter doesn't count the two half lines.
864 if (position
>= vtotal
)
865 position
= vtotal
- 1;
868 * Start of vblank interrupt is triggered at start of hsync,
869 * just prior to the first active line of vblank. However we
870 * consider lines to start at the leading edge of horizontal
871 * active. So, should we get here before we've crossed into
872 * the horizontal active of the first line in vblank, we would
873 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
874 * always add htotal-hsync_start to the current pixel position.
876 position
= (position
+ htotal
- hsync_start
) % vtotal
;
879 /* Get optional system timestamp after query. */
881 *etime
= ktime_get();
883 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
885 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
887 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
890 * While in vblank, position will be negative
891 * counting up towards 0 at vbl_end. And outside
892 * vblank, position will be positive counting
895 if (position
>= vbl_start
)
898 position
+= vtotal
- vbl_end
;
900 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
904 *vpos
= position
/ htotal
;
905 *hpos
= position
- (*vpos
* htotal
);
910 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
915 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
917 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
918 unsigned long irqflags
;
921 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
922 position
= __intel_get_crtc_scanline(crtc
);
923 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
928 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
930 struct timeval
*vblank_time
,
933 struct drm_crtc
*crtc
;
935 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
936 DRM_ERROR("Invalid crtc %u\n", pipe
);
940 /* Get drm_crtc to timestamp: */
941 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
943 DRM_ERROR("Invalid crtc %u\n", pipe
);
947 if (!crtc
->hwmode
.crtc_clock
) {
948 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
952 /* Helper routine in DRM core does all the work: */
953 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
958 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
961 u32 busy_up
, busy_down
, max_avg
, min_avg
;
964 spin_lock(&mchdev_lock
);
966 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
968 new_delay
= dev_priv
->ips
.cur_delay
;
970 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
971 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
972 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
973 max_avg
= I915_READ(RCBMAXAVG
);
974 min_avg
= I915_READ(RCBMINAVG
);
976 /* Handle RCS change request from hw */
977 if (busy_up
> max_avg
) {
978 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
979 new_delay
= dev_priv
->ips
.cur_delay
- 1;
980 if (new_delay
< dev_priv
->ips
.max_delay
)
981 new_delay
= dev_priv
->ips
.max_delay
;
982 } else if (busy_down
< min_avg
) {
983 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
984 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
985 if (new_delay
> dev_priv
->ips
.min_delay
)
986 new_delay
= dev_priv
->ips
.min_delay
;
989 if (ironlake_set_drps(dev
, new_delay
))
990 dev_priv
->ips
.cur_delay
= new_delay
;
992 spin_unlock(&mchdev_lock
);
997 static void notify_ring(struct intel_engine_cs
*engine
)
999 if (!intel_engine_initialized(engine
))
1002 trace_i915_gem_request_notify(engine
);
1004 wake_up_all(&engine
->irq_queue
);
1007 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1008 struct intel_rps_ei
*ei
)
1010 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1011 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1012 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1015 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
1016 const struct intel_rps_ei
*old
,
1017 const struct intel_rps_ei
*now
,
1021 unsigned int mul
= 100;
1023 if (old
->cz_clock
== 0)
1026 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1029 time
= now
->cz_clock
- old
->cz_clock
;
1030 time
*= threshold
* dev_priv
->czclk_freq
;
1032 /* Workload can be split between render + media, e.g. SwapBuffers
1033 * being blitted in X after being rendered in mesa. To account for
1034 * this we need to combine both engines into our activity counter.
1036 c0
= now
->render_c0
- old
->render_c0
;
1037 c0
+= now
->media_c0
- old
->media_c0
;
1038 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1043 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1045 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1046 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1049 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1051 struct intel_rps_ei now
;
1054 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1057 vlv_c0_read(dev_priv
, &now
);
1058 if (now
.cz_clock
== 0)
1061 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1062 if (!vlv_c0_above(dev_priv
,
1063 &dev_priv
->rps
.down_ei
, &now
,
1064 dev_priv
->rps
.down_threshold
))
1065 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1066 dev_priv
->rps
.down_ei
= now
;
1069 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1070 if (vlv_c0_above(dev_priv
,
1071 &dev_priv
->rps
.up_ei
, &now
,
1072 dev_priv
->rps
.up_threshold
))
1073 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1074 dev_priv
->rps
.up_ei
= now
;
1080 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1082 struct intel_engine_cs
*engine
;
1084 for_each_engine(engine
, dev_priv
)
1085 if (engine
->irq_refcount
)
1091 static void gen6_pm_rps_work(struct work_struct
*work
)
1093 struct drm_i915_private
*dev_priv
=
1094 container_of(work
, struct drm_i915_private
, rps
.work
);
1096 int new_delay
, adj
, min
, max
;
1099 spin_lock_irq(&dev_priv
->irq_lock
);
1100 /* Speed up work cancelation during disabling rps interrupts. */
1101 if (!dev_priv
->rps
.interrupts_enabled
) {
1102 spin_unlock_irq(&dev_priv
->irq_lock
);
1107 * The RPS work is synced during runtime suspend, we don't require a
1108 * wakeref. TODO: instead of disabling the asserts make sure that we
1109 * always hold an RPM reference while the work is running.
1111 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1113 pm_iir
= dev_priv
->rps
.pm_iir
;
1114 dev_priv
->rps
.pm_iir
= 0;
1115 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1116 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1117 client_boost
= dev_priv
->rps
.client_boost
;
1118 dev_priv
->rps
.client_boost
= false;
1119 spin_unlock_irq(&dev_priv
->irq_lock
);
1121 /* Make sure we didn't queue anything we're not going to process. */
1122 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1124 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1127 mutex_lock(&dev_priv
->rps
.hw_lock
);
1129 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1131 adj
= dev_priv
->rps
.last_adj
;
1132 new_delay
= dev_priv
->rps
.cur_freq
;
1133 min
= dev_priv
->rps
.min_freq_softlimit
;
1134 max
= dev_priv
->rps
.max_freq_softlimit
;
1137 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1139 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1142 else /* CHV needs even encode values */
1143 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1145 * For better performance, jump directly
1146 * to RPe if we're below it.
1148 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1149 new_delay
= dev_priv
->rps
.efficient_freq
;
1152 } else if (any_waiters(dev_priv
)) {
1154 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1155 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1156 new_delay
= dev_priv
->rps
.efficient_freq
;
1158 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1160 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1163 else /* CHV needs even encode values */
1164 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1165 } else { /* unknown event */
1169 dev_priv
->rps
.last_adj
= adj
;
1171 /* sysfs frequency interfaces may have snuck in while servicing the
1175 new_delay
= clamp_t(int, new_delay
, min
, max
);
1177 intel_set_rps(dev_priv
->dev
, new_delay
);
1179 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1181 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1186 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1188 * @work: workqueue struct
1190 * Doesn't actually do anything except notify userspace. As a consequence of
1191 * this event, userspace should try to remap the bad rows since statistically
1192 * it is likely the same row is more likely to go bad again.
1194 static void ivybridge_parity_work(struct work_struct
*work
)
1196 struct drm_i915_private
*dev_priv
=
1197 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1198 u32 error_status
, row
, bank
, subbank
;
1199 char *parity_event
[6];
1203 /* We must turn off DOP level clock gating to access the L3 registers.
1204 * In order to prevent a get/put style interface, acquire struct mutex
1205 * any time we access those registers.
1207 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1209 /* If we've screwed up tracking, just let the interrupt fire again */
1210 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1213 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1214 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1215 POSTING_READ(GEN7_MISCCPCTL
);
1217 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1221 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1224 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1226 reg
= GEN7_L3CDERRST1(slice
);
1228 error_status
= I915_READ(reg
);
1229 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1230 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1231 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1233 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1236 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1237 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1238 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1239 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1240 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1241 parity_event
[5] = NULL
;
1243 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1244 KOBJ_CHANGE
, parity_event
);
1246 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1247 slice
, row
, bank
, subbank
);
1249 kfree(parity_event
[4]);
1250 kfree(parity_event
[3]);
1251 kfree(parity_event
[2]);
1252 kfree(parity_event
[1]);
1255 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1258 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1259 spin_lock_irq(&dev_priv
->irq_lock
);
1260 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1261 spin_unlock_irq(&dev_priv
->irq_lock
);
1263 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1266 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 if (!HAS_L3_DPF(dev
))
1273 spin_lock(&dev_priv
->irq_lock
);
1274 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1275 spin_unlock(&dev_priv
->irq_lock
);
1277 iir
&= GT_PARITY_ERROR(dev
);
1278 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1279 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1281 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1282 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1284 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1287 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1288 struct drm_i915_private
*dev_priv
,
1292 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1293 notify_ring(&dev_priv
->engine
[RCS
]);
1294 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1295 notify_ring(&dev_priv
->engine
[VCS
]);
1298 static void snb_gt_irq_handler(struct drm_device
*dev
,
1299 struct drm_i915_private
*dev_priv
,
1304 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1305 notify_ring(&dev_priv
->engine
[RCS
]);
1306 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1307 notify_ring(&dev_priv
->engine
[VCS
]);
1308 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1309 notify_ring(&dev_priv
->engine
[BCS
]);
1311 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1312 GT_BSD_CS_ERROR_INTERRUPT
|
1313 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1314 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1316 if (gt_iir
& GT_PARITY_ERROR(dev
))
1317 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1320 static __always_inline
void
1321 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1323 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1324 notify_ring(engine
);
1325 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1326 tasklet_schedule(&engine
->irq_tasklet
);
1329 static irqreturn_t
gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1332 irqreturn_t ret
= IRQ_NONE
;
1334 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1335 u32 iir
= I915_READ_FW(GEN8_GT_IIR(0));
1337 I915_WRITE_FW(GEN8_GT_IIR(0), iir
);
1340 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1341 iir
, GEN8_RCS_IRQ_SHIFT
);
1343 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1344 iir
, GEN8_BCS_IRQ_SHIFT
);
1346 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1349 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1350 u32 iir
= I915_READ_FW(GEN8_GT_IIR(1));
1352 I915_WRITE_FW(GEN8_GT_IIR(1), iir
);
1355 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1356 iir
, GEN8_VCS1_IRQ_SHIFT
);
1358 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1359 iir
, GEN8_VCS2_IRQ_SHIFT
);
1361 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1364 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1365 u32 iir
= I915_READ_FW(GEN8_GT_IIR(3));
1367 I915_WRITE_FW(GEN8_GT_IIR(3), iir
);
1370 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1371 iir
, GEN8_VECS_IRQ_SHIFT
);
1373 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1376 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1377 u32 iir
= I915_READ_FW(GEN8_GT_IIR(2));
1378 if (iir
& dev_priv
->pm_rps_events
) {
1379 I915_WRITE_FW(GEN8_GT_IIR(2),
1380 iir
& dev_priv
->pm_rps_events
);
1382 gen6_rps_irq_handler(dev_priv
, iir
);
1384 DRM_ERROR("The master control interrupt lied (PM)!\n");
1390 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1394 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1396 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1398 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1404 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1408 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1414 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1418 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1420 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1422 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1424 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1430 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1434 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1440 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1444 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1446 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1448 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1454 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1458 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1460 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1462 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1469 * Get a bit mask of pins that have triggered, and which ones may be long.
1470 * This can be called multiple times with the same masks to accumulate
1471 * hotplug detection results from several registers.
1473 * Note that the caller is expected to zero out the masks initially.
1475 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1476 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1477 const u32 hpd
[HPD_NUM_PINS
],
1478 bool long_pulse_detect(enum port port
, u32 val
))
1483 for_each_hpd_pin(i
) {
1484 if ((hpd
[i
] & hotplug_trigger
) == 0)
1487 *pin_mask
|= BIT(i
);
1489 if (!intel_hpd_pin_to_port(i
, &port
))
1492 if (long_pulse_detect(port
, dig_hotplug_reg
))
1493 *long_mask
|= BIT(i
);
1496 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1497 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1501 static void gmbus_irq_handler(struct drm_device
*dev
)
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1505 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1508 static void dp_aux_irq_handler(struct drm_device
*dev
)
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1515 #if defined(CONFIG_DEBUG_FS)
1516 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1517 uint32_t crc0
, uint32_t crc1
,
1518 uint32_t crc2
, uint32_t crc3
,
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1523 struct intel_pipe_crc_entry
*entry
;
1526 spin_lock(&pipe_crc
->lock
);
1528 if (!pipe_crc
->entries
) {
1529 spin_unlock(&pipe_crc
->lock
);
1530 DRM_DEBUG_KMS("spurious interrupt\n");
1534 head
= pipe_crc
->head
;
1535 tail
= pipe_crc
->tail
;
1537 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1538 spin_unlock(&pipe_crc
->lock
);
1539 DRM_ERROR("CRC buffer overflowing\n");
1543 entry
= &pipe_crc
->entries
[head
];
1545 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1546 entry
->crc
[0] = crc0
;
1547 entry
->crc
[1] = crc1
;
1548 entry
->crc
[2] = crc2
;
1549 entry
->crc
[3] = crc3
;
1550 entry
->crc
[4] = crc4
;
1552 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1553 pipe_crc
->head
= head
;
1555 spin_unlock(&pipe_crc
->lock
);
1557 wake_up_interruptible(&pipe_crc
->wq
);
1561 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1562 uint32_t crc0
, uint32_t crc1
,
1563 uint32_t crc2
, uint32_t crc3
,
1568 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1572 display_pipe_crc_irq_handler(dev
, pipe
,
1573 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1577 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 display_pipe_crc_irq_handler(dev
, pipe
,
1582 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1583 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1584 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1585 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1586 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1589 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1592 uint32_t res1
, res2
;
1594 if (INTEL_INFO(dev
)->gen
>= 3)
1595 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1599 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1600 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1604 display_pipe_crc_irq_handler(dev
, pipe
,
1605 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1606 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1607 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1611 /* The RPS events need forcewake, so we add them to a work queue and mask their
1612 * IMR bits until the work is done. Other interrupts can be processed without
1613 * the work queue. */
1614 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1616 if (pm_iir
& dev_priv
->pm_rps_events
) {
1617 spin_lock(&dev_priv
->irq_lock
);
1618 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1619 if (dev_priv
->rps
.interrupts_enabled
) {
1620 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1621 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1623 spin_unlock(&dev_priv
->irq_lock
);
1626 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1629 if (HAS_VEBOX(dev_priv
->dev
)) {
1630 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1631 notify_ring(&dev_priv
->engine
[VECS
]);
1633 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1634 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1638 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1640 if (!drm_handle_vblank(dev
, pipe
))
1646 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1649 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1652 spin_lock(&dev_priv
->irq_lock
);
1654 if (!dev_priv
->display_irqs_enabled
) {
1655 spin_unlock(&dev_priv
->irq_lock
);
1659 for_each_pipe(dev_priv
, pipe
) {
1661 u32 mask
, iir_bit
= 0;
1664 * PIPESTAT bits get signalled even when the interrupt is
1665 * disabled with the mask bits, and some of the status bits do
1666 * not generate interrupts at all (like the underrun bit). Hence
1667 * we need to be careful that we only handle what we want to
1671 /* fifo underruns are filterered in the underrun handler. */
1672 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1676 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1679 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1682 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1686 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1691 reg
= PIPESTAT(pipe
);
1692 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1693 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1696 * Clear the PIPE*STAT regs before the IIR
1698 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1699 PIPESTAT_INT_STATUS_MASK
))
1700 I915_WRITE(reg
, pipe_stats
[pipe
]);
1702 spin_unlock(&dev_priv
->irq_lock
);
1704 for_each_pipe(dev_priv
, pipe
) {
1705 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1706 intel_pipe_handle_vblank(dev
, pipe
))
1707 intel_check_page_flip(dev
, pipe
);
1709 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1710 intel_prepare_page_flip(dev
, pipe
);
1711 intel_finish_page_flip(dev
, pipe
);
1714 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1715 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1717 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1718 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1721 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1722 gmbus_irq_handler(dev
);
1725 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1728 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1729 u32 pin_mask
= 0, long_mask
= 0;
1731 if (!hotplug_status
)
1734 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1736 * Make sure hotplug status is cleared before we clear IIR, or else we
1737 * may miss hotplug events.
1739 POSTING_READ(PORT_HOTPLUG_STAT
);
1741 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1742 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1744 if (hotplug_trigger
) {
1745 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1746 hotplug_trigger
, hpd_status_g4x
,
1747 i9xx_port_hotplug_long_detect
);
1749 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1752 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1753 dp_aux_irq_handler(dev
);
1755 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1757 if (hotplug_trigger
) {
1758 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1759 hotplug_trigger
, hpd_status_i915
,
1760 i9xx_port_hotplug_long_detect
);
1761 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1766 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1768 struct drm_device
*dev
= arg
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 u32 iir
, gt_iir
, pm_iir
;
1771 irqreturn_t ret
= IRQ_NONE
;
1773 if (!intel_irqs_enabled(dev_priv
))
1776 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1777 disable_rpm_wakeref_asserts(dev_priv
);
1780 /* Find, clear, then process each source of interrupt */
1782 gt_iir
= I915_READ(GTIIR
);
1784 I915_WRITE(GTIIR
, gt_iir
);
1786 pm_iir
= I915_READ(GEN6_PMIIR
);
1788 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1790 iir
= I915_READ(VLV_IIR
);
1792 /* Consume port before clearing IIR or we'll miss events */
1793 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1794 i9xx_hpd_irq_handler(dev
);
1795 I915_WRITE(VLV_IIR
, iir
);
1798 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1804 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1806 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1807 /* Call regardless, as some status bits might not be
1808 * signalled in iir */
1809 valleyview_pipestat_irq_handler(dev
, iir
);
1813 enable_rpm_wakeref_asserts(dev_priv
);
1818 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1820 struct drm_device
*dev
= arg
;
1821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1822 u32 master_ctl
, iir
;
1823 irqreturn_t ret
= IRQ_NONE
;
1825 if (!intel_irqs_enabled(dev_priv
))
1828 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1829 disable_rpm_wakeref_asserts(dev_priv
);
1832 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1833 iir
= I915_READ(VLV_IIR
);
1835 if (master_ctl
== 0 && iir
== 0)
1840 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1842 /* Find, clear, then process each source of interrupt */
1845 /* Consume port before clearing IIR or we'll miss events */
1846 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1847 i9xx_hpd_irq_handler(dev
);
1848 I915_WRITE(VLV_IIR
, iir
);
1851 gen8_gt_irq_handler(dev_priv
, master_ctl
);
1853 /* Call regardless, as some status bits might not be
1854 * signalled in iir */
1855 valleyview_pipestat_irq_handler(dev
, iir
);
1857 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1858 POSTING_READ(GEN8_MASTER_IRQ
);
1861 enable_rpm_wakeref_asserts(dev_priv
);
1866 static void ibx_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
1867 const u32 hpd
[HPD_NUM_PINS
])
1869 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1870 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1873 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1874 * unless we touch the hotplug register, even if hotplug_trigger is
1875 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1878 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1879 if (!hotplug_trigger
) {
1880 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1881 PORTD_HOTPLUG_STATUS_MASK
|
1882 PORTC_HOTPLUG_STATUS_MASK
|
1883 PORTB_HOTPLUG_STATUS_MASK
;
1884 dig_hotplug_reg
&= ~mask
;
1887 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1888 if (!hotplug_trigger
)
1891 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1892 dig_hotplug_reg
, hpd
,
1893 pch_port_hotplug_long_detect
);
1895 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1898 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1902 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1904 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1906 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1907 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1908 SDE_AUDIO_POWER_SHIFT
);
1909 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1913 if (pch_iir
& SDE_AUX_MASK
)
1914 dp_aux_irq_handler(dev
);
1916 if (pch_iir
& SDE_GMBUS
)
1917 gmbus_irq_handler(dev
);
1919 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1920 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1922 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1923 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1925 if (pch_iir
& SDE_POISON
)
1926 DRM_ERROR("PCH poison interrupt\n");
1928 if (pch_iir
& SDE_FDI_MASK
)
1929 for_each_pipe(dev_priv
, pipe
)
1930 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1932 I915_READ(FDI_RX_IIR(pipe
)));
1934 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1935 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1937 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1938 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1940 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1941 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1943 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1944 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1947 static void ivb_err_int_handler(struct drm_device
*dev
)
1949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1950 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1953 if (err_int
& ERR_INT_POISON
)
1954 DRM_ERROR("Poison interrupt\n");
1956 for_each_pipe(dev_priv
, pipe
) {
1957 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1958 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1960 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1961 if (IS_IVYBRIDGE(dev
))
1962 ivb_pipe_crc_irq_handler(dev
, pipe
);
1964 hsw_pipe_crc_irq_handler(dev
, pipe
);
1968 I915_WRITE(GEN7_ERR_INT
, err_int
);
1971 static void cpt_serr_int_handler(struct drm_device
*dev
)
1973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1974 u32 serr_int
= I915_READ(SERR_INT
);
1976 if (serr_int
& SERR_INT_POISON
)
1977 DRM_ERROR("PCH poison interrupt\n");
1979 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1980 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1982 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1983 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1985 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1986 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
1988 I915_WRITE(SERR_INT
, serr_int
);
1991 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1997 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1999 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2000 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2001 SDE_AUDIO_POWER_SHIFT_CPT
);
2002 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2006 if (pch_iir
& SDE_AUX_MASK_CPT
)
2007 dp_aux_irq_handler(dev
);
2009 if (pch_iir
& SDE_GMBUS_CPT
)
2010 gmbus_irq_handler(dev
);
2012 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2013 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2015 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2016 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2018 if (pch_iir
& SDE_FDI_MASK_CPT
)
2019 for_each_pipe(dev_priv
, pipe
)
2020 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2022 I915_READ(FDI_RX_IIR(pipe
)));
2024 if (pch_iir
& SDE_ERROR_CPT
)
2025 cpt_serr_int_handler(dev
);
2028 static void spt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2031 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2032 ~SDE_PORTE_HOTPLUG_SPT
;
2033 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2034 u32 pin_mask
= 0, long_mask
= 0;
2036 if (hotplug_trigger
) {
2037 u32 dig_hotplug_reg
;
2039 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2040 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2042 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2043 dig_hotplug_reg
, hpd_spt
,
2044 spt_port_hotplug_long_detect
);
2047 if (hotplug2_trigger
) {
2048 u32 dig_hotplug_reg
;
2050 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2051 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2053 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2054 dig_hotplug_reg
, hpd_spt
,
2055 spt_port_hotplug2_long_detect
);
2059 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2061 if (pch_iir
& SDE_GMBUS_CPT
)
2062 gmbus_irq_handler(dev
);
2065 static void ilk_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
2066 const u32 hpd
[HPD_NUM_PINS
])
2068 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2069 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2071 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2072 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2074 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2075 dig_hotplug_reg
, hpd
,
2076 ilk_port_hotplug_long_detect
);
2078 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2081 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2085 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2087 if (hotplug_trigger
)
2088 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ilk
);
2090 if (de_iir
& DE_AUX_CHANNEL_A
)
2091 dp_aux_irq_handler(dev
);
2093 if (de_iir
& DE_GSE
)
2094 intel_opregion_asle_intr(dev
);
2096 if (de_iir
& DE_POISON
)
2097 DRM_ERROR("Poison interrupt\n");
2099 for_each_pipe(dev_priv
, pipe
) {
2100 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2101 intel_pipe_handle_vblank(dev
, pipe
))
2102 intel_check_page_flip(dev
, pipe
);
2104 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2105 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2107 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2108 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2110 /* plane/pipes map 1:1 on ilk+ */
2111 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2112 intel_prepare_page_flip(dev
, pipe
);
2113 intel_finish_page_flip_plane(dev
, pipe
);
2117 /* check event from PCH */
2118 if (de_iir
& DE_PCH_EVENT
) {
2119 u32 pch_iir
= I915_READ(SDEIIR
);
2121 if (HAS_PCH_CPT(dev
))
2122 cpt_irq_handler(dev
, pch_iir
);
2124 ibx_irq_handler(dev
, pch_iir
);
2126 /* should clear PCH hotplug event before clear CPU irq */
2127 I915_WRITE(SDEIIR
, pch_iir
);
2130 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2131 ironlake_rps_change_irq_handler(dev
);
2134 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2138 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2140 if (hotplug_trigger
)
2141 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ivb
);
2143 if (de_iir
& DE_ERR_INT_IVB
)
2144 ivb_err_int_handler(dev
);
2146 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2147 dp_aux_irq_handler(dev
);
2149 if (de_iir
& DE_GSE_IVB
)
2150 intel_opregion_asle_intr(dev
);
2152 for_each_pipe(dev_priv
, pipe
) {
2153 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2154 intel_pipe_handle_vblank(dev
, pipe
))
2155 intel_check_page_flip(dev
, pipe
);
2157 /* plane/pipes map 1:1 on ilk+ */
2158 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2159 intel_prepare_page_flip(dev
, pipe
);
2160 intel_finish_page_flip_plane(dev
, pipe
);
2164 /* check event from PCH */
2165 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2166 u32 pch_iir
= I915_READ(SDEIIR
);
2168 cpt_irq_handler(dev
, pch_iir
);
2170 /* clear PCH hotplug event before clear CPU irq */
2171 I915_WRITE(SDEIIR
, pch_iir
);
2176 * To handle irqs with the minimum potential races with fresh interrupts, we:
2177 * 1 - Disable Master Interrupt Control.
2178 * 2 - Find the source(s) of the interrupt.
2179 * 3 - Clear the Interrupt Identity bits (IIR).
2180 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2181 * 5 - Re-enable Master Interrupt Control.
2183 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2185 struct drm_device
*dev
= arg
;
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2187 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2188 irqreturn_t ret
= IRQ_NONE
;
2190 if (!intel_irqs_enabled(dev_priv
))
2193 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2194 disable_rpm_wakeref_asserts(dev_priv
);
2196 /* disable master interrupt before clearing iir */
2197 de_ier
= I915_READ(DEIER
);
2198 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2199 POSTING_READ(DEIER
);
2201 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2202 * interrupts will will be stored on its back queue, and then we'll be
2203 * able to process them after we restore SDEIER (as soon as we restore
2204 * it, we'll get an interrupt if SDEIIR still has something to process
2205 * due to its back queue). */
2206 if (!HAS_PCH_NOP(dev
)) {
2207 sde_ier
= I915_READ(SDEIER
);
2208 I915_WRITE(SDEIER
, 0);
2209 POSTING_READ(SDEIER
);
2212 /* Find, clear, then process each source of interrupt */
2214 gt_iir
= I915_READ(GTIIR
);
2216 I915_WRITE(GTIIR
, gt_iir
);
2218 if (INTEL_INFO(dev
)->gen
>= 6)
2219 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2221 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2224 de_iir
= I915_READ(DEIIR
);
2226 I915_WRITE(DEIIR
, de_iir
);
2228 if (INTEL_INFO(dev
)->gen
>= 7)
2229 ivb_display_irq_handler(dev
, de_iir
);
2231 ilk_display_irq_handler(dev
, de_iir
);
2234 if (INTEL_INFO(dev
)->gen
>= 6) {
2235 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2237 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2239 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2243 I915_WRITE(DEIER
, de_ier
);
2244 POSTING_READ(DEIER
);
2245 if (!HAS_PCH_NOP(dev
)) {
2246 I915_WRITE(SDEIER
, sde_ier
);
2247 POSTING_READ(SDEIER
);
2250 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2251 enable_rpm_wakeref_asserts(dev_priv
);
2256 static void bxt_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
2257 const u32 hpd
[HPD_NUM_PINS
])
2259 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2260 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2262 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2263 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2265 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2266 dig_hotplug_reg
, hpd
,
2267 bxt_port_hotplug_long_detect
);
2269 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2273 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2275 struct drm_device
*dev
= dev_priv
->dev
;
2276 irqreturn_t ret
= IRQ_NONE
;
2280 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2281 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2283 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2285 if (iir
& GEN8_DE_MISC_GSE
)
2286 intel_opregion_asle_intr(dev
);
2288 DRM_ERROR("Unexpected DE Misc interrupt\n");
2291 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2294 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2295 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2300 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2303 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2304 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2305 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2306 GEN9_AUX_CHANNEL_C
|
2309 if (iir
& tmp_mask
) {
2310 dp_aux_irq_handler(dev
);
2314 if (IS_BROXTON(dev_priv
)) {
2315 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2317 bxt_hpd_irq_handler(dev
, tmp_mask
, hpd_bxt
);
2320 } else if (IS_BROADWELL(dev_priv
)) {
2321 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2323 ilk_hpd_irq_handler(dev
, tmp_mask
, hpd_bdw
);
2328 if (IS_BROXTON(dev
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2329 gmbus_irq_handler(dev
);
2334 DRM_ERROR("Unexpected DE Port interrupt\n");
2337 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2340 for_each_pipe(dev_priv
, pipe
) {
2341 u32 flip_done
, fault_errors
;
2343 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2346 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2348 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2353 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2355 if (iir
& GEN8_PIPE_VBLANK
&&
2356 intel_pipe_handle_vblank(dev
, pipe
))
2357 intel_check_page_flip(dev
, pipe
);
2360 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2361 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2363 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2366 intel_prepare_page_flip(dev
, pipe
);
2367 intel_finish_page_flip_plane(dev
, pipe
);
2370 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2371 hsw_pipe_crc_irq_handler(dev
, pipe
);
2373 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2374 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2377 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2378 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2380 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2383 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2388 if (HAS_PCH_SPLIT(dev
) && !HAS_PCH_NOP(dev
) &&
2389 master_ctl
& GEN8_DE_PCH_IRQ
) {
2391 * FIXME(BDW): Assume for now that the new interrupt handling
2392 * scheme also closed the SDE interrupt handling race we've seen
2393 * on older pch-split platforms. But this needs testing.
2395 iir
= I915_READ(SDEIIR
);
2397 I915_WRITE(SDEIIR
, iir
);
2400 if (HAS_PCH_SPT(dev_priv
))
2401 spt_irq_handler(dev
, iir
);
2403 cpt_irq_handler(dev
, iir
);
2406 * Like on previous PCH there seems to be something
2407 * fishy going on with forwarding PCH interrupts.
2409 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2416 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2418 struct drm_device
*dev
= arg
;
2419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2423 if (!intel_irqs_enabled(dev_priv
))
2426 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2427 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2431 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2433 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2434 disable_rpm_wakeref_asserts(dev_priv
);
2436 /* Find, clear, then process each source of interrupt */
2437 ret
= gen8_gt_irq_handler(dev_priv
, master_ctl
);
2438 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2440 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2441 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2443 enable_rpm_wakeref_asserts(dev_priv
);
2448 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2449 bool reset_completed
)
2451 struct intel_engine_cs
*engine
;
2454 * Notify all waiters for GPU completion events that reset state has
2455 * been changed, and that they need to restart their wait after
2456 * checking for potential errors (and bail out to drop locks if there is
2457 * a gpu reset pending so that i915_error_work_func can acquire them).
2460 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2461 for_each_engine(engine
, dev_priv
)
2462 wake_up_all(&engine
->irq_queue
);
2464 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2465 wake_up_all(&dev_priv
->pending_flip_queue
);
2468 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2469 * reset state is cleared.
2471 if (reset_completed
)
2472 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2476 * i915_reset_and_wakeup - do process context error handling work
2479 * Fire an error uevent so userspace can see that a hang or error
2482 static void i915_reset_and_wakeup(struct drm_device
*dev
)
2484 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2485 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
2486 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2487 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2488 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2491 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2494 * Note that there's only one work item which does gpu resets, so we
2495 * need not worry about concurrent gpu resets potentially incrementing
2496 * error->reset_counter twice. We only need to take care of another
2497 * racing irq/hangcheck declaring the gpu dead for a second time. A
2498 * quick check for that is good enough: schedule_work ensures the
2499 * correct ordering between hang detection and this work item, and since
2500 * the reset in-progress bit is only ever set by code outside of this
2501 * work we don't need to worry about any other races.
2503 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2504 DRM_DEBUG_DRIVER("resetting chip\n");
2505 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2509 * In most cases it's guaranteed that we get here with an RPM
2510 * reference held, for example because there is a pending GPU
2511 * request that won't finish until the reset is done. This
2512 * isn't the case at least when we get here by doing a
2513 * simulated reset via debugs, so get an RPM reference.
2515 intel_runtime_pm_get(dev_priv
);
2517 intel_prepare_reset(dev
);
2520 * All state reset _must_ be completed before we update the
2521 * reset counter, for otherwise waiters might miss the reset
2522 * pending state and not properly drop locks, resulting in
2523 * deadlocks with the reset work.
2525 ret
= i915_reset(dev
);
2527 intel_finish_reset(dev
);
2529 intel_runtime_pm_put(dev_priv
);
2533 * After all the gem state is reset, increment the reset
2534 * counter and wake up everyone waiting for the reset to
2537 * Since unlock operations are a one-sided barrier only,
2538 * we need to insert a barrier here to order any seqno
2540 * the counter increment.
2542 smp_mb__before_atomic();
2543 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2545 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2546 KOBJ_CHANGE
, reset_done_event
);
2548 atomic_or(I915_WEDGED
, &error
->reset_counter
);
2552 * Note: The wake_up also serves as a memory barrier so that
2553 * waiters see the update value of the reset counter atomic_t.
2555 i915_error_wake_up(dev_priv
, true);
2559 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2563 u32 eir
= I915_READ(EIR
);
2569 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2571 i915_get_extra_instdone(dev
, instdone
);
2574 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2575 u32 ipeir
= I915_READ(IPEIR_I965
);
2577 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2578 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2579 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2580 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2581 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2582 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2583 I915_WRITE(IPEIR_I965
, ipeir
);
2584 POSTING_READ(IPEIR_I965
);
2586 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2587 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2588 pr_err("page table error\n");
2589 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2590 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2591 POSTING_READ(PGTBL_ER
);
2595 if (!IS_GEN2(dev
)) {
2596 if (eir
& I915_ERROR_PAGE_TABLE
) {
2597 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2598 pr_err("page table error\n");
2599 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2600 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2601 POSTING_READ(PGTBL_ER
);
2605 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2606 pr_err("memory refresh error:\n");
2607 for_each_pipe(dev_priv
, pipe
)
2608 pr_err("pipe %c stat: 0x%08x\n",
2609 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2610 /* pipestat has already been acked */
2612 if (eir
& I915_ERROR_INSTRUCTION
) {
2613 pr_err("instruction error\n");
2614 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2615 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2616 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2617 if (INTEL_INFO(dev
)->gen
< 4) {
2618 u32 ipeir
= I915_READ(IPEIR
);
2620 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2621 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2622 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2623 I915_WRITE(IPEIR
, ipeir
);
2624 POSTING_READ(IPEIR
);
2626 u32 ipeir
= I915_READ(IPEIR_I965
);
2628 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2629 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2630 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2631 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2632 I915_WRITE(IPEIR_I965
, ipeir
);
2633 POSTING_READ(IPEIR_I965
);
2637 I915_WRITE(EIR
, eir
);
2639 eir
= I915_READ(EIR
);
2642 * some errors might have become stuck,
2645 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2646 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2647 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2652 * i915_handle_error - handle a gpu error
2654 * @engine_mask: mask representing engines that are hung
2655 * Do some basic checking of register state at error time and
2656 * dump it to the syslog. Also call i915_capture_error_state() to make
2657 * sure we get a record and make it available in debugfs. Fire a uevent
2658 * so userspace knows something bad happened (should trigger collection
2659 * of a ring dump etc.).
2661 void i915_handle_error(struct drm_device
*dev
, u32 engine_mask
,
2662 const char *fmt
, ...)
2664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2668 va_start(args
, fmt
);
2669 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2672 i915_capture_error_state(dev
, engine_mask
, error_msg
);
2673 i915_report_and_clear_eir(dev
);
2676 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2677 &dev_priv
->gpu_error
.reset_counter
);
2680 * Wakeup waiting processes so that the reset function
2681 * i915_reset_and_wakeup doesn't deadlock trying to grab
2682 * various locks. By bumping the reset counter first, the woken
2683 * processes will see a reset in progress and back off,
2684 * releasing their locks and then wait for the reset completion.
2685 * We must do this for _all_ gpu waiters that might hold locks
2686 * that the reset work needs to acquire.
2688 * Note: The wake_up serves as the required memory barrier to
2689 * ensure that the waiters see the updated value of the reset
2692 i915_error_wake_up(dev_priv
, false);
2695 i915_reset_and_wakeup(dev
);
2698 /* Called from drm generic code, passed 'crtc' which
2699 * we use as a pipe index
2701 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2704 unsigned long irqflags
;
2706 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2707 if (INTEL_INFO(dev
)->gen
>= 4)
2708 i915_enable_pipestat(dev_priv
, pipe
,
2709 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2711 i915_enable_pipestat(dev_priv
, pipe
,
2712 PIPE_VBLANK_INTERRUPT_STATUS
);
2713 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2718 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2721 unsigned long irqflags
;
2722 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2723 DE_PIPE_VBLANK(pipe
);
2725 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2726 ilk_enable_display_irq(dev_priv
, bit
);
2727 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2732 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2735 unsigned long irqflags
;
2737 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2738 i915_enable_pipestat(dev_priv
, pipe
,
2739 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2740 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2745 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 unsigned long irqflags
;
2750 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2751 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2752 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2757 /* Called from drm generic code, passed 'crtc' which
2758 * we use as a pipe index
2760 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2763 unsigned long irqflags
;
2765 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2766 i915_disable_pipestat(dev_priv
, pipe
,
2767 PIPE_VBLANK_INTERRUPT_STATUS
|
2768 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2769 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2772 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2775 unsigned long irqflags
;
2776 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2777 DE_PIPE_VBLANK(pipe
);
2779 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2780 ilk_disable_display_irq(dev_priv
, bit
);
2781 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2784 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 unsigned long irqflags
;
2789 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2790 i915_disable_pipestat(dev_priv
, pipe
,
2791 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2792 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2795 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 unsigned long irqflags
;
2800 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2801 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2802 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2806 ring_idle(struct intel_engine_cs
*engine
, u32 seqno
)
2808 return (list_empty(&engine
->request_list
) ||
2809 i915_seqno_passed(seqno
, engine
->last_submitted_seqno
));
2813 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2815 if (INTEL_INFO(dev
)->gen
>= 8) {
2816 return (ipehr
>> 23) == 0x1c;
2818 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2819 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2820 MI_SEMAPHORE_REGISTER
);
2824 static struct intel_engine_cs
*
2825 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2828 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2829 struct intel_engine_cs
*signaller
;
2831 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2832 for_each_engine(signaller
, dev_priv
) {
2833 if (engine
== signaller
)
2836 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2840 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2842 for_each_engine(signaller
, dev_priv
) {
2843 if(engine
== signaller
)
2846 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2851 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2852 engine
->id
, ipehr
, offset
);
2857 static struct intel_engine_cs
*
2858 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2860 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2861 u32 cmd
, ipehr
, head
;
2866 * This function does not support execlist mode - any attempt to
2867 * proceed further into this function will result in a kernel panic
2868 * when dereferencing ring->buffer, which is not set up in execlist
2871 * The correct way of doing it would be to derive the currently
2872 * executing ring buffer from the current context, which is derived
2873 * from the currently running request. Unfortunately, to get the
2874 * current request we would have to grab the struct_mutex before doing
2875 * anything else, which would be ill-advised since some other thread
2876 * might have grabbed it already and managed to hang itself, causing
2877 * the hang checker to deadlock.
2879 * Therefore, this function does not support execlist mode in its
2880 * current form. Just return NULL and move on.
2882 if (engine
->buffer
== NULL
)
2885 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2886 if (!ipehr_is_semaphore_wait(engine
->dev
, ipehr
))
2890 * HEAD is likely pointing to the dword after the actual command,
2891 * so scan backwards until we find the MBOX. But limit it to just 3
2892 * or 4 dwords depending on the semaphore wait command size.
2893 * Note that we don't care about ACTHD here since that might
2894 * point at at batch, and semaphores are always emitted into the
2895 * ringbuffer itself.
2897 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2898 backwards
= (INTEL_INFO(engine
->dev
)->gen
>= 8) ? 5 : 4;
2900 for (i
= backwards
; i
; --i
) {
2902 * Be paranoid and presume the hw has gone off into the wild -
2903 * our ring is smaller than what the hardware (and hence
2904 * HEAD_ADDR) allows. Also handles wrap-around.
2906 head
&= engine
->buffer
->size
- 1;
2908 /* This here seems to blow up */
2909 cmd
= ioread32(engine
->buffer
->virtual_start
+ head
);
2919 *seqno
= ioread32(engine
->buffer
->virtual_start
+ head
+ 4) + 1;
2920 if (INTEL_INFO(engine
->dev
)->gen
>= 8) {
2921 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 12);
2923 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 8);
2925 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2928 static int semaphore_passed(struct intel_engine_cs
*engine
)
2930 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2931 struct intel_engine_cs
*signaller
;
2934 engine
->hangcheck
.deadlock
++;
2936 signaller
= semaphore_waits_for(engine
, &seqno
);
2937 if (signaller
== NULL
)
2940 /* Prevent pathological recursion due to driver bugs */
2941 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2944 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2947 /* cursory check for an unkickable deadlock */
2948 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2949 semaphore_passed(signaller
) < 0)
2955 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2957 struct intel_engine_cs
*engine
;
2959 for_each_engine(engine
, dev_priv
)
2960 engine
->hangcheck
.deadlock
= 0;
2963 static bool subunits_stuck(struct intel_engine_cs
*engine
)
2965 u32 instdone
[I915_NUM_INSTDONE_REG
];
2969 if (engine
->id
!= RCS
)
2972 i915_get_extra_instdone(engine
->dev
, instdone
);
2974 /* There might be unstable subunit states even when
2975 * actual head is not moving. Filter out the unstable ones by
2976 * accumulating the undone -> done transitions and only
2977 * consider those as progress.
2980 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
2981 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
2983 if (tmp
!= engine
->hangcheck
.instdone
[i
])
2986 engine
->hangcheck
.instdone
[i
] |= tmp
;
2992 static enum intel_ring_hangcheck_action
2993 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
2995 if (acthd
!= engine
->hangcheck
.acthd
) {
2997 /* Clear subunit states on head movement */
2998 memset(engine
->hangcheck
.instdone
, 0,
2999 sizeof(engine
->hangcheck
.instdone
));
3001 return HANGCHECK_ACTIVE
;
3004 if (!subunits_stuck(engine
))
3005 return HANGCHECK_ACTIVE
;
3007 return HANGCHECK_HUNG
;
3010 static enum intel_ring_hangcheck_action
3011 ring_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3013 struct drm_device
*dev
= engine
->dev
;
3014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3015 enum intel_ring_hangcheck_action ha
;
3018 ha
= head_stuck(engine
, acthd
);
3019 if (ha
!= HANGCHECK_HUNG
)
3023 return HANGCHECK_HUNG
;
3025 /* Is the chip hanging on a WAIT_FOR_EVENT?
3026 * If so we can simply poke the RB_WAIT bit
3027 * and break the hang. This should work on
3028 * all but the second generation chipsets.
3030 tmp
= I915_READ_CTL(engine
);
3031 if (tmp
& RING_WAIT
) {
3032 i915_handle_error(dev
, 0,
3033 "Kicking stuck wait on %s",
3035 I915_WRITE_CTL(engine
, tmp
);
3036 return HANGCHECK_KICK
;
3039 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3040 switch (semaphore_passed(engine
)) {
3042 return HANGCHECK_HUNG
;
3044 i915_handle_error(dev
, 0,
3045 "Kicking stuck semaphore on %s",
3047 I915_WRITE_CTL(engine
, tmp
);
3048 return HANGCHECK_KICK
;
3050 return HANGCHECK_WAIT
;
3054 return HANGCHECK_HUNG
;
3058 * This is called when the chip hasn't reported back with completed
3059 * batchbuffers in a long time. We keep track per ring seqno progress and
3060 * if there are no progress, hangcheck score for that ring is increased.
3061 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3062 * we kick the ring. If we see no progress on three subsequent calls
3063 * we assume chip is wedged and try to fix it by resetting the chip.
3065 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3067 struct drm_i915_private
*dev_priv
=
3068 container_of(work
, typeof(*dev_priv
),
3069 gpu_error
.hangcheck_work
.work
);
3070 struct drm_device
*dev
= dev_priv
->dev
;
3071 struct intel_engine_cs
*engine
;
3072 enum intel_engine_id id
;
3073 int busy_count
= 0, rings_hung
= 0;
3074 bool stuck
[I915_NUM_ENGINES
] = { 0 };
3078 #define ACTIVE_DECAY 15
3080 if (!i915
.enable_hangcheck
)
3084 * The hangcheck work is synced during runtime suspend, we don't
3085 * require a wakeref. TODO: instead of disabling the asserts make
3086 * sure that we hold a reference when this work is running.
3088 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3090 /* As enabling the GPU requires fairly extensive mmio access,
3091 * periodically arm the mmio checker to see if we are triggering
3092 * any invalid access.
3094 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3096 for_each_engine_id(engine
, dev_priv
, id
) {
3101 semaphore_clear_deadlocks(dev_priv
);
3103 seqno
= engine
->get_seqno(engine
, false);
3104 acthd
= intel_ring_get_active_head(engine
);
3106 if (engine
->hangcheck
.seqno
== seqno
) {
3107 if (ring_idle(engine
, seqno
)) {
3108 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3110 if (waitqueue_active(&engine
->irq_queue
)) {
3111 /* Issue a wake-up to catch stuck h/w. */
3112 if (!test_and_set_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
3113 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_engine_flag(engine
)))
3114 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3117 DRM_INFO("Fake missed irq on %s\n",
3119 wake_up_all(&engine
->irq_queue
);
3121 /* Safeguard against driver failure */
3122 engine
->hangcheck
.score
+= BUSY
;
3126 /* We always increment the hangcheck score
3127 * if the ring is busy and still processing
3128 * the same request, so that no single request
3129 * can run indefinitely (such as a chain of
3130 * batches). The only time we do not increment
3131 * the hangcheck score on this ring, if this
3132 * ring is in a legitimate wait for another
3133 * ring. In that case the waiting ring is a
3134 * victim and we want to be sure we catch the
3135 * right culprit. Then every time we do kick
3136 * the ring, add a small increment to the
3137 * score so that we can catch a batch that is
3138 * being repeatedly kicked and so responsible
3139 * for stalling the machine.
3141 engine
->hangcheck
.action
= ring_stuck(engine
,
3144 switch (engine
->hangcheck
.action
) {
3145 case HANGCHECK_IDLE
:
3146 case HANGCHECK_WAIT
:
3148 case HANGCHECK_ACTIVE
:
3149 engine
->hangcheck
.score
+= BUSY
;
3151 case HANGCHECK_KICK
:
3152 engine
->hangcheck
.score
+= KICK
;
3154 case HANGCHECK_HUNG
:
3155 engine
->hangcheck
.score
+= HUNG
;
3161 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3163 /* Gradually reduce the count so that we catch DoS
3164 * attempts across multiple batches.
3166 if (engine
->hangcheck
.score
> 0)
3167 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3168 if (engine
->hangcheck
.score
< 0)
3169 engine
->hangcheck
.score
= 0;
3171 /* Clear head and subunit states on seqno movement */
3172 engine
->hangcheck
.acthd
= 0;
3174 memset(engine
->hangcheck
.instdone
, 0,
3175 sizeof(engine
->hangcheck
.instdone
));
3178 engine
->hangcheck
.seqno
= seqno
;
3179 engine
->hangcheck
.acthd
= acthd
;
3183 for_each_engine_id(engine
, dev_priv
, id
) {
3184 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3185 DRM_INFO("%s on %s\n",
3186 stuck
[id
] ? "stuck" : "no progress",
3188 rings_hung
|= intel_engine_flag(engine
);
3193 i915_handle_error(dev
, rings_hung
, "Engine(s) hung");
3198 /* Reset timer case chip hangs without another request
3200 i915_queue_hangcheck(dev
);
3203 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3206 void i915_queue_hangcheck(struct drm_device
*dev
)
3208 struct i915_gpu_error
*e
= &to_i915(dev
)->gpu_error
;
3210 if (!i915
.enable_hangcheck
)
3213 /* Don't continually defer the hangcheck so that it is always run at
3214 * least once after work has been scheduled on any ring. Otherwise,
3215 * we will ignore a hung ring if a second ring is kept busy.
3218 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3219 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3222 static void ibx_irq_reset(struct drm_device
*dev
)
3224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3226 if (HAS_PCH_NOP(dev
))
3229 GEN5_IRQ_RESET(SDE
);
3231 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3232 I915_WRITE(SERR_INT
, 0xffffffff);
3236 * SDEIER is also touched by the interrupt handler to work around missed PCH
3237 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3238 * instead we unconditionally enable all PCH interrupt sources here, but then
3239 * only unmask them as needed with SDEIMR.
3241 * This function needs to be called before interrupts are enabled.
3243 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3247 if (HAS_PCH_NOP(dev
))
3250 WARN_ON(I915_READ(SDEIER
) != 0);
3251 I915_WRITE(SDEIER
, 0xffffffff);
3252 POSTING_READ(SDEIER
);
3255 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3260 if (INTEL_INFO(dev
)->gen
>= 6)
3261 GEN5_IRQ_RESET(GEN6_PM
);
3266 static void ironlake_irq_reset(struct drm_device
*dev
)
3268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3270 I915_WRITE(HWSTAM
, 0xffffffff);
3274 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3276 gen5_gt_irq_reset(dev
);
3281 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3285 i915_hotplug_interrupt_update(dev_priv
, 0xFFFFFFFF, 0);
3286 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3288 for_each_pipe(dev_priv
, pipe
)
3289 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3291 GEN5_IRQ_RESET(VLV_
);
3294 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3299 I915_WRITE(VLV_IMR
, 0);
3300 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3301 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3302 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3304 gen5_gt_irq_reset(dev
);
3306 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3308 vlv_display_irq_reset(dev_priv
);
3311 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3313 GEN8_IRQ_RESET_NDX(GT
, 0);
3314 GEN8_IRQ_RESET_NDX(GT
, 1);
3315 GEN8_IRQ_RESET_NDX(GT
, 2);
3316 GEN8_IRQ_RESET_NDX(GT
, 3);
3319 static void gen8_irq_reset(struct drm_device
*dev
)
3321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3324 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3325 POSTING_READ(GEN8_MASTER_IRQ
);
3327 gen8_gt_irq_reset(dev_priv
);
3329 for_each_pipe(dev_priv
, pipe
)
3330 if (intel_display_power_is_enabled(dev_priv
,
3331 POWER_DOMAIN_PIPE(pipe
)))
3332 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3334 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3335 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3336 GEN5_IRQ_RESET(GEN8_PCU_
);
3338 if (HAS_PCH_SPLIT(dev
))
3342 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3343 unsigned int pipe_mask
)
3345 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3348 spin_lock_irq(&dev_priv
->irq_lock
);
3349 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3350 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3351 dev_priv
->de_irq_mask
[pipe
],
3352 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3353 spin_unlock_irq(&dev_priv
->irq_lock
);
3356 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3357 unsigned int pipe_mask
)
3361 spin_lock_irq(&dev_priv
->irq_lock
);
3362 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3363 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3364 spin_unlock_irq(&dev_priv
->irq_lock
);
3366 /* make sure we're done processing display irqs */
3367 synchronize_irq(dev_priv
->dev
->irq
);
3370 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3374 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3375 POSTING_READ(GEN8_MASTER_IRQ
);
3377 gen8_gt_irq_reset(dev_priv
);
3379 GEN5_IRQ_RESET(GEN8_PCU_
);
3381 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3383 vlv_display_irq_reset(dev_priv
);
3386 static u32
intel_hpd_enabled_irqs(struct drm_device
*dev
,
3387 const u32 hpd
[HPD_NUM_PINS
])
3389 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3390 struct intel_encoder
*encoder
;
3391 u32 enabled_irqs
= 0;
3393 for_each_intel_encoder(dev
, encoder
)
3394 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3395 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3397 return enabled_irqs
;
3400 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3403 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3405 if (HAS_PCH_IBX(dev
)) {
3406 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3407 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ibx
);
3409 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3410 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_cpt
);
3413 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3416 * Enable digital hotplug on the PCH, and configure the DP short pulse
3417 * duration to 2ms (which is the minimum in the Display Port spec).
3418 * The pulse duration bits are reserved on LPT+.
3420 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3421 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3422 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3423 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3424 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3426 * When CPU and PCH are on the same package, port A
3427 * HPD must be enabled in both north and south.
3429 if (HAS_PCH_LPT_LP(dev
))
3430 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3431 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3434 static void spt_hpd_irq_setup(struct drm_device
*dev
)
3436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3437 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3439 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3440 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_spt
);
3442 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3444 /* Enable digital hotplug on the PCH */
3445 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3446 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3447 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3448 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3450 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3451 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3452 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3455 static void ilk_hpd_irq_setup(struct drm_device
*dev
)
3457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3458 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3460 if (INTEL_INFO(dev
)->gen
>= 8) {
3461 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3462 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bdw
);
3464 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3465 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3466 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3467 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ivb
);
3469 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3471 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3472 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ilk
);
3474 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3478 * Enable digital hotplug on the CPU, and configure the DP short pulse
3479 * duration to 2ms (which is the minimum in the Display Port spec)
3480 * The pulse duration bits are reserved on HSW+.
3482 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3483 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3484 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3485 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3487 ibx_hpd_irq_setup(dev
);
3490 static void bxt_hpd_irq_setup(struct drm_device
*dev
)
3492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3493 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3495 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bxt
);
3496 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3498 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3500 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3501 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3502 PORTA_HOTPLUG_ENABLE
;
3504 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3505 hotplug
, enabled_irqs
);
3506 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3509 * For BXT invert bit has to be set based on AOB design
3510 * for HPD detection logic, update it based on VBT fields.
3513 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3514 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3515 hotplug
|= BXT_DDIA_HPD_INVERT
;
3516 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3517 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3518 hotplug
|= BXT_DDIB_HPD_INVERT
;
3519 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3520 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3521 hotplug
|= BXT_DDIC_HPD_INVERT
;
3523 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3526 static void ibx_irq_postinstall(struct drm_device
*dev
)
3528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3531 if (HAS_PCH_NOP(dev
))
3534 if (HAS_PCH_IBX(dev
))
3535 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3537 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3539 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3540 I915_WRITE(SDEIMR
, ~mask
);
3543 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3546 u32 pm_irqs
, gt_irqs
;
3548 pm_irqs
= gt_irqs
= 0;
3550 dev_priv
->gt_irq_mask
= ~0;
3551 if (HAS_L3_DPF(dev
)) {
3552 /* L3 parity interrupt is always unmasked. */
3553 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3554 gt_irqs
|= GT_PARITY_ERROR(dev
);
3557 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3559 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3560 ILK_BSD_USER_INTERRUPT
;
3562 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3565 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3567 if (INTEL_INFO(dev
)->gen
>= 6) {
3569 * RPS interrupts will get enabled/disabled on demand when RPS
3570 * itself is enabled/disabled.
3573 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3575 dev_priv
->pm_irq_mask
= 0xffffffff;
3576 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3580 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3583 u32 display_mask
, extra_mask
;
3585 if (INTEL_INFO(dev
)->gen
>= 7) {
3586 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3587 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3588 DE_PLANEB_FLIP_DONE_IVB
|
3589 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3590 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3591 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3592 DE_DP_A_HOTPLUG_IVB
);
3594 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3595 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3597 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3599 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3600 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3604 dev_priv
->irq_mask
= ~display_mask
;
3606 I915_WRITE(HWSTAM
, 0xeffe);
3608 ibx_irq_pre_postinstall(dev
);
3610 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3612 gen5_gt_irq_postinstall(dev
);
3614 ibx_irq_postinstall(dev
);
3616 if (IS_IRONLAKE_M(dev
)) {
3617 /* Enable PCU event interrupts
3619 * spinlocking not required here for correctness since interrupt
3620 * setup is guaranteed to run in single-threaded context. But we
3621 * need it to make the assert_spin_locked happy. */
3622 spin_lock_irq(&dev_priv
->irq_lock
);
3623 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3624 spin_unlock_irq(&dev_priv
->irq_lock
);
3630 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3636 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3637 PIPE_FIFO_UNDERRUN_STATUS
;
3639 for_each_pipe(dev_priv
, pipe
)
3640 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3641 POSTING_READ(PIPESTAT(PIPE_A
));
3643 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3644 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3646 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3647 for_each_pipe(dev_priv
, pipe
)
3648 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3650 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3651 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3652 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3653 if (IS_CHERRYVIEW(dev_priv
))
3654 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3655 dev_priv
->irq_mask
&= ~iir_mask
;
3657 I915_WRITE(VLV_IIR
, iir_mask
);
3658 I915_WRITE(VLV_IIR
, iir_mask
);
3659 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3660 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3661 POSTING_READ(VLV_IMR
);
3664 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3670 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3671 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3672 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3673 if (IS_CHERRYVIEW(dev_priv
))
3674 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3676 dev_priv
->irq_mask
|= iir_mask
;
3677 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3678 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3679 I915_WRITE(VLV_IIR
, iir_mask
);
3680 I915_WRITE(VLV_IIR
, iir_mask
);
3681 POSTING_READ(VLV_IIR
);
3683 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3684 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3686 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3687 for_each_pipe(dev_priv
, pipe
)
3688 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3690 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3691 PIPE_FIFO_UNDERRUN_STATUS
;
3693 for_each_pipe(dev_priv
, pipe
)
3694 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3695 POSTING_READ(PIPESTAT(PIPE_A
));
3698 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3700 assert_spin_locked(&dev_priv
->irq_lock
);
3702 if (dev_priv
->display_irqs_enabled
)
3705 dev_priv
->display_irqs_enabled
= true;
3707 if (intel_irqs_enabled(dev_priv
))
3708 valleyview_display_irqs_install(dev_priv
);
3711 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3713 assert_spin_locked(&dev_priv
->irq_lock
);
3715 if (!dev_priv
->display_irqs_enabled
)
3718 dev_priv
->display_irqs_enabled
= false;
3720 if (intel_irqs_enabled(dev_priv
))
3721 valleyview_display_irqs_uninstall(dev_priv
);
3724 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3726 dev_priv
->irq_mask
= ~0;
3728 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3729 POSTING_READ(PORT_HOTPLUG_EN
);
3731 I915_WRITE(VLV_IIR
, 0xffffffff);
3732 I915_WRITE(VLV_IIR
, 0xffffffff);
3733 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3734 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3735 POSTING_READ(VLV_IMR
);
3737 /* Interrupt setup is already guaranteed to be single-threaded, this is
3738 * just to make the assert_spin_locked check happy. */
3739 spin_lock_irq(&dev_priv
->irq_lock
);
3740 if (dev_priv
->display_irqs_enabled
)
3741 valleyview_display_irqs_install(dev_priv
);
3742 spin_unlock_irq(&dev_priv
->irq_lock
);
3745 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3749 vlv_display_irq_postinstall(dev_priv
);
3751 gen5_gt_irq_postinstall(dev
);
3753 /* ack & enable invalid PTE error interrupts */
3754 #if 0 /* FIXME: add support to irq handler for checking these bits */
3755 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3756 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3759 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3764 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3766 /* These are interrupts we'll toggle with the ring mask register */
3767 uint32_t gt_interrupts
[] = {
3768 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3769 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3770 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3771 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3772 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3773 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3774 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3775 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3776 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3778 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3779 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3782 dev_priv
->pm_irq_mask
= 0xffffffff;
3783 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3784 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3786 * RPS interrupts will get enabled/disabled on demand when RPS itself
3787 * is enabled/disabled.
3789 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3790 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3793 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3795 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3796 uint32_t de_pipe_enables
;
3797 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3798 u32 de_port_enables
;
3801 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3802 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3803 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3804 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3806 if (IS_BROXTON(dev_priv
))
3807 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3809 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3810 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3813 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3814 GEN8_PIPE_FIFO_UNDERRUN
;
3816 de_port_enables
= de_port_masked
;
3817 if (IS_BROXTON(dev_priv
))
3818 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3819 else if (IS_BROADWELL(dev_priv
))
3820 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3822 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3823 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3824 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3826 for_each_pipe(dev_priv
, pipe
)
3827 if (intel_display_power_is_enabled(dev_priv
,
3828 POWER_DOMAIN_PIPE(pipe
)))
3829 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3830 dev_priv
->de_irq_mask
[pipe
],
3833 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3836 static int gen8_irq_postinstall(struct drm_device
*dev
)
3838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3840 if (HAS_PCH_SPLIT(dev
))
3841 ibx_irq_pre_postinstall(dev
);
3843 gen8_gt_irq_postinstall(dev_priv
);
3844 gen8_de_irq_postinstall(dev_priv
);
3846 if (HAS_PCH_SPLIT(dev
))
3847 ibx_irq_postinstall(dev
);
3849 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3850 POSTING_READ(GEN8_MASTER_IRQ
);
3855 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3859 vlv_display_irq_postinstall(dev_priv
);
3861 gen8_gt_irq_postinstall(dev_priv
);
3863 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3864 POSTING_READ(GEN8_MASTER_IRQ
);
3869 static void gen8_irq_uninstall(struct drm_device
*dev
)
3871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3876 gen8_irq_reset(dev
);
3879 static void vlv_display_irq_uninstall(struct drm_i915_private
*dev_priv
)
3881 /* Interrupt setup is already guaranteed to be single-threaded, this is
3882 * just to make the assert_spin_locked check happy. */
3883 spin_lock_irq(&dev_priv
->irq_lock
);
3884 if (dev_priv
->display_irqs_enabled
)
3885 valleyview_display_irqs_uninstall(dev_priv
);
3886 spin_unlock_irq(&dev_priv
->irq_lock
);
3888 vlv_display_irq_reset(dev_priv
);
3890 dev_priv
->irq_mask
= ~0;
3893 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3900 I915_WRITE(VLV_MASTER_IER
, 0);
3902 gen5_gt_irq_reset(dev
);
3904 I915_WRITE(HWSTAM
, 0xffffffff);
3906 vlv_display_irq_uninstall(dev_priv
);
3909 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3916 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3917 POSTING_READ(GEN8_MASTER_IRQ
);
3919 gen8_gt_irq_reset(dev_priv
);
3921 GEN5_IRQ_RESET(GEN8_PCU_
);
3923 vlv_display_irq_uninstall(dev_priv
);
3926 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3933 ironlake_irq_reset(dev
);
3936 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3941 for_each_pipe(dev_priv
, pipe
)
3942 I915_WRITE(PIPESTAT(pipe
), 0);
3943 I915_WRITE16(IMR
, 0xffff);
3944 I915_WRITE16(IER
, 0x0);
3945 POSTING_READ16(IER
);
3948 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3953 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3955 /* Unmask the interrupts that we always want on. */
3956 dev_priv
->irq_mask
=
3957 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3958 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3959 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3960 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3961 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3964 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3965 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3966 I915_USER_INTERRUPT
);
3967 POSTING_READ16(IER
);
3969 /* Interrupt setup is already guaranteed to be single-threaded, this is
3970 * just to make the assert_spin_locked check happy. */
3971 spin_lock_irq(&dev_priv
->irq_lock
);
3972 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3973 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3974 spin_unlock_irq(&dev_priv
->irq_lock
);
3980 * Returns true when a page flip has completed.
3982 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3983 int plane
, int pipe
, u32 iir
)
3985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3986 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3988 if (!intel_pipe_handle_vblank(dev
, pipe
))
3991 if ((iir
& flip_pending
) == 0)
3992 goto check_page_flip
;
3994 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3995 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3996 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3997 * the flip is completed (no longer pending). Since this doesn't raise
3998 * an interrupt per se, we watch for the change at vblank.
4000 if (I915_READ16(ISR
) & flip_pending
)
4001 goto check_page_flip
;
4003 intel_prepare_page_flip(dev
, plane
);
4004 intel_finish_page_flip(dev
, pipe
);
4008 intel_check_page_flip(dev
, pipe
);
4012 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
4014 struct drm_device
*dev
= arg
;
4015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4020 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4021 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4024 if (!intel_irqs_enabled(dev_priv
))
4027 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4028 disable_rpm_wakeref_asserts(dev_priv
);
4031 iir
= I915_READ16(IIR
);
4035 while (iir
& ~flip_mask
) {
4036 /* Can't rely on pipestat interrupt bit in iir as it might
4037 * have been cleared after the pipestat interrupt was received.
4038 * It doesn't set the bit in iir again, but it still produces
4039 * interrupts (for non-MSI).
4041 spin_lock(&dev_priv
->irq_lock
);
4042 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4043 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4045 for_each_pipe(dev_priv
, pipe
) {
4046 i915_reg_t reg
= PIPESTAT(pipe
);
4047 pipe_stats
[pipe
] = I915_READ(reg
);
4050 * Clear the PIPE*STAT regs before the IIR
4052 if (pipe_stats
[pipe
] & 0x8000ffff)
4053 I915_WRITE(reg
, pipe_stats
[pipe
]);
4055 spin_unlock(&dev_priv
->irq_lock
);
4057 I915_WRITE16(IIR
, iir
& ~flip_mask
);
4058 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
4060 if (iir
& I915_USER_INTERRUPT
)
4061 notify_ring(&dev_priv
->engine
[RCS
]);
4063 for_each_pipe(dev_priv
, pipe
) {
4068 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4069 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
4070 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4072 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4073 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4075 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4076 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4085 enable_rpm_wakeref_asserts(dev_priv
);
4090 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4095 for_each_pipe(dev_priv
, pipe
) {
4096 /* Clear enable bits; then clear status bits */
4097 I915_WRITE(PIPESTAT(pipe
), 0);
4098 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4100 I915_WRITE16(IMR
, 0xffff);
4101 I915_WRITE16(IER
, 0x0);
4102 I915_WRITE16(IIR
, I915_READ16(IIR
));
4105 static void i915_irq_preinstall(struct drm_device
* dev
)
4107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4110 if (I915_HAS_HOTPLUG(dev
)) {
4111 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4112 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4115 I915_WRITE16(HWSTAM
, 0xeffe);
4116 for_each_pipe(dev_priv
, pipe
)
4117 I915_WRITE(PIPESTAT(pipe
), 0);
4118 I915_WRITE(IMR
, 0xffffffff);
4119 I915_WRITE(IER
, 0x0);
4123 static int i915_irq_postinstall(struct drm_device
*dev
)
4125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4128 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4130 /* Unmask the interrupts that we always want on. */
4131 dev_priv
->irq_mask
=
4132 ~(I915_ASLE_INTERRUPT
|
4133 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4134 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4135 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4136 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4139 I915_ASLE_INTERRUPT
|
4140 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4141 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4142 I915_USER_INTERRUPT
;
4144 if (I915_HAS_HOTPLUG(dev
)) {
4145 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4146 POSTING_READ(PORT_HOTPLUG_EN
);
4148 /* Enable in IER... */
4149 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4150 /* and unmask in IMR */
4151 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4154 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4155 I915_WRITE(IER
, enable_mask
);
4158 i915_enable_asle_pipestat(dev
);
4160 /* Interrupt setup is already guaranteed to be single-threaded, this is
4161 * just to make the assert_spin_locked check happy. */
4162 spin_lock_irq(&dev_priv
->irq_lock
);
4163 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4164 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4165 spin_unlock_irq(&dev_priv
->irq_lock
);
4171 * Returns true when a page flip has completed.
4173 static bool i915_handle_vblank(struct drm_device
*dev
,
4174 int plane
, int pipe
, u32 iir
)
4176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4177 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4179 if (!intel_pipe_handle_vblank(dev
, pipe
))
4182 if ((iir
& flip_pending
) == 0)
4183 goto check_page_flip
;
4185 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4186 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4187 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4188 * the flip is completed (no longer pending). Since this doesn't raise
4189 * an interrupt per se, we watch for the change at vblank.
4191 if (I915_READ(ISR
) & flip_pending
)
4192 goto check_page_flip
;
4194 intel_prepare_page_flip(dev
, plane
);
4195 intel_finish_page_flip(dev
, pipe
);
4199 intel_check_page_flip(dev
, pipe
);
4203 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4205 struct drm_device
*dev
= arg
;
4206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4207 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4209 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4210 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4211 int pipe
, ret
= IRQ_NONE
;
4213 if (!intel_irqs_enabled(dev_priv
))
4216 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4217 disable_rpm_wakeref_asserts(dev_priv
);
4219 iir
= I915_READ(IIR
);
4221 bool irq_received
= (iir
& ~flip_mask
) != 0;
4222 bool blc_event
= false;
4224 /* Can't rely on pipestat interrupt bit in iir as it might
4225 * have been cleared after the pipestat interrupt was received.
4226 * It doesn't set the bit in iir again, but it still produces
4227 * interrupts (for non-MSI).
4229 spin_lock(&dev_priv
->irq_lock
);
4230 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4231 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4233 for_each_pipe(dev_priv
, pipe
) {
4234 i915_reg_t reg
= PIPESTAT(pipe
);
4235 pipe_stats
[pipe
] = I915_READ(reg
);
4237 /* Clear the PIPE*STAT regs before the IIR */
4238 if (pipe_stats
[pipe
] & 0x8000ffff) {
4239 I915_WRITE(reg
, pipe_stats
[pipe
]);
4240 irq_received
= true;
4243 spin_unlock(&dev_priv
->irq_lock
);
4248 /* Consume port. Then clear IIR or we'll miss events */
4249 if (I915_HAS_HOTPLUG(dev
) &&
4250 iir
& I915_DISPLAY_PORT_INTERRUPT
)
4251 i9xx_hpd_irq_handler(dev
);
4253 I915_WRITE(IIR
, iir
& ~flip_mask
);
4254 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4256 if (iir
& I915_USER_INTERRUPT
)
4257 notify_ring(&dev_priv
->engine
[RCS
]);
4259 for_each_pipe(dev_priv
, pipe
) {
4264 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4265 i915_handle_vblank(dev
, plane
, pipe
, iir
))
4266 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4268 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4271 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4272 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4274 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4275 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4279 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4280 intel_opregion_asle_intr(dev
);
4282 /* With MSI, interrupts are only generated when iir
4283 * transitions from zero to nonzero. If another bit got
4284 * set while we were handling the existing iir bits, then
4285 * we would never get another interrupt.
4287 * This is fine on non-MSI as well, as if we hit this path
4288 * we avoid exiting the interrupt handler only to generate
4291 * Note that for MSI this could cause a stray interrupt report
4292 * if an interrupt landed in the time between writing IIR and
4293 * the posting read. This should be rare enough to never
4294 * trigger the 99% of 100,000 interrupts test for disabling
4299 } while (iir
& ~flip_mask
);
4301 enable_rpm_wakeref_asserts(dev_priv
);
4306 static void i915_irq_uninstall(struct drm_device
* dev
)
4308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4311 if (I915_HAS_HOTPLUG(dev
)) {
4312 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4313 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4316 I915_WRITE16(HWSTAM
, 0xffff);
4317 for_each_pipe(dev_priv
, pipe
) {
4318 /* Clear enable bits; then clear status bits */
4319 I915_WRITE(PIPESTAT(pipe
), 0);
4320 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4322 I915_WRITE(IMR
, 0xffffffff);
4323 I915_WRITE(IER
, 0x0);
4325 I915_WRITE(IIR
, I915_READ(IIR
));
4328 static void i965_irq_preinstall(struct drm_device
* dev
)
4330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4333 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4334 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4336 I915_WRITE(HWSTAM
, 0xeffe);
4337 for_each_pipe(dev_priv
, pipe
)
4338 I915_WRITE(PIPESTAT(pipe
), 0);
4339 I915_WRITE(IMR
, 0xffffffff);
4340 I915_WRITE(IER
, 0x0);
4344 static int i965_irq_postinstall(struct drm_device
*dev
)
4346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4350 /* Unmask the interrupts that we always want on. */
4351 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4352 I915_DISPLAY_PORT_INTERRUPT
|
4353 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4354 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4355 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4356 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4357 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4359 enable_mask
= ~dev_priv
->irq_mask
;
4360 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4361 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4362 enable_mask
|= I915_USER_INTERRUPT
;
4365 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4367 /* Interrupt setup is already guaranteed to be single-threaded, this is
4368 * just to make the assert_spin_locked check happy. */
4369 spin_lock_irq(&dev_priv
->irq_lock
);
4370 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4371 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4372 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4373 spin_unlock_irq(&dev_priv
->irq_lock
);
4376 * Enable some error detection, note the instruction error mask
4377 * bit is reserved, so we leave it masked.
4380 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4381 GM45_ERROR_MEM_PRIV
|
4382 GM45_ERROR_CP_PRIV
|
4383 I915_ERROR_MEMORY_REFRESH
);
4385 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4386 I915_ERROR_MEMORY_REFRESH
);
4388 I915_WRITE(EMR
, error_mask
);
4390 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4391 I915_WRITE(IER
, enable_mask
);
4394 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4395 POSTING_READ(PORT_HOTPLUG_EN
);
4397 i915_enable_asle_pipestat(dev
);
4402 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4407 assert_spin_locked(&dev_priv
->irq_lock
);
4409 /* Note HDMI and DP share hotplug bits */
4410 /* enable bits are the same for all generations */
4411 hotplug_en
= intel_hpd_enabled_irqs(dev
, hpd_mask_i915
);
4412 /* Programming the CRT detection parameters tends
4413 to generate a spurious hotplug event about three
4414 seconds later. So just do it once.
4417 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4418 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4420 /* Ignore TV since it's buggy */
4421 i915_hotplug_interrupt_update_locked(dev_priv
,
4422 HOTPLUG_INT_EN_MASK
|
4423 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4424 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4428 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4430 struct drm_device
*dev
= arg
;
4431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4433 u32 pipe_stats
[I915_MAX_PIPES
];
4434 int ret
= IRQ_NONE
, pipe
;
4436 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4437 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4439 if (!intel_irqs_enabled(dev_priv
))
4442 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4443 disable_rpm_wakeref_asserts(dev_priv
);
4445 iir
= I915_READ(IIR
);
4448 bool irq_received
= (iir
& ~flip_mask
) != 0;
4449 bool blc_event
= false;
4451 /* Can't rely on pipestat interrupt bit in iir as it might
4452 * have been cleared after the pipestat interrupt was received.
4453 * It doesn't set the bit in iir again, but it still produces
4454 * interrupts (for non-MSI).
4456 spin_lock(&dev_priv
->irq_lock
);
4457 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4458 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4460 for_each_pipe(dev_priv
, pipe
) {
4461 i915_reg_t reg
= PIPESTAT(pipe
);
4462 pipe_stats
[pipe
] = I915_READ(reg
);
4465 * Clear the PIPE*STAT regs before the IIR
4467 if (pipe_stats
[pipe
] & 0x8000ffff) {
4468 I915_WRITE(reg
, pipe_stats
[pipe
]);
4469 irq_received
= true;
4472 spin_unlock(&dev_priv
->irq_lock
);
4479 /* Consume port. Then clear IIR or we'll miss events */
4480 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4481 i9xx_hpd_irq_handler(dev
);
4483 I915_WRITE(IIR
, iir
& ~flip_mask
);
4484 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4486 if (iir
& I915_USER_INTERRUPT
)
4487 notify_ring(&dev_priv
->engine
[RCS
]);
4488 if (iir
& I915_BSD_USER_INTERRUPT
)
4489 notify_ring(&dev_priv
->engine
[VCS
]);
4491 for_each_pipe(dev_priv
, pipe
) {
4492 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4493 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4494 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4496 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4499 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4500 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4502 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4503 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4506 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4507 intel_opregion_asle_intr(dev
);
4509 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4510 gmbus_irq_handler(dev
);
4512 /* With MSI, interrupts are only generated when iir
4513 * transitions from zero to nonzero. If another bit got
4514 * set while we were handling the existing iir bits, then
4515 * we would never get another interrupt.
4517 * This is fine on non-MSI as well, as if we hit this path
4518 * we avoid exiting the interrupt handler only to generate
4521 * Note that for MSI this could cause a stray interrupt report
4522 * if an interrupt landed in the time between writing IIR and
4523 * the posting read. This should be rare enough to never
4524 * trigger the 99% of 100,000 interrupts test for disabling
4530 enable_rpm_wakeref_asserts(dev_priv
);
4535 static void i965_irq_uninstall(struct drm_device
* dev
)
4537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4543 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4544 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4546 I915_WRITE(HWSTAM
, 0xffffffff);
4547 for_each_pipe(dev_priv
, pipe
)
4548 I915_WRITE(PIPESTAT(pipe
), 0);
4549 I915_WRITE(IMR
, 0xffffffff);
4550 I915_WRITE(IER
, 0x0);
4552 for_each_pipe(dev_priv
, pipe
)
4553 I915_WRITE(PIPESTAT(pipe
),
4554 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4555 I915_WRITE(IIR
, I915_READ(IIR
));
4559 * intel_irq_init - initializes irq support
4560 * @dev_priv: i915 device instance
4562 * This function initializes all the irq support including work items, timers
4563 * and all the vtables. It does not setup the interrupt itself though.
4565 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4567 struct drm_device
*dev
= dev_priv
->dev
;
4569 intel_hpd_init_work(dev_priv
);
4571 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4572 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4574 /* Let's track the enabled rps events */
4575 if (IS_VALLEYVIEW(dev_priv
))
4576 /* WaGsvRC0ResidencyMethod:vlv */
4577 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4579 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4581 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4582 i915_hangcheck_elapsed
);
4584 if (IS_GEN2(dev_priv
)) {
4585 dev
->max_vblank_count
= 0;
4586 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4587 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4588 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4589 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4591 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4592 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4596 * Opt out of the vblank disable timer on everything except gen2.
4597 * Gen2 doesn't have a hardware frame counter and so depends on
4598 * vblank interrupts to produce sane vblank seuquence numbers.
4600 if (!IS_GEN2(dev_priv
))
4601 dev
->vblank_disable_immediate
= true;
4603 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4604 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4606 if (IS_CHERRYVIEW(dev_priv
)) {
4607 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4608 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4609 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4610 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4611 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4612 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4613 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4614 } else if (IS_VALLEYVIEW(dev_priv
)) {
4615 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4616 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4617 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4618 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4619 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4620 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4621 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4622 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4623 dev
->driver
->irq_handler
= gen8_irq_handler
;
4624 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4625 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4626 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4627 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4628 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4629 if (IS_BROXTON(dev
))
4630 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4631 else if (HAS_PCH_SPT(dev
))
4632 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4634 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4635 } else if (HAS_PCH_SPLIT(dev
)) {
4636 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4637 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4638 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4639 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4640 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4641 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4642 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4644 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4645 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4646 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4647 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4648 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4649 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4650 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4651 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4652 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4653 dev
->driver
->irq_handler
= i915_irq_handler
;
4655 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4656 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4657 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4658 dev
->driver
->irq_handler
= i965_irq_handler
;
4660 if (I915_HAS_HOTPLUG(dev_priv
))
4661 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4662 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4663 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4668 * intel_irq_install - enables the hardware interrupt
4669 * @dev_priv: i915 device instance
4671 * This function enables the hardware interrupt handling, but leaves the hotplug
4672 * handling still disabled. It is called after intel_irq_init().
4674 * In the driver load and resume code we need working interrupts in a few places
4675 * but don't want to deal with the hassle of concurrent probe and hotplug
4676 * workers. Hence the split into this two-stage approach.
4678 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4681 * We enable some interrupt sources in our postinstall hooks, so mark
4682 * interrupts as enabled _before_ actually enabling them to avoid
4683 * special cases in our ordering checks.
4685 dev_priv
->pm
.irqs_enabled
= true;
4687 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4691 * intel_irq_uninstall - finilizes all irq handling
4692 * @dev_priv: i915 device instance
4694 * This stops interrupt and hotplug handling and unregisters and frees all
4695 * resources acquired in the init functions.
4697 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4699 drm_irq_uninstall(dev_priv
->dev
);
4700 intel_hpd_cancel_work(dev_priv
);
4701 dev_priv
->pm
.irqs_enabled
= false;
4705 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4706 * @dev_priv: i915 device instance
4708 * This function is used to disable interrupts at runtime, both in the runtime
4709 * pm and the system suspend/resume code.
4711 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4713 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4714 dev_priv
->pm
.irqs_enabled
= false;
4715 synchronize_irq(dev_priv
->dev
->irq
);
4719 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4720 * @dev_priv: i915 device instance
4722 * This function is used to enable interrupts at runtime, both in the runtime
4723 * pm and the system suspend/resume code.
4725 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4727 dev_priv
->pm
.irqs_enabled
= true;
4728 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4729 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);