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drm/i915: add support for checking if we hold an RPM reference
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
89
90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
93 struct intel_crtc_state *pipe_config);
94
95 static int intel_framebuffer_init(struct drm_device *dev,
96 struct intel_framebuffer *ifb,
97 struct drm_mode_fb_cmd2 *mode_cmd,
98 struct drm_i915_gem_object *obj);
99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
116 int num_connectors);
117 static void skylake_pfit_enable(struct intel_crtc *crtc);
118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
121
122 typedef struct {
123 int min, max;
124 } intel_range_t;
125
126 typedef struct {
127 int dot_limit;
128 int p2_slow, p2_fast;
129 } intel_p2_t;
130
131 typedef struct intel_limit intel_limit_t;
132 struct intel_limit {
133 intel_range_t dot, vco, n, m, m1, m2, p, p1;
134 intel_p2_t p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
139 {
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149 }
150
151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg)
153 {
154 u32 val;
155 int divider;
156
157 if (dev_priv->hpll_freq == 0)
158 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
171 }
172
173 int
174 intel_pch_rawclk(struct drm_device *dev)
175 {
176 struct drm_i915_private *dev_priv = dev->dev_private;
177
178 WARN_ON(!HAS_PCH_SPLIT(dev));
179
180 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
181 }
182
183 /* hrawclock is 1/4 the FSB frequency */
184 int intel_hrawclk(struct drm_device *dev)
185 {
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 uint32_t clkcfg;
188
189 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
190 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
191 return 200;
192
193 clkcfg = I915_READ(CLKCFG);
194 switch (clkcfg & CLKCFG_FSB_MASK) {
195 case CLKCFG_FSB_400:
196 return 100;
197 case CLKCFG_FSB_533:
198 return 133;
199 case CLKCFG_FSB_667:
200 return 166;
201 case CLKCFG_FSB_800:
202 return 200;
203 case CLKCFG_FSB_1067:
204 return 266;
205 case CLKCFG_FSB_1333:
206 return 333;
207 /* these two are just a guess; one of them might be right */
208 case CLKCFG_FSB_1600:
209 case CLKCFG_FSB_1600_ALT:
210 return 400;
211 default:
212 return 133;
213 }
214 }
215
216 static void intel_update_czclk(struct drm_i915_private *dev_priv)
217 {
218 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
219 return;
220
221 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
222 CCK_CZ_CLOCK_CONTROL);
223
224 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
225 }
226
227 static inline u32 /* units of 100MHz */
228 intel_fdi_link_freq(struct drm_device *dev)
229 {
230 if (IS_GEN5(dev)) {
231 struct drm_i915_private *dev_priv = dev->dev_private;
232 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
233 } else
234 return 27;
235 }
236
237 static const intel_limit_t intel_limits_i8xx_dac = {
238 .dot = { .min = 25000, .max = 350000 },
239 .vco = { .min = 908000, .max = 1512000 },
240 .n = { .min = 2, .max = 16 },
241 .m = { .min = 96, .max = 140 },
242 .m1 = { .min = 18, .max = 26 },
243 .m2 = { .min = 6, .max = 16 },
244 .p = { .min = 4, .max = 128 },
245 .p1 = { .min = 2, .max = 33 },
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 4, .p2_fast = 2 },
248 };
249
250 static const intel_limit_t intel_limits_i8xx_dvo = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 908000, .max = 1512000 },
253 .n = { .min = 2, .max = 16 },
254 .m = { .min = 96, .max = 140 },
255 .m1 = { .min = 18, .max = 26 },
256 .m2 = { .min = 6, .max = 16 },
257 .p = { .min = 4, .max = 128 },
258 .p1 = { .min = 2, .max = 33 },
259 .p2 = { .dot_limit = 165000,
260 .p2_slow = 4, .p2_fast = 4 },
261 };
262
263 static const intel_limit_t intel_limits_i8xx_lvds = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 1, .max = 6 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 14, .p2_fast = 7 },
274 };
275
276 static const intel_limit_t intel_limits_i9xx_sdvo = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1400000, .max = 2800000 },
279 .n = { .min = 1, .max = 6 },
280 .m = { .min = 70, .max = 120 },
281 .m1 = { .min = 8, .max = 18 },
282 .m2 = { .min = 3, .max = 7 },
283 .p = { .min = 5, .max = 80 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 200000,
286 .p2_slow = 10, .p2_fast = 5 },
287 };
288
289 static const intel_limit_t intel_limits_i9xx_lvds = {
290 .dot = { .min = 20000, .max = 400000 },
291 .vco = { .min = 1400000, .max = 2800000 },
292 .n = { .min = 1, .max = 6 },
293 .m = { .min = 70, .max = 120 },
294 .m1 = { .min = 8, .max = 18 },
295 .m2 = { .min = 3, .max = 7 },
296 .p = { .min = 7, .max = 98 },
297 .p1 = { .min = 1, .max = 8 },
298 .p2 = { .dot_limit = 112000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302
303 static const intel_limit_t intel_limits_g4x_sdvo = {
304 .dot = { .min = 25000, .max = 270000 },
305 .vco = { .min = 1750000, .max = 3500000},
306 .n = { .min = 1, .max = 4 },
307 .m = { .min = 104, .max = 138 },
308 .m1 = { .min = 17, .max = 23 },
309 .m2 = { .min = 5, .max = 11 },
310 .p = { .min = 10, .max = 30 },
311 .p1 = { .min = 1, .max = 3},
312 .p2 = { .dot_limit = 270000,
313 .p2_slow = 10,
314 .p2_fast = 10
315 },
316 };
317
318 static const intel_limit_t intel_limits_g4x_hdmi = {
319 .dot = { .min = 22000, .max = 400000 },
320 .vco = { .min = 1750000, .max = 3500000},
321 .n = { .min = 1, .max = 4 },
322 .m = { .min = 104, .max = 138 },
323 .m1 = { .min = 16, .max = 23 },
324 .m2 = { .min = 5, .max = 11 },
325 .p = { .min = 5, .max = 80 },
326 .p1 = { .min = 1, .max = 8},
327 .p2 = { .dot_limit = 165000,
328 .p2_slow = 10, .p2_fast = 5 },
329 };
330
331 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
332 .dot = { .min = 20000, .max = 115000 },
333 .vco = { .min = 1750000, .max = 3500000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 104, .max = 138 },
336 .m1 = { .min = 17, .max = 23 },
337 .m2 = { .min = 5, .max = 11 },
338 .p = { .min = 28, .max = 112 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 0,
341 .p2_slow = 14, .p2_fast = 14
342 },
343 };
344
345 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
346 .dot = { .min = 80000, .max = 224000 },
347 .vco = { .min = 1750000, .max = 3500000 },
348 .n = { .min = 1, .max = 3 },
349 .m = { .min = 104, .max = 138 },
350 .m1 = { .min = 17, .max = 23 },
351 .m2 = { .min = 5, .max = 11 },
352 .p = { .min = 14, .max = 42 },
353 .p1 = { .min = 2, .max = 6 },
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 7, .p2_fast = 7
356 },
357 };
358
359 static const intel_limit_t intel_limits_pineview_sdvo = {
360 .dot = { .min = 20000, .max = 400000},
361 .vco = { .min = 1700000, .max = 3500000 },
362 /* Pineview's Ncounter is a ring counter */
363 .n = { .min = 3, .max = 6 },
364 .m = { .min = 2, .max = 256 },
365 /* Pineview only has one combined m divider, which we treat as m2. */
366 .m1 = { .min = 0, .max = 0 },
367 .m2 = { .min = 0, .max = 254 },
368 .p = { .min = 5, .max = 80 },
369 .p1 = { .min = 1, .max = 8 },
370 .p2 = { .dot_limit = 200000,
371 .p2_slow = 10, .p2_fast = 5 },
372 };
373
374 static const intel_limit_t intel_limits_pineview_lvds = {
375 .dot = { .min = 20000, .max = 400000 },
376 .vco = { .min = 1700000, .max = 3500000 },
377 .n = { .min = 3, .max = 6 },
378 .m = { .min = 2, .max = 256 },
379 .m1 = { .min = 0, .max = 0 },
380 .m2 = { .min = 0, .max = 254 },
381 .p = { .min = 7, .max = 112 },
382 .p1 = { .min = 1, .max = 8 },
383 .p2 = { .dot_limit = 112000,
384 .p2_slow = 14, .p2_fast = 14 },
385 };
386
387 /* Ironlake / Sandybridge
388 *
389 * We calculate clock using (register_value + 2) for N/M1/M2, so here
390 * the range value for them is (actual_value - 2).
391 */
392 static const intel_limit_t intel_limits_ironlake_dac = {
393 .dot = { .min = 25000, .max = 350000 },
394 .vco = { .min = 1760000, .max = 3510000 },
395 .n = { .min = 1, .max = 5 },
396 .m = { .min = 79, .max = 127 },
397 .m1 = { .min = 12, .max = 22 },
398 .m2 = { .min = 5, .max = 9 },
399 .p = { .min = 5, .max = 80 },
400 .p1 = { .min = 1, .max = 8 },
401 .p2 = { .dot_limit = 225000,
402 .p2_slow = 10, .p2_fast = 5 },
403 };
404
405 static const intel_limit_t intel_limits_ironlake_single_lvds = {
406 .dot = { .min = 25000, .max = 350000 },
407 .vco = { .min = 1760000, .max = 3510000 },
408 .n = { .min = 1, .max = 3 },
409 .m = { .min = 79, .max = 118 },
410 .m1 = { .min = 12, .max = 22 },
411 .m2 = { .min = 5, .max = 9 },
412 .p = { .min = 28, .max = 112 },
413 .p1 = { .min = 2, .max = 8 },
414 .p2 = { .dot_limit = 225000,
415 .p2_slow = 14, .p2_fast = 14 },
416 };
417
418 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 3 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 14, .max = 56 },
426 .p1 = { .min = 2, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 7, .p2_fast = 7 },
429 };
430
431 /* LVDS 100mhz refclk limits. */
432 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
433 .dot = { .min = 25000, .max = 350000 },
434 .vco = { .min = 1760000, .max = 3510000 },
435 .n = { .min = 1, .max = 2 },
436 .m = { .min = 79, .max = 126 },
437 .m1 = { .min = 12, .max = 22 },
438 .m2 = { .min = 5, .max = 9 },
439 .p = { .min = 28, .max = 112 },
440 .p1 = { .min = 2, .max = 8 },
441 .p2 = { .dot_limit = 225000,
442 .p2_slow = 14, .p2_fast = 14 },
443 };
444
445 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
446 .dot = { .min = 25000, .max = 350000 },
447 .vco = { .min = 1760000, .max = 3510000 },
448 .n = { .min = 1, .max = 3 },
449 .m = { .min = 79, .max = 126 },
450 .m1 = { .min = 12, .max = 22 },
451 .m2 = { .min = 5, .max = 9 },
452 .p = { .min = 14, .max = 42 },
453 .p1 = { .min = 2, .max = 6 },
454 .p2 = { .dot_limit = 225000,
455 .p2_slow = 7, .p2_fast = 7 },
456 };
457
458 static const intel_limit_t intel_limits_vlv = {
459 /*
460 * These are the data rate limits (measured in fast clocks)
461 * since those are the strictest limits we have. The fast
462 * clock and actual rate limits are more relaxed, so checking
463 * them would make no difference.
464 */
465 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
466 .vco = { .min = 4000000, .max = 6000000 },
467 .n = { .min = 1, .max = 7 },
468 .m1 = { .min = 2, .max = 3 },
469 .m2 = { .min = 11, .max = 156 },
470 .p1 = { .min = 2, .max = 3 },
471 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
472 };
473
474 static const intel_limit_t intel_limits_chv = {
475 /*
476 * These are the data rate limits (measured in fast clocks)
477 * since those are the strictest limits we have. The fast
478 * clock and actual rate limits are more relaxed, so checking
479 * them would make no difference.
480 */
481 .dot = { .min = 25000 * 5, .max = 540000 * 5},
482 .vco = { .min = 4800000, .max = 6480000 },
483 .n = { .min = 1, .max = 1 },
484 .m1 = { .min = 2, .max = 2 },
485 .m2 = { .min = 24 << 22, .max = 175 << 22 },
486 .p1 = { .min = 2, .max = 4 },
487 .p2 = { .p2_slow = 1, .p2_fast = 14 },
488 };
489
490 static const intel_limit_t intel_limits_bxt = {
491 /* FIXME: find real dot limits */
492 .dot = { .min = 0, .max = INT_MAX },
493 .vco = { .min = 4800000, .max = 6700000 },
494 .n = { .min = 1, .max = 1 },
495 .m1 = { .min = 2, .max = 2 },
496 /* FIXME: find real m2 limits */
497 .m2 = { .min = 2 << 22, .max = 255 << 22 },
498 .p1 = { .min = 2, .max = 4 },
499 .p2 = { .p2_slow = 1, .p2_fast = 20 },
500 };
501
502 static bool
503 needs_modeset(struct drm_crtc_state *state)
504 {
505 return drm_atomic_crtc_needs_modeset(state);
506 }
507
508 /**
509 * Returns whether any output on the specified pipe is of the specified type
510 */
511 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
512 {
513 struct drm_device *dev = crtc->base.dev;
514 struct intel_encoder *encoder;
515
516 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
517 if (encoder->type == type)
518 return true;
519
520 return false;
521 }
522
523 /**
524 * Returns whether any output on the specified pipe will have the specified
525 * type after a staged modeset is complete, i.e., the same as
526 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
527 * encoder->crtc.
528 */
529 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
530 int type)
531 {
532 struct drm_atomic_state *state = crtc_state->base.state;
533 struct drm_connector *connector;
534 struct drm_connector_state *connector_state;
535 struct intel_encoder *encoder;
536 int i, num_connectors = 0;
537
538 for_each_connector_in_state(state, connector, connector_state, i) {
539 if (connector_state->crtc != crtc_state->base.crtc)
540 continue;
541
542 num_connectors++;
543
544 encoder = to_intel_encoder(connector_state->best_encoder);
545 if (encoder->type == type)
546 return true;
547 }
548
549 WARN_ON(num_connectors == 0);
550
551 return false;
552 }
553
554 static const intel_limit_t *
555 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
556 {
557 struct drm_device *dev = crtc_state->base.crtc->dev;
558 const intel_limit_t *limit;
559
560 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
561 if (intel_is_dual_link_lvds(dev)) {
562 if (refclk == 100000)
563 limit = &intel_limits_ironlake_dual_lvds_100m;
564 else
565 limit = &intel_limits_ironlake_dual_lvds;
566 } else {
567 if (refclk == 100000)
568 limit = &intel_limits_ironlake_single_lvds_100m;
569 else
570 limit = &intel_limits_ironlake_single_lvds;
571 }
572 } else
573 limit = &intel_limits_ironlake_dac;
574
575 return limit;
576 }
577
578 static const intel_limit_t *
579 intel_g4x_limit(struct intel_crtc_state *crtc_state)
580 {
581 struct drm_device *dev = crtc_state->base.crtc->dev;
582 const intel_limit_t *limit;
583
584 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
585 if (intel_is_dual_link_lvds(dev))
586 limit = &intel_limits_g4x_dual_channel_lvds;
587 else
588 limit = &intel_limits_g4x_single_channel_lvds;
589 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
590 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
591 limit = &intel_limits_g4x_hdmi;
592 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
593 limit = &intel_limits_g4x_sdvo;
594 } else /* The option is for other outputs */
595 limit = &intel_limits_i9xx_sdvo;
596
597 return limit;
598 }
599
600 static const intel_limit_t *
601 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
602 {
603 struct drm_device *dev = crtc_state->base.crtc->dev;
604 const intel_limit_t *limit;
605
606 if (IS_BROXTON(dev))
607 limit = &intel_limits_bxt;
608 else if (HAS_PCH_SPLIT(dev))
609 limit = intel_ironlake_limit(crtc_state, refclk);
610 else if (IS_G4X(dev)) {
611 limit = intel_g4x_limit(crtc_state);
612 } else if (IS_PINEVIEW(dev)) {
613 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
614 limit = &intel_limits_pineview_lvds;
615 else
616 limit = &intel_limits_pineview_sdvo;
617 } else if (IS_CHERRYVIEW(dev)) {
618 limit = &intel_limits_chv;
619 } else if (IS_VALLEYVIEW(dev)) {
620 limit = &intel_limits_vlv;
621 } else if (!IS_GEN2(dev)) {
622 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
623 limit = &intel_limits_i9xx_lvds;
624 else
625 limit = &intel_limits_i9xx_sdvo;
626 } else {
627 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
628 limit = &intel_limits_i8xx_lvds;
629 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
630 limit = &intel_limits_i8xx_dvo;
631 else
632 limit = &intel_limits_i8xx_dac;
633 }
634 return limit;
635 }
636
637 /*
638 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
639 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
640 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
641 * The helpers' return value is the rate of the clock that is fed to the
642 * display engine's pipe which can be the above fast dot clock rate or a
643 * divided-down version of it.
644 */
645 /* m1 is reserved as 0 in Pineview, n is a ring counter */
646 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
647 {
648 clock->m = clock->m2 + 2;
649 clock->p = clock->p1 * clock->p2;
650 if (WARN_ON(clock->n == 0 || clock->p == 0))
651 return 0;
652 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
653 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
654
655 return clock->dot;
656 }
657
658 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
659 {
660 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
661 }
662
663 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
664 {
665 clock->m = i9xx_dpll_compute_m(clock);
666 clock->p = clock->p1 * clock->p2;
667 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
668 return 0;
669 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
670 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
671
672 return clock->dot;
673 }
674
675 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
676 {
677 clock->m = clock->m1 * clock->m2;
678 clock->p = clock->p1 * clock->p2;
679 if (WARN_ON(clock->n == 0 || clock->p == 0))
680 return 0;
681 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
682 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
683
684 return clock->dot / 5;
685 }
686
687 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
688 {
689 clock->m = clock->m1 * clock->m2;
690 clock->p = clock->p1 * clock->p2;
691 if (WARN_ON(clock->n == 0 || clock->p == 0))
692 return 0;
693 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
694 clock->n << 22);
695 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
696
697 return clock->dot / 5;
698 }
699
700 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
701 /**
702 * Returns whether the given set of divisors are valid for a given refclk with
703 * the given connectors.
704 */
705
706 static bool intel_PLL_is_valid(struct drm_device *dev,
707 const intel_limit_t *limit,
708 const intel_clock_t *clock)
709 {
710 if (clock->n < limit->n.min || limit->n.max < clock->n)
711 INTELPllInvalid("n out of range\n");
712 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
713 INTELPllInvalid("p1 out of range\n");
714 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
715 INTELPllInvalid("m2 out of range\n");
716 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
717 INTELPllInvalid("m1 out of range\n");
718
719 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
720 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
721 if (clock->m1 <= clock->m2)
722 INTELPllInvalid("m1 <= m2\n");
723
724 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
725 if (clock->p < limit->p.min || limit->p.max < clock->p)
726 INTELPllInvalid("p out of range\n");
727 if (clock->m < limit->m.min || limit->m.max < clock->m)
728 INTELPllInvalid("m out of range\n");
729 }
730
731 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
732 INTELPllInvalid("vco out of range\n");
733 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
734 * connector, etc., rather than just a single range.
735 */
736 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
737 INTELPllInvalid("dot out of range\n");
738
739 return true;
740 }
741
742 static int
743 i9xx_select_p2_div(const intel_limit_t *limit,
744 const struct intel_crtc_state *crtc_state,
745 int target)
746 {
747 struct drm_device *dev = crtc_state->base.crtc->dev;
748
749 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
750 /*
751 * For LVDS just rely on its current settings for dual-channel.
752 * We haven't figured out how to reliably set up different
753 * single/dual channel state, if we even can.
754 */
755 if (intel_is_dual_link_lvds(dev))
756 return limit->p2.p2_fast;
757 else
758 return limit->p2.p2_slow;
759 } else {
760 if (target < limit->p2.dot_limit)
761 return limit->p2.p2_slow;
762 else
763 return limit->p2.p2_fast;
764 }
765 }
766
767 static bool
768 i9xx_find_best_dpll(const intel_limit_t *limit,
769 struct intel_crtc_state *crtc_state,
770 int target, int refclk, intel_clock_t *match_clock,
771 intel_clock_t *best_clock)
772 {
773 struct drm_device *dev = crtc_state->base.crtc->dev;
774 intel_clock_t clock;
775 int err = target;
776
777 memset(best_clock, 0, sizeof(*best_clock));
778
779 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780
781 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 clock.m1++) {
783 for (clock.m2 = limit->m2.min;
784 clock.m2 <= limit->m2.max; clock.m2++) {
785 if (clock.m2 >= clock.m1)
786 break;
787 for (clock.n = limit->n.min;
788 clock.n <= limit->n.max; clock.n++) {
789 for (clock.p1 = limit->p1.min;
790 clock.p1 <= limit->p1.max; clock.p1++) {
791 int this_err;
792
793 i9xx_calc_dpll_params(refclk, &clock);
794 if (!intel_PLL_is_valid(dev, limit,
795 &clock))
796 continue;
797 if (match_clock &&
798 clock.p != match_clock->p)
799 continue;
800
801 this_err = abs(clock.dot - target);
802 if (this_err < err) {
803 *best_clock = clock;
804 err = this_err;
805 }
806 }
807 }
808 }
809 }
810
811 return (err != target);
812 }
813
814 static bool
815 pnv_find_best_dpll(const intel_limit_t *limit,
816 struct intel_crtc_state *crtc_state,
817 int target, int refclk, intel_clock_t *match_clock,
818 intel_clock_t *best_clock)
819 {
820 struct drm_device *dev = crtc_state->base.crtc->dev;
821 intel_clock_t clock;
822 int err = target;
823
824 memset(best_clock, 0, sizeof(*best_clock));
825
826 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
827
828 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
829 clock.m1++) {
830 for (clock.m2 = limit->m2.min;
831 clock.m2 <= limit->m2.max; clock.m2++) {
832 for (clock.n = limit->n.min;
833 clock.n <= limit->n.max; clock.n++) {
834 for (clock.p1 = limit->p1.min;
835 clock.p1 <= limit->p1.max; clock.p1++) {
836 int this_err;
837
838 pnv_calc_dpll_params(refclk, &clock);
839 if (!intel_PLL_is_valid(dev, limit,
840 &clock))
841 continue;
842 if (match_clock &&
843 clock.p != match_clock->p)
844 continue;
845
846 this_err = abs(clock.dot - target);
847 if (this_err < err) {
848 *best_clock = clock;
849 err = this_err;
850 }
851 }
852 }
853 }
854 }
855
856 return (err != target);
857 }
858
859 static bool
860 g4x_find_best_dpll(const intel_limit_t *limit,
861 struct intel_crtc_state *crtc_state,
862 int target, int refclk, intel_clock_t *match_clock,
863 intel_clock_t *best_clock)
864 {
865 struct drm_device *dev = crtc_state->base.crtc->dev;
866 intel_clock_t clock;
867 int max_n;
868 bool found = false;
869 /* approximately equals target * 0.00585 */
870 int err_most = (target >> 8) + (target >> 9);
871
872 memset(best_clock, 0, sizeof(*best_clock));
873
874 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
875
876 max_n = limit->n.max;
877 /* based on hardware requirement, prefer smaller n to precision */
878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
879 /* based on hardware requirement, prefere larger m1,m2 */
880 for (clock.m1 = limit->m1.max;
881 clock.m1 >= limit->m1.min; clock.m1--) {
882 for (clock.m2 = limit->m2.max;
883 clock.m2 >= limit->m2.min; clock.m2--) {
884 for (clock.p1 = limit->p1.max;
885 clock.p1 >= limit->p1.min; clock.p1--) {
886 int this_err;
887
888 i9xx_calc_dpll_params(refclk, &clock);
889 if (!intel_PLL_is_valid(dev, limit,
890 &clock))
891 continue;
892
893 this_err = abs(clock.dot - target);
894 if (this_err < err_most) {
895 *best_clock = clock;
896 err_most = this_err;
897 max_n = clock.n;
898 found = true;
899 }
900 }
901 }
902 }
903 }
904 return found;
905 }
906
907 /*
908 * Check if the calculated PLL configuration is more optimal compared to the
909 * best configuration and error found so far. Return the calculated error.
910 */
911 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
912 const intel_clock_t *calculated_clock,
913 const intel_clock_t *best_clock,
914 unsigned int best_error_ppm,
915 unsigned int *error_ppm)
916 {
917 /*
918 * For CHV ignore the error and consider only the P value.
919 * Prefer a bigger P value based on HW requirements.
920 */
921 if (IS_CHERRYVIEW(dev)) {
922 *error_ppm = 0;
923
924 return calculated_clock->p > best_clock->p;
925 }
926
927 if (WARN_ON_ONCE(!target_freq))
928 return false;
929
930 *error_ppm = div_u64(1000000ULL *
931 abs(target_freq - calculated_clock->dot),
932 target_freq);
933 /*
934 * Prefer a better P value over a better (smaller) error if the error
935 * is small. Ensure this preference for future configurations too by
936 * setting the error to 0.
937 */
938 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
939 *error_ppm = 0;
940
941 return true;
942 }
943
944 return *error_ppm + 10 < best_error_ppm;
945 }
946
947 static bool
948 vlv_find_best_dpll(const intel_limit_t *limit,
949 struct intel_crtc_state *crtc_state,
950 int target, int refclk, intel_clock_t *match_clock,
951 intel_clock_t *best_clock)
952 {
953 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
954 struct drm_device *dev = crtc->base.dev;
955 intel_clock_t clock;
956 unsigned int bestppm = 1000000;
957 /* min update 19.2 MHz */
958 int max_n = min(limit->n.max, refclk / 19200);
959 bool found = false;
960
961 target *= 5; /* fast clock */
962
963 memset(best_clock, 0, sizeof(*best_clock));
964
965 /* based on hardware requirement, prefer smaller n to precision */
966 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
969 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
970 clock.p = clock.p1 * clock.p2;
971 /* based on hardware requirement, prefer bigger m1,m2 values */
972 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
973 unsigned int ppm;
974
975 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
976 refclk * clock.m1);
977
978 vlv_calc_dpll_params(refclk, &clock);
979
980 if (!intel_PLL_is_valid(dev, limit,
981 &clock))
982 continue;
983
984 if (!vlv_PLL_is_optimal(dev, target,
985 &clock,
986 best_clock,
987 bestppm, &ppm))
988 continue;
989
990 *best_clock = clock;
991 bestppm = ppm;
992 found = true;
993 }
994 }
995 }
996 }
997
998 return found;
999 }
1000
1001 static bool
1002 chv_find_best_dpll(const intel_limit_t *limit,
1003 struct intel_crtc_state *crtc_state,
1004 int target, int refclk, intel_clock_t *match_clock,
1005 intel_clock_t *best_clock)
1006 {
1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1008 struct drm_device *dev = crtc->base.dev;
1009 unsigned int best_error_ppm;
1010 intel_clock_t clock;
1011 uint64_t m2;
1012 int found = false;
1013
1014 memset(best_clock, 0, sizeof(*best_clock));
1015 best_error_ppm = 1000000;
1016
1017 /*
1018 * Based on hardware doc, the n always set to 1, and m1 always
1019 * set to 2. If requires to support 200Mhz refclk, we need to
1020 * revisit this because n may not 1 anymore.
1021 */
1022 clock.n = 1, clock.m1 = 2;
1023 target *= 5; /* fast clock */
1024
1025 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1026 for (clock.p2 = limit->p2.p2_fast;
1027 clock.p2 >= limit->p2.p2_slow;
1028 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1029 unsigned int error_ppm;
1030
1031 clock.p = clock.p1 * clock.p2;
1032
1033 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1034 clock.n) << 22, refclk * clock.m1);
1035
1036 if (m2 > INT_MAX/clock.m1)
1037 continue;
1038
1039 clock.m2 = m2;
1040
1041 chv_calc_dpll_params(refclk, &clock);
1042
1043 if (!intel_PLL_is_valid(dev, limit, &clock))
1044 continue;
1045
1046 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1047 best_error_ppm, &error_ppm))
1048 continue;
1049
1050 *best_clock = clock;
1051 best_error_ppm = error_ppm;
1052 found = true;
1053 }
1054 }
1055
1056 return found;
1057 }
1058
1059 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1060 intel_clock_t *best_clock)
1061 {
1062 int refclk = i9xx_get_refclk(crtc_state, 0);
1063
1064 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1065 target_clock, refclk, NULL, best_clock);
1066 }
1067
1068 bool intel_crtc_active(struct drm_crtc *crtc)
1069 {
1070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071
1072 /* Be paranoid as we can arrive here with only partial
1073 * state retrieved from the hardware during setup.
1074 *
1075 * We can ditch the adjusted_mode.crtc_clock check as soon
1076 * as Haswell has gained clock readout/fastboot support.
1077 *
1078 * We can ditch the crtc->primary->fb check as soon as we can
1079 * properly reconstruct framebuffers.
1080 *
1081 * FIXME: The intel_crtc->active here should be switched to
1082 * crtc->state->active once we have proper CRTC states wired up
1083 * for atomic.
1084 */
1085 return intel_crtc->active && crtc->primary->state->fb &&
1086 intel_crtc->config->base.adjusted_mode.crtc_clock;
1087 }
1088
1089 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1090 enum pipe pipe)
1091 {
1092 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1094
1095 return intel_crtc->config->cpu_transcoder;
1096 }
1097
1098 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1099 {
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1101 i915_reg_t reg = PIPEDSL(pipe);
1102 u32 line1, line2;
1103 u32 line_mask;
1104
1105 if (IS_GEN2(dev))
1106 line_mask = DSL_LINEMASK_GEN2;
1107 else
1108 line_mask = DSL_LINEMASK_GEN3;
1109
1110 line1 = I915_READ(reg) & line_mask;
1111 msleep(5);
1112 line2 = I915_READ(reg) & line_mask;
1113
1114 return line1 == line2;
1115 }
1116
1117 /*
1118 * intel_wait_for_pipe_off - wait for pipe to turn off
1119 * @crtc: crtc whose pipe to wait for
1120 *
1121 * After disabling a pipe, we can't wait for vblank in the usual way,
1122 * spinning on the vblank interrupt status bit, since we won't actually
1123 * see an interrupt when the pipe is disabled.
1124 *
1125 * On Gen4 and above:
1126 * wait for the pipe register state bit to turn off
1127 *
1128 * Otherwise:
1129 * wait for the display line value to settle (it usually
1130 * ends up stopping at the start of the next frame).
1131 *
1132 */
1133 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1134 {
1135 struct drm_device *dev = crtc->base.dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1138 enum pipe pipe = crtc->pipe;
1139
1140 if (INTEL_INFO(dev)->gen >= 4) {
1141 i915_reg_t reg = PIPECONF(cpu_transcoder);
1142
1143 /* Wait for the Pipe State to go off */
1144 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1145 100))
1146 WARN(1, "pipe_off wait timed out\n");
1147 } else {
1148 /* Wait for the display line to settle */
1149 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1150 WARN(1, "pipe_off wait timed out\n");
1151 }
1152 }
1153
1154 static const char *state_string(bool enabled)
1155 {
1156 return enabled ? "on" : "off";
1157 }
1158
1159 /* Only for pre-ILK configs */
1160 void assert_pll(struct drm_i915_private *dev_priv,
1161 enum pipe pipe, bool state)
1162 {
1163 u32 val;
1164 bool cur_state;
1165
1166 val = I915_READ(DPLL(pipe));
1167 cur_state = !!(val & DPLL_VCO_ENABLE);
1168 I915_STATE_WARN(cur_state != state,
1169 "PLL state assertion failure (expected %s, current %s)\n",
1170 state_string(state), state_string(cur_state));
1171 }
1172
1173 /* XXX: the dsi pll is shared between MIPI DSI ports */
1174 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1175 {
1176 u32 val;
1177 bool cur_state;
1178
1179 mutex_lock(&dev_priv->sb_lock);
1180 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1181 mutex_unlock(&dev_priv->sb_lock);
1182
1183 cur_state = val & DSI_PLL_VCO_EN;
1184 I915_STATE_WARN(cur_state != state,
1185 "DSI PLL state assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1189 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1190
1191 struct intel_shared_dpll *
1192 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1193 {
1194 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1195
1196 if (crtc->config->shared_dpll < 0)
1197 return NULL;
1198
1199 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1200 }
1201
1202 /* For ILK+ */
1203 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1204 struct intel_shared_dpll *pll,
1205 bool state)
1206 {
1207 bool cur_state;
1208 struct intel_dpll_hw_state hw_state;
1209
1210 if (WARN (!pll,
1211 "asserting DPLL %s with no DPLL\n", state_string(state)))
1212 return;
1213
1214 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1215 I915_STATE_WARN(cur_state != state,
1216 "%s assertion failure (expected %s, current %s)\n",
1217 pll->name, state_string(state), state_string(cur_state));
1218 }
1219
1220 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, bool state)
1222 {
1223 bool cur_state;
1224 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 pipe);
1226
1227 if (HAS_DDI(dev_priv->dev)) {
1228 /* DDI does not have a specific FDI_TX register */
1229 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1230 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1231 } else {
1232 u32 val = I915_READ(FDI_TX_CTL(pipe));
1233 cur_state = !!(val & FDI_TX_ENABLE);
1234 }
1235 I915_STATE_WARN(cur_state != state,
1236 "FDI TX state assertion failure (expected %s, current %s)\n",
1237 state_string(state), state_string(cur_state));
1238 }
1239 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1240 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1241
1242 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 u32 val;
1246 bool cur_state;
1247
1248 val = I915_READ(FDI_RX_CTL(pipe));
1249 cur_state = !!(val & FDI_RX_ENABLE);
1250 I915_STATE_WARN(cur_state != state,
1251 "FDI RX state assertion failure (expected %s, current %s)\n",
1252 state_string(state), state_string(cur_state));
1253 }
1254 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1255 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1256
1257 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 u32 val;
1261
1262 /* ILK FDI PLL is always enabled */
1263 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1264 return;
1265
1266 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1267 if (HAS_DDI(dev_priv->dev))
1268 return;
1269
1270 val = I915_READ(FDI_TX_CTL(pipe));
1271 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1272 }
1273
1274 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276 {
1277 u32 val;
1278 bool cur_state;
1279
1280 val = I915_READ(FDI_RX_CTL(pipe));
1281 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1282 I915_STATE_WARN(cur_state != state,
1283 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1284 state_string(state), state_string(cur_state));
1285 }
1286
1287 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289 {
1290 struct drm_device *dev = dev_priv->dev;
1291 i915_reg_t pp_reg;
1292 u32 val;
1293 enum pipe panel_pipe = PIPE_A;
1294 bool locked = true;
1295
1296 if (WARN_ON(HAS_DDI(dev)))
1297 return;
1298
1299 if (HAS_PCH_SPLIT(dev)) {
1300 u32 port_sel;
1301
1302 pp_reg = PCH_PP_CONTROL;
1303 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1304
1305 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1306 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1307 panel_pipe = PIPE_B;
1308 /* XXX: else fix for eDP */
1309 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1310 /* presumably write lock depends on pipe, not port select */
1311 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1312 panel_pipe = pipe;
1313 } else {
1314 pp_reg = PP_CONTROL;
1315 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1316 panel_pipe = PIPE_B;
1317 }
1318
1319 val = I915_READ(pp_reg);
1320 if (!(val & PANEL_POWER_ON) ||
1321 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1322 locked = false;
1323
1324 I915_STATE_WARN(panel_pipe == pipe && locked,
1325 "panel assertion failure, pipe %c regs locked\n",
1326 pipe_name(pipe));
1327 }
1328
1329 static void assert_cursor(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, bool state)
1331 {
1332 struct drm_device *dev = dev_priv->dev;
1333 bool cur_state;
1334
1335 if (IS_845G(dev) || IS_I865G(dev))
1336 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1337 else
1338 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1345 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1346
1347 void assert_pipe(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, bool state)
1349 {
1350 bool cur_state;
1351 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1352 pipe);
1353
1354 /* if we need the pipe quirk it must be always on */
1355 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1356 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1357 state = true;
1358
1359 if (!intel_display_power_is_enabled(dev_priv,
1360 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1361 cur_state = false;
1362 } else {
1363 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1364 cur_state = !!(val & PIPECONF_ENABLE);
1365 }
1366
1367 I915_STATE_WARN(cur_state != state,
1368 "pipe %c assertion failure (expected %s, current %s)\n",
1369 pipe_name(pipe), state_string(state), state_string(cur_state));
1370 }
1371
1372 static void assert_plane(struct drm_i915_private *dev_priv,
1373 enum plane plane, bool state)
1374 {
1375 u32 val;
1376 bool cur_state;
1377
1378 val = I915_READ(DSPCNTR(plane));
1379 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1380 I915_STATE_WARN(cur_state != state,
1381 "plane %c assertion failure (expected %s, current %s)\n",
1382 plane_name(plane), state_string(state), state_string(cur_state));
1383 }
1384
1385 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1386 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1387
1388 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1389 enum pipe pipe)
1390 {
1391 struct drm_device *dev = dev_priv->dev;
1392 int i;
1393
1394 /* Primary planes are fixed to pipes on gen4+ */
1395 if (INTEL_INFO(dev)->gen >= 4) {
1396 u32 val = I915_READ(DSPCNTR(pipe));
1397 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1398 "plane %c assertion failure, should be disabled but not\n",
1399 plane_name(pipe));
1400 return;
1401 }
1402
1403 /* Need to check both planes against the pipe */
1404 for_each_pipe(dev_priv, i) {
1405 u32 val = I915_READ(DSPCNTR(i));
1406 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1407 DISPPLANE_SEL_PIPE_SHIFT;
1408 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1409 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1410 plane_name(i), pipe_name(pipe));
1411 }
1412 }
1413
1414 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1415 enum pipe pipe)
1416 {
1417 struct drm_device *dev = dev_priv->dev;
1418 int sprite;
1419
1420 if (INTEL_INFO(dev)->gen >= 9) {
1421 for_each_sprite(dev_priv, pipe, sprite) {
1422 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1423 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1424 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1425 sprite, pipe_name(pipe));
1426 }
1427 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1428 for_each_sprite(dev_priv, pipe, sprite) {
1429 u32 val = I915_READ(SPCNTR(pipe, sprite));
1430 I915_STATE_WARN(val & SP_ENABLE,
1431 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1432 sprite_name(pipe, sprite), pipe_name(pipe));
1433 }
1434 } else if (INTEL_INFO(dev)->gen >= 7) {
1435 u32 val = I915_READ(SPRCTL(pipe));
1436 I915_STATE_WARN(val & SPRITE_ENABLE,
1437 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1438 plane_name(pipe), pipe_name(pipe));
1439 } else if (INTEL_INFO(dev)->gen >= 5) {
1440 u32 val = I915_READ(DVSCNTR(pipe));
1441 I915_STATE_WARN(val & DVS_ENABLE,
1442 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1443 plane_name(pipe), pipe_name(pipe));
1444 }
1445 }
1446
1447 static void assert_vblank_disabled(struct drm_crtc *crtc)
1448 {
1449 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1450 drm_crtc_vblank_put(crtc);
1451 }
1452
1453 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1454 {
1455 u32 val;
1456 bool enabled;
1457
1458 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1459
1460 val = I915_READ(PCH_DREF_CONTROL);
1461 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1462 DREF_SUPERSPREAD_SOURCE_MASK));
1463 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1464 }
1465
1466 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 u32 val;
1470 bool enabled;
1471
1472 val = I915_READ(PCH_TRANSCONF(pipe));
1473 enabled = !!(val & TRANS_ENABLE);
1474 I915_STATE_WARN(enabled,
1475 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1476 pipe_name(pipe));
1477 }
1478
1479 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 port_sel, u32 val)
1481 {
1482 if ((val & DP_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1487 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1488 return false;
1489 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1490 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1491 return false;
1492 } else {
1493 if ((val & DP_PIPE_MASK) != (pipe << 30))
1494 return false;
1495 }
1496 return true;
1497 }
1498
1499 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1500 enum pipe pipe, u32 val)
1501 {
1502 if ((val & SDVO_ENABLE) == 0)
1503 return false;
1504
1505 if (HAS_PCH_CPT(dev_priv->dev)) {
1506 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1507 return false;
1508 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1509 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1510 return false;
1511 } else {
1512 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1513 return false;
1514 }
1515 return true;
1516 }
1517
1518 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1519 enum pipe pipe, u32 val)
1520 {
1521 if ((val & LVDS_PORT_EN) == 0)
1522 return false;
1523
1524 if (HAS_PCH_CPT(dev_priv->dev)) {
1525 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 return false;
1527 } else {
1528 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1529 return false;
1530 }
1531 return true;
1532 }
1533
1534 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1535 enum pipe pipe, u32 val)
1536 {
1537 if ((val & ADPA_DAC_ENABLE) == 0)
1538 return false;
1539 if (HAS_PCH_CPT(dev_priv->dev)) {
1540 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1541 return false;
1542 } else {
1543 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1544 return false;
1545 }
1546 return true;
1547 }
1548
1549 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1550 enum pipe pipe, i915_reg_t reg,
1551 u32 port_sel)
1552 {
1553 u32 val = I915_READ(reg);
1554 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1555 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1556 i915_mmio_reg_offset(reg), pipe_name(pipe));
1557
1558 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1559 && (val & DP_PIPEB_SELECT),
1560 "IBX PCH dp port still using transcoder B\n");
1561 }
1562
1563 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1564 enum pipe pipe, i915_reg_t reg)
1565 {
1566 u32 val = I915_READ(reg);
1567 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1568 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1569 i915_mmio_reg_offset(reg), pipe_name(pipe));
1570
1571 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1572 && (val & SDVO_PIPE_B_SELECT),
1573 "IBX PCH hdmi port still using transcoder B\n");
1574 }
1575
1576 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1577 enum pipe pipe)
1578 {
1579 u32 val;
1580
1581 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1582 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1583 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1584
1585 val = I915_READ(PCH_ADPA);
1586 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1587 "PCH VGA enabled on transcoder %c, should be disabled\n",
1588 pipe_name(pipe));
1589
1590 val = I915_READ(PCH_LVDS);
1591 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1592 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1593 pipe_name(pipe));
1594
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1596 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1597 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1598 }
1599
1600 static void vlv_enable_pll(struct intel_crtc *crtc,
1601 const struct intel_crtc_state *pipe_config)
1602 {
1603 struct drm_device *dev = crtc->base.dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 i915_reg_t reg = DPLL(crtc->pipe);
1606 u32 dpll = pipe_config->dpll_hw_state.dpll;
1607
1608 assert_pipe_disabled(dev_priv, crtc->pipe);
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 mutex_lock(&dev_priv->sb_lock);
1648
1649 /* Enable back the 10bit clock to display controller */
1650 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1651 tmp |= DPIO_DCLKP_EN;
1652 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1653
1654 mutex_unlock(&dev_priv->sb_lock);
1655
1656 /*
1657 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1658 */
1659 udelay(1);
1660
1661 /* Enable PLL */
1662 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1663
1664 /* Check PLL is locked */
1665 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1666 DRM_ERROR("PLL %d failed to lock\n", pipe);
1667
1668 /* not sure when this should be written */
1669 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1670 POSTING_READ(DPLL_MD(pipe));
1671 }
1672
1673 static int intel_num_dvo_pipes(struct drm_device *dev)
1674 {
1675 struct intel_crtc *crtc;
1676 int count = 0;
1677
1678 for_each_intel_crtc(dev, crtc)
1679 count += crtc->base.state->active &&
1680 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1681
1682 return count;
1683 }
1684
1685 static void i9xx_enable_pll(struct intel_crtc *crtc)
1686 {
1687 struct drm_device *dev = crtc->base.dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 i915_reg_t reg = DPLL(crtc->pipe);
1690 u32 dpll = crtc->config->dpll_hw_state.dpll;
1691
1692 assert_pipe_disabled(dev_priv, crtc->pipe);
1693
1694 /* No really, not for ILK+ */
1695 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1696
1697 /* PLL is protected by panel, make sure we can write it */
1698 if (IS_MOBILE(dev) && !IS_I830(dev))
1699 assert_panel_unlocked(dev_priv, crtc->pipe);
1700
1701 /* Enable DVO 2x clock on both PLLs if necessary */
1702 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1703 /*
1704 * It appears to be important that we don't enable this
1705 * for the current pipe before otherwise configuring the
1706 * PLL. No idea how this should be handled if multiple
1707 * DVO outputs are enabled simultaneosly.
1708 */
1709 dpll |= DPLL_DVO_2X_MODE;
1710 I915_WRITE(DPLL(!crtc->pipe),
1711 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1712 }
1713
1714 /*
1715 * Apparently we need to have VGA mode enabled prior to changing
1716 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1717 * dividers, even though the register value does change.
1718 */
1719 I915_WRITE(reg, 0);
1720
1721 I915_WRITE(reg, dpll);
1722
1723 /* Wait for the clocks to stabilize. */
1724 POSTING_READ(reg);
1725 udelay(150);
1726
1727 if (INTEL_INFO(dev)->gen >= 4) {
1728 I915_WRITE(DPLL_MD(crtc->pipe),
1729 crtc->config->dpll_hw_state.dpll_md);
1730 } else {
1731 /* The pixel multiplier can only be updated once the
1732 * DPLL is enabled and the clocks are stable.
1733 *
1734 * So write it again.
1735 */
1736 I915_WRITE(reg, dpll);
1737 }
1738
1739 /* We do this three times for luck */
1740 I915_WRITE(reg, dpll);
1741 POSTING_READ(reg);
1742 udelay(150); /* wait for warmup */
1743 I915_WRITE(reg, dpll);
1744 POSTING_READ(reg);
1745 udelay(150); /* wait for warmup */
1746 I915_WRITE(reg, dpll);
1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
1749 }
1750
1751 /**
1752 * i9xx_disable_pll - disable a PLL
1753 * @dev_priv: i915 private structure
1754 * @pipe: pipe PLL to disable
1755 *
1756 * Disable the PLL for @pipe, making sure the pipe is off first.
1757 *
1758 * Note! This is for pre-ILK only.
1759 */
1760 static void i9xx_disable_pll(struct intel_crtc *crtc)
1761 {
1762 struct drm_device *dev = crtc->base.dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 enum pipe pipe = crtc->pipe;
1765
1766 /* Disable DVO 2x clock on both PLLs if necessary */
1767 if (IS_I830(dev) &&
1768 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1769 !intel_num_dvo_pipes(dev)) {
1770 I915_WRITE(DPLL(PIPE_B),
1771 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1772 I915_WRITE(DPLL(PIPE_A),
1773 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1774 }
1775
1776 /* Don't disable pipe or pipe PLLs if needed */
1777 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1778 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1779 return;
1780
1781 /* Make sure the pipe isn't still relying on us */
1782 assert_pipe_disabled(dev_priv, pipe);
1783
1784 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1785 POSTING_READ(DPLL(pipe));
1786 }
1787
1788 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1789 {
1790 u32 val;
1791
1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
1794
1795 /*
1796 * Leave integrated clock source and reference clock enabled for pipe B.
1797 * The latter is needed for VGA hotplug / manual detection.
1798 */
1799 val = DPLL_VGA_MODE_DIS;
1800 if (pipe == PIPE_B)
1801 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1802 I915_WRITE(DPLL(pipe), val);
1803 POSTING_READ(DPLL(pipe));
1804
1805 }
1806
1807 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1808 {
1809 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1810 u32 val;
1811
1812 /* Make sure the pipe isn't still relying on us */
1813 assert_pipe_disabled(dev_priv, pipe);
1814
1815 /* Set PLL en = 0 */
1816 val = DPLL_SSC_REF_CLK_CHV |
1817 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1818 if (pipe != PIPE_A)
1819 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1820 I915_WRITE(DPLL(pipe), val);
1821 POSTING_READ(DPLL(pipe));
1822
1823 mutex_lock(&dev_priv->sb_lock);
1824
1825 /* Disable 10bit clock to display controller */
1826 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1827 val &= ~DPIO_DCLKP_EN;
1828 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1829
1830 mutex_unlock(&dev_priv->sb_lock);
1831 }
1832
1833 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1834 struct intel_digital_port *dport,
1835 unsigned int expected_mask)
1836 {
1837 u32 port_mask;
1838 i915_reg_t dpll_reg;
1839
1840 switch (dport->port) {
1841 case PORT_B:
1842 port_mask = DPLL_PORTB_READY_MASK;
1843 dpll_reg = DPLL(0);
1844 break;
1845 case PORT_C:
1846 port_mask = DPLL_PORTC_READY_MASK;
1847 dpll_reg = DPLL(0);
1848 expected_mask <<= 4;
1849 break;
1850 case PORT_D:
1851 port_mask = DPLL_PORTD_READY_MASK;
1852 dpll_reg = DPIO_PHY_STATUS;
1853 break;
1854 default:
1855 BUG();
1856 }
1857
1858 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1859 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1860 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1861 }
1862
1863 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1864 {
1865 struct drm_device *dev = crtc->base.dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1868
1869 if (WARN_ON(pll == NULL))
1870 return;
1871
1872 WARN_ON(!pll->config.crtc_mask);
1873 if (pll->active == 0) {
1874 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1875 WARN_ON(pll->on);
1876 assert_shared_dpll_disabled(dev_priv, pll);
1877
1878 pll->mode_set(dev_priv, pll);
1879 }
1880 }
1881
1882 /**
1883 * intel_enable_shared_dpll - enable PCH PLL
1884 * @dev_priv: i915 private structure
1885 * @pipe: pipe PLL to enable
1886 *
1887 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1888 * drives the transcoder clock.
1889 */
1890 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1891 {
1892 struct drm_device *dev = crtc->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1895
1896 if (WARN_ON(pll == NULL))
1897 return;
1898
1899 if (WARN_ON(pll->config.crtc_mask == 0))
1900 return;
1901
1902 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1903 pll->name, pll->active, pll->on,
1904 crtc->base.base.id);
1905
1906 if (pll->active++) {
1907 WARN_ON(!pll->on);
1908 assert_shared_dpll_enabled(dev_priv, pll);
1909 return;
1910 }
1911 WARN_ON(pll->on);
1912
1913 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1914
1915 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1916 pll->enable(dev_priv, pll);
1917 pll->on = true;
1918 }
1919
1920 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1921 {
1922 struct drm_device *dev = crtc->base.dev;
1923 struct drm_i915_private *dev_priv = dev->dev_private;
1924 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1925
1926 /* PCH only available on ILK+ */
1927 if (INTEL_INFO(dev)->gen < 5)
1928 return;
1929
1930 if (pll == NULL)
1931 return;
1932
1933 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1934 return;
1935
1936 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937 pll->name, pll->active, pll->on,
1938 crtc->base.base.id);
1939
1940 if (WARN_ON(pll->active == 0)) {
1941 assert_shared_dpll_disabled(dev_priv, pll);
1942 return;
1943 }
1944
1945 assert_shared_dpll_enabled(dev_priv, pll);
1946 WARN_ON(!pll->on);
1947 if (--pll->active)
1948 return;
1949
1950 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1951 pll->disable(dev_priv, pll);
1952 pll->on = false;
1953
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1955 }
1956
1957 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 enum pipe pipe)
1959 {
1960 struct drm_device *dev = dev_priv->dev;
1961 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1963 i915_reg_t reg;
1964 uint32_t val, pipeconf_val;
1965
1966 /* PCH only available on ILK+ */
1967 BUG_ON(!HAS_PCH_SPLIT(dev));
1968
1969 /* Make sure PCH DPLL is enabled */
1970 assert_shared_dpll_enabled(dev_priv,
1971 intel_crtc_to_shared_dpll(intel_crtc));
1972
1973 /* FDI must be feeding us bits for PCH ports */
1974 assert_fdi_tx_enabled(dev_priv, pipe);
1975 assert_fdi_rx_enabled(dev_priv, pipe);
1976
1977 if (HAS_PCH_CPT(dev)) {
1978 /* Workaround: Set the timing override bit before enabling the
1979 * pch transcoder. */
1980 reg = TRANS_CHICKEN2(pipe);
1981 val = I915_READ(reg);
1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(reg, val);
1984 }
1985
1986 reg = PCH_TRANSCONF(pipe);
1987 val = I915_READ(reg);
1988 pipeconf_val = I915_READ(PIPECONF(pipe));
1989
1990 if (HAS_PCH_IBX(dev_priv->dev)) {
1991 /*
1992 * Make the BPC in transcoder be consistent with
1993 * that in pipeconf reg. For HDMI we must use 8bpc
1994 * here for both 8bpc and 12bpc.
1995 */
1996 val &= ~PIPECONF_BPC_MASK;
1997 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1998 val |= PIPECONF_8BPC;
1999 else
2000 val |= pipeconf_val & PIPECONF_BPC_MASK;
2001 }
2002
2003 val &= ~TRANS_INTERLACE_MASK;
2004 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2005 if (HAS_PCH_IBX(dev_priv->dev) &&
2006 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2007 val |= TRANS_LEGACY_INTERLACED_ILK;
2008 else
2009 val |= TRANS_INTERLACED;
2010 else
2011 val |= TRANS_PROGRESSIVE;
2012
2013 I915_WRITE(reg, val | TRANS_ENABLE);
2014 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2015 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2016 }
2017
2018 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2019 enum transcoder cpu_transcoder)
2020 {
2021 u32 val, pipeconf_val;
2022
2023 /* PCH only available on ILK+ */
2024 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2025
2026 /* FDI must be feeding us bits for PCH ports */
2027 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2028 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2029
2030 /* Workaround: set timing override bit. */
2031 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2032 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2033 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2034
2035 val = TRANS_ENABLE;
2036 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2037
2038 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2039 PIPECONF_INTERLACED_ILK)
2040 val |= TRANS_INTERLACED;
2041 else
2042 val |= TRANS_PROGRESSIVE;
2043
2044 I915_WRITE(LPT_TRANSCONF, val);
2045 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2046 DRM_ERROR("Failed to enable PCH transcoder\n");
2047 }
2048
2049 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2050 enum pipe pipe)
2051 {
2052 struct drm_device *dev = dev_priv->dev;
2053 i915_reg_t reg;
2054 uint32_t val;
2055
2056 /* FDI relies on the transcoder */
2057 assert_fdi_tx_disabled(dev_priv, pipe);
2058 assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060 /* Ports must be off as well */
2061 assert_pch_ports_disabled(dev_priv, pipe);
2062
2063 reg = PCH_TRANSCONF(pipe);
2064 val = I915_READ(reg);
2065 val &= ~TRANS_ENABLE;
2066 I915_WRITE(reg, val);
2067 /* wait for PCH transcoder off, transcoder state */
2068 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071 if (HAS_PCH_CPT(dev)) {
2072 /* Workaround: Clear the timing override chicken bit again. */
2073 reg = TRANS_CHICKEN2(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076 I915_WRITE(reg, val);
2077 }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082 u32 val;
2083
2084 val = I915_READ(LPT_TRANSCONF);
2085 val &= ~TRANS_ENABLE;
2086 I915_WRITE(LPT_TRANSCONF, val);
2087 /* wait for PCH transcoder off, transcoder state */
2088 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091 /* Workaround: clear timing override bit. */
2092 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098 * intel_enable_pipe - enable a pipe, asserting requirements
2099 * @crtc: crtc responsible for the pipe
2100 *
2101 * Enable @crtc's pipe, making sure that various hardware specific requirements
2102 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103 */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106 struct drm_device *dev = crtc->base.dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 enum pipe pipe = crtc->pipe;
2109 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2110 enum pipe pch_transcoder;
2111 i915_reg_t reg;
2112 u32 val;
2113
2114 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2115
2116 assert_planes_disabled(dev_priv, pipe);
2117 assert_cursor_disabled(dev_priv, pipe);
2118 assert_sprites_disabled(dev_priv, pipe);
2119
2120 if (HAS_PCH_LPT(dev_priv->dev))
2121 pch_transcoder = TRANSCODER_A;
2122 else
2123 pch_transcoder = pipe;
2124
2125 /*
2126 * A pipe without a PLL won't actually be able to drive bits from
2127 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2128 * need the check.
2129 */
2130 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2131 if (crtc->config->has_dsi_encoder)
2132 assert_dsi_pll_enabled(dev_priv);
2133 else
2134 assert_pll_enabled(dev_priv, pipe);
2135 else {
2136 if (crtc->config->has_pch_encoder) {
2137 /* if driving the PCH, we need FDI enabled */
2138 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2139 assert_fdi_tx_pll_enabled(dev_priv,
2140 (enum pipe) cpu_transcoder);
2141 }
2142 /* FIXME: assert CPU port conditions for SNB+ */
2143 }
2144
2145 reg = PIPECONF(cpu_transcoder);
2146 val = I915_READ(reg);
2147 if (val & PIPECONF_ENABLE) {
2148 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2149 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2150 return;
2151 }
2152
2153 I915_WRITE(reg, val | PIPECONF_ENABLE);
2154 POSTING_READ(reg);
2155 }
2156
2157 /**
2158 * intel_disable_pipe - disable a pipe, asserting requirements
2159 * @crtc: crtc whose pipes is to be disabled
2160 *
2161 * Disable the pipe of @crtc, making sure that various hardware
2162 * specific requirements are met, if applicable, e.g. plane
2163 * disabled, panel fitter off, etc.
2164 *
2165 * Will wait until the pipe has shut down before returning.
2166 */
2167 static void intel_disable_pipe(struct intel_crtc *crtc)
2168 {
2169 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2170 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2171 enum pipe pipe = crtc->pipe;
2172 i915_reg_t reg;
2173 u32 val;
2174
2175 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2176
2177 /*
2178 * Make sure planes won't keep trying to pump pixels to us,
2179 * or we might hang the display.
2180 */
2181 assert_planes_disabled(dev_priv, pipe);
2182 assert_cursor_disabled(dev_priv, pipe);
2183 assert_sprites_disabled(dev_priv, pipe);
2184
2185 reg = PIPECONF(cpu_transcoder);
2186 val = I915_READ(reg);
2187 if ((val & PIPECONF_ENABLE) == 0)
2188 return;
2189
2190 /*
2191 * Double wide has implications for planes
2192 * so best keep it disabled when not needed.
2193 */
2194 if (crtc->config->double_wide)
2195 val &= ~PIPECONF_DOUBLE_WIDE;
2196
2197 /* Don't disable pipe or pipe PLLs if needed */
2198 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2199 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2200 val &= ~PIPECONF_ENABLE;
2201
2202 I915_WRITE(reg, val);
2203 if ((val & PIPECONF_ENABLE) == 0)
2204 intel_wait_for_pipe_off(crtc);
2205 }
2206
2207 static bool need_vtd_wa(struct drm_device *dev)
2208 {
2209 #ifdef CONFIG_INTEL_IOMMU
2210 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2211 return true;
2212 #endif
2213 return false;
2214 }
2215
2216 unsigned int
2217 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2218 uint64_t fb_format_modifier, unsigned int plane)
2219 {
2220 unsigned int tile_height;
2221 uint32_t pixel_bytes;
2222
2223 switch (fb_format_modifier) {
2224 case DRM_FORMAT_MOD_NONE:
2225 tile_height = 1;
2226 break;
2227 case I915_FORMAT_MOD_X_TILED:
2228 tile_height = IS_GEN2(dev) ? 16 : 8;
2229 break;
2230 case I915_FORMAT_MOD_Y_TILED:
2231 tile_height = 32;
2232 break;
2233 case I915_FORMAT_MOD_Yf_TILED:
2234 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2235 switch (pixel_bytes) {
2236 default:
2237 case 1:
2238 tile_height = 64;
2239 break;
2240 case 2:
2241 case 4:
2242 tile_height = 32;
2243 break;
2244 case 8:
2245 tile_height = 16;
2246 break;
2247 case 16:
2248 WARN_ONCE(1,
2249 "128-bit pixels are not supported for display!");
2250 tile_height = 16;
2251 break;
2252 }
2253 break;
2254 default:
2255 MISSING_CASE(fb_format_modifier);
2256 tile_height = 1;
2257 break;
2258 }
2259
2260 return tile_height;
2261 }
2262
2263 unsigned int
2264 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2265 uint32_t pixel_format, uint64_t fb_format_modifier)
2266 {
2267 return ALIGN(height, intel_tile_height(dev, pixel_format,
2268 fb_format_modifier, 0));
2269 }
2270
2271 static void
2272 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2273 const struct drm_plane_state *plane_state)
2274 {
2275 struct intel_rotation_info *info = &view->params.rotation_info;
2276 unsigned int tile_height, tile_pitch;
2277
2278 *view = i915_ggtt_view_normal;
2279
2280 if (!plane_state)
2281 return;
2282
2283 if (!intel_rotation_90_or_270(plane_state->rotation))
2284 return;
2285
2286 *view = i915_ggtt_view_rotated;
2287
2288 info->height = fb->height;
2289 info->pixel_format = fb->pixel_format;
2290 info->pitch = fb->pitches[0];
2291 info->uv_offset = fb->offsets[1];
2292 info->fb_modifier = fb->modifier[0];
2293
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 0);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2299 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2300
2301 if (info->pixel_format == DRM_FORMAT_NV12) {
2302 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2303 fb->modifier[0], 1);
2304 tile_pitch = PAGE_SIZE / tile_height;
2305 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2306 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2307 tile_height);
2308 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2309 PAGE_SIZE;
2310 }
2311 }
2312
2313 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2314 {
2315 if (INTEL_INFO(dev_priv)->gen >= 9)
2316 return 256 * 1024;
2317 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2318 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2319 return 128 * 1024;
2320 else if (INTEL_INFO(dev_priv)->gen >= 4)
2321 return 4 * 1024;
2322 else
2323 return 0;
2324 }
2325
2326 int
2327 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2328 struct drm_framebuffer *fb,
2329 const struct drm_plane_state *plane_state)
2330 {
2331 struct drm_device *dev = fb->dev;
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2334 struct i915_ggtt_view view;
2335 u32 alignment;
2336 int ret;
2337
2338 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339
2340 switch (fb->modifier[0]) {
2341 case DRM_FORMAT_MOD_NONE:
2342 alignment = intel_linear_alignment(dev_priv);
2343 break;
2344 case I915_FORMAT_MOD_X_TILED:
2345 if (INTEL_INFO(dev)->gen >= 9)
2346 alignment = 256 * 1024;
2347 else {
2348 /* pin() will align the object as required by fence */
2349 alignment = 0;
2350 }
2351 break;
2352 case I915_FORMAT_MOD_Y_TILED:
2353 case I915_FORMAT_MOD_Yf_TILED:
2354 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2355 "Y tiling bo slipped through, driver bug!\n"))
2356 return -EINVAL;
2357 alignment = 1 * 1024 * 1024;
2358 break;
2359 default:
2360 MISSING_CASE(fb->modifier[0]);
2361 return -EINVAL;
2362 }
2363
2364 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2365
2366 /* Note that the w/a also requires 64 PTE of padding following the
2367 * bo. We currently fill all unused PTE with the shadow page and so
2368 * we should always have valid PTE following the scanout preventing
2369 * the VT-d warning.
2370 */
2371 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2372 alignment = 256 * 1024;
2373
2374 /*
2375 * Global gtt pte registers are special registers which actually forward
2376 * writes to a chunk of system memory. Which means that there is no risk
2377 * that the register values disappear as soon as we call
2378 * intel_runtime_pm_put(), so it is correct to wrap only the
2379 * pin/unpin/fence and not more.
2380 */
2381 intel_runtime_pm_get(dev_priv);
2382
2383 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2384 &view);
2385 if (ret)
2386 goto err_pm;
2387
2388 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2389 * fence, whereas 965+ only requires a fence if using
2390 * framebuffer compression. For simplicity, we always install
2391 * a fence as the cost is not that onerous.
2392 */
2393 if (view.type == I915_GGTT_VIEW_NORMAL) {
2394 ret = i915_gem_object_get_fence(obj);
2395 if (ret == -EDEADLK) {
2396 /*
2397 * -EDEADLK means there are no free fences
2398 * no pending flips.
2399 *
2400 * This is propagated to atomic, but it uses
2401 * -EDEADLK to force a locking recovery, so
2402 * change the returned error to -EBUSY.
2403 */
2404 ret = -EBUSY;
2405 goto err_unpin;
2406 } else if (ret)
2407 goto err_unpin;
2408
2409 i915_gem_object_pin_fence(obj);
2410 }
2411
2412 intel_runtime_pm_put(dev_priv);
2413 return 0;
2414
2415 err_unpin:
2416 i915_gem_object_unpin_from_display_plane(obj, &view);
2417 err_pm:
2418 intel_runtime_pm_put(dev_priv);
2419 return ret;
2420 }
2421
2422 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2423 const struct drm_plane_state *plane_state)
2424 {
2425 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2426 struct i915_ggtt_view view;
2427
2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
2430 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431
2432 if (view.type == I915_GGTT_VIEW_NORMAL)
2433 i915_gem_object_unpin_fence(obj);
2434
2435 i915_gem_object_unpin_from_display_plane(obj, &view);
2436 }
2437
2438 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2439 * is assumed to be a power-of-two. */
2440 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2441 int *x, int *y,
2442 unsigned int tiling_mode,
2443 unsigned int cpp,
2444 unsigned int pitch)
2445 {
2446 if (tiling_mode != I915_TILING_NONE) {
2447 unsigned int tile_rows, tiles;
2448
2449 tile_rows = *y / 8;
2450 *y %= 8;
2451
2452 tiles = *x / (512/cpp);
2453 *x %= 512/cpp;
2454
2455 return tile_rows * pitch * 8 + tiles * 4096;
2456 } else {
2457 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2458 unsigned int offset;
2459
2460 offset = *y * pitch + *x * cpp;
2461 *y = (offset & alignment) / pitch;
2462 *x = ((offset & alignment) - *y * pitch) / cpp;
2463 return offset & ~alignment;
2464 }
2465 }
2466
2467 static int i9xx_format_to_fourcc(int format)
2468 {
2469 switch (format) {
2470 case DISPPLANE_8BPP:
2471 return DRM_FORMAT_C8;
2472 case DISPPLANE_BGRX555:
2473 return DRM_FORMAT_XRGB1555;
2474 case DISPPLANE_BGRX565:
2475 return DRM_FORMAT_RGB565;
2476 default:
2477 case DISPPLANE_BGRX888:
2478 return DRM_FORMAT_XRGB8888;
2479 case DISPPLANE_RGBX888:
2480 return DRM_FORMAT_XBGR8888;
2481 case DISPPLANE_BGRX101010:
2482 return DRM_FORMAT_XRGB2101010;
2483 case DISPPLANE_RGBX101010:
2484 return DRM_FORMAT_XBGR2101010;
2485 }
2486 }
2487
2488 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2489 {
2490 switch (format) {
2491 case PLANE_CTL_FORMAT_RGB_565:
2492 return DRM_FORMAT_RGB565;
2493 default:
2494 case PLANE_CTL_FORMAT_XRGB_8888:
2495 if (rgb_order) {
2496 if (alpha)
2497 return DRM_FORMAT_ABGR8888;
2498 else
2499 return DRM_FORMAT_XBGR8888;
2500 } else {
2501 if (alpha)
2502 return DRM_FORMAT_ARGB8888;
2503 else
2504 return DRM_FORMAT_XRGB8888;
2505 }
2506 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 if (rgb_order)
2508 return DRM_FORMAT_XBGR2101010;
2509 else
2510 return DRM_FORMAT_XRGB2101010;
2511 }
2512 }
2513
2514 static bool
2515 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2516 struct intel_initial_plane_config *plane_config)
2517 {
2518 struct drm_device *dev = crtc->base.dev;
2519 struct drm_i915_private *dev_priv = to_i915(dev);
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2522 struct drm_framebuffer *fb = &plane_config->fb->base;
2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
2528
2529 if (plane_config->size == 0)
2530 return false;
2531
2532 /* If the FB is too big, just don't use it since fbdev is not very
2533 * important and we should probably use that space with FBC or other
2534 * features. */
2535 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2536 return false;
2537
2538 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2539 base_aligned,
2540 base_aligned,
2541 size_aligned);
2542 if (!obj)
2543 return false;
2544
2545 obj->tiling_mode = plane_config->tiling;
2546 if (obj->tiling_mode == I915_TILING_X)
2547 obj->stride = fb->pitches[0];
2548
2549 mode_cmd.pixel_format = fb->pixel_format;
2550 mode_cmd.width = fb->width;
2551 mode_cmd.height = fb->height;
2552 mode_cmd.pitches[0] = fb->pitches[0];
2553 mode_cmd.modifier[0] = fb->modifier[0];
2554 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2555
2556 mutex_lock(&dev->struct_mutex);
2557 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2558 &mode_cmd, obj)) {
2559 DRM_DEBUG_KMS("intel fb init failed\n");
2560 goto out_unref_obj;
2561 }
2562 mutex_unlock(&dev->struct_mutex);
2563
2564 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2565 return true;
2566
2567 out_unref_obj:
2568 drm_gem_object_unreference(&obj->base);
2569 mutex_unlock(&dev->struct_mutex);
2570 return false;
2571 }
2572
2573 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2574 static void
2575 update_state_fb(struct drm_plane *plane)
2576 {
2577 if (plane->fb == plane->state->fb)
2578 return;
2579
2580 if (plane->state->fb)
2581 drm_framebuffer_unreference(plane->state->fb);
2582 plane->state->fb = plane->fb;
2583 if (plane->state->fb)
2584 drm_framebuffer_reference(plane->state->fb);
2585 }
2586
2587 static void
2588 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2589 struct intel_initial_plane_config *plane_config)
2590 {
2591 struct drm_device *dev = intel_crtc->base.dev;
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct drm_crtc *c;
2594 struct intel_crtc *i;
2595 struct drm_i915_gem_object *obj;
2596 struct drm_plane *primary = intel_crtc->base.primary;
2597 struct drm_plane_state *plane_state = primary->state;
2598 struct drm_framebuffer *fb;
2599
2600 if (!plane_config->fb)
2601 return;
2602
2603 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2604 fb = &plane_config->fb->base;
2605 goto valid_fb;
2606 }
2607
2608 kfree(plane_config->fb);
2609
2610 /*
2611 * Failed to alloc the obj, check to see if we should share
2612 * an fb with another CRTC instead
2613 */
2614 for_each_crtc(dev, c) {
2615 i = to_intel_crtc(c);
2616
2617 if (c == &intel_crtc->base)
2618 continue;
2619
2620 if (!i->active)
2621 continue;
2622
2623 fb = c->primary->fb;
2624 if (!fb)
2625 continue;
2626
2627 obj = intel_fb_obj(fb);
2628 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2629 drm_framebuffer_reference(fb);
2630 goto valid_fb;
2631 }
2632 }
2633
2634 return;
2635
2636 valid_fb:
2637 plane_state->src_x = 0;
2638 plane_state->src_y = 0;
2639 plane_state->src_w = fb->width << 16;
2640 plane_state->src_h = fb->height << 16;
2641
2642 plane_state->crtc_x = 0;
2643 plane_state->crtc_y = 0;
2644 plane_state->crtc_w = fb->width;
2645 plane_state->crtc_h = fb->height;
2646
2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2650
2651 drm_framebuffer_reference(fb);
2652 primary->fb = primary->state->fb = fb;
2653 primary->crtc = primary->state->crtc = &intel_crtc->base;
2654 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2660 int x, int y)
2661 {
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2665 struct drm_plane *primary = crtc->primary;
2666 bool visible = to_intel_plane_state(primary->state)->visible;
2667 struct drm_i915_gem_object *obj;
2668 int plane = intel_crtc->plane;
2669 unsigned long linear_offset;
2670 u32 dspcntr;
2671 i915_reg_t reg = DSPCNTR(plane);
2672 int pixel_size;
2673
2674 if (!visible || !fb) {
2675 I915_WRITE(reg, 0);
2676 if (INTEL_INFO(dev)->gen >= 4)
2677 I915_WRITE(DSPSURF(plane), 0);
2678 else
2679 I915_WRITE(DSPADDR(plane), 0);
2680 POSTING_READ(reg);
2681 return;
2682 }
2683
2684 obj = intel_fb_obj(fb);
2685 if (WARN_ON(obj == NULL))
2686 return;
2687
2688 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2689
2690 dspcntr = DISPPLANE_GAMMA_ENABLE;
2691
2692 dspcntr |= DISPLAY_PLANE_ENABLE;
2693
2694 if (INTEL_INFO(dev)->gen < 4) {
2695 if (intel_crtc->pipe == PIPE_B)
2696 dspcntr |= DISPPLANE_SEL_PIPE_B;
2697
2698 /* pipesrc and dspsize control the size that is scaled from,
2699 * which should always be the user's requested size.
2700 */
2701 I915_WRITE(DSPSIZE(plane),
2702 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2703 (intel_crtc->config->pipe_src_w - 1));
2704 I915_WRITE(DSPPOS(plane), 0);
2705 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2706 I915_WRITE(PRIMSIZE(plane),
2707 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708 (intel_crtc->config->pipe_src_w - 1));
2709 I915_WRITE(PRIMPOS(plane), 0);
2710 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2711 }
2712
2713 switch (fb->pixel_format) {
2714 case DRM_FORMAT_C8:
2715 dspcntr |= DISPPLANE_8BPP;
2716 break;
2717 case DRM_FORMAT_XRGB1555:
2718 dspcntr |= DISPPLANE_BGRX555;
2719 break;
2720 case DRM_FORMAT_RGB565:
2721 dspcntr |= DISPPLANE_BGRX565;
2722 break;
2723 case DRM_FORMAT_XRGB8888:
2724 dspcntr |= DISPPLANE_BGRX888;
2725 break;
2726 case DRM_FORMAT_XBGR8888:
2727 dspcntr |= DISPPLANE_RGBX888;
2728 break;
2729 case DRM_FORMAT_XRGB2101010:
2730 dspcntr |= DISPPLANE_BGRX101010;
2731 break;
2732 case DRM_FORMAT_XBGR2101010:
2733 dspcntr |= DISPPLANE_RGBX101010;
2734 break;
2735 default:
2736 BUG();
2737 }
2738
2739 if (INTEL_INFO(dev)->gen >= 4 &&
2740 obj->tiling_mode != I915_TILING_NONE)
2741 dspcntr |= DISPPLANE_TILED;
2742
2743 if (IS_G4X(dev))
2744 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2745
2746 linear_offset = y * fb->pitches[0] + x * pixel_size;
2747
2748 if (INTEL_INFO(dev)->gen >= 4) {
2749 intel_crtc->dspaddr_offset =
2750 intel_gen4_compute_page_offset(dev_priv,
2751 &x, &y, obj->tiling_mode,
2752 pixel_size,
2753 fb->pitches[0]);
2754 linear_offset -= intel_crtc->dspaddr_offset;
2755 } else {
2756 intel_crtc->dspaddr_offset = linear_offset;
2757 }
2758
2759 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2760 dspcntr |= DISPPLANE_ROTATE_180;
2761
2762 x += (intel_crtc->config->pipe_src_w - 1);
2763 y += (intel_crtc->config->pipe_src_h - 1);
2764
2765 /* Finding the last pixel of the last line of the display
2766 data and adding to linear_offset*/
2767 linear_offset +=
2768 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2769 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2770 }
2771
2772 intel_crtc->adjusted_x = x;
2773 intel_crtc->adjusted_y = y;
2774
2775 I915_WRITE(reg, dspcntr);
2776
2777 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2778 if (INTEL_INFO(dev)->gen >= 4) {
2779 I915_WRITE(DSPSURF(plane),
2780 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2781 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2782 I915_WRITE(DSPLINOFF(plane), linear_offset);
2783 } else
2784 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2785 POSTING_READ(reg);
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2789 struct drm_framebuffer *fb,
2790 int x, int y)
2791 {
2792 struct drm_device *dev = crtc->dev;
2793 struct drm_i915_private *dev_priv = dev->dev_private;
2794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795 struct drm_plane *primary = crtc->primary;
2796 bool visible = to_intel_plane_state(primary->state)->visible;
2797 struct drm_i915_gem_object *obj;
2798 int plane = intel_crtc->plane;
2799 unsigned long linear_offset;
2800 u32 dspcntr;
2801 i915_reg_t reg = DSPCNTR(plane);
2802 int pixel_size;
2803
2804 if (!visible || !fb) {
2805 I915_WRITE(reg, 0);
2806 I915_WRITE(DSPSURF(plane), 0);
2807 POSTING_READ(reg);
2808 return;
2809 }
2810
2811 obj = intel_fb_obj(fb);
2812 if (WARN_ON(obj == NULL))
2813 return;
2814
2815 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2816
2817 dspcntr = DISPPLANE_GAMMA_ENABLE;
2818
2819 dspcntr |= DISPLAY_PLANE_ENABLE;
2820
2821 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2822 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2823
2824 switch (fb->pixel_format) {
2825 case DRM_FORMAT_C8:
2826 dspcntr |= DISPPLANE_8BPP;
2827 break;
2828 case DRM_FORMAT_RGB565:
2829 dspcntr |= DISPPLANE_BGRX565;
2830 break;
2831 case DRM_FORMAT_XRGB8888:
2832 dspcntr |= DISPPLANE_BGRX888;
2833 break;
2834 case DRM_FORMAT_XBGR8888:
2835 dspcntr |= DISPPLANE_RGBX888;
2836 break;
2837 case DRM_FORMAT_XRGB2101010:
2838 dspcntr |= DISPPLANE_BGRX101010;
2839 break;
2840 case DRM_FORMAT_XBGR2101010:
2841 dspcntr |= DISPPLANE_RGBX101010;
2842 break;
2843 default:
2844 BUG();
2845 }
2846
2847 if (obj->tiling_mode != I915_TILING_NONE)
2848 dspcntr |= DISPPLANE_TILED;
2849
2850 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2851 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2852
2853 linear_offset = y * fb->pitches[0] + x * pixel_size;
2854 intel_crtc->dspaddr_offset =
2855 intel_gen4_compute_page_offset(dev_priv,
2856 &x, &y, obj->tiling_mode,
2857 pixel_size,
2858 fb->pitches[0]);
2859 linear_offset -= intel_crtc->dspaddr_offset;
2860 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2861 dspcntr |= DISPPLANE_ROTATE_180;
2862
2863 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2864 x += (intel_crtc->config->pipe_src_w - 1);
2865 y += (intel_crtc->config->pipe_src_h - 1);
2866
2867 /* Finding the last pixel of the last line of the display
2868 data and adding to linear_offset*/
2869 linear_offset +=
2870 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2871 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2872 }
2873 }
2874
2875 intel_crtc->adjusted_x = x;
2876 intel_crtc->adjusted_y = y;
2877
2878 I915_WRITE(reg, dspcntr);
2879
2880 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2881 I915_WRITE(DSPSURF(plane),
2882 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2883 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2884 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2885 } else {
2886 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2887 I915_WRITE(DSPLINOFF(plane), linear_offset);
2888 }
2889 POSTING_READ(reg);
2890 }
2891
2892 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2893 uint32_t pixel_format)
2894 {
2895 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2896
2897 /*
2898 * The stride is either expressed as a multiple of 64 bytes
2899 * chunks for linear buffers or in number of tiles for tiled
2900 * buffers.
2901 */
2902 switch (fb_modifier) {
2903 case DRM_FORMAT_MOD_NONE:
2904 return 64;
2905 case I915_FORMAT_MOD_X_TILED:
2906 if (INTEL_INFO(dev)->gen == 2)
2907 return 128;
2908 return 512;
2909 case I915_FORMAT_MOD_Y_TILED:
2910 /* No need to check for old gens and Y tiling since this is
2911 * about the display engine and those will be blocked before
2912 * we get here.
2913 */
2914 return 128;
2915 case I915_FORMAT_MOD_Yf_TILED:
2916 if (bits_per_pixel == 8)
2917 return 64;
2918 else
2919 return 128;
2920 default:
2921 MISSING_CASE(fb_modifier);
2922 return 64;
2923 }
2924 }
2925
2926 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2927 struct drm_i915_gem_object *obj,
2928 unsigned int plane)
2929 {
2930 struct i915_ggtt_view view;
2931 struct i915_vma *vma;
2932 u64 offset;
2933
2934 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2935 intel_plane->base.state);
2936
2937 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2938 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2939 view.type))
2940 return -1;
2941
2942 offset = vma->node.start;
2943
2944 if (plane == 1) {
2945 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2946 PAGE_SIZE;
2947 }
2948
2949 WARN_ON(upper_32_bits(offset));
2950
2951 return lower_32_bits(offset);
2952 }
2953
2954 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2955 {
2956 struct drm_device *dev = intel_crtc->base.dev;
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2958
2959 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2960 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2961 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2962 }
2963
2964 /*
2965 * This function detaches (aka. unbinds) unused scalers in hardware
2966 */
2967 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2968 {
2969 struct intel_crtc_scaler_state *scaler_state;
2970 int i;
2971
2972 scaler_state = &intel_crtc->config->scaler_state;
2973
2974 /* loop through and disable scalers that aren't in use */
2975 for (i = 0; i < intel_crtc->num_scalers; i++) {
2976 if (!scaler_state->scalers[i].in_use)
2977 skl_detach_scaler(intel_crtc, i);
2978 }
2979 }
2980
2981 u32 skl_plane_ctl_format(uint32_t pixel_format)
2982 {
2983 switch (pixel_format) {
2984 case DRM_FORMAT_C8:
2985 return PLANE_CTL_FORMAT_INDEXED;
2986 case DRM_FORMAT_RGB565:
2987 return PLANE_CTL_FORMAT_RGB_565;
2988 case DRM_FORMAT_XBGR8888:
2989 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2990 case DRM_FORMAT_XRGB8888:
2991 return PLANE_CTL_FORMAT_XRGB_8888;
2992 /*
2993 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2994 * to be already pre-multiplied. We need to add a knob (or a different
2995 * DRM_FORMAT) for user-space to configure that.
2996 */
2997 case DRM_FORMAT_ABGR8888:
2998 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2999 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3000 case DRM_FORMAT_ARGB8888:
3001 return PLANE_CTL_FORMAT_XRGB_8888 |
3002 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3003 case DRM_FORMAT_XRGB2101010:
3004 return PLANE_CTL_FORMAT_XRGB_2101010;
3005 case DRM_FORMAT_XBGR2101010:
3006 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3007 case DRM_FORMAT_YUYV:
3008 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3009 case DRM_FORMAT_YVYU:
3010 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3011 case DRM_FORMAT_UYVY:
3012 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3013 case DRM_FORMAT_VYUY:
3014 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3015 default:
3016 MISSING_CASE(pixel_format);
3017 }
3018
3019 return 0;
3020 }
3021
3022 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3023 {
3024 switch (fb_modifier) {
3025 case DRM_FORMAT_MOD_NONE:
3026 break;
3027 case I915_FORMAT_MOD_X_TILED:
3028 return PLANE_CTL_TILED_X;
3029 case I915_FORMAT_MOD_Y_TILED:
3030 return PLANE_CTL_TILED_Y;
3031 case I915_FORMAT_MOD_Yf_TILED:
3032 return PLANE_CTL_TILED_YF;
3033 default:
3034 MISSING_CASE(fb_modifier);
3035 }
3036
3037 return 0;
3038 }
3039
3040 u32 skl_plane_ctl_rotation(unsigned int rotation)
3041 {
3042 switch (rotation) {
3043 case BIT(DRM_ROTATE_0):
3044 break;
3045 /*
3046 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3047 * while i915 HW rotation is clockwise, thats why this swapping.
3048 */
3049 case BIT(DRM_ROTATE_90):
3050 return PLANE_CTL_ROTATE_270;
3051 case BIT(DRM_ROTATE_180):
3052 return PLANE_CTL_ROTATE_180;
3053 case BIT(DRM_ROTATE_270):
3054 return PLANE_CTL_ROTATE_90;
3055 default:
3056 MISSING_CASE(rotation);
3057 }
3058
3059 return 0;
3060 }
3061
3062 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3063 struct drm_framebuffer *fb,
3064 int x, int y)
3065 {
3066 struct drm_device *dev = crtc->dev;
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3069 struct drm_plane *plane = crtc->primary;
3070 bool visible = to_intel_plane_state(plane->state)->visible;
3071 struct drm_i915_gem_object *obj;
3072 int pipe = intel_crtc->pipe;
3073 u32 plane_ctl, stride_div, stride;
3074 u32 tile_height, plane_offset, plane_size;
3075 unsigned int rotation;
3076 int x_offset, y_offset;
3077 u32 surf_addr;
3078 struct intel_crtc_state *crtc_state = intel_crtc->config;
3079 struct intel_plane_state *plane_state;
3080 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3081 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3082 int scaler_id = -1;
3083
3084 plane_state = to_intel_plane_state(plane->state);
3085
3086 if (!visible || !fb) {
3087 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3088 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3089 POSTING_READ(PLANE_CTL(pipe, 0));
3090 return;
3091 }
3092
3093 plane_ctl = PLANE_CTL_ENABLE |
3094 PLANE_CTL_PIPE_GAMMA_ENABLE |
3095 PLANE_CTL_PIPE_CSC_ENABLE;
3096
3097 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3098 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3099 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3100
3101 rotation = plane->state->rotation;
3102 plane_ctl |= skl_plane_ctl_rotation(rotation);
3103
3104 obj = intel_fb_obj(fb);
3105 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3106 fb->pixel_format);
3107 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3108
3109 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3110
3111 scaler_id = plane_state->scaler_id;
3112 src_x = plane_state->src.x1 >> 16;
3113 src_y = plane_state->src.y1 >> 16;
3114 src_w = drm_rect_width(&plane_state->src) >> 16;
3115 src_h = drm_rect_height(&plane_state->src) >> 16;
3116 dst_x = plane_state->dst.x1;
3117 dst_y = plane_state->dst.y1;
3118 dst_w = drm_rect_width(&plane_state->dst);
3119 dst_h = drm_rect_height(&plane_state->dst);
3120
3121 WARN_ON(x != src_x || y != src_y);
3122
3123 if (intel_rotation_90_or_270(rotation)) {
3124 /* stride = Surface height in tiles */
3125 tile_height = intel_tile_height(dev, fb->pixel_format,
3126 fb->modifier[0], 0);
3127 stride = DIV_ROUND_UP(fb->height, tile_height);
3128 x_offset = stride * tile_height - y - src_h;
3129 y_offset = x;
3130 plane_size = (src_w - 1) << 16 | (src_h - 1);
3131 } else {
3132 stride = fb->pitches[0] / stride_div;
3133 x_offset = x;
3134 y_offset = y;
3135 plane_size = (src_h - 1) << 16 | (src_w - 1);
3136 }
3137 plane_offset = y_offset << 16 | x_offset;
3138
3139 intel_crtc->adjusted_x = x_offset;
3140 intel_crtc->adjusted_y = y_offset;
3141
3142 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3143 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3144 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3145 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3146
3147 if (scaler_id >= 0) {
3148 uint32_t ps_ctrl = 0;
3149
3150 WARN_ON(!dst_w || !dst_h);
3151 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3152 crtc_state->scaler_state.scalers[scaler_id].mode;
3153 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3154 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3155 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3156 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3157 I915_WRITE(PLANE_POS(pipe, 0), 0);
3158 } else {
3159 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3160 }
3161
3162 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3163
3164 POSTING_READ(PLANE_SURF(pipe, 0));
3165 }
3166
3167 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3168 static int
3169 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3170 int x, int y, enum mode_set_atomic state)
3171 {
3172 struct drm_device *dev = crtc->dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174
3175 if (dev_priv->fbc.deactivate)
3176 dev_priv->fbc.deactivate(dev_priv);
3177
3178 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3179
3180 return 0;
3181 }
3182
3183 static void intel_complete_page_flips(struct drm_device *dev)
3184 {
3185 struct drm_crtc *crtc;
3186
3187 for_each_crtc(dev, crtc) {
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 enum plane plane = intel_crtc->plane;
3190
3191 intel_prepare_page_flip(dev, plane);
3192 intel_finish_page_flip_plane(dev, plane);
3193 }
3194 }
3195
3196 static void intel_update_primary_planes(struct drm_device *dev)
3197 {
3198 struct drm_crtc *crtc;
3199
3200 for_each_crtc(dev, crtc) {
3201 struct intel_plane *plane = to_intel_plane(crtc->primary);
3202 struct intel_plane_state *plane_state;
3203
3204 drm_modeset_lock_crtc(crtc, &plane->base);
3205 plane_state = to_intel_plane_state(plane->base.state);
3206
3207 if (crtc->state->active && plane_state->base.fb)
3208 plane->commit_plane(&plane->base, plane_state);
3209
3210 drm_modeset_unlock_crtc(crtc);
3211 }
3212 }
3213
3214 void intel_prepare_reset(struct drm_device *dev)
3215 {
3216 /* no reset support for gen2 */
3217 if (IS_GEN2(dev))
3218 return;
3219
3220 /* reset doesn't touch the display */
3221 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3222 return;
3223
3224 drm_modeset_lock_all(dev);
3225 /*
3226 * Disabling the crtcs gracefully seems nicer. Also the
3227 * g33 docs say we should at least disable all the planes.
3228 */
3229 intel_display_suspend(dev);
3230 }
3231
3232 void intel_finish_reset(struct drm_device *dev)
3233 {
3234 struct drm_i915_private *dev_priv = to_i915(dev);
3235
3236 /*
3237 * Flips in the rings will be nuked by the reset,
3238 * so complete all pending flips so that user space
3239 * will get its events and not get stuck.
3240 */
3241 intel_complete_page_flips(dev);
3242
3243 /* no reset support for gen2 */
3244 if (IS_GEN2(dev))
3245 return;
3246
3247 /* reset doesn't touch the display */
3248 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3249 /*
3250 * Flips in the rings have been nuked by the reset,
3251 * so update the base address of all primary
3252 * planes to the the last fb to make sure we're
3253 * showing the correct fb after a reset.
3254 *
3255 * FIXME: Atomic will make this obsolete since we won't schedule
3256 * CS-based flips (which might get lost in gpu resets) any more.
3257 */
3258 intel_update_primary_planes(dev);
3259 return;
3260 }
3261
3262 /*
3263 * The display has been reset as well,
3264 * so need a full re-initialization.
3265 */
3266 intel_runtime_pm_disable_interrupts(dev_priv);
3267 intel_runtime_pm_enable_interrupts(dev_priv);
3268
3269 intel_modeset_init_hw(dev);
3270
3271 spin_lock_irq(&dev_priv->irq_lock);
3272 if (dev_priv->display.hpd_irq_setup)
3273 dev_priv->display.hpd_irq_setup(dev);
3274 spin_unlock_irq(&dev_priv->irq_lock);
3275
3276 intel_display_resume(dev);
3277
3278 intel_hpd_init(dev_priv);
3279
3280 drm_modeset_unlock_all(dev);
3281 }
3282
3283 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3284 {
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 bool pending;
3289
3290 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3291 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3292 return false;
3293
3294 spin_lock_irq(&dev->event_lock);
3295 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3296 spin_unlock_irq(&dev->event_lock);
3297
3298 return pending;
3299 }
3300
3301 static void intel_update_pipe_config(struct intel_crtc *crtc,
3302 struct intel_crtc_state *old_crtc_state)
3303 {
3304 struct drm_device *dev = crtc->base.dev;
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306 struct intel_crtc_state *pipe_config =
3307 to_intel_crtc_state(crtc->base.state);
3308
3309 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3310 crtc->base.mode = crtc->base.state->mode;
3311
3312 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3313 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3314 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3315
3316 if (HAS_DDI(dev))
3317 intel_set_pipe_csc(&crtc->base);
3318
3319 /*
3320 * Update pipe size and adjust fitter if needed: the reason for this is
3321 * that in compute_mode_changes we check the native mode (not the pfit
3322 * mode) to see if we can flip rather than do a full mode set. In the
3323 * fastboot case, we'll flip, but if we don't update the pipesrc and
3324 * pfit state, we'll end up with a big fb scanned out into the wrong
3325 * sized surface.
3326 */
3327
3328 I915_WRITE(PIPESRC(crtc->pipe),
3329 ((pipe_config->pipe_src_w - 1) << 16) |
3330 (pipe_config->pipe_src_h - 1));
3331
3332 /* on skylake this is done by detaching scalers */
3333 if (INTEL_INFO(dev)->gen >= 9) {
3334 skl_detach_scalers(crtc);
3335
3336 if (pipe_config->pch_pfit.enabled)
3337 skylake_pfit_enable(crtc);
3338 } else if (HAS_PCH_SPLIT(dev)) {
3339 if (pipe_config->pch_pfit.enabled)
3340 ironlake_pfit_enable(crtc);
3341 else if (old_crtc_state->pch_pfit.enabled)
3342 ironlake_pfit_disable(crtc, true);
3343 }
3344 }
3345
3346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3347 {
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 int pipe = intel_crtc->pipe;
3352 i915_reg_t reg;
3353 u32 temp;
3354
3355 /* enable normal train */
3356 reg = FDI_TX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (IS_IVYBRIDGE(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3360 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3364 }
3365 I915_WRITE(reg, temp);
3366
3367 reg = FDI_RX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 if (HAS_PCH_CPT(dev)) {
3370 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3371 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3372 } else {
3373 temp &= ~FDI_LINK_TRAIN_NONE;
3374 temp |= FDI_LINK_TRAIN_NONE;
3375 }
3376 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3377
3378 /* wait one idle pattern time */
3379 POSTING_READ(reg);
3380 udelay(1000);
3381
3382 /* IVB wants error correction enabled */
3383 if (IS_IVYBRIDGE(dev))
3384 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3385 FDI_FE_ERRC_ENABLE);
3386 }
3387
3388 /* The FDI link training functions for ILK/Ibexpeak. */
3389 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3390 {
3391 struct drm_device *dev = crtc->dev;
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394 int pipe = intel_crtc->pipe;
3395 i915_reg_t reg;
3396 u32 temp, tries;
3397
3398 /* FDI needs bits from pipe first */
3399 assert_pipe_enabled(dev_priv, pipe);
3400
3401 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3402 for train result */
3403 reg = FDI_RX_IMR(pipe);
3404 temp = I915_READ(reg);
3405 temp &= ~FDI_RX_SYMBOL_LOCK;
3406 temp &= ~FDI_RX_BIT_LOCK;
3407 I915_WRITE(reg, temp);
3408 I915_READ(reg);
3409 udelay(150);
3410
3411 /* enable CPU FDI TX and PCH FDI RX */
3412 reg = FDI_TX_CTL(pipe);
3413 temp = I915_READ(reg);
3414 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3415 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3416 temp &= ~FDI_LINK_TRAIN_NONE;
3417 temp |= FDI_LINK_TRAIN_PATTERN_1;
3418 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3419
3420 reg = FDI_RX_CTL(pipe);
3421 temp = I915_READ(reg);
3422 temp &= ~FDI_LINK_TRAIN_NONE;
3423 temp |= FDI_LINK_TRAIN_PATTERN_1;
3424 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3425
3426 POSTING_READ(reg);
3427 udelay(150);
3428
3429 /* Ironlake workaround, enable clock pointer after FDI enable*/
3430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3432 FDI_RX_PHASE_SYNC_POINTER_EN);
3433
3434 reg = FDI_RX_IIR(pipe);
3435 for (tries = 0; tries < 5; tries++) {
3436 temp = I915_READ(reg);
3437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3438
3439 if ((temp & FDI_RX_BIT_LOCK)) {
3440 DRM_DEBUG_KMS("FDI train 1 done.\n");
3441 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3442 break;
3443 }
3444 }
3445 if (tries == 5)
3446 DRM_ERROR("FDI train 1 fail!\n");
3447
3448 /* Train 2 */
3449 reg = FDI_TX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_2;
3453 I915_WRITE(reg, temp);
3454
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_2;
3459 I915_WRITE(reg, temp);
3460
3461 POSTING_READ(reg);
3462 udelay(150);
3463
3464 reg = FDI_RX_IIR(pipe);
3465 for (tries = 0; tries < 5; tries++) {
3466 temp = I915_READ(reg);
3467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3468
3469 if (temp & FDI_RX_SYMBOL_LOCK) {
3470 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3471 DRM_DEBUG_KMS("FDI train 2 done.\n");
3472 break;
3473 }
3474 }
3475 if (tries == 5)
3476 DRM_ERROR("FDI train 2 fail!\n");
3477
3478 DRM_DEBUG_KMS("FDI train done\n");
3479
3480 }
3481
3482 static const int snb_b_fdi_train_param[] = {
3483 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3484 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3485 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3486 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3487 };
3488
3489 /* The FDI link training functions for SNB/Cougarpoint. */
3490 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3491 {
3492 struct drm_device *dev = crtc->dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495 int pipe = intel_crtc->pipe;
3496 i915_reg_t reg;
3497 u32 temp, i, retry;
3498
3499 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3500 for train result */
3501 reg = FDI_RX_IMR(pipe);
3502 temp = I915_READ(reg);
3503 temp &= ~FDI_RX_SYMBOL_LOCK;
3504 temp &= ~FDI_RX_BIT_LOCK;
3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
3508 udelay(150);
3509
3510 /* enable CPU FDI TX and PCH FDI RX */
3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
3513 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3514 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1;
3517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518 /* SNB-B */
3519 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3520 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3521
3522 I915_WRITE(FDI_RX_MISC(pipe),
3523 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3524
3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
3527 if (HAS_PCH_CPT(dev)) {
3528 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3530 } else {
3531 temp &= ~FDI_LINK_TRAIN_NONE;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1;
3533 }
3534 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3535
3536 POSTING_READ(reg);
3537 udelay(150);
3538
3539 for (i = 0; i < 4; i++) {
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3543 temp |= snb_b_fdi_train_param[i];
3544 I915_WRITE(reg, temp);
3545
3546 POSTING_READ(reg);
3547 udelay(500);
3548
3549 for (retry = 0; retry < 5; retry++) {
3550 reg = FDI_RX_IIR(pipe);
3551 temp = I915_READ(reg);
3552 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3553 if (temp & FDI_RX_BIT_LOCK) {
3554 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3555 DRM_DEBUG_KMS("FDI train 1 done.\n");
3556 break;
3557 }
3558 udelay(50);
3559 }
3560 if (retry < 5)
3561 break;
3562 }
3563 if (i == 4)
3564 DRM_ERROR("FDI train 1 fail!\n");
3565
3566 /* Train 2 */
3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_NONE;
3570 temp |= FDI_LINK_TRAIN_PATTERN_2;
3571 if (IS_GEN6(dev)) {
3572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3573 /* SNB-B */
3574 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3575 }
3576 I915_WRITE(reg, temp);
3577
3578 reg = FDI_RX_CTL(pipe);
3579 temp = I915_READ(reg);
3580 if (HAS_PCH_CPT(dev)) {
3581 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3583 } else {
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 }
3587 I915_WRITE(reg, temp);
3588
3589 POSTING_READ(reg);
3590 udelay(150);
3591
3592 for (i = 0; i < 4; i++) {
3593 reg = FDI_TX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3596 temp |= snb_b_fdi_train_param[i];
3597 I915_WRITE(reg, temp);
3598
3599 POSTING_READ(reg);
3600 udelay(500);
3601
3602 for (retry = 0; retry < 5; retry++) {
3603 reg = FDI_RX_IIR(pipe);
3604 temp = I915_READ(reg);
3605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3606 if (temp & FDI_RX_SYMBOL_LOCK) {
3607 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3608 DRM_DEBUG_KMS("FDI train 2 done.\n");
3609 break;
3610 }
3611 udelay(50);
3612 }
3613 if (retry < 5)
3614 break;
3615 }
3616 if (i == 4)
3617 DRM_ERROR("FDI train 2 fail!\n");
3618
3619 DRM_DEBUG_KMS("FDI train done.\n");
3620 }
3621
3622 /* Manual link training for Ivy Bridge A0 parts */
3623 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3624 {
3625 struct drm_device *dev = crtc->dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 int pipe = intel_crtc->pipe;
3629 i915_reg_t reg;
3630 u32 temp, i, j;
3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
3654
3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
3661
3662 /* enable CPU FDI TX and PCH FDI RX */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3672
3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3675
3676 reg = FDI_RX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3681
3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
3684
3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3689
3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
3703
3704 /* Train 2 */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
3718 udelay(2); /* should be 1.5us */
3719
3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3724
3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
3733 }
3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3736 }
3737
3738 train_done:
3739 DRM_DEBUG_KMS("FDI train done.\n");
3740 }
3741
3742 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3743 {
3744 struct drm_device *dev = intel_crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 int pipe = intel_crtc->pipe;
3747 i915_reg_t reg;
3748 u32 temp;
3749
3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
3766 udelay(200);
3767
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3773
3774 POSTING_READ(reg);
3775 udelay(100);
3776 }
3777 }
3778
3779 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780 {
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 i915_reg_t reg;
3785 u32 temp;
3786
3787 /* Switch from PCDclk to Rawclk */
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3791
3792 /* Disable CPU FDI TX PLL */
3793 reg = FDI_TX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3796
3797 POSTING_READ(reg);
3798 udelay(100);
3799
3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3803
3804 /* Wait for the clocks to turn off. */
3805 POSTING_READ(reg);
3806 udelay(100);
3807 }
3808
3809 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3810 {
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814 int pipe = intel_crtc->pipe;
3815 i915_reg_t reg;
3816 u32 temp;
3817
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822 POSTING_READ(reg);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(0x7 << 16);
3827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830 POSTING_READ(reg);
3831 udelay(100);
3832
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
3834 if (HAS_PCH_IBX(dev))
3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836
3837 /* still set train pattern 1 */
3838 reg = FDI_TX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1;
3842 I915_WRITE(reg, temp);
3843
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849 } else {
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852 }
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp &= ~(0x07 << 16);
3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856 I915_WRITE(reg, temp);
3857
3858 POSTING_READ(reg);
3859 udelay(100);
3860 }
3861
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 {
3864 struct intel_crtc *crtc;
3865
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3872 */
3873 for_each_intel_crtc(dev, crtc) {
3874 if (atomic_read(&crtc->unpin_work_count) == 0)
3875 continue;
3876
3877 if (crtc->unpin_work)
3878 intel_wait_for_vblank(dev, crtc->pipe);
3879
3880 return true;
3881 }
3882
3883 return false;
3884 }
3885
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 {
3888 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889 struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3892 smp_rmb();
3893 intel_crtc->unpin_work = NULL;
3894
3895 if (work->event)
3896 drm_send_vblank_event(intel_crtc->base.dev,
3897 intel_crtc->pipe,
3898 work->event);
3899
3900 drm_crtc_vblank_put(&intel_crtc->base);
3901
3902 wake_up_all(&dev_priv->pending_flip_queue);
3903 queue_work(dev_priv->wq, &work->work);
3904
3905 trace_i915_flip_complete(intel_crtc->plane,
3906 work->pending_flip_obj);
3907 }
3908
3909 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 {
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 long ret;
3914
3915 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3916
3917 ret = wait_event_interruptible_timeout(
3918 dev_priv->pending_flip_queue,
3919 !intel_crtc_has_pending_flip(crtc),
3920 60*HZ);
3921
3922 if (ret < 0)
3923 return ret;
3924
3925 if (ret == 0) {
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927
3928 spin_lock_irq(&dev->event_lock);
3929 if (intel_crtc->unpin_work) {
3930 WARN_ONCE(1, "Removing stuck page flip\n");
3931 page_flip_completed(intel_crtc);
3932 }
3933 spin_unlock_irq(&dev->event_lock);
3934 }
3935
3936 return 0;
3937 }
3938
3939 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3940 {
3941 u32 temp;
3942
3943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3944
3945 mutex_lock(&dev_priv->sb_lock);
3946
3947 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3948 temp |= SBI_SSCCTL_DISABLE;
3949 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3950
3951 mutex_unlock(&dev_priv->sb_lock);
3952 }
3953
3954 /* Program iCLKIP clock to the desired frequency */
3955 static void lpt_program_iclkip(struct drm_crtc *crtc)
3956 {
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3960 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3961 u32 temp;
3962
3963 lpt_disable_iclkip(dev_priv);
3964
3965 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3966 if (clock == 20000) {
3967 auxdiv = 1;
3968 divsel = 0x41;
3969 phaseinc = 0x20;
3970 } else {
3971 /* The iCLK virtual clock root frequency is in MHz,
3972 * but the adjusted_mode->crtc_clock in in KHz. To get the
3973 * divisors, it is necessary to divide one by another, so we
3974 * convert the virtual clock precision to KHz here for higher
3975 * precision.
3976 */
3977 u32 iclk_virtual_root_freq = 172800 * 1000;
3978 u32 iclk_pi_range = 64;
3979 u32 desired_divisor, msb_divisor_value, pi_value;
3980
3981 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3982 msb_divisor_value = desired_divisor / iclk_pi_range;
3983 pi_value = desired_divisor % iclk_pi_range;
3984
3985 auxdiv = 0;
3986 divsel = msb_divisor_value - 2;
3987 phaseinc = pi_value;
3988 }
3989
3990 /* This should not happen with any sane values */
3991 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3992 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3993 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3994 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3995
3996 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3997 clock,
3998 auxdiv,
3999 divsel,
4000 phasedir,
4001 phaseinc);
4002
4003 mutex_lock(&dev_priv->sb_lock);
4004
4005 /* Program SSCDIVINTPHASE6 */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4007 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4008 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4009 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4011 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4012 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4013 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4014
4015 /* Program SSCAUXDIV */
4016 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4017 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4018 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4019 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4020
4021 /* Enable modulator and associated divider */
4022 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4023 temp &= ~SBI_SSCCTL_DISABLE;
4024 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4025
4026 mutex_unlock(&dev_priv->sb_lock);
4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4032 }
4033
4034 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4035 enum pipe pch_transcoder)
4036 {
4037 struct drm_device *dev = crtc->base.dev;
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4040
4041 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4042 I915_READ(HTOTAL(cpu_transcoder)));
4043 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4044 I915_READ(HBLANK(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4046 I915_READ(HSYNC(cpu_transcoder)));
4047
4048 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4049 I915_READ(VTOTAL(cpu_transcoder)));
4050 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4051 I915_READ(VBLANK(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4053 I915_READ(VSYNC(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4055 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4056 }
4057
4058 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4059 {
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 uint32_t temp;
4062
4063 temp = I915_READ(SOUTH_CHICKEN1);
4064 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4065 return;
4066
4067 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4068 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4069
4070 temp &= ~FDI_BC_BIFURCATION_SELECT;
4071 if (enable)
4072 temp |= FDI_BC_BIFURCATION_SELECT;
4073
4074 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4075 I915_WRITE(SOUTH_CHICKEN1, temp);
4076 POSTING_READ(SOUTH_CHICKEN1);
4077 }
4078
4079 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4080 {
4081 struct drm_device *dev = intel_crtc->base.dev;
4082
4083 switch (intel_crtc->pipe) {
4084 case PIPE_A:
4085 break;
4086 case PIPE_B:
4087 if (intel_crtc->config->fdi_lanes > 2)
4088 cpt_set_fdi_bc_bifurcation(dev, false);
4089 else
4090 cpt_set_fdi_bc_bifurcation(dev, true);
4091
4092 break;
4093 case PIPE_C:
4094 cpt_set_fdi_bc_bifurcation(dev, true);
4095
4096 break;
4097 default:
4098 BUG();
4099 }
4100 }
4101
4102 /* Return which DP Port should be selected for Transcoder DP control */
4103 static enum port
4104 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 struct intel_encoder *encoder;
4108
4109 for_each_encoder_on_crtc(dev, crtc, encoder) {
4110 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4111 encoder->type == INTEL_OUTPUT_EDP)
4112 return enc_to_dig_port(&encoder->base)->port;
4113 }
4114
4115 return -1;
4116 }
4117
4118 /*
4119 * Enable PCH resources required for PCH ports:
4120 * - PCH PLLs
4121 * - FDI training & RX/TX
4122 * - update transcoder timings
4123 * - DP transcoding bits
4124 * - transcoder
4125 */
4126 static void ironlake_pch_enable(struct drm_crtc *crtc)
4127 {
4128 struct drm_device *dev = crtc->dev;
4129 struct drm_i915_private *dev_priv = dev->dev_private;
4130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131 int pipe = intel_crtc->pipe;
4132 u32 temp;
4133
4134 assert_pch_transcoder_disabled(dev_priv, pipe);
4135
4136 if (IS_IVYBRIDGE(dev))
4137 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4138
4139 /* Write the TU size bits before fdi link training, so that error
4140 * detection works. */
4141 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4142 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4143
4144 /*
4145 * Sometimes spurious CPU pipe underruns happen during FDI
4146 * training, at least with VGA+HDMI cloning. Suppress them.
4147 */
4148 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4149
4150 /* For PCH output, training FDI link */
4151 dev_priv->display.fdi_link_train(crtc);
4152
4153 /* We need to program the right clock selection before writing the pixel
4154 * mutliplier into the DPLL. */
4155 if (HAS_PCH_CPT(dev)) {
4156 u32 sel;
4157
4158 temp = I915_READ(PCH_DPLL_SEL);
4159 temp |= TRANS_DPLL_ENABLE(pipe);
4160 sel = TRANS_DPLLB_SEL(pipe);
4161 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4162 temp |= sel;
4163 else
4164 temp &= ~sel;
4165 I915_WRITE(PCH_DPLL_SEL, temp);
4166 }
4167
4168 /* XXX: pch pll's can be enabled any time before we enable the PCH
4169 * transcoder, and we actually should do this to not upset any PCH
4170 * transcoder that already use the clock when we share it.
4171 *
4172 * Note that enable_shared_dpll tries to do the right thing, but
4173 * get_shared_dpll unconditionally resets the pll - we need that to have
4174 * the right LVDS enable sequence. */
4175 intel_enable_shared_dpll(intel_crtc);
4176
4177 /* set transcoder timing, panel must allow it */
4178 assert_panel_unlocked(dev_priv, pipe);
4179 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4180
4181 intel_fdi_normal_train(crtc);
4182
4183 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4184
4185 /* For PCH DP, enable TRANS_DP_CTL */
4186 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4187 const struct drm_display_mode *adjusted_mode =
4188 &intel_crtc->config->base.adjusted_mode;
4189 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4190 i915_reg_t reg = TRANS_DP_CTL(pipe);
4191 temp = I915_READ(reg);
4192 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4193 TRANS_DP_SYNC_MASK |
4194 TRANS_DP_BPC_MASK);
4195 temp |= TRANS_DP_OUTPUT_ENABLE;
4196 temp |= bpc << 9; /* same format but at 11:9 */
4197
4198 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4199 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4200 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4201 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4202
4203 switch (intel_trans_dp_port_sel(crtc)) {
4204 case PORT_B:
4205 temp |= TRANS_DP_PORT_SEL_B;
4206 break;
4207 case PORT_C:
4208 temp |= TRANS_DP_PORT_SEL_C;
4209 break;
4210 case PORT_D:
4211 temp |= TRANS_DP_PORT_SEL_D;
4212 break;
4213 default:
4214 BUG();
4215 }
4216
4217 I915_WRITE(reg, temp);
4218 }
4219
4220 ironlake_enable_pch_transcoder(dev_priv, pipe);
4221 }
4222
4223 static void lpt_pch_enable(struct drm_crtc *crtc)
4224 {
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4229
4230 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4231
4232 lpt_program_iclkip(crtc);
4233
4234 /* Set transcoder timing. */
4235 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4236
4237 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4238 }
4239
4240 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4241 struct intel_crtc_state *crtc_state)
4242 {
4243 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4244 struct intel_shared_dpll *pll;
4245 struct intel_shared_dpll_config *shared_dpll;
4246 enum intel_dpll_id i;
4247 int max = dev_priv->num_shared_dpll;
4248
4249 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4250
4251 if (HAS_PCH_IBX(dev_priv->dev)) {
4252 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4253 i = (enum intel_dpll_id) crtc->pipe;
4254 pll = &dev_priv->shared_dplls[i];
4255
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258
4259 WARN_ON(shared_dpll[i].crtc_mask);
4260
4261 goto found;
4262 }
4263
4264 if (IS_BROXTON(dev_priv->dev)) {
4265 /* PLL is attached to port in bxt */
4266 struct intel_encoder *encoder;
4267 struct intel_digital_port *intel_dig_port;
4268
4269 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4270 if (WARN_ON(!encoder))
4271 return NULL;
4272
4273 intel_dig_port = enc_to_dig_port(&encoder->base);
4274 /* 1:1 mapping between ports and PLLs */
4275 i = (enum intel_dpll_id)intel_dig_port->port;
4276 pll = &dev_priv->shared_dplls[i];
4277 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4278 crtc->base.base.id, pll->name);
4279 WARN_ON(shared_dpll[i].crtc_mask);
4280
4281 goto found;
4282 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4283 /* Do not consider SPLL */
4284 max = 2;
4285
4286 for (i = 0; i < max; i++) {
4287 pll = &dev_priv->shared_dplls[i];
4288
4289 /* Only want to check enabled timings first */
4290 if (shared_dpll[i].crtc_mask == 0)
4291 continue;
4292
4293 if (memcmp(&crtc_state->dpll_hw_state,
4294 &shared_dpll[i].hw_state,
4295 sizeof(crtc_state->dpll_hw_state)) == 0) {
4296 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4297 crtc->base.base.id, pll->name,
4298 shared_dpll[i].crtc_mask,
4299 pll->active);
4300 goto found;
4301 }
4302 }
4303
4304 /* Ok no matching timings, maybe there's a free one? */
4305 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4306 pll = &dev_priv->shared_dplls[i];
4307 if (shared_dpll[i].crtc_mask == 0) {
4308 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4309 crtc->base.base.id, pll->name);
4310 goto found;
4311 }
4312 }
4313
4314 return NULL;
4315
4316 found:
4317 if (shared_dpll[i].crtc_mask == 0)
4318 shared_dpll[i].hw_state =
4319 crtc_state->dpll_hw_state;
4320
4321 crtc_state->shared_dpll = i;
4322 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4323 pipe_name(crtc->pipe));
4324
4325 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4326
4327 return pll;
4328 }
4329
4330 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4331 {
4332 struct drm_i915_private *dev_priv = to_i915(state->dev);
4333 struct intel_shared_dpll_config *shared_dpll;
4334 struct intel_shared_dpll *pll;
4335 enum intel_dpll_id i;
4336
4337 if (!to_intel_atomic_state(state)->dpll_set)
4338 return;
4339
4340 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4341 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4342 pll = &dev_priv->shared_dplls[i];
4343 pll->config = shared_dpll[i];
4344 }
4345 }
4346
4347 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4348 {
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 i915_reg_t dslreg = PIPEDSL(pipe);
4351 u32 temp;
4352
4353 temp = I915_READ(dslreg);
4354 udelay(500);
4355 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4356 if (wait_for(I915_READ(dslreg) != temp, 5))
4357 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4358 }
4359 }
4360
4361 static int
4362 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4363 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4364 int src_w, int src_h, int dst_w, int dst_h)
4365 {
4366 struct intel_crtc_scaler_state *scaler_state =
4367 &crtc_state->scaler_state;
4368 struct intel_crtc *intel_crtc =
4369 to_intel_crtc(crtc_state->base.crtc);
4370 int need_scaling;
4371
4372 need_scaling = intel_rotation_90_or_270(rotation) ?
4373 (src_h != dst_w || src_w != dst_h):
4374 (src_w != dst_w || src_h != dst_h);
4375
4376 /*
4377 * if plane is being disabled or scaler is no more required or force detach
4378 * - free scaler binded to this plane/crtc
4379 * - in order to do this, update crtc->scaler_usage
4380 *
4381 * Here scaler state in crtc_state is set free so that
4382 * scaler can be assigned to other user. Actual register
4383 * update to free the scaler is done in plane/panel-fit programming.
4384 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4385 */
4386 if (force_detach || !need_scaling) {
4387 if (*scaler_id >= 0) {
4388 scaler_state->scaler_users &= ~(1 << scaler_user);
4389 scaler_state->scalers[*scaler_id].in_use = 0;
4390
4391 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4392 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4393 intel_crtc->pipe, scaler_user, *scaler_id,
4394 scaler_state->scaler_users);
4395 *scaler_id = -1;
4396 }
4397 return 0;
4398 }
4399
4400 /* range checks */
4401 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4402 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4403
4404 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4405 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4406 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4407 "size is out of scaler range\n",
4408 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4409 return -EINVAL;
4410 }
4411
4412 /* mark this plane as a scaler user in crtc_state */
4413 scaler_state->scaler_users |= (1 << scaler_user);
4414 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4415 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4416 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4417 scaler_state->scaler_users);
4418
4419 return 0;
4420 }
4421
4422 /**
4423 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4424 *
4425 * @state: crtc's scaler state
4426 *
4427 * Return
4428 * 0 - scaler_usage updated successfully
4429 * error - requested scaling cannot be supported or other error condition
4430 */
4431 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4432 {
4433 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4434 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4435
4436 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4437 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4438
4439 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4440 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4441 state->pipe_src_w, state->pipe_src_h,
4442 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4443 }
4444
4445 /**
4446 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4447 *
4448 * @state: crtc's scaler state
4449 * @plane_state: atomic plane state to update
4450 *
4451 * Return
4452 * 0 - scaler_usage updated successfully
4453 * error - requested scaling cannot be supported or other error condition
4454 */
4455 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4456 struct intel_plane_state *plane_state)
4457 {
4458
4459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4460 struct intel_plane *intel_plane =
4461 to_intel_plane(plane_state->base.plane);
4462 struct drm_framebuffer *fb = plane_state->base.fb;
4463 int ret;
4464
4465 bool force_detach = !fb || !plane_state->visible;
4466
4467 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4468 intel_plane->base.base.id, intel_crtc->pipe,
4469 drm_plane_index(&intel_plane->base));
4470
4471 ret = skl_update_scaler(crtc_state, force_detach,
4472 drm_plane_index(&intel_plane->base),
4473 &plane_state->scaler_id,
4474 plane_state->base.rotation,
4475 drm_rect_width(&plane_state->src) >> 16,
4476 drm_rect_height(&plane_state->src) >> 16,
4477 drm_rect_width(&plane_state->dst),
4478 drm_rect_height(&plane_state->dst));
4479
4480 if (ret || plane_state->scaler_id < 0)
4481 return ret;
4482
4483 /* check colorkey */
4484 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4485 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4486 intel_plane->base.base.id);
4487 return -EINVAL;
4488 }
4489
4490 /* Check src format */
4491 switch (fb->pixel_format) {
4492 case DRM_FORMAT_RGB565:
4493 case DRM_FORMAT_XBGR8888:
4494 case DRM_FORMAT_XRGB8888:
4495 case DRM_FORMAT_ABGR8888:
4496 case DRM_FORMAT_ARGB8888:
4497 case DRM_FORMAT_XRGB2101010:
4498 case DRM_FORMAT_XBGR2101010:
4499 case DRM_FORMAT_YUYV:
4500 case DRM_FORMAT_YVYU:
4501 case DRM_FORMAT_UYVY:
4502 case DRM_FORMAT_VYUY:
4503 break;
4504 default:
4505 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4506 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4507 return -EINVAL;
4508 }
4509
4510 return 0;
4511 }
4512
4513 static void skylake_scaler_disable(struct intel_crtc *crtc)
4514 {
4515 int i;
4516
4517 for (i = 0; i < crtc->num_scalers; i++)
4518 skl_detach_scaler(crtc, i);
4519 }
4520
4521 static void skylake_pfit_enable(struct intel_crtc *crtc)
4522 {
4523 struct drm_device *dev = crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 int pipe = crtc->pipe;
4526 struct intel_crtc_scaler_state *scaler_state =
4527 &crtc->config->scaler_state;
4528
4529 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4530
4531 if (crtc->config->pch_pfit.enabled) {
4532 int id;
4533
4534 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4535 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4536 return;
4537 }
4538
4539 id = scaler_state->scaler_id;
4540 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4541 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4542 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4543 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4544
4545 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4546 }
4547 }
4548
4549 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4550 {
4551 struct drm_device *dev = crtc->base.dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 int pipe = crtc->pipe;
4554
4555 if (crtc->config->pch_pfit.enabled) {
4556 /* Force use of hard-coded filter coefficients
4557 * as some pre-programmed values are broken,
4558 * e.g. x201.
4559 */
4560 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4561 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4562 PF_PIPE_SEL_IVB(pipe));
4563 else
4564 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4565 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4566 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4567 }
4568 }
4569
4570 void hsw_enable_ips(struct intel_crtc *crtc)
4571 {
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574
4575 if (!crtc->config->ips_enabled)
4576 return;
4577
4578 /* We can only enable IPS after we enable a plane and wait for a vblank */
4579 intel_wait_for_vblank(dev, crtc->pipe);
4580
4581 assert_plane_enabled(dev_priv, crtc->plane);
4582 if (IS_BROADWELL(dev)) {
4583 mutex_lock(&dev_priv->rps.hw_lock);
4584 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4585 mutex_unlock(&dev_priv->rps.hw_lock);
4586 /* Quoting Art Runyan: "its not safe to expect any particular
4587 * value in IPS_CTL bit 31 after enabling IPS through the
4588 * mailbox." Moreover, the mailbox may return a bogus state,
4589 * so we need to just enable it and continue on.
4590 */
4591 } else {
4592 I915_WRITE(IPS_CTL, IPS_ENABLE);
4593 /* The bit only becomes 1 in the next vblank, so this wait here
4594 * is essentially intel_wait_for_vblank. If we don't have this
4595 * and don't wait for vblanks until the end of crtc_enable, then
4596 * the HW state readout code will complain that the expected
4597 * IPS_CTL value is not the one we read. */
4598 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4599 DRM_ERROR("Timed out waiting for IPS enable\n");
4600 }
4601 }
4602
4603 void hsw_disable_ips(struct intel_crtc *crtc)
4604 {
4605 struct drm_device *dev = crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607
4608 if (!crtc->config->ips_enabled)
4609 return;
4610
4611 assert_plane_enabled(dev_priv, crtc->plane);
4612 if (IS_BROADWELL(dev)) {
4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4617 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4618 DRM_ERROR("Timed out waiting for IPS disable\n");
4619 } else {
4620 I915_WRITE(IPS_CTL, 0);
4621 POSTING_READ(IPS_CTL);
4622 }
4623
4624 /* We need to wait for a vblank before we can disable the plane. */
4625 intel_wait_for_vblank(dev, crtc->pipe);
4626 }
4627
4628 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4629 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4630 {
4631 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634 enum pipe pipe = intel_crtc->pipe;
4635 int i;
4636 bool reenable_ips = false;
4637
4638 /* The clocks have to be on to load the palette. */
4639 if (!crtc->state->active)
4640 return;
4641
4642 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4643 if (intel_crtc->config->has_dsi_encoder)
4644 assert_dsi_pll_enabled(dev_priv);
4645 else
4646 assert_pll_enabled(dev_priv, pipe);
4647 }
4648
4649 /* Workaround : Do not read or write the pipe palette/gamma data while
4650 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4651 */
4652 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4653 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4654 GAMMA_MODE_MODE_SPLIT)) {
4655 hsw_disable_ips(intel_crtc);
4656 reenable_ips = true;
4657 }
4658
4659 for (i = 0; i < 256; i++) {
4660 i915_reg_t palreg;
4661
4662 if (HAS_GMCH_DISPLAY(dev))
4663 palreg = PALETTE(pipe, i);
4664 else
4665 palreg = LGC_PALETTE(pipe, i);
4666
4667 I915_WRITE(palreg,
4668 (intel_crtc->lut_r[i] << 16) |
4669 (intel_crtc->lut_g[i] << 8) |
4670 intel_crtc->lut_b[i]);
4671 }
4672
4673 if (reenable_ips)
4674 hsw_enable_ips(intel_crtc);
4675 }
4676
4677 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4678 {
4679 if (intel_crtc->overlay) {
4680 struct drm_device *dev = intel_crtc->base.dev;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682
4683 mutex_lock(&dev->struct_mutex);
4684 dev_priv->mm.interruptible = false;
4685 (void) intel_overlay_switch_off(intel_crtc->overlay);
4686 dev_priv->mm.interruptible = true;
4687 mutex_unlock(&dev->struct_mutex);
4688 }
4689
4690 /* Let userspace switch the overlay on again. In most cases userspace
4691 * has to recompute where to put it anyway.
4692 */
4693 }
4694
4695 /**
4696 * intel_post_enable_primary - Perform operations after enabling primary plane
4697 * @crtc: the CRTC whose primary plane was just enabled
4698 *
4699 * Performs potentially sleeping operations that must be done after the primary
4700 * plane is enabled, such as updating FBC and IPS. Note that this may be
4701 * called due to an explicit primary plane update, or due to an implicit
4702 * re-enable that is caused when a sprite plane is updated to no longer
4703 * completely hide the primary plane.
4704 */
4705 static void
4706 intel_post_enable_primary(struct drm_crtc *crtc)
4707 {
4708 struct drm_device *dev = crtc->dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4711 int pipe = intel_crtc->pipe;
4712
4713 /*
4714 * FIXME IPS should be fine as long as one plane is
4715 * enabled, but in practice it seems to have problems
4716 * when going from primary only to sprite only and vice
4717 * versa.
4718 */
4719 hsw_enable_ips(intel_crtc);
4720
4721 /*
4722 * Gen2 reports pipe underruns whenever all planes are disabled.
4723 * So don't enable underrun reporting before at least some planes
4724 * are enabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4727 */
4728 if (IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730
4731 /* Underruns don't always raise interrupts, so check manually. */
4732 intel_check_cpu_fifo_underruns(dev_priv);
4733 intel_check_pch_fifo_underruns(dev_priv);
4734 }
4735
4736 /**
4737 * intel_pre_disable_primary - Perform operations before disabling primary plane
4738 * @crtc: the CRTC whose primary plane is to be disabled
4739 *
4740 * Performs potentially sleeping operations that must be done before the
4741 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4742 * be called due to an explicit primary plane update, or due to an implicit
4743 * disable that is caused when a sprite plane completely hides the primary
4744 * plane.
4745 */
4746 static void
4747 intel_pre_disable_primary(struct drm_crtc *crtc)
4748 {
4749 struct drm_device *dev = crtc->dev;
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4752 int pipe = intel_crtc->pipe;
4753
4754 /*
4755 * Gen2 reports pipe underruns whenever all planes are disabled.
4756 * So diasble underrun reporting before all the planes get disabled.
4757 * FIXME: Need to fix the logic to work when we turn off all planes
4758 * but leave the pipe running.
4759 */
4760 if (IS_GEN2(dev))
4761 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4762
4763 /*
4764 * Vblank time updates from the shadow to live plane control register
4765 * are blocked if the memory self-refresh mode is active at that
4766 * moment. So to make sure the plane gets truly disabled, disable
4767 * first the self-refresh mode. The self-refresh enable bit in turn
4768 * will be checked/applied by the HW only at the next frame start
4769 * event which is after the vblank start event, so we need to have a
4770 * wait-for-vblank between disabling the plane and the pipe.
4771 */
4772 if (HAS_GMCH_DISPLAY(dev)) {
4773 intel_set_memory_cxsr(dev_priv, false);
4774 dev_priv->wm.vlv.cxsr = false;
4775 intel_wait_for_vblank(dev, pipe);
4776 }
4777
4778 /*
4779 * FIXME IPS should be fine as long as one plane is
4780 * enabled, but in practice it seems to have problems
4781 * when going from primary only to sprite only and vice
4782 * versa.
4783 */
4784 hsw_disable_ips(intel_crtc);
4785 }
4786
4787 static void intel_post_plane_update(struct intel_crtc *crtc)
4788 {
4789 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4790 struct intel_crtc_state *pipe_config =
4791 to_intel_crtc_state(crtc->base.state);
4792 struct drm_device *dev = crtc->base.dev;
4793
4794 if (atomic->wait_vblank)
4795 intel_wait_for_vblank(dev, crtc->pipe);
4796
4797 intel_frontbuffer_flip(dev, atomic->fb_bits);
4798
4799 crtc->wm.cxsr_allowed = true;
4800
4801 if (pipe_config->wm_changed && pipe_config->base.active)
4802 intel_update_watermarks(&crtc->base);
4803
4804 if (atomic->update_fbc)
4805 intel_fbc_update(crtc);
4806
4807 if (atomic->post_enable_primary)
4808 intel_post_enable_primary(&crtc->base);
4809
4810 memset(atomic, 0, sizeof(*atomic));
4811 }
4812
4813 static void intel_pre_plane_update(struct intel_crtc *crtc)
4814 {
4815 struct drm_device *dev = crtc->base.dev;
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4818 struct intel_crtc_state *pipe_config =
4819 to_intel_crtc_state(crtc->base.state);
4820
4821 if (atomic->disable_fbc)
4822 intel_fbc_deactivate(crtc);
4823
4824 if (crtc->atomic.disable_ips)
4825 hsw_disable_ips(crtc);
4826
4827 if (atomic->pre_disable_primary)
4828 intel_pre_disable_primary(&crtc->base);
4829
4830 if (pipe_config->disable_cxsr) {
4831 crtc->wm.cxsr_allowed = false;
4832 intel_set_memory_cxsr(dev_priv, false);
4833 }
4834
4835 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4836 intel_update_watermarks(&crtc->base);
4837 }
4838
4839 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4840 {
4841 struct drm_device *dev = crtc->dev;
4842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4843 struct drm_plane *p;
4844 int pipe = intel_crtc->pipe;
4845
4846 intel_crtc_dpms_overlay_disable(intel_crtc);
4847
4848 drm_for_each_plane_mask(p, dev, plane_mask)
4849 to_intel_plane(p)->disable_plane(p, crtc);
4850
4851 /*
4852 * FIXME: Once we grow proper nuclear flip support out of this we need
4853 * to compute the mask of flip planes precisely. For the time being
4854 * consider this a flip to a NULL plane.
4855 */
4856 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4857 }
4858
4859 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4860 {
4861 struct drm_device *dev = crtc->dev;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4864 struct intel_encoder *encoder;
4865 int pipe = intel_crtc->pipe;
4866
4867 if (WARN_ON(intel_crtc->active))
4868 return;
4869
4870 if (intel_crtc->config->has_pch_encoder)
4871 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4872
4873 if (intel_crtc->config->has_pch_encoder)
4874 intel_prepare_shared_dpll(intel_crtc);
4875
4876 if (intel_crtc->config->has_dp_encoder)
4877 intel_dp_set_m_n(intel_crtc, M1_N1);
4878
4879 intel_set_pipe_timings(intel_crtc);
4880
4881 if (intel_crtc->config->has_pch_encoder) {
4882 intel_cpu_transcoder_set_m_n(intel_crtc,
4883 &intel_crtc->config->fdi_m_n, NULL);
4884 }
4885
4886 ironlake_set_pipeconf(crtc);
4887
4888 intel_crtc->active = true;
4889
4890 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4891
4892 for_each_encoder_on_crtc(dev, crtc, encoder)
4893 if (encoder->pre_enable)
4894 encoder->pre_enable(encoder);
4895
4896 if (intel_crtc->config->has_pch_encoder) {
4897 /* Note: FDI PLL enabling _must_ be done before we enable the
4898 * cpu pipes, hence this is separate from all the other fdi/pch
4899 * enabling. */
4900 ironlake_fdi_pll_enable(intel_crtc);
4901 } else {
4902 assert_fdi_tx_disabled(dev_priv, pipe);
4903 assert_fdi_rx_disabled(dev_priv, pipe);
4904 }
4905
4906 ironlake_pfit_enable(intel_crtc);
4907
4908 /*
4909 * On ILK+ LUT must be loaded before the pipe is running but with
4910 * clocks enabled
4911 */
4912 intel_crtc_load_lut(crtc);
4913
4914 intel_update_watermarks(crtc);
4915 intel_enable_pipe(intel_crtc);
4916
4917 if (intel_crtc->config->has_pch_encoder)
4918 ironlake_pch_enable(crtc);
4919
4920 assert_vblank_disabled(crtc);
4921 drm_crtc_vblank_on(crtc);
4922
4923 for_each_encoder_on_crtc(dev, crtc, encoder)
4924 encoder->enable(encoder);
4925
4926 if (HAS_PCH_CPT(dev))
4927 cpt_verify_modeset(dev, intel_crtc->pipe);
4928
4929 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4930 if (intel_crtc->config->has_pch_encoder)
4931 intel_wait_for_vblank(dev, pipe);
4932 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4933
4934 intel_fbc_enable(intel_crtc);
4935 }
4936
4937 /* IPS only exists on ULT machines and is tied to pipe A. */
4938 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4939 {
4940 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4941 }
4942
4943 static void haswell_crtc_enable(struct drm_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 struct intel_encoder *encoder;
4949 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4950 struct intel_crtc_state *pipe_config =
4951 to_intel_crtc_state(crtc->state);
4952
4953 if (WARN_ON(intel_crtc->active))
4954 return;
4955
4956 if (intel_crtc->config->has_pch_encoder)
4957 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4958 false);
4959
4960 if (intel_crtc_to_shared_dpll(intel_crtc))
4961 intel_enable_shared_dpll(intel_crtc);
4962
4963 if (intel_crtc->config->has_dp_encoder)
4964 intel_dp_set_m_n(intel_crtc, M1_N1);
4965
4966 intel_set_pipe_timings(intel_crtc);
4967
4968 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4969 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4970 intel_crtc->config->pixel_multiplier - 1);
4971 }
4972
4973 if (intel_crtc->config->has_pch_encoder) {
4974 intel_cpu_transcoder_set_m_n(intel_crtc,
4975 &intel_crtc->config->fdi_m_n, NULL);
4976 }
4977
4978 haswell_set_pipeconf(crtc);
4979
4980 intel_set_pipe_csc(crtc);
4981
4982 intel_crtc->active = true;
4983
4984 if (intel_crtc->config->has_pch_encoder)
4985 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4986 else
4987 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989 for_each_encoder_on_crtc(dev, crtc, encoder) {
4990 if (encoder->pre_enable)
4991 encoder->pre_enable(encoder);
4992 }
4993
4994 if (intel_crtc->config->has_pch_encoder)
4995 dev_priv->display.fdi_link_train(crtc);
4996
4997 if (!intel_crtc->config->has_dsi_encoder)
4998 intel_ddi_enable_pipe_clock(intel_crtc);
4999
5000 if (INTEL_INFO(dev)->gen >= 9)
5001 skylake_pfit_enable(intel_crtc);
5002 else
5003 ironlake_pfit_enable(intel_crtc);
5004
5005 /*
5006 * On ILK+ LUT must be loaded before the pipe is running but with
5007 * clocks enabled
5008 */
5009 intel_crtc_load_lut(crtc);
5010
5011 intel_ddi_set_pipe_settings(crtc);
5012 if (!intel_crtc->config->has_dsi_encoder)
5013 intel_ddi_enable_transcoder_func(crtc);
5014
5015 intel_update_watermarks(crtc);
5016 intel_enable_pipe(intel_crtc);
5017
5018 if (intel_crtc->config->has_pch_encoder)
5019 lpt_pch_enable(crtc);
5020
5021 if (intel_crtc->config->dp_encoder_is_mst)
5022 intel_ddi_set_vc_payload_alloc(crtc, true);
5023
5024 assert_vblank_disabled(crtc);
5025 drm_crtc_vblank_on(crtc);
5026
5027 for_each_encoder_on_crtc(dev, crtc, encoder) {
5028 encoder->enable(encoder);
5029 intel_opregion_notify_encoder(encoder, true);
5030 }
5031
5032 if (intel_crtc->config->has_pch_encoder) {
5033 intel_wait_for_vblank(dev, pipe);
5034 intel_wait_for_vblank(dev, pipe);
5035 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5036 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5037 true);
5038 }
5039
5040 /* If we change the relative order between pipe/planes enabling, we need
5041 * to change the workaround. */
5042 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5043 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5044 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5045 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046 }
5047
5048 intel_fbc_enable(intel_crtc);
5049 }
5050
5051 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5052 {
5053 struct drm_device *dev = crtc->base.dev;
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 int pipe = crtc->pipe;
5056
5057 /* To avoid upsetting the power well on haswell only disable the pfit if
5058 * it's in use. The hw state code will make sure we get this right. */
5059 if (force || crtc->config->pch_pfit.enabled) {
5060 I915_WRITE(PF_CTL(pipe), 0);
5061 I915_WRITE(PF_WIN_POS(pipe), 0);
5062 I915_WRITE(PF_WIN_SZ(pipe), 0);
5063 }
5064 }
5065
5066 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5067 {
5068 struct drm_device *dev = crtc->dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071 struct intel_encoder *encoder;
5072 int pipe = intel_crtc->pipe;
5073
5074 if (intel_crtc->config->has_pch_encoder)
5075 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5076
5077 for_each_encoder_on_crtc(dev, crtc, encoder)
5078 encoder->disable(encoder);
5079
5080 drm_crtc_vblank_off(crtc);
5081 assert_vblank_disabled(crtc);
5082
5083 /*
5084 * Sometimes spurious CPU pipe underruns happen when the
5085 * pipe is already disabled, but FDI RX/TX is still enabled.
5086 * Happens at least with VGA+HDMI cloning. Suppress them.
5087 */
5088 if (intel_crtc->config->has_pch_encoder)
5089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5090
5091 intel_disable_pipe(intel_crtc);
5092
5093 ironlake_pfit_disable(intel_crtc, false);
5094
5095 if (intel_crtc->config->has_pch_encoder) {
5096 ironlake_fdi_disable(crtc);
5097 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5098 }
5099
5100 for_each_encoder_on_crtc(dev, crtc, encoder)
5101 if (encoder->post_disable)
5102 encoder->post_disable(encoder);
5103
5104 if (intel_crtc->config->has_pch_encoder) {
5105 ironlake_disable_pch_transcoder(dev_priv, pipe);
5106
5107 if (HAS_PCH_CPT(dev)) {
5108 i915_reg_t reg;
5109 u32 temp;
5110
5111 /* disable TRANS_DP_CTL */
5112 reg = TRANS_DP_CTL(pipe);
5113 temp = I915_READ(reg);
5114 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5115 TRANS_DP_PORT_SEL_MASK);
5116 temp |= TRANS_DP_PORT_SEL_NONE;
5117 I915_WRITE(reg, temp);
5118
5119 /* disable DPLL_SEL */
5120 temp = I915_READ(PCH_DPLL_SEL);
5121 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5122 I915_WRITE(PCH_DPLL_SEL, temp);
5123 }
5124
5125 ironlake_fdi_pll_disable(intel_crtc);
5126 }
5127
5128 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5129
5130 intel_fbc_disable_crtc(intel_crtc);
5131 }
5132
5133 static void haswell_crtc_disable(struct drm_crtc *crtc)
5134 {
5135 struct drm_device *dev = crtc->dev;
5136 struct drm_i915_private *dev_priv = dev->dev_private;
5137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5138 struct intel_encoder *encoder;
5139 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5140
5141 if (intel_crtc->config->has_pch_encoder)
5142 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5143 false);
5144
5145 for_each_encoder_on_crtc(dev, crtc, encoder) {
5146 intel_opregion_notify_encoder(encoder, false);
5147 encoder->disable(encoder);
5148 }
5149
5150 drm_crtc_vblank_off(crtc);
5151 assert_vblank_disabled(crtc);
5152
5153 intel_disable_pipe(intel_crtc);
5154
5155 if (intel_crtc->config->dp_encoder_is_mst)
5156 intel_ddi_set_vc_payload_alloc(crtc, false);
5157
5158 if (!intel_crtc->config->has_dsi_encoder)
5159 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5160
5161 if (INTEL_INFO(dev)->gen >= 9)
5162 skylake_scaler_disable(intel_crtc);
5163 else
5164 ironlake_pfit_disable(intel_crtc, false);
5165
5166 if (!intel_crtc->config->has_dsi_encoder)
5167 intel_ddi_disable_pipe_clock(intel_crtc);
5168
5169 for_each_encoder_on_crtc(dev, crtc, encoder)
5170 if (encoder->post_disable)
5171 encoder->post_disable(encoder);
5172
5173 if (intel_crtc->config->has_pch_encoder) {
5174 lpt_disable_pch_transcoder(dev_priv);
5175 lpt_disable_iclkip(dev_priv);
5176 intel_ddi_fdi_disable(crtc);
5177
5178 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5179 true);
5180 }
5181
5182 intel_fbc_disable_crtc(intel_crtc);
5183 }
5184
5185 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5186 {
5187 struct drm_device *dev = crtc->base.dev;
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 struct intel_crtc_state *pipe_config = crtc->config;
5190
5191 if (!pipe_config->gmch_pfit.control)
5192 return;
5193
5194 /*
5195 * The panel fitter should only be adjusted whilst the pipe is disabled,
5196 * according to register description and PRM.
5197 */
5198 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5199 assert_pipe_disabled(dev_priv, crtc->pipe);
5200
5201 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5202 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5203
5204 /* Border color in case we don't scale up to the full screen. Black by
5205 * default, change to something else for debugging. */
5206 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5207 }
5208
5209 static enum intel_display_power_domain port_to_power_domain(enum port port)
5210 {
5211 switch (port) {
5212 case PORT_A:
5213 return POWER_DOMAIN_PORT_DDI_A_LANES;
5214 case PORT_B:
5215 return POWER_DOMAIN_PORT_DDI_B_LANES;
5216 case PORT_C:
5217 return POWER_DOMAIN_PORT_DDI_C_LANES;
5218 case PORT_D:
5219 return POWER_DOMAIN_PORT_DDI_D_LANES;
5220 case PORT_E:
5221 return POWER_DOMAIN_PORT_DDI_E_LANES;
5222 default:
5223 MISSING_CASE(port);
5224 return POWER_DOMAIN_PORT_OTHER;
5225 }
5226 }
5227
5228 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5229 {
5230 switch (port) {
5231 case PORT_A:
5232 return POWER_DOMAIN_AUX_A;
5233 case PORT_B:
5234 return POWER_DOMAIN_AUX_B;
5235 case PORT_C:
5236 return POWER_DOMAIN_AUX_C;
5237 case PORT_D:
5238 return POWER_DOMAIN_AUX_D;
5239 case PORT_E:
5240 /* FIXME: Check VBT for actual wiring of PORT E */
5241 return POWER_DOMAIN_AUX_D;
5242 default:
5243 MISSING_CASE(port);
5244 return POWER_DOMAIN_AUX_A;
5245 }
5246 }
5247
5248 enum intel_display_power_domain
5249 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5250 {
5251 struct drm_device *dev = intel_encoder->base.dev;
5252 struct intel_digital_port *intel_dig_port;
5253
5254 switch (intel_encoder->type) {
5255 case INTEL_OUTPUT_UNKNOWN:
5256 /* Only DDI platforms should ever use this output type */
5257 WARN_ON_ONCE(!HAS_DDI(dev));
5258 case INTEL_OUTPUT_DISPLAYPORT:
5259 case INTEL_OUTPUT_HDMI:
5260 case INTEL_OUTPUT_EDP:
5261 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5262 return port_to_power_domain(intel_dig_port->port);
5263 case INTEL_OUTPUT_DP_MST:
5264 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5265 return port_to_power_domain(intel_dig_port->port);
5266 case INTEL_OUTPUT_ANALOG:
5267 return POWER_DOMAIN_PORT_CRT;
5268 case INTEL_OUTPUT_DSI:
5269 return POWER_DOMAIN_PORT_DSI;
5270 default:
5271 return POWER_DOMAIN_PORT_OTHER;
5272 }
5273 }
5274
5275 enum intel_display_power_domain
5276 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5277 {
5278 struct drm_device *dev = intel_encoder->base.dev;
5279 struct intel_digital_port *intel_dig_port;
5280
5281 switch (intel_encoder->type) {
5282 case INTEL_OUTPUT_UNKNOWN:
5283 case INTEL_OUTPUT_HDMI:
5284 /*
5285 * Only DDI platforms should ever use these output types.
5286 * We can get here after the HDMI detect code has already set
5287 * the type of the shared encoder. Since we can't be sure
5288 * what's the status of the given connectors, play safe and
5289 * run the DP detection too.
5290 */
5291 WARN_ON_ONCE(!HAS_DDI(dev));
5292 case INTEL_OUTPUT_DISPLAYPORT:
5293 case INTEL_OUTPUT_EDP:
5294 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5295 return port_to_aux_power_domain(intel_dig_port->port);
5296 case INTEL_OUTPUT_DP_MST:
5297 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5298 return port_to_aux_power_domain(intel_dig_port->port);
5299 default:
5300 MISSING_CASE(intel_encoder->type);
5301 return POWER_DOMAIN_AUX_A;
5302 }
5303 }
5304
5305 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5306 {
5307 struct drm_device *dev = crtc->dev;
5308 struct intel_encoder *intel_encoder;
5309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310 enum pipe pipe = intel_crtc->pipe;
5311 unsigned long mask;
5312 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5313
5314 if (!crtc->state->active)
5315 return 0;
5316
5317 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5318 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5319 if (intel_crtc->config->pch_pfit.enabled ||
5320 intel_crtc->config->pch_pfit.force_thru)
5321 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5322
5323 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5324 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5325
5326 return mask;
5327 }
5328
5329 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5330 {
5331 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333 enum intel_display_power_domain domain;
5334 unsigned long domains, new_domains, old_domains;
5335
5336 old_domains = intel_crtc->enabled_power_domains;
5337 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5338
5339 domains = new_domains & ~old_domains;
5340
5341 for_each_power_domain(domain, domains)
5342 intel_display_power_get(dev_priv, domain);
5343
5344 return old_domains & ~new_domains;
5345 }
5346
5347 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5348 unsigned long domains)
5349 {
5350 enum intel_display_power_domain domain;
5351
5352 for_each_power_domain(domain, domains)
5353 intel_display_power_put(dev_priv, domain);
5354 }
5355
5356 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5357 {
5358 struct drm_device *dev = state->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 unsigned long put_domains[I915_MAX_PIPES] = {};
5361 struct drm_crtc_state *crtc_state;
5362 struct drm_crtc *crtc;
5363 int i;
5364
5365 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5366 if (needs_modeset(crtc->state))
5367 put_domains[to_intel_crtc(crtc)->pipe] =
5368 modeset_get_crtc_power_domains(crtc);
5369 }
5370
5371 if (dev_priv->display.modeset_commit_cdclk) {
5372 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5373
5374 if (cdclk != dev_priv->cdclk_freq &&
5375 !WARN_ON(!state->allow_modeset))
5376 dev_priv->display.modeset_commit_cdclk(state);
5377 }
5378
5379 for (i = 0; i < I915_MAX_PIPES; i++)
5380 if (put_domains[i])
5381 modeset_put_power_domains(dev_priv, put_domains[i]);
5382 }
5383
5384 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5385 {
5386 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5387
5388 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5389 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5390 return max_cdclk_freq;
5391 else if (IS_CHERRYVIEW(dev_priv))
5392 return max_cdclk_freq*95/100;
5393 else if (INTEL_INFO(dev_priv)->gen < 4)
5394 return 2*max_cdclk_freq*90/100;
5395 else
5396 return max_cdclk_freq*90/100;
5397 }
5398
5399 static void intel_update_max_cdclk(struct drm_device *dev)
5400 {
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402
5403 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5404 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5405
5406 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5407 dev_priv->max_cdclk_freq = 675000;
5408 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5409 dev_priv->max_cdclk_freq = 540000;
5410 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5411 dev_priv->max_cdclk_freq = 450000;
5412 else
5413 dev_priv->max_cdclk_freq = 337500;
5414 } else if (IS_BROADWELL(dev)) {
5415 /*
5416 * FIXME with extra cooling we can allow
5417 * 540 MHz for ULX and 675 Mhz for ULT.
5418 * How can we know if extra cooling is
5419 * available? PCI ID, VTB, something else?
5420 */
5421 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5422 dev_priv->max_cdclk_freq = 450000;
5423 else if (IS_BDW_ULX(dev))
5424 dev_priv->max_cdclk_freq = 450000;
5425 else if (IS_BDW_ULT(dev))
5426 dev_priv->max_cdclk_freq = 540000;
5427 else
5428 dev_priv->max_cdclk_freq = 675000;
5429 } else if (IS_CHERRYVIEW(dev)) {
5430 dev_priv->max_cdclk_freq = 320000;
5431 } else if (IS_VALLEYVIEW(dev)) {
5432 dev_priv->max_cdclk_freq = 400000;
5433 } else {
5434 /* otherwise assume cdclk is fixed */
5435 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5436 }
5437
5438 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5439
5440 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5441 dev_priv->max_cdclk_freq);
5442
5443 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5444 dev_priv->max_dotclk_freq);
5445 }
5446
5447 static void intel_update_cdclk(struct drm_device *dev)
5448 {
5449 struct drm_i915_private *dev_priv = dev->dev_private;
5450
5451 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5452 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5453 dev_priv->cdclk_freq);
5454
5455 /*
5456 * Program the gmbus_freq based on the cdclk frequency.
5457 * BSpec erroneously claims we should aim for 4MHz, but
5458 * in fact 1MHz is the correct frequency.
5459 */
5460 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5461 /*
5462 * Program the gmbus_freq based on the cdclk frequency.
5463 * BSpec erroneously claims we should aim for 4MHz, but
5464 * in fact 1MHz is the correct frequency.
5465 */
5466 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5467 }
5468
5469 if (dev_priv->max_cdclk_freq == 0)
5470 intel_update_max_cdclk(dev);
5471 }
5472
5473 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5474 {
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 uint32_t divider;
5477 uint32_t ratio;
5478 uint32_t current_freq;
5479 int ret;
5480
5481 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5482 switch (frequency) {
5483 case 144000:
5484 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5485 ratio = BXT_DE_PLL_RATIO(60);
5486 break;
5487 case 288000:
5488 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5489 ratio = BXT_DE_PLL_RATIO(60);
5490 break;
5491 case 384000:
5492 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5493 ratio = BXT_DE_PLL_RATIO(60);
5494 break;
5495 case 576000:
5496 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5497 ratio = BXT_DE_PLL_RATIO(60);
5498 break;
5499 case 624000:
5500 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5501 ratio = BXT_DE_PLL_RATIO(65);
5502 break;
5503 case 19200:
5504 /*
5505 * Bypass frequency with DE PLL disabled. Init ratio, divider
5506 * to suppress GCC warning.
5507 */
5508 ratio = 0;
5509 divider = 0;
5510 break;
5511 default:
5512 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5513
5514 return;
5515 }
5516
5517 mutex_lock(&dev_priv->rps.hw_lock);
5518 /* Inform power controller of upcoming frequency change */
5519 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520 0x80000000);
5521 mutex_unlock(&dev_priv->rps.hw_lock);
5522
5523 if (ret) {
5524 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5525 ret, frequency);
5526 return;
5527 }
5528
5529 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5530 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5531 current_freq = current_freq * 500 + 1000;
5532
5533 /*
5534 * DE PLL has to be disabled when
5535 * - setting to 19.2MHz (bypass, PLL isn't used)
5536 * - before setting to 624MHz (PLL needs toggling)
5537 * - before setting to any frequency from 624MHz (PLL needs toggling)
5538 */
5539 if (frequency == 19200 || frequency == 624000 ||
5540 current_freq == 624000) {
5541 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5542 /* Timeout 200us */
5543 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5544 1))
5545 DRM_ERROR("timout waiting for DE PLL unlock\n");
5546 }
5547
5548 if (frequency != 19200) {
5549 uint32_t val;
5550
5551 val = I915_READ(BXT_DE_PLL_CTL);
5552 val &= ~BXT_DE_PLL_RATIO_MASK;
5553 val |= ratio;
5554 I915_WRITE(BXT_DE_PLL_CTL, val);
5555
5556 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5557 /* Timeout 200us */
5558 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5559 DRM_ERROR("timeout waiting for DE PLL lock\n");
5560
5561 val = I915_READ(CDCLK_CTL);
5562 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5563 val |= divider;
5564 /*
5565 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5566 * enable otherwise.
5567 */
5568 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5569 if (frequency >= 500000)
5570 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5571
5572 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5573 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5574 val |= (frequency - 1000) / 500;
5575 I915_WRITE(CDCLK_CTL, val);
5576 }
5577
5578 mutex_lock(&dev_priv->rps.hw_lock);
5579 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5580 DIV_ROUND_UP(frequency, 25000));
5581 mutex_unlock(&dev_priv->rps.hw_lock);
5582
5583 if (ret) {
5584 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5585 ret, frequency);
5586 return;
5587 }
5588
5589 intel_update_cdclk(dev);
5590 }
5591
5592 void broxton_init_cdclk(struct drm_device *dev)
5593 {
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5595 uint32_t val;
5596
5597 /*
5598 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5599 * or else the reset will hang because there is no PCH to respond.
5600 * Move the handshake programming to initialization sequence.
5601 * Previously was left up to BIOS.
5602 */
5603 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5604 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5605 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5606
5607 /* Enable PG1 for cdclk */
5608 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5609
5610 /* check if cd clock is enabled */
5611 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5612 DRM_DEBUG_KMS("Display already initialized\n");
5613 return;
5614 }
5615
5616 /*
5617 * FIXME:
5618 * - The initial CDCLK needs to be read from VBT.
5619 * Need to make this change after VBT has changes for BXT.
5620 * - check if setting the max (or any) cdclk freq is really necessary
5621 * here, it belongs to modeset time
5622 */
5623 broxton_set_cdclk(dev, 624000);
5624
5625 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5626 POSTING_READ(DBUF_CTL);
5627
5628 udelay(10);
5629
5630 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5631 DRM_ERROR("DBuf power enable timeout!\n");
5632 }
5633
5634 void broxton_uninit_cdclk(struct drm_device *dev)
5635 {
5636 struct drm_i915_private *dev_priv = dev->dev_private;
5637
5638 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5639 POSTING_READ(DBUF_CTL);
5640
5641 udelay(10);
5642
5643 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5644 DRM_ERROR("DBuf power disable timeout!\n");
5645
5646 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5647 broxton_set_cdclk(dev, 19200);
5648
5649 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5650 }
5651
5652 static const struct skl_cdclk_entry {
5653 unsigned int freq;
5654 unsigned int vco;
5655 } skl_cdclk_frequencies[] = {
5656 { .freq = 308570, .vco = 8640 },
5657 { .freq = 337500, .vco = 8100 },
5658 { .freq = 432000, .vco = 8640 },
5659 { .freq = 450000, .vco = 8100 },
5660 { .freq = 540000, .vco = 8100 },
5661 { .freq = 617140, .vco = 8640 },
5662 { .freq = 675000, .vco = 8100 },
5663 };
5664
5665 static unsigned int skl_cdclk_decimal(unsigned int freq)
5666 {
5667 return (freq - 1000) / 500;
5668 }
5669
5670 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5671 {
5672 unsigned int i;
5673
5674 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5675 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5676
5677 if (e->freq == freq)
5678 return e->vco;
5679 }
5680
5681 return 8100;
5682 }
5683
5684 static void
5685 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5686 {
5687 unsigned int min_freq;
5688 u32 val;
5689
5690 /* select the minimum CDCLK before enabling DPLL 0 */
5691 val = I915_READ(CDCLK_CTL);
5692 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5693 val |= CDCLK_FREQ_337_308;
5694
5695 if (required_vco == 8640)
5696 min_freq = 308570;
5697 else
5698 min_freq = 337500;
5699
5700 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5701
5702 I915_WRITE(CDCLK_CTL, val);
5703 POSTING_READ(CDCLK_CTL);
5704
5705 /*
5706 * We always enable DPLL0 with the lowest link rate possible, but still
5707 * taking into account the VCO required to operate the eDP panel at the
5708 * desired frequency. The usual DP link rates operate with a VCO of
5709 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5710 * The modeset code is responsible for the selection of the exact link
5711 * rate later on, with the constraint of choosing a frequency that
5712 * works with required_vco.
5713 */
5714 val = I915_READ(DPLL_CTRL1);
5715
5716 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5717 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5718 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5719 if (required_vco == 8640)
5720 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5721 SKL_DPLL0);
5722 else
5723 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5724 SKL_DPLL0);
5725
5726 I915_WRITE(DPLL_CTRL1, val);
5727 POSTING_READ(DPLL_CTRL1);
5728
5729 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5730
5731 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5732 DRM_ERROR("DPLL0 not locked\n");
5733 }
5734
5735 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5736 {
5737 int ret;
5738 u32 val;
5739
5740 /* inform PCU we want to change CDCLK */
5741 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5742 mutex_lock(&dev_priv->rps.hw_lock);
5743 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5744 mutex_unlock(&dev_priv->rps.hw_lock);
5745
5746 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5747 }
5748
5749 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5750 {
5751 unsigned int i;
5752
5753 for (i = 0; i < 15; i++) {
5754 if (skl_cdclk_pcu_ready(dev_priv))
5755 return true;
5756 udelay(10);
5757 }
5758
5759 return false;
5760 }
5761
5762 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5763 {
5764 struct drm_device *dev = dev_priv->dev;
5765 u32 freq_select, pcu_ack;
5766
5767 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5768
5769 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5770 DRM_ERROR("failed to inform PCU about cdclk change\n");
5771 return;
5772 }
5773
5774 /* set CDCLK_CTL */
5775 switch(freq) {
5776 case 450000:
5777 case 432000:
5778 freq_select = CDCLK_FREQ_450_432;
5779 pcu_ack = 1;
5780 break;
5781 case 540000:
5782 freq_select = CDCLK_FREQ_540;
5783 pcu_ack = 2;
5784 break;
5785 case 308570:
5786 case 337500:
5787 default:
5788 freq_select = CDCLK_FREQ_337_308;
5789 pcu_ack = 0;
5790 break;
5791 case 617140:
5792 case 675000:
5793 freq_select = CDCLK_FREQ_675_617;
5794 pcu_ack = 3;
5795 break;
5796 }
5797
5798 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5799 POSTING_READ(CDCLK_CTL);
5800
5801 /* inform PCU of the change */
5802 mutex_lock(&dev_priv->rps.hw_lock);
5803 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5804 mutex_unlock(&dev_priv->rps.hw_lock);
5805
5806 intel_update_cdclk(dev);
5807 }
5808
5809 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5810 {
5811 /* disable DBUF power */
5812 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5813 POSTING_READ(DBUF_CTL);
5814
5815 udelay(10);
5816
5817 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5818 DRM_ERROR("DBuf power disable timeout\n");
5819
5820 /* disable DPLL0 */
5821 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5822 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5823 DRM_ERROR("Couldn't disable DPLL0\n");
5824 }
5825
5826 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5827 {
5828 unsigned int required_vco;
5829
5830 /* DPLL0 not enabled (happens on early BIOS versions) */
5831 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5832 /* enable DPLL0 */
5833 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5834 skl_dpll0_enable(dev_priv, required_vco);
5835 }
5836
5837 /* set CDCLK to the frequency the BIOS chose */
5838 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5839
5840 /* enable DBUF power */
5841 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5842 POSTING_READ(DBUF_CTL);
5843
5844 udelay(10);
5845
5846 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5847 DRM_ERROR("DBuf power enable timeout\n");
5848 }
5849
5850 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5851 {
5852 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5853 uint32_t cdctl = I915_READ(CDCLK_CTL);
5854 int freq = dev_priv->skl_boot_cdclk;
5855
5856 /*
5857 * check if the pre-os intialized the display
5858 * There is SWF18 scratchpad register defined which is set by the
5859 * pre-os which can be used by the OS drivers to check the status
5860 */
5861 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5862 goto sanitize;
5863
5864 /* Is PLL enabled and locked ? */
5865 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5866 goto sanitize;
5867
5868 /* DPLL okay; verify the cdclock
5869 *
5870 * Noticed in some instances that the freq selection is correct but
5871 * decimal part is programmed wrong from BIOS where pre-os does not
5872 * enable display. Verify the same as well.
5873 */
5874 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5875 /* All well; nothing to sanitize */
5876 return false;
5877 sanitize:
5878 /*
5879 * As of now initialize with max cdclk till
5880 * we get dynamic cdclk support
5881 * */
5882 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5883 skl_init_cdclk(dev_priv);
5884
5885 /* we did have to sanitize */
5886 return true;
5887 }
5888
5889 /* Adjust CDclk dividers to allow high res or save power if possible */
5890 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5891 {
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893 u32 val, cmd;
5894
5895 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5896 != dev_priv->cdclk_freq);
5897
5898 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5899 cmd = 2;
5900 else if (cdclk == 266667)
5901 cmd = 1;
5902 else
5903 cmd = 0;
5904
5905 mutex_lock(&dev_priv->rps.hw_lock);
5906 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5907 val &= ~DSPFREQGUAR_MASK;
5908 val |= (cmd << DSPFREQGUAR_SHIFT);
5909 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5910 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5911 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5912 50)) {
5913 DRM_ERROR("timed out waiting for CDclk change\n");
5914 }
5915 mutex_unlock(&dev_priv->rps.hw_lock);
5916
5917 mutex_lock(&dev_priv->sb_lock);
5918
5919 if (cdclk == 400000) {
5920 u32 divider;
5921
5922 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5923
5924 /* adjust cdclk divider */
5925 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5926 val &= ~CCK_FREQUENCY_VALUES;
5927 val |= divider;
5928 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5929
5930 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5931 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5932 50))
5933 DRM_ERROR("timed out waiting for CDclk change\n");
5934 }
5935
5936 /* adjust self-refresh exit latency value */
5937 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5938 val &= ~0x7f;
5939
5940 /*
5941 * For high bandwidth configs, we set a higher latency in the bunit
5942 * so that the core display fetch happens in time to avoid underruns.
5943 */
5944 if (cdclk == 400000)
5945 val |= 4500 / 250; /* 4.5 usec */
5946 else
5947 val |= 3000 / 250; /* 3.0 usec */
5948 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5949
5950 mutex_unlock(&dev_priv->sb_lock);
5951
5952 intel_update_cdclk(dev);
5953 }
5954
5955 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5956 {
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958 u32 val, cmd;
5959
5960 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5961 != dev_priv->cdclk_freq);
5962
5963 switch (cdclk) {
5964 case 333333:
5965 case 320000:
5966 case 266667:
5967 case 200000:
5968 break;
5969 default:
5970 MISSING_CASE(cdclk);
5971 return;
5972 }
5973
5974 /*
5975 * Specs are full of misinformation, but testing on actual
5976 * hardware has shown that we just need to write the desired
5977 * CCK divider into the Punit register.
5978 */
5979 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5980
5981 mutex_lock(&dev_priv->rps.hw_lock);
5982 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5983 val &= ~DSPFREQGUAR_MASK_CHV;
5984 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5985 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5986 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5987 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5988 50)) {
5989 DRM_ERROR("timed out waiting for CDclk change\n");
5990 }
5991 mutex_unlock(&dev_priv->rps.hw_lock);
5992
5993 intel_update_cdclk(dev);
5994 }
5995
5996 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5997 int max_pixclk)
5998 {
5999 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6000 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6001
6002 /*
6003 * Really only a few cases to deal with, as only 4 CDclks are supported:
6004 * 200MHz
6005 * 267MHz
6006 * 320/333MHz (depends on HPLL freq)
6007 * 400MHz (VLV only)
6008 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6009 * of the lower bin and adjust if needed.
6010 *
6011 * We seem to get an unstable or solid color picture at 200MHz.
6012 * Not sure what's wrong. For now use 200MHz only when all pipes
6013 * are off.
6014 */
6015 if (!IS_CHERRYVIEW(dev_priv) &&
6016 max_pixclk > freq_320*limit/100)
6017 return 400000;
6018 else if (max_pixclk > 266667*limit/100)
6019 return freq_320;
6020 else if (max_pixclk > 0)
6021 return 266667;
6022 else
6023 return 200000;
6024 }
6025
6026 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6027 int max_pixclk)
6028 {
6029 /*
6030 * FIXME:
6031 * - remove the guardband, it's not needed on BXT
6032 * - set 19.2MHz bypass frequency if there are no active pipes
6033 */
6034 if (max_pixclk > 576000*9/10)
6035 return 624000;
6036 else if (max_pixclk > 384000*9/10)
6037 return 576000;
6038 else if (max_pixclk > 288000*9/10)
6039 return 384000;
6040 else if (max_pixclk > 144000*9/10)
6041 return 288000;
6042 else
6043 return 144000;
6044 }
6045
6046 /* Compute the max pixel clock for new configuration. Uses atomic state if
6047 * that's non-NULL, look at current state otherwise. */
6048 static int intel_mode_max_pixclk(struct drm_device *dev,
6049 struct drm_atomic_state *state)
6050 {
6051 struct intel_crtc *intel_crtc;
6052 struct intel_crtc_state *crtc_state;
6053 int max_pixclk = 0;
6054
6055 for_each_intel_crtc(dev, intel_crtc) {
6056 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6057 if (IS_ERR(crtc_state))
6058 return PTR_ERR(crtc_state);
6059
6060 if (!crtc_state->base.enable)
6061 continue;
6062
6063 max_pixclk = max(max_pixclk,
6064 crtc_state->base.adjusted_mode.crtc_clock);
6065 }
6066
6067 return max_pixclk;
6068 }
6069
6070 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6071 {
6072 struct drm_device *dev = state->dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074 int max_pixclk = intel_mode_max_pixclk(dev, state);
6075
6076 if (max_pixclk < 0)
6077 return max_pixclk;
6078
6079 to_intel_atomic_state(state)->cdclk =
6080 valleyview_calc_cdclk(dev_priv, max_pixclk);
6081
6082 return 0;
6083 }
6084
6085 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6086 {
6087 struct drm_device *dev = state->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 int max_pixclk = intel_mode_max_pixclk(dev, state);
6090
6091 if (max_pixclk < 0)
6092 return max_pixclk;
6093
6094 to_intel_atomic_state(state)->cdclk =
6095 broxton_calc_cdclk(dev_priv, max_pixclk);
6096
6097 return 0;
6098 }
6099
6100 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6101 {
6102 unsigned int credits, default_credits;
6103
6104 if (IS_CHERRYVIEW(dev_priv))
6105 default_credits = PFI_CREDIT(12);
6106 else
6107 default_credits = PFI_CREDIT(8);
6108
6109 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6110 /* CHV suggested value is 31 or 63 */
6111 if (IS_CHERRYVIEW(dev_priv))
6112 credits = PFI_CREDIT_63;
6113 else
6114 credits = PFI_CREDIT(15);
6115 } else {
6116 credits = default_credits;
6117 }
6118
6119 /*
6120 * WA - write default credits before re-programming
6121 * FIXME: should we also set the resend bit here?
6122 */
6123 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6124 default_credits);
6125
6126 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6127 credits | PFI_CREDIT_RESEND);
6128
6129 /*
6130 * FIXME is this guaranteed to clear
6131 * immediately or should we poll for it?
6132 */
6133 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6134 }
6135
6136 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6137 {
6138 struct drm_device *dev = old_state->dev;
6139 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142 /*
6143 * FIXME: We can end up here with all power domains off, yet
6144 * with a CDCLK frequency other than the minimum. To account
6145 * for this take the PIPE-A power domain, which covers the HW
6146 * blocks needed for the following programming. This can be
6147 * removed once it's guaranteed that we get here either with
6148 * the minimum CDCLK set, or the required power domains
6149 * enabled.
6150 */
6151 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6152
6153 if (IS_CHERRYVIEW(dev))
6154 cherryview_set_cdclk(dev, req_cdclk);
6155 else
6156 valleyview_set_cdclk(dev, req_cdclk);
6157
6158 vlv_program_pfi_credits(dev_priv);
6159
6160 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6161 }
6162
6163 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6164 {
6165 struct drm_device *dev = crtc->dev;
6166 struct drm_i915_private *dev_priv = to_i915(dev);
6167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168 struct intel_encoder *encoder;
6169 int pipe = intel_crtc->pipe;
6170
6171 if (WARN_ON(intel_crtc->active))
6172 return;
6173
6174 if (intel_crtc->config->has_dp_encoder)
6175 intel_dp_set_m_n(intel_crtc, M1_N1);
6176
6177 intel_set_pipe_timings(intel_crtc);
6178
6179 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181
6182 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6183 I915_WRITE(CHV_CANVAS(pipe), 0);
6184 }
6185
6186 i9xx_set_pipeconf(intel_crtc);
6187
6188 intel_crtc->active = true;
6189
6190 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6191
6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 if (encoder->pre_pll_enable)
6194 encoder->pre_pll_enable(encoder);
6195
6196 if (!intel_crtc->config->has_dsi_encoder) {
6197 if (IS_CHERRYVIEW(dev)) {
6198 chv_prepare_pll(intel_crtc, intel_crtc->config);
6199 chv_enable_pll(intel_crtc, intel_crtc->config);
6200 } else {
6201 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6202 vlv_enable_pll(intel_crtc, intel_crtc->config);
6203 }
6204 }
6205
6206 for_each_encoder_on_crtc(dev, crtc, encoder)
6207 if (encoder->pre_enable)
6208 encoder->pre_enable(encoder);
6209
6210 i9xx_pfit_enable(intel_crtc);
6211
6212 intel_crtc_load_lut(crtc);
6213
6214 intel_enable_pipe(intel_crtc);
6215
6216 assert_vblank_disabled(crtc);
6217 drm_crtc_vblank_on(crtc);
6218
6219 for_each_encoder_on_crtc(dev, crtc, encoder)
6220 encoder->enable(encoder);
6221 }
6222
6223 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6224 {
6225 struct drm_device *dev = crtc->base.dev;
6226 struct drm_i915_private *dev_priv = dev->dev_private;
6227
6228 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6229 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6230 }
6231
6232 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6233 {
6234 struct drm_device *dev = crtc->dev;
6235 struct drm_i915_private *dev_priv = to_i915(dev);
6236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237 struct intel_encoder *encoder;
6238 int pipe = intel_crtc->pipe;
6239
6240 if (WARN_ON(intel_crtc->active))
6241 return;
6242
6243 i9xx_set_pll_dividers(intel_crtc);
6244
6245 if (intel_crtc->config->has_dp_encoder)
6246 intel_dp_set_m_n(intel_crtc, M1_N1);
6247
6248 intel_set_pipe_timings(intel_crtc);
6249
6250 i9xx_set_pipeconf(intel_crtc);
6251
6252 intel_crtc->active = true;
6253
6254 if (!IS_GEN2(dev))
6255 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6256
6257 for_each_encoder_on_crtc(dev, crtc, encoder)
6258 if (encoder->pre_enable)
6259 encoder->pre_enable(encoder);
6260
6261 i9xx_enable_pll(intel_crtc);
6262
6263 i9xx_pfit_enable(intel_crtc);
6264
6265 intel_crtc_load_lut(crtc);
6266
6267 intel_update_watermarks(crtc);
6268 intel_enable_pipe(intel_crtc);
6269
6270 assert_vblank_disabled(crtc);
6271 drm_crtc_vblank_on(crtc);
6272
6273 for_each_encoder_on_crtc(dev, crtc, encoder)
6274 encoder->enable(encoder);
6275
6276 intel_fbc_enable(intel_crtc);
6277 }
6278
6279 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6280 {
6281 struct drm_device *dev = crtc->base.dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284 if (!crtc->config->gmch_pfit.control)
6285 return;
6286
6287 assert_pipe_disabled(dev_priv, crtc->pipe);
6288
6289 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6290 I915_READ(PFIT_CONTROL));
6291 I915_WRITE(PFIT_CONTROL, 0);
6292 }
6293
6294 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6295 {
6296 struct drm_device *dev = crtc->dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 struct intel_encoder *encoder;
6300 int pipe = intel_crtc->pipe;
6301
6302 /*
6303 * On gen2 planes are double buffered but the pipe isn't, so we must
6304 * wait for planes to fully turn off before disabling the pipe.
6305 * We also need to wait on all gmch platforms because of the
6306 * self-refresh mode constraint explained above.
6307 */
6308 intel_wait_for_vblank(dev, pipe);
6309
6310 for_each_encoder_on_crtc(dev, crtc, encoder)
6311 encoder->disable(encoder);
6312
6313 drm_crtc_vblank_off(crtc);
6314 assert_vblank_disabled(crtc);
6315
6316 intel_disable_pipe(intel_crtc);
6317
6318 i9xx_pfit_disable(intel_crtc);
6319
6320 for_each_encoder_on_crtc(dev, crtc, encoder)
6321 if (encoder->post_disable)
6322 encoder->post_disable(encoder);
6323
6324 if (!intel_crtc->config->has_dsi_encoder) {
6325 if (IS_CHERRYVIEW(dev))
6326 chv_disable_pll(dev_priv, pipe);
6327 else if (IS_VALLEYVIEW(dev))
6328 vlv_disable_pll(dev_priv, pipe);
6329 else
6330 i9xx_disable_pll(intel_crtc);
6331 }
6332
6333 for_each_encoder_on_crtc(dev, crtc, encoder)
6334 if (encoder->post_pll_disable)
6335 encoder->post_pll_disable(encoder);
6336
6337 if (!IS_GEN2(dev))
6338 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6339
6340 intel_fbc_disable_crtc(intel_crtc);
6341 }
6342
6343 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6344 {
6345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6347 enum intel_display_power_domain domain;
6348 unsigned long domains;
6349
6350 if (!intel_crtc->active)
6351 return;
6352
6353 if (to_intel_plane_state(crtc->primary->state)->visible) {
6354 WARN_ON(intel_crtc->unpin_work);
6355
6356 intel_pre_disable_primary(crtc);
6357
6358 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6359 to_intel_plane_state(crtc->primary->state)->visible = false;
6360 }
6361
6362 dev_priv->display.crtc_disable(crtc);
6363 intel_crtc->active = false;
6364 intel_update_watermarks(crtc);
6365 intel_disable_shared_dpll(intel_crtc);
6366
6367 domains = intel_crtc->enabled_power_domains;
6368 for_each_power_domain(domain, domains)
6369 intel_display_power_put(dev_priv, domain);
6370 intel_crtc->enabled_power_domains = 0;
6371 }
6372
6373 /*
6374 * turn all crtc's off, but do not adjust state
6375 * This has to be paired with a call to intel_modeset_setup_hw_state.
6376 */
6377 int intel_display_suspend(struct drm_device *dev)
6378 {
6379 struct drm_mode_config *config = &dev->mode_config;
6380 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6381 struct drm_atomic_state *state;
6382 struct drm_crtc *crtc;
6383 unsigned crtc_mask = 0;
6384 int ret = 0;
6385
6386 if (WARN_ON(!ctx))
6387 return 0;
6388
6389 lockdep_assert_held(&ctx->ww_ctx);
6390 state = drm_atomic_state_alloc(dev);
6391 if (WARN_ON(!state))
6392 return -ENOMEM;
6393
6394 state->acquire_ctx = ctx;
6395 state->allow_modeset = true;
6396
6397 for_each_crtc(dev, crtc) {
6398 struct drm_crtc_state *crtc_state =
6399 drm_atomic_get_crtc_state(state, crtc);
6400
6401 ret = PTR_ERR_OR_ZERO(crtc_state);
6402 if (ret)
6403 goto free;
6404
6405 if (!crtc_state->active)
6406 continue;
6407
6408 crtc_state->active = false;
6409 crtc_mask |= 1 << drm_crtc_index(crtc);
6410 }
6411
6412 if (crtc_mask) {
6413 ret = drm_atomic_commit(state);
6414
6415 if (!ret) {
6416 for_each_crtc(dev, crtc)
6417 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6418 crtc->state->active = true;
6419
6420 return ret;
6421 }
6422 }
6423
6424 free:
6425 if (ret)
6426 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6427 drm_atomic_state_free(state);
6428 return ret;
6429 }
6430
6431 void intel_encoder_destroy(struct drm_encoder *encoder)
6432 {
6433 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6434
6435 drm_encoder_cleanup(encoder);
6436 kfree(intel_encoder);
6437 }
6438
6439 /* Cross check the actual hw state with our own modeset state tracking (and it's
6440 * internal consistency). */
6441 static void intel_connector_check_state(struct intel_connector *connector)
6442 {
6443 struct drm_crtc *crtc = connector->base.state->crtc;
6444
6445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6446 connector->base.base.id,
6447 connector->base.name);
6448
6449 if (connector->get_hw_state(connector)) {
6450 struct intel_encoder *encoder = connector->encoder;
6451 struct drm_connector_state *conn_state = connector->base.state;
6452
6453 I915_STATE_WARN(!crtc,
6454 "connector enabled without attached crtc\n");
6455
6456 if (!crtc)
6457 return;
6458
6459 I915_STATE_WARN(!crtc->state->active,
6460 "connector is active, but attached crtc isn't\n");
6461
6462 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6463 return;
6464
6465 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6466 "atomic encoder doesn't match attached encoder\n");
6467
6468 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6469 "attached encoder crtc differs from connector crtc\n");
6470 } else {
6471 I915_STATE_WARN(crtc && crtc->state->active,
6472 "attached crtc is active, but connector isn't\n");
6473 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6474 "best encoder set without crtc!\n");
6475 }
6476 }
6477
6478 int intel_connector_init(struct intel_connector *connector)
6479 {
6480 struct drm_connector_state *connector_state;
6481
6482 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6483 if (!connector_state)
6484 return -ENOMEM;
6485
6486 connector->base.state = connector_state;
6487 return 0;
6488 }
6489
6490 struct intel_connector *intel_connector_alloc(void)
6491 {
6492 struct intel_connector *connector;
6493
6494 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6495 if (!connector)
6496 return NULL;
6497
6498 if (intel_connector_init(connector) < 0) {
6499 kfree(connector);
6500 return NULL;
6501 }
6502
6503 return connector;
6504 }
6505
6506 /* Simple connector->get_hw_state implementation for encoders that support only
6507 * one connector and no cloning and hence the encoder state determines the state
6508 * of the connector. */
6509 bool intel_connector_get_hw_state(struct intel_connector *connector)
6510 {
6511 enum pipe pipe = 0;
6512 struct intel_encoder *encoder = connector->encoder;
6513
6514 return encoder->get_hw_state(encoder, &pipe);
6515 }
6516
6517 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6518 {
6519 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6520 return crtc_state->fdi_lanes;
6521
6522 return 0;
6523 }
6524
6525 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6526 struct intel_crtc_state *pipe_config)
6527 {
6528 struct drm_atomic_state *state = pipe_config->base.state;
6529 struct intel_crtc *other_crtc;
6530 struct intel_crtc_state *other_crtc_state;
6531
6532 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6533 pipe_name(pipe), pipe_config->fdi_lanes);
6534 if (pipe_config->fdi_lanes > 4) {
6535 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6536 pipe_name(pipe), pipe_config->fdi_lanes);
6537 return -EINVAL;
6538 }
6539
6540 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6541 if (pipe_config->fdi_lanes > 2) {
6542 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6543 pipe_config->fdi_lanes);
6544 return -EINVAL;
6545 } else {
6546 return 0;
6547 }
6548 }
6549
6550 if (INTEL_INFO(dev)->num_pipes == 2)
6551 return 0;
6552
6553 /* Ivybridge 3 pipe is really complicated */
6554 switch (pipe) {
6555 case PIPE_A:
6556 return 0;
6557 case PIPE_B:
6558 if (pipe_config->fdi_lanes <= 2)
6559 return 0;
6560
6561 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6562 other_crtc_state =
6563 intel_atomic_get_crtc_state(state, other_crtc);
6564 if (IS_ERR(other_crtc_state))
6565 return PTR_ERR(other_crtc_state);
6566
6567 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6568 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6569 pipe_name(pipe), pipe_config->fdi_lanes);
6570 return -EINVAL;
6571 }
6572 return 0;
6573 case PIPE_C:
6574 if (pipe_config->fdi_lanes > 2) {
6575 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6576 pipe_name(pipe), pipe_config->fdi_lanes);
6577 return -EINVAL;
6578 }
6579
6580 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6581 other_crtc_state =
6582 intel_atomic_get_crtc_state(state, other_crtc);
6583 if (IS_ERR(other_crtc_state))
6584 return PTR_ERR(other_crtc_state);
6585
6586 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6587 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6588 return -EINVAL;
6589 }
6590 return 0;
6591 default:
6592 BUG();
6593 }
6594 }
6595
6596 #define RETRY 1
6597 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6598 struct intel_crtc_state *pipe_config)
6599 {
6600 struct drm_device *dev = intel_crtc->base.dev;
6601 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6602 int lane, link_bw, fdi_dotclock, ret;
6603 bool needs_recompute = false;
6604
6605 retry:
6606 /* FDI is a binary signal running at ~2.7GHz, encoding
6607 * each output octet as 10 bits. The actual frequency
6608 * is stored as a divider into a 100MHz clock, and the
6609 * mode pixel clock is stored in units of 1KHz.
6610 * Hence the bw of each lane in terms of the mode signal
6611 * is:
6612 */
6613 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6614
6615 fdi_dotclock = adjusted_mode->crtc_clock;
6616
6617 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6618 pipe_config->pipe_bpp);
6619
6620 pipe_config->fdi_lanes = lane;
6621
6622 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6623 link_bw, &pipe_config->fdi_m_n);
6624
6625 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6626 intel_crtc->pipe, pipe_config);
6627 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6628 pipe_config->pipe_bpp -= 2*3;
6629 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6630 pipe_config->pipe_bpp);
6631 needs_recompute = true;
6632 pipe_config->bw_constrained = true;
6633
6634 goto retry;
6635 }
6636
6637 if (needs_recompute)
6638 return RETRY;
6639
6640 return ret;
6641 }
6642
6643 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6644 struct intel_crtc_state *pipe_config)
6645 {
6646 if (pipe_config->pipe_bpp > 24)
6647 return false;
6648
6649 /* HSW can handle pixel rate up to cdclk? */
6650 if (IS_HASWELL(dev_priv->dev))
6651 return true;
6652
6653 /*
6654 * We compare against max which means we must take
6655 * the increased cdclk requirement into account when
6656 * calculating the new cdclk.
6657 *
6658 * Should measure whether using a lower cdclk w/o IPS
6659 */
6660 return ilk_pipe_pixel_rate(pipe_config) <=
6661 dev_priv->max_cdclk_freq * 95 / 100;
6662 }
6663
6664 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6665 struct intel_crtc_state *pipe_config)
6666 {
6667 struct drm_device *dev = crtc->base.dev;
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669
6670 pipe_config->ips_enabled = i915.enable_ips &&
6671 hsw_crtc_supports_ips(crtc) &&
6672 pipe_config_supports_ips(dev_priv, pipe_config);
6673 }
6674
6675 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6676 {
6677 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6678
6679 /* GDG double wide on either pipe, otherwise pipe A only */
6680 return INTEL_INFO(dev_priv)->gen < 4 &&
6681 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6682 }
6683
6684 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6685 struct intel_crtc_state *pipe_config)
6686 {
6687 struct drm_device *dev = crtc->base.dev;
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6690
6691 /* FIXME should check pixel clock limits on all platforms */
6692 if (INTEL_INFO(dev)->gen < 4) {
6693 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6694
6695 /*
6696 * Enable double wide mode when the dot clock
6697 * is > 90% of the (display) core speed.
6698 */
6699 if (intel_crtc_supports_double_wide(crtc) &&
6700 adjusted_mode->crtc_clock > clock_limit) {
6701 clock_limit *= 2;
6702 pipe_config->double_wide = true;
6703 }
6704
6705 if (adjusted_mode->crtc_clock > clock_limit) {
6706 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6707 adjusted_mode->crtc_clock, clock_limit,
6708 yesno(pipe_config->double_wide));
6709 return -EINVAL;
6710 }
6711 }
6712
6713 /*
6714 * Pipe horizontal size must be even in:
6715 * - DVO ganged mode
6716 * - LVDS dual channel mode
6717 * - Double wide pipe
6718 */
6719 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6720 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6721 pipe_config->pipe_src_w &= ~1;
6722
6723 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6724 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6725 */
6726 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6727 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6728 return -EINVAL;
6729
6730 if (HAS_IPS(dev))
6731 hsw_compute_ips_config(crtc, pipe_config);
6732
6733 if (pipe_config->has_pch_encoder)
6734 return ironlake_fdi_compute_config(crtc, pipe_config);
6735
6736 return 0;
6737 }
6738
6739 static int skylake_get_display_clock_speed(struct drm_device *dev)
6740 {
6741 struct drm_i915_private *dev_priv = to_i915(dev);
6742 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6743 uint32_t cdctl = I915_READ(CDCLK_CTL);
6744 uint32_t linkrate;
6745
6746 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6747 return 24000; /* 24MHz is the cd freq with NSSC ref */
6748
6749 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6750 return 540000;
6751
6752 linkrate = (I915_READ(DPLL_CTRL1) &
6753 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6754
6755 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6756 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6757 /* vco 8640 */
6758 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6759 case CDCLK_FREQ_450_432:
6760 return 432000;
6761 case CDCLK_FREQ_337_308:
6762 return 308570;
6763 case CDCLK_FREQ_675_617:
6764 return 617140;
6765 default:
6766 WARN(1, "Unknown cd freq selection\n");
6767 }
6768 } else {
6769 /* vco 8100 */
6770 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6771 case CDCLK_FREQ_450_432:
6772 return 450000;
6773 case CDCLK_FREQ_337_308:
6774 return 337500;
6775 case CDCLK_FREQ_675_617:
6776 return 675000;
6777 default:
6778 WARN(1, "Unknown cd freq selection\n");
6779 }
6780 }
6781
6782 /* error case, do as if DPLL0 isn't enabled */
6783 return 24000;
6784 }
6785
6786 static int broxton_get_display_clock_speed(struct drm_device *dev)
6787 {
6788 struct drm_i915_private *dev_priv = to_i915(dev);
6789 uint32_t cdctl = I915_READ(CDCLK_CTL);
6790 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6791 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6792 int cdclk;
6793
6794 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6795 return 19200;
6796
6797 cdclk = 19200 * pll_ratio / 2;
6798
6799 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6800 case BXT_CDCLK_CD2X_DIV_SEL_1:
6801 return cdclk; /* 576MHz or 624MHz */
6802 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6803 return cdclk * 2 / 3; /* 384MHz */
6804 case BXT_CDCLK_CD2X_DIV_SEL_2:
6805 return cdclk / 2; /* 288MHz */
6806 case BXT_CDCLK_CD2X_DIV_SEL_4:
6807 return cdclk / 4; /* 144MHz */
6808 }
6809
6810 /* error case, do as if DE PLL isn't enabled */
6811 return 19200;
6812 }
6813
6814 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6815 {
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817 uint32_t lcpll = I915_READ(LCPLL_CTL);
6818 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6819
6820 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6821 return 800000;
6822 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6823 return 450000;
6824 else if (freq == LCPLL_CLK_FREQ_450)
6825 return 450000;
6826 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6827 return 540000;
6828 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6829 return 337500;
6830 else
6831 return 675000;
6832 }
6833
6834 static int haswell_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 uint32_t lcpll = I915_READ(LCPLL_CTL);
6838 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6839
6840 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6841 return 800000;
6842 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6843 return 450000;
6844 else if (freq == LCPLL_CLK_FREQ_450)
6845 return 450000;
6846 else if (IS_HSW_ULT(dev))
6847 return 337500;
6848 else
6849 return 540000;
6850 }
6851
6852 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6853 {
6854 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6855 CCK_DISPLAY_CLOCK_CONTROL);
6856 }
6857
6858 static int ilk_get_display_clock_speed(struct drm_device *dev)
6859 {
6860 return 450000;
6861 }
6862
6863 static int i945_get_display_clock_speed(struct drm_device *dev)
6864 {
6865 return 400000;
6866 }
6867
6868 static int i915_get_display_clock_speed(struct drm_device *dev)
6869 {
6870 return 333333;
6871 }
6872
6873 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6874 {
6875 return 200000;
6876 }
6877
6878 static int pnv_get_display_clock_speed(struct drm_device *dev)
6879 {
6880 u16 gcfgc = 0;
6881
6882 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6883
6884 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6885 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6886 return 266667;
6887 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6888 return 333333;
6889 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6890 return 444444;
6891 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6892 return 200000;
6893 default:
6894 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6895 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6896 return 133333;
6897 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6898 return 166667;
6899 }
6900 }
6901
6902 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6903 {
6904 u16 gcfgc = 0;
6905
6906 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6907
6908 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6909 return 133333;
6910 else {
6911 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6912 case GC_DISPLAY_CLOCK_333_MHZ:
6913 return 333333;
6914 default:
6915 case GC_DISPLAY_CLOCK_190_200_MHZ:
6916 return 190000;
6917 }
6918 }
6919 }
6920
6921 static int i865_get_display_clock_speed(struct drm_device *dev)
6922 {
6923 return 266667;
6924 }
6925
6926 static int i85x_get_display_clock_speed(struct drm_device *dev)
6927 {
6928 u16 hpllcc = 0;
6929
6930 /*
6931 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6932 * encoding is different :(
6933 * FIXME is this the right way to detect 852GM/852GMV?
6934 */
6935 if (dev->pdev->revision == 0x1)
6936 return 133333;
6937
6938 pci_bus_read_config_word(dev->pdev->bus,
6939 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6940
6941 /* Assume that the hardware is in the high speed state. This
6942 * should be the default.
6943 */
6944 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6945 case GC_CLOCK_133_200:
6946 case GC_CLOCK_133_200_2:
6947 case GC_CLOCK_100_200:
6948 return 200000;
6949 case GC_CLOCK_166_250:
6950 return 250000;
6951 case GC_CLOCK_100_133:
6952 return 133333;
6953 case GC_CLOCK_133_266:
6954 case GC_CLOCK_133_266_2:
6955 case GC_CLOCK_166_266:
6956 return 266667;
6957 }
6958
6959 /* Shouldn't happen */
6960 return 0;
6961 }
6962
6963 static int i830_get_display_clock_speed(struct drm_device *dev)
6964 {
6965 return 133333;
6966 }
6967
6968 static unsigned int intel_hpll_vco(struct drm_device *dev)
6969 {
6970 struct drm_i915_private *dev_priv = dev->dev_private;
6971 static const unsigned int blb_vco[8] = {
6972 [0] = 3200000,
6973 [1] = 4000000,
6974 [2] = 5333333,
6975 [3] = 4800000,
6976 [4] = 6400000,
6977 };
6978 static const unsigned int pnv_vco[8] = {
6979 [0] = 3200000,
6980 [1] = 4000000,
6981 [2] = 5333333,
6982 [3] = 4800000,
6983 [4] = 2666667,
6984 };
6985 static const unsigned int cl_vco[8] = {
6986 [0] = 3200000,
6987 [1] = 4000000,
6988 [2] = 5333333,
6989 [3] = 6400000,
6990 [4] = 3333333,
6991 [5] = 3566667,
6992 [6] = 4266667,
6993 };
6994 static const unsigned int elk_vco[8] = {
6995 [0] = 3200000,
6996 [1] = 4000000,
6997 [2] = 5333333,
6998 [3] = 4800000,
6999 };
7000 static const unsigned int ctg_vco[8] = {
7001 [0] = 3200000,
7002 [1] = 4000000,
7003 [2] = 5333333,
7004 [3] = 6400000,
7005 [4] = 2666667,
7006 [5] = 4266667,
7007 };
7008 const unsigned int *vco_table;
7009 unsigned int vco;
7010 uint8_t tmp = 0;
7011
7012 /* FIXME other chipsets? */
7013 if (IS_GM45(dev))
7014 vco_table = ctg_vco;
7015 else if (IS_G4X(dev))
7016 vco_table = elk_vco;
7017 else if (IS_CRESTLINE(dev))
7018 vco_table = cl_vco;
7019 else if (IS_PINEVIEW(dev))
7020 vco_table = pnv_vco;
7021 else if (IS_G33(dev))
7022 vco_table = blb_vco;
7023 else
7024 return 0;
7025
7026 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7027
7028 vco = vco_table[tmp & 0x7];
7029 if (vco == 0)
7030 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7031 else
7032 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7033
7034 return vco;
7035 }
7036
7037 static int gm45_get_display_clock_speed(struct drm_device *dev)
7038 {
7039 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7040 uint16_t tmp = 0;
7041
7042 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7043
7044 cdclk_sel = (tmp >> 12) & 0x1;
7045
7046 switch (vco) {
7047 case 2666667:
7048 case 4000000:
7049 case 5333333:
7050 return cdclk_sel ? 333333 : 222222;
7051 case 3200000:
7052 return cdclk_sel ? 320000 : 228571;
7053 default:
7054 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7055 return 222222;
7056 }
7057 }
7058
7059 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7060 {
7061 static const uint8_t div_3200[] = { 16, 10, 8 };
7062 static const uint8_t div_4000[] = { 20, 12, 10 };
7063 static const uint8_t div_5333[] = { 24, 16, 14 };
7064 const uint8_t *div_table;
7065 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7066 uint16_t tmp = 0;
7067
7068 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7069
7070 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7071
7072 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7073 goto fail;
7074
7075 switch (vco) {
7076 case 3200000:
7077 div_table = div_3200;
7078 break;
7079 case 4000000:
7080 div_table = div_4000;
7081 break;
7082 case 5333333:
7083 div_table = div_5333;
7084 break;
7085 default:
7086 goto fail;
7087 }
7088
7089 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7090
7091 fail:
7092 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7093 return 200000;
7094 }
7095
7096 static int g33_get_display_clock_speed(struct drm_device *dev)
7097 {
7098 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7099 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7100 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7101 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7102 const uint8_t *div_table;
7103 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7104 uint16_t tmp = 0;
7105
7106 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7107
7108 cdclk_sel = (tmp >> 4) & 0x7;
7109
7110 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7111 goto fail;
7112
7113 switch (vco) {
7114 case 3200000:
7115 div_table = div_3200;
7116 break;
7117 case 4000000:
7118 div_table = div_4000;
7119 break;
7120 case 4800000:
7121 div_table = div_4800;
7122 break;
7123 case 5333333:
7124 div_table = div_5333;
7125 break;
7126 default:
7127 goto fail;
7128 }
7129
7130 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7131
7132 fail:
7133 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7134 return 190476;
7135 }
7136
7137 static void
7138 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7139 {
7140 while (*num > DATA_LINK_M_N_MASK ||
7141 *den > DATA_LINK_M_N_MASK) {
7142 *num >>= 1;
7143 *den >>= 1;
7144 }
7145 }
7146
7147 static void compute_m_n(unsigned int m, unsigned int n,
7148 uint32_t *ret_m, uint32_t *ret_n)
7149 {
7150 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7151 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7152 intel_reduce_m_n_ratio(ret_m, ret_n);
7153 }
7154
7155 void
7156 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7157 int pixel_clock, int link_clock,
7158 struct intel_link_m_n *m_n)
7159 {
7160 m_n->tu = 64;
7161
7162 compute_m_n(bits_per_pixel * pixel_clock,
7163 link_clock * nlanes * 8,
7164 &m_n->gmch_m, &m_n->gmch_n);
7165
7166 compute_m_n(pixel_clock, link_clock,
7167 &m_n->link_m, &m_n->link_n);
7168 }
7169
7170 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7171 {
7172 if (i915.panel_use_ssc >= 0)
7173 return i915.panel_use_ssc != 0;
7174 return dev_priv->vbt.lvds_use_ssc
7175 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7176 }
7177
7178 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7179 int num_connectors)
7180 {
7181 struct drm_device *dev = crtc_state->base.crtc->dev;
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 int refclk;
7184
7185 WARN_ON(!crtc_state->base.state);
7186
7187 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7188 refclk = 100000;
7189 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7190 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7191 refclk = dev_priv->vbt.lvds_ssc_freq;
7192 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7193 } else if (!IS_GEN2(dev)) {
7194 refclk = 96000;
7195 } else {
7196 refclk = 48000;
7197 }
7198
7199 return refclk;
7200 }
7201
7202 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7203 {
7204 return (1 << dpll->n) << 16 | dpll->m2;
7205 }
7206
7207 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7208 {
7209 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7210 }
7211
7212 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7213 struct intel_crtc_state *crtc_state,
7214 intel_clock_t *reduced_clock)
7215 {
7216 struct drm_device *dev = crtc->base.dev;
7217 u32 fp, fp2 = 0;
7218
7219 if (IS_PINEVIEW(dev)) {
7220 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7221 if (reduced_clock)
7222 fp2 = pnv_dpll_compute_fp(reduced_clock);
7223 } else {
7224 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7225 if (reduced_clock)
7226 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7227 }
7228
7229 crtc_state->dpll_hw_state.fp0 = fp;
7230
7231 crtc->lowfreq_avail = false;
7232 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7233 reduced_clock) {
7234 crtc_state->dpll_hw_state.fp1 = fp2;
7235 crtc->lowfreq_avail = true;
7236 } else {
7237 crtc_state->dpll_hw_state.fp1 = fp;
7238 }
7239 }
7240
7241 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7242 pipe)
7243 {
7244 u32 reg_val;
7245
7246 /*
7247 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7248 * and set it to a reasonable value instead.
7249 */
7250 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7251 reg_val &= 0xffffff00;
7252 reg_val |= 0x00000030;
7253 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7254
7255 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7256 reg_val &= 0x8cffffff;
7257 reg_val = 0x8c000000;
7258 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7259
7260 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7261 reg_val &= 0xffffff00;
7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7263
7264 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7265 reg_val &= 0x00ffffff;
7266 reg_val |= 0xb0000000;
7267 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7268 }
7269
7270 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7271 struct intel_link_m_n *m_n)
7272 {
7273 struct drm_device *dev = crtc->base.dev;
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 int pipe = crtc->pipe;
7276
7277 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7278 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7279 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7280 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7281 }
7282
7283 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7284 struct intel_link_m_n *m_n,
7285 struct intel_link_m_n *m2_n2)
7286 {
7287 struct drm_device *dev = crtc->base.dev;
7288 struct drm_i915_private *dev_priv = dev->dev_private;
7289 int pipe = crtc->pipe;
7290 enum transcoder transcoder = crtc->config->cpu_transcoder;
7291
7292 if (INTEL_INFO(dev)->gen >= 5) {
7293 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7294 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7295 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7296 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7297 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7298 * for gen < 8) and if DRRS is supported (to make sure the
7299 * registers are not unnecessarily accessed).
7300 */
7301 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7302 crtc->config->has_drrs) {
7303 I915_WRITE(PIPE_DATA_M2(transcoder),
7304 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7305 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7306 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7307 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7308 }
7309 } else {
7310 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7311 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7312 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7313 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7314 }
7315 }
7316
7317 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7318 {
7319 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7320
7321 if (m_n == M1_N1) {
7322 dp_m_n = &crtc->config->dp_m_n;
7323 dp_m2_n2 = &crtc->config->dp_m2_n2;
7324 } else if (m_n == M2_N2) {
7325
7326 /*
7327 * M2_N2 registers are not supported. Hence m2_n2 divider value
7328 * needs to be programmed into M1_N1.
7329 */
7330 dp_m_n = &crtc->config->dp_m2_n2;
7331 } else {
7332 DRM_ERROR("Unsupported divider value\n");
7333 return;
7334 }
7335
7336 if (crtc->config->has_pch_encoder)
7337 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7338 else
7339 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7340 }
7341
7342 static void vlv_compute_dpll(struct intel_crtc *crtc,
7343 struct intel_crtc_state *pipe_config)
7344 {
7345 u32 dpll, dpll_md;
7346
7347 /*
7348 * Enable DPIO clock input. We should never disable the reference
7349 * clock for pipe B, since VGA hotplug / manual detection depends
7350 * on it.
7351 */
7352 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7353 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7354 /* We should never disable this, set it here for state tracking */
7355 if (crtc->pipe == PIPE_B)
7356 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7357 dpll |= DPLL_VCO_ENABLE;
7358 pipe_config->dpll_hw_state.dpll = dpll;
7359
7360 dpll_md = (pipe_config->pixel_multiplier - 1)
7361 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7362 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7363 }
7364
7365 static void vlv_prepare_pll(struct intel_crtc *crtc,
7366 const struct intel_crtc_state *pipe_config)
7367 {
7368 struct drm_device *dev = crtc->base.dev;
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 int pipe = crtc->pipe;
7371 u32 mdiv;
7372 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7373 u32 coreclk, reg_val;
7374
7375 mutex_lock(&dev_priv->sb_lock);
7376
7377 bestn = pipe_config->dpll.n;
7378 bestm1 = pipe_config->dpll.m1;
7379 bestm2 = pipe_config->dpll.m2;
7380 bestp1 = pipe_config->dpll.p1;
7381 bestp2 = pipe_config->dpll.p2;
7382
7383 /* See eDP HDMI DPIO driver vbios notes doc */
7384
7385 /* PLL B needs special handling */
7386 if (pipe == PIPE_B)
7387 vlv_pllb_recal_opamp(dev_priv, pipe);
7388
7389 /* Set up Tx target for periodic Rcomp update */
7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7391
7392 /* Disable target IRef on PLL */
7393 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7394 reg_val &= 0x00ffffff;
7395 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7396
7397 /* Disable fast lock */
7398 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7399
7400 /* Set idtafcrecal before PLL is enabled */
7401 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7402 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7403 mdiv |= ((bestn << DPIO_N_SHIFT));
7404 mdiv |= (1 << DPIO_K_SHIFT);
7405
7406 /*
7407 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7408 * but we don't support that).
7409 * Note: don't use the DAC post divider as it seems unstable.
7410 */
7411 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7412 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7413
7414 mdiv |= DPIO_ENABLE_CALIBRATION;
7415 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7416
7417 /* Set HBR and RBR LPF coefficients */
7418 if (pipe_config->port_clock == 162000 ||
7419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7420 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7421 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7422 0x009f0003);
7423 else
7424 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7425 0x00d0000f);
7426
7427 if (pipe_config->has_dp_encoder) {
7428 /* Use SSC source */
7429 if (pipe == PIPE_A)
7430 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7431 0x0df40000);
7432 else
7433 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7434 0x0df70000);
7435 } else { /* HDMI or VGA */
7436 /* Use bend source */
7437 if (pipe == PIPE_A)
7438 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7439 0x0df70000);
7440 else
7441 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7442 0x0df40000);
7443 }
7444
7445 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7446 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7447 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7448 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7449 coreclk |= 0x01000000;
7450 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7451
7452 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7453 mutex_unlock(&dev_priv->sb_lock);
7454 }
7455
7456 static void chv_compute_dpll(struct intel_crtc *crtc,
7457 struct intel_crtc_state *pipe_config)
7458 {
7459 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7460 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7461 DPLL_VCO_ENABLE;
7462 if (crtc->pipe != PIPE_A)
7463 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7464
7465 pipe_config->dpll_hw_state.dpll_md =
7466 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7467 }
7468
7469 static void chv_prepare_pll(struct intel_crtc *crtc,
7470 const struct intel_crtc_state *pipe_config)
7471 {
7472 struct drm_device *dev = crtc->base.dev;
7473 struct drm_i915_private *dev_priv = dev->dev_private;
7474 int pipe = crtc->pipe;
7475 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7476 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7477 u32 loopfilter, tribuf_calcntr;
7478 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7479 u32 dpio_val;
7480 int vco;
7481
7482 bestn = pipe_config->dpll.n;
7483 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7484 bestm1 = pipe_config->dpll.m1;
7485 bestm2 = pipe_config->dpll.m2 >> 22;
7486 bestp1 = pipe_config->dpll.p1;
7487 bestp2 = pipe_config->dpll.p2;
7488 vco = pipe_config->dpll.vco;
7489 dpio_val = 0;
7490 loopfilter = 0;
7491
7492 /*
7493 * Enable Refclk and SSC
7494 */
7495 I915_WRITE(dpll_reg,
7496 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7497
7498 mutex_lock(&dev_priv->sb_lock);
7499
7500 /* p1 and p2 divider */
7501 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7502 5 << DPIO_CHV_S1_DIV_SHIFT |
7503 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7504 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7505 1 << DPIO_CHV_K_DIV_SHIFT);
7506
7507 /* Feedback post-divider - m2 */
7508 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7509
7510 /* Feedback refclk divider - n and m1 */
7511 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7512 DPIO_CHV_M1_DIV_BY_2 |
7513 1 << DPIO_CHV_N_DIV_SHIFT);
7514
7515 /* M2 fraction division */
7516 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7517
7518 /* M2 fraction division enable */
7519 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7520 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7521 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7522 if (bestm2_frac)
7523 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7524 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7525
7526 /* Program digital lock detect threshold */
7527 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7528 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7529 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7530 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7531 if (!bestm2_frac)
7532 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7533 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7534
7535 /* Loop filter */
7536 if (vco == 5400000) {
7537 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7538 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7539 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7540 tribuf_calcntr = 0x9;
7541 } else if (vco <= 6200000) {
7542 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7543 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7544 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7545 tribuf_calcntr = 0x9;
7546 } else if (vco <= 6480000) {
7547 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7548 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7549 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7550 tribuf_calcntr = 0x8;
7551 } else {
7552 /* Not supported. Apply the same limits as in the max case */
7553 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7554 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7555 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7556 tribuf_calcntr = 0;
7557 }
7558 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7559
7560 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7561 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7562 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7563 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7564
7565 /* AFC Recal */
7566 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7567 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7568 DPIO_AFC_RECAL);
7569
7570 mutex_unlock(&dev_priv->sb_lock);
7571 }
7572
7573 /**
7574 * vlv_force_pll_on - forcibly enable just the PLL
7575 * @dev_priv: i915 private structure
7576 * @pipe: pipe PLL to enable
7577 * @dpll: PLL configuration
7578 *
7579 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7580 * in cases where we need the PLL enabled even when @pipe is not going to
7581 * be enabled.
7582 */
7583 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7584 const struct dpll *dpll)
7585 {
7586 struct intel_crtc *crtc =
7587 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7588 struct intel_crtc_state pipe_config = {
7589 .base.crtc = &crtc->base,
7590 .pixel_multiplier = 1,
7591 .dpll = *dpll,
7592 };
7593
7594 if (IS_CHERRYVIEW(dev)) {
7595 chv_compute_dpll(crtc, &pipe_config);
7596 chv_prepare_pll(crtc, &pipe_config);
7597 chv_enable_pll(crtc, &pipe_config);
7598 } else {
7599 vlv_compute_dpll(crtc, &pipe_config);
7600 vlv_prepare_pll(crtc, &pipe_config);
7601 vlv_enable_pll(crtc, &pipe_config);
7602 }
7603 }
7604
7605 /**
7606 * vlv_force_pll_off - forcibly disable just the PLL
7607 * @dev_priv: i915 private structure
7608 * @pipe: pipe PLL to disable
7609 *
7610 * Disable the PLL for @pipe. To be used in cases where we need
7611 * the PLL enabled even when @pipe is not going to be enabled.
7612 */
7613 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7614 {
7615 if (IS_CHERRYVIEW(dev))
7616 chv_disable_pll(to_i915(dev), pipe);
7617 else
7618 vlv_disable_pll(to_i915(dev), pipe);
7619 }
7620
7621 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7622 struct intel_crtc_state *crtc_state,
7623 intel_clock_t *reduced_clock,
7624 int num_connectors)
7625 {
7626 struct drm_device *dev = crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 u32 dpll;
7629 bool is_sdvo;
7630 struct dpll *clock = &crtc_state->dpll;
7631
7632 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7633
7634 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7635 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7636
7637 dpll = DPLL_VGA_MODE_DIS;
7638
7639 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7640 dpll |= DPLLB_MODE_LVDS;
7641 else
7642 dpll |= DPLLB_MODE_DAC_SERIAL;
7643
7644 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7645 dpll |= (crtc_state->pixel_multiplier - 1)
7646 << SDVO_MULTIPLIER_SHIFT_HIRES;
7647 }
7648
7649 if (is_sdvo)
7650 dpll |= DPLL_SDVO_HIGH_SPEED;
7651
7652 if (crtc_state->has_dp_encoder)
7653 dpll |= DPLL_SDVO_HIGH_SPEED;
7654
7655 /* compute bitmask from p1 value */
7656 if (IS_PINEVIEW(dev))
7657 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7658 else {
7659 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7660 if (IS_G4X(dev) && reduced_clock)
7661 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7662 }
7663 switch (clock->p2) {
7664 case 5:
7665 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7666 break;
7667 case 7:
7668 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7669 break;
7670 case 10:
7671 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7672 break;
7673 case 14:
7674 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7675 break;
7676 }
7677 if (INTEL_INFO(dev)->gen >= 4)
7678 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7679
7680 if (crtc_state->sdvo_tv_clock)
7681 dpll |= PLL_REF_INPUT_TVCLKINBC;
7682 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7683 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7684 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7685 else
7686 dpll |= PLL_REF_INPUT_DREFCLK;
7687
7688 dpll |= DPLL_VCO_ENABLE;
7689 crtc_state->dpll_hw_state.dpll = dpll;
7690
7691 if (INTEL_INFO(dev)->gen >= 4) {
7692 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7693 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7694 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7695 }
7696 }
7697
7698 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7699 struct intel_crtc_state *crtc_state,
7700 intel_clock_t *reduced_clock,
7701 int num_connectors)
7702 {
7703 struct drm_device *dev = crtc->base.dev;
7704 struct drm_i915_private *dev_priv = dev->dev_private;
7705 u32 dpll;
7706 struct dpll *clock = &crtc_state->dpll;
7707
7708 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7709
7710 dpll = DPLL_VGA_MODE_DIS;
7711
7712 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7713 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7714 } else {
7715 if (clock->p1 == 2)
7716 dpll |= PLL_P1_DIVIDE_BY_TWO;
7717 else
7718 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7719 if (clock->p2 == 4)
7720 dpll |= PLL_P2_DIVIDE_BY_4;
7721 }
7722
7723 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7724 dpll |= DPLL_DVO_2X_MODE;
7725
7726 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7727 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7728 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7729 else
7730 dpll |= PLL_REF_INPUT_DREFCLK;
7731
7732 dpll |= DPLL_VCO_ENABLE;
7733 crtc_state->dpll_hw_state.dpll = dpll;
7734 }
7735
7736 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7737 {
7738 struct drm_device *dev = intel_crtc->base.dev;
7739 struct drm_i915_private *dev_priv = dev->dev_private;
7740 enum pipe pipe = intel_crtc->pipe;
7741 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7742 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7743 uint32_t crtc_vtotal, crtc_vblank_end;
7744 int vsyncshift = 0;
7745
7746 /* We need to be careful not to changed the adjusted mode, for otherwise
7747 * the hw state checker will get angry at the mismatch. */
7748 crtc_vtotal = adjusted_mode->crtc_vtotal;
7749 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7750
7751 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7752 /* the chip adds 2 halflines automatically */
7753 crtc_vtotal -= 1;
7754 crtc_vblank_end -= 1;
7755
7756 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7757 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7758 else
7759 vsyncshift = adjusted_mode->crtc_hsync_start -
7760 adjusted_mode->crtc_htotal / 2;
7761 if (vsyncshift < 0)
7762 vsyncshift += adjusted_mode->crtc_htotal;
7763 }
7764
7765 if (INTEL_INFO(dev)->gen > 3)
7766 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7767
7768 I915_WRITE(HTOTAL(cpu_transcoder),
7769 (adjusted_mode->crtc_hdisplay - 1) |
7770 ((adjusted_mode->crtc_htotal - 1) << 16));
7771 I915_WRITE(HBLANK(cpu_transcoder),
7772 (adjusted_mode->crtc_hblank_start - 1) |
7773 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7774 I915_WRITE(HSYNC(cpu_transcoder),
7775 (adjusted_mode->crtc_hsync_start - 1) |
7776 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7777
7778 I915_WRITE(VTOTAL(cpu_transcoder),
7779 (adjusted_mode->crtc_vdisplay - 1) |
7780 ((crtc_vtotal - 1) << 16));
7781 I915_WRITE(VBLANK(cpu_transcoder),
7782 (adjusted_mode->crtc_vblank_start - 1) |
7783 ((crtc_vblank_end - 1) << 16));
7784 I915_WRITE(VSYNC(cpu_transcoder),
7785 (adjusted_mode->crtc_vsync_start - 1) |
7786 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7787
7788 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7789 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7790 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7791 * bits. */
7792 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7793 (pipe == PIPE_B || pipe == PIPE_C))
7794 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7795
7796 /* pipesrc controls the size that is scaled from, which should
7797 * always be the user's requested size.
7798 */
7799 I915_WRITE(PIPESRC(pipe),
7800 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7801 (intel_crtc->config->pipe_src_h - 1));
7802 }
7803
7804 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7805 struct intel_crtc_state *pipe_config)
7806 {
7807 struct drm_device *dev = crtc->base.dev;
7808 struct drm_i915_private *dev_priv = dev->dev_private;
7809 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7810 uint32_t tmp;
7811
7812 tmp = I915_READ(HTOTAL(cpu_transcoder));
7813 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7814 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7815 tmp = I915_READ(HBLANK(cpu_transcoder));
7816 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7817 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7818 tmp = I915_READ(HSYNC(cpu_transcoder));
7819 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7820 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7821
7822 tmp = I915_READ(VTOTAL(cpu_transcoder));
7823 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7824 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7825 tmp = I915_READ(VBLANK(cpu_transcoder));
7826 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7827 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7828 tmp = I915_READ(VSYNC(cpu_transcoder));
7829 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7830 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7831
7832 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7833 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7834 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7835 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7836 }
7837
7838 tmp = I915_READ(PIPESRC(crtc->pipe));
7839 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7840 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7841
7842 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7843 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7844 }
7845
7846 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7847 struct intel_crtc_state *pipe_config)
7848 {
7849 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7850 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7851 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7852 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7853
7854 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7855 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7856 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7857 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7858
7859 mode->flags = pipe_config->base.adjusted_mode.flags;
7860 mode->type = DRM_MODE_TYPE_DRIVER;
7861
7862 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7863 mode->flags |= pipe_config->base.adjusted_mode.flags;
7864
7865 mode->hsync = drm_mode_hsync(mode);
7866 mode->vrefresh = drm_mode_vrefresh(mode);
7867 drm_mode_set_name(mode);
7868 }
7869
7870 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7871 {
7872 struct drm_device *dev = intel_crtc->base.dev;
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 uint32_t pipeconf;
7875
7876 pipeconf = 0;
7877
7878 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7879 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7880 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7881
7882 if (intel_crtc->config->double_wide)
7883 pipeconf |= PIPECONF_DOUBLE_WIDE;
7884
7885 /* only g4x and later have fancy bpc/dither controls */
7886 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7887 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7888 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7889 pipeconf |= PIPECONF_DITHER_EN |
7890 PIPECONF_DITHER_TYPE_SP;
7891
7892 switch (intel_crtc->config->pipe_bpp) {
7893 case 18:
7894 pipeconf |= PIPECONF_6BPC;
7895 break;
7896 case 24:
7897 pipeconf |= PIPECONF_8BPC;
7898 break;
7899 case 30:
7900 pipeconf |= PIPECONF_10BPC;
7901 break;
7902 default:
7903 /* Case prevented by intel_choose_pipe_bpp_dither. */
7904 BUG();
7905 }
7906 }
7907
7908 if (HAS_PIPE_CXSR(dev)) {
7909 if (intel_crtc->lowfreq_avail) {
7910 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7911 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7912 } else {
7913 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7914 }
7915 }
7916
7917 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7918 if (INTEL_INFO(dev)->gen < 4 ||
7919 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7920 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7921 else
7922 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7923 } else
7924 pipeconf |= PIPECONF_PROGRESSIVE;
7925
7926 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7927 intel_crtc->config->limited_color_range)
7928 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7929
7930 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7931 POSTING_READ(PIPECONF(intel_crtc->pipe));
7932 }
7933
7934 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7935 struct intel_crtc_state *crtc_state)
7936 {
7937 struct drm_device *dev = crtc->base.dev;
7938 struct drm_i915_private *dev_priv = dev->dev_private;
7939 int refclk, num_connectors = 0;
7940 intel_clock_t clock;
7941 bool ok;
7942 const intel_limit_t *limit;
7943 struct drm_atomic_state *state = crtc_state->base.state;
7944 struct drm_connector *connector;
7945 struct drm_connector_state *connector_state;
7946 int i;
7947
7948 memset(&crtc_state->dpll_hw_state, 0,
7949 sizeof(crtc_state->dpll_hw_state));
7950
7951 if (crtc_state->has_dsi_encoder)
7952 return 0;
7953
7954 for_each_connector_in_state(state, connector, connector_state, i) {
7955 if (connector_state->crtc == &crtc->base)
7956 num_connectors++;
7957 }
7958
7959 if (!crtc_state->clock_set) {
7960 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7961
7962 /*
7963 * Returns a set of divisors for the desired target clock with
7964 * the given refclk, or FALSE. The returned values represent
7965 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7966 * 2) / p1 / p2.
7967 */
7968 limit = intel_limit(crtc_state, refclk);
7969 ok = dev_priv->display.find_dpll(limit, crtc_state,
7970 crtc_state->port_clock,
7971 refclk, NULL, &clock);
7972 if (!ok) {
7973 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7974 return -EINVAL;
7975 }
7976
7977 /* Compat-code for transition, will disappear. */
7978 crtc_state->dpll.n = clock.n;
7979 crtc_state->dpll.m1 = clock.m1;
7980 crtc_state->dpll.m2 = clock.m2;
7981 crtc_state->dpll.p1 = clock.p1;
7982 crtc_state->dpll.p2 = clock.p2;
7983 }
7984
7985 if (IS_GEN2(dev)) {
7986 i8xx_compute_dpll(crtc, crtc_state, NULL,
7987 num_connectors);
7988 } else if (IS_CHERRYVIEW(dev)) {
7989 chv_compute_dpll(crtc, crtc_state);
7990 } else if (IS_VALLEYVIEW(dev)) {
7991 vlv_compute_dpll(crtc, crtc_state);
7992 } else {
7993 i9xx_compute_dpll(crtc, crtc_state, NULL,
7994 num_connectors);
7995 }
7996
7997 return 0;
7998 }
7999
8000 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8001 struct intel_crtc_state *pipe_config)
8002 {
8003 struct drm_device *dev = crtc->base.dev;
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005 uint32_t tmp;
8006
8007 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8008 return;
8009
8010 tmp = I915_READ(PFIT_CONTROL);
8011 if (!(tmp & PFIT_ENABLE))
8012 return;
8013
8014 /* Check whether the pfit is attached to our pipe. */
8015 if (INTEL_INFO(dev)->gen < 4) {
8016 if (crtc->pipe != PIPE_B)
8017 return;
8018 } else {
8019 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8020 return;
8021 }
8022
8023 pipe_config->gmch_pfit.control = tmp;
8024 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8025 if (INTEL_INFO(dev)->gen < 5)
8026 pipe_config->gmch_pfit.lvds_border_bits =
8027 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8028 }
8029
8030 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8031 struct intel_crtc_state *pipe_config)
8032 {
8033 struct drm_device *dev = crtc->base.dev;
8034 struct drm_i915_private *dev_priv = dev->dev_private;
8035 int pipe = pipe_config->cpu_transcoder;
8036 intel_clock_t clock;
8037 u32 mdiv;
8038 int refclk = 100000;
8039
8040 /* In case of MIPI DPLL will not even be used */
8041 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8042 return;
8043
8044 mutex_lock(&dev_priv->sb_lock);
8045 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8046 mutex_unlock(&dev_priv->sb_lock);
8047
8048 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8049 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8050 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8051 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8052 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8053
8054 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8055 }
8056
8057 static void
8058 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8059 struct intel_initial_plane_config *plane_config)
8060 {
8061 struct drm_device *dev = crtc->base.dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 u32 val, base, offset;
8064 int pipe = crtc->pipe, plane = crtc->plane;
8065 int fourcc, pixel_format;
8066 unsigned int aligned_height;
8067 struct drm_framebuffer *fb;
8068 struct intel_framebuffer *intel_fb;
8069
8070 val = I915_READ(DSPCNTR(plane));
8071 if (!(val & DISPLAY_PLANE_ENABLE))
8072 return;
8073
8074 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8075 if (!intel_fb) {
8076 DRM_DEBUG_KMS("failed to alloc fb\n");
8077 return;
8078 }
8079
8080 fb = &intel_fb->base;
8081
8082 if (INTEL_INFO(dev)->gen >= 4) {
8083 if (val & DISPPLANE_TILED) {
8084 plane_config->tiling = I915_TILING_X;
8085 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8086 }
8087 }
8088
8089 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8090 fourcc = i9xx_format_to_fourcc(pixel_format);
8091 fb->pixel_format = fourcc;
8092 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8093
8094 if (INTEL_INFO(dev)->gen >= 4) {
8095 if (plane_config->tiling)
8096 offset = I915_READ(DSPTILEOFF(plane));
8097 else
8098 offset = I915_READ(DSPLINOFF(plane));
8099 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8100 } else {
8101 base = I915_READ(DSPADDR(plane));
8102 }
8103 plane_config->base = base;
8104
8105 val = I915_READ(PIPESRC(pipe));
8106 fb->width = ((val >> 16) & 0xfff) + 1;
8107 fb->height = ((val >> 0) & 0xfff) + 1;
8108
8109 val = I915_READ(DSPSTRIDE(pipe));
8110 fb->pitches[0] = val & 0xffffffc0;
8111
8112 aligned_height = intel_fb_align_height(dev, fb->height,
8113 fb->pixel_format,
8114 fb->modifier[0]);
8115
8116 plane_config->size = fb->pitches[0] * aligned_height;
8117
8118 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8119 pipe_name(pipe), plane, fb->width, fb->height,
8120 fb->bits_per_pixel, base, fb->pitches[0],
8121 plane_config->size);
8122
8123 plane_config->fb = intel_fb;
8124 }
8125
8126 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8127 struct intel_crtc_state *pipe_config)
8128 {
8129 struct drm_device *dev = crtc->base.dev;
8130 struct drm_i915_private *dev_priv = dev->dev_private;
8131 int pipe = pipe_config->cpu_transcoder;
8132 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8133 intel_clock_t clock;
8134 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8135 int refclk = 100000;
8136
8137 mutex_lock(&dev_priv->sb_lock);
8138 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8139 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8140 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8141 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8142 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8143 mutex_unlock(&dev_priv->sb_lock);
8144
8145 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8146 clock.m2 = (pll_dw0 & 0xff) << 22;
8147 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8148 clock.m2 |= pll_dw2 & 0x3fffff;
8149 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8150 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8151 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8152
8153 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8154 }
8155
8156 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8157 struct intel_crtc_state *pipe_config)
8158 {
8159 struct drm_device *dev = crtc->base.dev;
8160 struct drm_i915_private *dev_priv = dev->dev_private;
8161 uint32_t tmp;
8162
8163 if (!intel_display_power_is_enabled(dev_priv,
8164 POWER_DOMAIN_PIPE(crtc->pipe)))
8165 return false;
8166
8167 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8168 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8169
8170 tmp = I915_READ(PIPECONF(crtc->pipe));
8171 if (!(tmp & PIPECONF_ENABLE))
8172 return false;
8173
8174 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8175 switch (tmp & PIPECONF_BPC_MASK) {
8176 case PIPECONF_6BPC:
8177 pipe_config->pipe_bpp = 18;
8178 break;
8179 case PIPECONF_8BPC:
8180 pipe_config->pipe_bpp = 24;
8181 break;
8182 case PIPECONF_10BPC:
8183 pipe_config->pipe_bpp = 30;
8184 break;
8185 default:
8186 break;
8187 }
8188 }
8189
8190 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8191 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8192 pipe_config->limited_color_range = true;
8193
8194 if (INTEL_INFO(dev)->gen < 4)
8195 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8196
8197 intel_get_pipe_timings(crtc, pipe_config);
8198
8199 i9xx_get_pfit_config(crtc, pipe_config);
8200
8201 if (INTEL_INFO(dev)->gen >= 4) {
8202 tmp = I915_READ(DPLL_MD(crtc->pipe));
8203 pipe_config->pixel_multiplier =
8204 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8205 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8206 pipe_config->dpll_hw_state.dpll_md = tmp;
8207 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8208 tmp = I915_READ(DPLL(crtc->pipe));
8209 pipe_config->pixel_multiplier =
8210 ((tmp & SDVO_MULTIPLIER_MASK)
8211 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8212 } else {
8213 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8214 * port and will be fixed up in the encoder->get_config
8215 * function. */
8216 pipe_config->pixel_multiplier = 1;
8217 }
8218 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8219 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8220 /*
8221 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8222 * on 830. Filter it out here so that we don't
8223 * report errors due to that.
8224 */
8225 if (IS_I830(dev))
8226 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8227
8228 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8229 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8230 } else {
8231 /* Mask out read-only status bits. */
8232 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8233 DPLL_PORTC_READY_MASK |
8234 DPLL_PORTB_READY_MASK);
8235 }
8236
8237 if (IS_CHERRYVIEW(dev))
8238 chv_crtc_clock_get(crtc, pipe_config);
8239 else if (IS_VALLEYVIEW(dev))
8240 vlv_crtc_clock_get(crtc, pipe_config);
8241 else
8242 i9xx_crtc_clock_get(crtc, pipe_config);
8243
8244 /*
8245 * Normally the dotclock is filled in by the encoder .get_config()
8246 * but in case the pipe is enabled w/o any ports we need a sane
8247 * default.
8248 */
8249 pipe_config->base.adjusted_mode.crtc_clock =
8250 pipe_config->port_clock / pipe_config->pixel_multiplier;
8251
8252 return true;
8253 }
8254
8255 static void ironlake_init_pch_refclk(struct drm_device *dev)
8256 {
8257 struct drm_i915_private *dev_priv = dev->dev_private;
8258 struct intel_encoder *encoder;
8259 u32 val, final;
8260 bool has_lvds = false;
8261 bool has_cpu_edp = false;
8262 bool has_panel = false;
8263 bool has_ck505 = false;
8264 bool can_ssc = false;
8265
8266 /* We need to take the global config into account */
8267 for_each_intel_encoder(dev, encoder) {
8268 switch (encoder->type) {
8269 case INTEL_OUTPUT_LVDS:
8270 has_panel = true;
8271 has_lvds = true;
8272 break;
8273 case INTEL_OUTPUT_EDP:
8274 has_panel = true;
8275 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8276 has_cpu_edp = true;
8277 break;
8278 default:
8279 break;
8280 }
8281 }
8282
8283 if (HAS_PCH_IBX(dev)) {
8284 has_ck505 = dev_priv->vbt.display_clock_mode;
8285 can_ssc = has_ck505;
8286 } else {
8287 has_ck505 = false;
8288 can_ssc = true;
8289 }
8290
8291 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8292 has_panel, has_lvds, has_ck505);
8293
8294 /* Ironlake: try to setup display ref clock before DPLL
8295 * enabling. This is only under driver's control after
8296 * PCH B stepping, previous chipset stepping should be
8297 * ignoring this setting.
8298 */
8299 val = I915_READ(PCH_DREF_CONTROL);
8300
8301 /* As we must carefully and slowly disable/enable each source in turn,
8302 * compute the final state we want first and check if we need to
8303 * make any changes at all.
8304 */
8305 final = val;
8306 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8307 if (has_ck505)
8308 final |= DREF_NONSPREAD_CK505_ENABLE;
8309 else
8310 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8311
8312 final &= ~DREF_SSC_SOURCE_MASK;
8313 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8314 final &= ~DREF_SSC1_ENABLE;
8315
8316 if (has_panel) {
8317 final |= DREF_SSC_SOURCE_ENABLE;
8318
8319 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8320 final |= DREF_SSC1_ENABLE;
8321
8322 if (has_cpu_edp) {
8323 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8324 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8325 else
8326 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8327 } else
8328 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8329 } else {
8330 final |= DREF_SSC_SOURCE_DISABLE;
8331 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8332 }
8333
8334 if (final == val)
8335 return;
8336
8337 /* Always enable nonspread source */
8338 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8339
8340 if (has_ck505)
8341 val |= DREF_NONSPREAD_CK505_ENABLE;
8342 else
8343 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8344
8345 if (has_panel) {
8346 val &= ~DREF_SSC_SOURCE_MASK;
8347 val |= DREF_SSC_SOURCE_ENABLE;
8348
8349 /* SSC must be turned on before enabling the CPU output */
8350 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8351 DRM_DEBUG_KMS("Using SSC on panel\n");
8352 val |= DREF_SSC1_ENABLE;
8353 } else
8354 val &= ~DREF_SSC1_ENABLE;
8355
8356 /* Get SSC going before enabling the outputs */
8357 I915_WRITE(PCH_DREF_CONTROL, val);
8358 POSTING_READ(PCH_DREF_CONTROL);
8359 udelay(200);
8360
8361 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8362
8363 /* Enable CPU source on CPU attached eDP */
8364 if (has_cpu_edp) {
8365 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8366 DRM_DEBUG_KMS("Using SSC on eDP\n");
8367 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8368 } else
8369 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8370 } else
8371 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8372
8373 I915_WRITE(PCH_DREF_CONTROL, val);
8374 POSTING_READ(PCH_DREF_CONTROL);
8375 udelay(200);
8376 } else {
8377 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8378
8379 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8380
8381 /* Turn off CPU output */
8382 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8383
8384 I915_WRITE(PCH_DREF_CONTROL, val);
8385 POSTING_READ(PCH_DREF_CONTROL);
8386 udelay(200);
8387
8388 /* Turn off the SSC source */
8389 val &= ~DREF_SSC_SOURCE_MASK;
8390 val |= DREF_SSC_SOURCE_DISABLE;
8391
8392 /* Turn off SSC1 */
8393 val &= ~DREF_SSC1_ENABLE;
8394
8395 I915_WRITE(PCH_DREF_CONTROL, val);
8396 POSTING_READ(PCH_DREF_CONTROL);
8397 udelay(200);
8398 }
8399
8400 BUG_ON(val != final);
8401 }
8402
8403 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8404 {
8405 uint32_t tmp;
8406
8407 tmp = I915_READ(SOUTH_CHICKEN2);
8408 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8409 I915_WRITE(SOUTH_CHICKEN2, tmp);
8410
8411 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8412 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8413 DRM_ERROR("FDI mPHY reset assert timeout\n");
8414
8415 tmp = I915_READ(SOUTH_CHICKEN2);
8416 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8417 I915_WRITE(SOUTH_CHICKEN2, tmp);
8418
8419 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8420 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8421 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8422 }
8423
8424 /* WaMPhyProgramming:hsw */
8425 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8426 {
8427 uint32_t tmp;
8428
8429 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8430 tmp &= ~(0xFF << 24);
8431 tmp |= (0x12 << 24);
8432 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8433
8434 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8435 tmp |= (1 << 11);
8436 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8437
8438 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8439 tmp |= (1 << 11);
8440 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8441
8442 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8443 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8444 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8445
8446 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8447 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8448 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8449
8450 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8451 tmp &= ~(7 << 13);
8452 tmp |= (5 << 13);
8453 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8456 tmp &= ~(7 << 13);
8457 tmp |= (5 << 13);
8458 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8459
8460 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8461 tmp &= ~0xFF;
8462 tmp |= 0x1C;
8463 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8466 tmp &= ~0xFF;
8467 tmp |= 0x1C;
8468 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8471 tmp &= ~(0xFF << 16);
8472 tmp |= (0x1C << 16);
8473 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8474
8475 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8476 tmp &= ~(0xFF << 16);
8477 tmp |= (0x1C << 16);
8478 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8479
8480 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8481 tmp |= (1 << 27);
8482 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8483
8484 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8485 tmp |= (1 << 27);
8486 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8487
8488 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8489 tmp &= ~(0xF << 28);
8490 tmp |= (4 << 28);
8491 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8494 tmp &= ~(0xF << 28);
8495 tmp |= (4 << 28);
8496 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8497 }
8498
8499 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8500 * Programming" based on the parameters passed:
8501 * - Sequence to enable CLKOUT_DP
8502 * - Sequence to enable CLKOUT_DP without spread
8503 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8504 */
8505 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8506 bool with_fdi)
8507 {
8508 struct drm_i915_private *dev_priv = dev->dev_private;
8509 uint32_t reg, tmp;
8510
8511 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8512 with_spread = true;
8513 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8514 with_fdi = false;
8515
8516 mutex_lock(&dev_priv->sb_lock);
8517
8518 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8519 tmp &= ~SBI_SSCCTL_DISABLE;
8520 tmp |= SBI_SSCCTL_PATHALT;
8521 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8522
8523 udelay(24);
8524
8525 if (with_spread) {
8526 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8527 tmp &= ~SBI_SSCCTL_PATHALT;
8528 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8529
8530 if (with_fdi) {
8531 lpt_reset_fdi_mphy(dev_priv);
8532 lpt_program_fdi_mphy(dev_priv);
8533 }
8534 }
8535
8536 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8537 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8538 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8539 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8540
8541 mutex_unlock(&dev_priv->sb_lock);
8542 }
8543
8544 /* Sequence to disable CLKOUT_DP */
8545 static void lpt_disable_clkout_dp(struct drm_device *dev)
8546 {
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8548 uint32_t reg, tmp;
8549
8550 mutex_lock(&dev_priv->sb_lock);
8551
8552 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8553 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8554 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8555 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8556
8557 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8558 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8559 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8560 tmp |= SBI_SSCCTL_PATHALT;
8561 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8562 udelay(32);
8563 }
8564 tmp |= SBI_SSCCTL_DISABLE;
8565 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8566 }
8567
8568 mutex_unlock(&dev_priv->sb_lock);
8569 }
8570
8571 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8572
8573 static const uint16_t sscdivintphase[] = {
8574 [BEND_IDX( 50)] = 0x3B23,
8575 [BEND_IDX( 45)] = 0x3B23,
8576 [BEND_IDX( 40)] = 0x3C23,
8577 [BEND_IDX( 35)] = 0x3C23,
8578 [BEND_IDX( 30)] = 0x3D23,
8579 [BEND_IDX( 25)] = 0x3D23,
8580 [BEND_IDX( 20)] = 0x3E23,
8581 [BEND_IDX( 15)] = 0x3E23,
8582 [BEND_IDX( 10)] = 0x3F23,
8583 [BEND_IDX( 5)] = 0x3F23,
8584 [BEND_IDX( 0)] = 0x0025,
8585 [BEND_IDX( -5)] = 0x0025,
8586 [BEND_IDX(-10)] = 0x0125,
8587 [BEND_IDX(-15)] = 0x0125,
8588 [BEND_IDX(-20)] = 0x0225,
8589 [BEND_IDX(-25)] = 0x0225,
8590 [BEND_IDX(-30)] = 0x0325,
8591 [BEND_IDX(-35)] = 0x0325,
8592 [BEND_IDX(-40)] = 0x0425,
8593 [BEND_IDX(-45)] = 0x0425,
8594 [BEND_IDX(-50)] = 0x0525,
8595 };
8596
8597 /*
8598 * Bend CLKOUT_DP
8599 * steps -50 to 50 inclusive, in steps of 5
8600 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8601 * change in clock period = -(steps / 10) * 5.787 ps
8602 */
8603 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8604 {
8605 uint32_t tmp;
8606 int idx = BEND_IDX(steps);
8607
8608 if (WARN_ON(steps % 5 != 0))
8609 return;
8610
8611 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8612 return;
8613
8614 mutex_lock(&dev_priv->sb_lock);
8615
8616 if (steps % 10 != 0)
8617 tmp = 0xAAAAAAAB;
8618 else
8619 tmp = 0x00000000;
8620 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8621
8622 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8623 tmp &= 0xffff0000;
8624 tmp |= sscdivintphase[idx];
8625 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8626
8627 mutex_unlock(&dev_priv->sb_lock);
8628 }
8629
8630 #undef BEND_IDX
8631
8632 static void lpt_init_pch_refclk(struct drm_device *dev)
8633 {
8634 struct intel_encoder *encoder;
8635 bool has_vga = false;
8636
8637 for_each_intel_encoder(dev, encoder) {
8638 switch (encoder->type) {
8639 case INTEL_OUTPUT_ANALOG:
8640 has_vga = true;
8641 break;
8642 default:
8643 break;
8644 }
8645 }
8646
8647 if (has_vga) {
8648 lpt_bend_clkout_dp(to_i915(dev), 0);
8649 lpt_enable_clkout_dp(dev, true, true);
8650 } else {
8651 lpt_disable_clkout_dp(dev);
8652 }
8653 }
8654
8655 /*
8656 * Initialize reference clocks when the driver loads
8657 */
8658 void intel_init_pch_refclk(struct drm_device *dev)
8659 {
8660 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8661 ironlake_init_pch_refclk(dev);
8662 else if (HAS_PCH_LPT(dev))
8663 lpt_init_pch_refclk(dev);
8664 }
8665
8666 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8667 {
8668 struct drm_device *dev = crtc_state->base.crtc->dev;
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670 struct drm_atomic_state *state = crtc_state->base.state;
8671 struct drm_connector *connector;
8672 struct drm_connector_state *connector_state;
8673 struct intel_encoder *encoder;
8674 int num_connectors = 0, i;
8675 bool is_lvds = false;
8676
8677 for_each_connector_in_state(state, connector, connector_state, i) {
8678 if (connector_state->crtc != crtc_state->base.crtc)
8679 continue;
8680
8681 encoder = to_intel_encoder(connector_state->best_encoder);
8682
8683 switch (encoder->type) {
8684 case INTEL_OUTPUT_LVDS:
8685 is_lvds = true;
8686 break;
8687 default:
8688 break;
8689 }
8690 num_connectors++;
8691 }
8692
8693 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8694 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8695 dev_priv->vbt.lvds_ssc_freq);
8696 return dev_priv->vbt.lvds_ssc_freq;
8697 }
8698
8699 return 120000;
8700 }
8701
8702 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8703 {
8704 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8706 int pipe = intel_crtc->pipe;
8707 uint32_t val;
8708
8709 val = 0;
8710
8711 switch (intel_crtc->config->pipe_bpp) {
8712 case 18:
8713 val |= PIPECONF_6BPC;
8714 break;
8715 case 24:
8716 val |= PIPECONF_8BPC;
8717 break;
8718 case 30:
8719 val |= PIPECONF_10BPC;
8720 break;
8721 case 36:
8722 val |= PIPECONF_12BPC;
8723 break;
8724 default:
8725 /* Case prevented by intel_choose_pipe_bpp_dither. */
8726 BUG();
8727 }
8728
8729 if (intel_crtc->config->dither)
8730 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8731
8732 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8733 val |= PIPECONF_INTERLACED_ILK;
8734 else
8735 val |= PIPECONF_PROGRESSIVE;
8736
8737 if (intel_crtc->config->limited_color_range)
8738 val |= PIPECONF_COLOR_RANGE_SELECT;
8739
8740 I915_WRITE(PIPECONF(pipe), val);
8741 POSTING_READ(PIPECONF(pipe));
8742 }
8743
8744 /*
8745 * Set up the pipe CSC unit.
8746 *
8747 * Currently only full range RGB to limited range RGB conversion
8748 * is supported, but eventually this should handle various
8749 * RGB<->YCbCr scenarios as well.
8750 */
8751 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8752 {
8753 struct drm_device *dev = crtc->dev;
8754 struct drm_i915_private *dev_priv = dev->dev_private;
8755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8756 int pipe = intel_crtc->pipe;
8757 uint16_t coeff = 0x7800; /* 1.0 */
8758
8759 /*
8760 * TODO: Check what kind of values actually come out of the pipe
8761 * with these coeff/postoff values and adjust to get the best
8762 * accuracy. Perhaps we even need to take the bpc value into
8763 * consideration.
8764 */
8765
8766 if (intel_crtc->config->limited_color_range)
8767 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8768
8769 /*
8770 * GY/GU and RY/RU should be the other way around according
8771 * to BSpec, but reality doesn't agree. Just set them up in
8772 * a way that results in the correct picture.
8773 */
8774 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8775 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8776
8777 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8778 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8779
8780 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8781 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8782
8783 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8784 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8785 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8786
8787 if (INTEL_INFO(dev)->gen > 6) {
8788 uint16_t postoff = 0;
8789
8790 if (intel_crtc->config->limited_color_range)
8791 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8792
8793 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8794 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8795 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8796
8797 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8798 } else {
8799 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8800
8801 if (intel_crtc->config->limited_color_range)
8802 mode |= CSC_BLACK_SCREEN_OFFSET;
8803
8804 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8805 }
8806 }
8807
8808 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8809 {
8810 struct drm_device *dev = crtc->dev;
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8813 enum pipe pipe = intel_crtc->pipe;
8814 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8815 uint32_t val;
8816
8817 val = 0;
8818
8819 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8820 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8821
8822 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8823 val |= PIPECONF_INTERLACED_ILK;
8824 else
8825 val |= PIPECONF_PROGRESSIVE;
8826
8827 I915_WRITE(PIPECONF(cpu_transcoder), val);
8828 POSTING_READ(PIPECONF(cpu_transcoder));
8829
8830 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8831 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8832
8833 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8834 val = 0;
8835
8836 switch (intel_crtc->config->pipe_bpp) {
8837 case 18:
8838 val |= PIPEMISC_DITHER_6_BPC;
8839 break;
8840 case 24:
8841 val |= PIPEMISC_DITHER_8_BPC;
8842 break;
8843 case 30:
8844 val |= PIPEMISC_DITHER_10_BPC;
8845 break;
8846 case 36:
8847 val |= PIPEMISC_DITHER_12_BPC;
8848 break;
8849 default:
8850 /* Case prevented by pipe_config_set_bpp. */
8851 BUG();
8852 }
8853
8854 if (intel_crtc->config->dither)
8855 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8856
8857 I915_WRITE(PIPEMISC(pipe), val);
8858 }
8859 }
8860
8861 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8862 struct intel_crtc_state *crtc_state,
8863 intel_clock_t *clock,
8864 bool *has_reduced_clock,
8865 intel_clock_t *reduced_clock)
8866 {
8867 struct drm_device *dev = crtc->dev;
8868 struct drm_i915_private *dev_priv = dev->dev_private;
8869 int refclk;
8870 const intel_limit_t *limit;
8871 bool ret;
8872
8873 refclk = ironlake_get_refclk(crtc_state);
8874
8875 /*
8876 * Returns a set of divisors for the desired target clock with the given
8877 * refclk, or FALSE. The returned values represent the clock equation:
8878 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8879 */
8880 limit = intel_limit(crtc_state, refclk);
8881 ret = dev_priv->display.find_dpll(limit, crtc_state,
8882 crtc_state->port_clock,
8883 refclk, NULL, clock);
8884 if (!ret)
8885 return false;
8886
8887 return true;
8888 }
8889
8890 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8891 {
8892 /*
8893 * Account for spread spectrum to avoid
8894 * oversubscribing the link. Max center spread
8895 * is 2.5%; use 5% for safety's sake.
8896 */
8897 u32 bps = target_clock * bpp * 21 / 20;
8898 return DIV_ROUND_UP(bps, link_bw * 8);
8899 }
8900
8901 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8902 {
8903 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8904 }
8905
8906 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8907 struct intel_crtc_state *crtc_state,
8908 u32 *fp,
8909 intel_clock_t *reduced_clock, u32 *fp2)
8910 {
8911 struct drm_crtc *crtc = &intel_crtc->base;
8912 struct drm_device *dev = crtc->dev;
8913 struct drm_i915_private *dev_priv = dev->dev_private;
8914 struct drm_atomic_state *state = crtc_state->base.state;
8915 struct drm_connector *connector;
8916 struct drm_connector_state *connector_state;
8917 struct intel_encoder *encoder;
8918 uint32_t dpll;
8919 int factor, num_connectors = 0, i;
8920 bool is_lvds = false, is_sdvo = false;
8921
8922 for_each_connector_in_state(state, connector, connector_state, i) {
8923 if (connector_state->crtc != crtc_state->base.crtc)
8924 continue;
8925
8926 encoder = to_intel_encoder(connector_state->best_encoder);
8927
8928 switch (encoder->type) {
8929 case INTEL_OUTPUT_LVDS:
8930 is_lvds = true;
8931 break;
8932 case INTEL_OUTPUT_SDVO:
8933 case INTEL_OUTPUT_HDMI:
8934 is_sdvo = true;
8935 break;
8936 default:
8937 break;
8938 }
8939
8940 num_connectors++;
8941 }
8942
8943 /* Enable autotuning of the PLL clock (if permissible) */
8944 factor = 21;
8945 if (is_lvds) {
8946 if ((intel_panel_use_ssc(dev_priv) &&
8947 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8948 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8949 factor = 25;
8950 } else if (crtc_state->sdvo_tv_clock)
8951 factor = 20;
8952
8953 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8954 *fp |= FP_CB_TUNE;
8955
8956 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8957 *fp2 |= FP_CB_TUNE;
8958
8959 dpll = 0;
8960
8961 if (is_lvds)
8962 dpll |= DPLLB_MODE_LVDS;
8963 else
8964 dpll |= DPLLB_MODE_DAC_SERIAL;
8965
8966 dpll |= (crtc_state->pixel_multiplier - 1)
8967 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8968
8969 if (is_sdvo)
8970 dpll |= DPLL_SDVO_HIGH_SPEED;
8971 if (crtc_state->has_dp_encoder)
8972 dpll |= DPLL_SDVO_HIGH_SPEED;
8973
8974 /* compute bitmask from p1 value */
8975 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8976 /* also FPA1 */
8977 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8978
8979 switch (crtc_state->dpll.p2) {
8980 case 5:
8981 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8982 break;
8983 case 7:
8984 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8985 break;
8986 case 10:
8987 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8988 break;
8989 case 14:
8990 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8991 break;
8992 }
8993
8994 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8995 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8996 else
8997 dpll |= PLL_REF_INPUT_DREFCLK;
8998
8999 return dpll | DPLL_VCO_ENABLE;
9000 }
9001
9002 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9003 struct intel_crtc_state *crtc_state)
9004 {
9005 struct drm_device *dev = crtc->base.dev;
9006 intel_clock_t clock, reduced_clock;
9007 u32 dpll = 0, fp = 0, fp2 = 0;
9008 bool ok, has_reduced_clock = false;
9009 bool is_lvds = false;
9010 struct intel_shared_dpll *pll;
9011
9012 memset(&crtc_state->dpll_hw_state, 0,
9013 sizeof(crtc_state->dpll_hw_state));
9014
9015 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9016
9017 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9018 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9019
9020 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9021 &has_reduced_clock, &reduced_clock);
9022 if (!ok && !crtc_state->clock_set) {
9023 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9024 return -EINVAL;
9025 }
9026 /* Compat-code for transition, will disappear. */
9027 if (!crtc_state->clock_set) {
9028 crtc_state->dpll.n = clock.n;
9029 crtc_state->dpll.m1 = clock.m1;
9030 crtc_state->dpll.m2 = clock.m2;
9031 crtc_state->dpll.p1 = clock.p1;
9032 crtc_state->dpll.p2 = clock.p2;
9033 }
9034
9035 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9036 if (crtc_state->has_pch_encoder) {
9037 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9038 if (has_reduced_clock)
9039 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9040
9041 dpll = ironlake_compute_dpll(crtc, crtc_state,
9042 &fp, &reduced_clock,
9043 has_reduced_clock ? &fp2 : NULL);
9044
9045 crtc_state->dpll_hw_state.dpll = dpll;
9046 crtc_state->dpll_hw_state.fp0 = fp;
9047 if (has_reduced_clock)
9048 crtc_state->dpll_hw_state.fp1 = fp2;
9049 else
9050 crtc_state->dpll_hw_state.fp1 = fp;
9051
9052 pll = intel_get_shared_dpll(crtc, crtc_state);
9053 if (pll == NULL) {
9054 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9055 pipe_name(crtc->pipe));
9056 return -EINVAL;
9057 }
9058 }
9059
9060 if (is_lvds && has_reduced_clock)
9061 crtc->lowfreq_avail = true;
9062 else
9063 crtc->lowfreq_avail = false;
9064
9065 return 0;
9066 }
9067
9068 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9069 struct intel_link_m_n *m_n)
9070 {
9071 struct drm_device *dev = crtc->base.dev;
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 enum pipe pipe = crtc->pipe;
9074
9075 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9076 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9077 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9078 & ~TU_SIZE_MASK;
9079 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9080 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9081 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9082 }
9083
9084 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9085 enum transcoder transcoder,
9086 struct intel_link_m_n *m_n,
9087 struct intel_link_m_n *m2_n2)
9088 {
9089 struct drm_device *dev = crtc->base.dev;
9090 struct drm_i915_private *dev_priv = dev->dev_private;
9091 enum pipe pipe = crtc->pipe;
9092
9093 if (INTEL_INFO(dev)->gen >= 5) {
9094 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9095 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9096 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9097 & ~TU_SIZE_MASK;
9098 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9099 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9100 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9101 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9102 * gen < 8) and if DRRS is supported (to make sure the
9103 * registers are not unnecessarily read).
9104 */
9105 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9106 crtc->config->has_drrs) {
9107 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9108 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9109 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9110 & ~TU_SIZE_MASK;
9111 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9112 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9113 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9114 }
9115 } else {
9116 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9117 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9118 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9119 & ~TU_SIZE_MASK;
9120 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9121 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9123 }
9124 }
9125
9126 void intel_dp_get_m_n(struct intel_crtc *crtc,
9127 struct intel_crtc_state *pipe_config)
9128 {
9129 if (pipe_config->has_pch_encoder)
9130 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9131 else
9132 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9133 &pipe_config->dp_m_n,
9134 &pipe_config->dp_m2_n2);
9135 }
9136
9137 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9138 struct intel_crtc_state *pipe_config)
9139 {
9140 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9141 &pipe_config->fdi_m_n, NULL);
9142 }
9143
9144 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9145 struct intel_crtc_state *pipe_config)
9146 {
9147 struct drm_device *dev = crtc->base.dev;
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9150 uint32_t ps_ctrl = 0;
9151 int id = -1;
9152 int i;
9153
9154 /* find scaler attached to this pipe */
9155 for (i = 0; i < crtc->num_scalers; i++) {
9156 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9157 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9158 id = i;
9159 pipe_config->pch_pfit.enabled = true;
9160 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9161 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9162 break;
9163 }
9164 }
9165
9166 scaler_state->scaler_id = id;
9167 if (id >= 0) {
9168 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9169 } else {
9170 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9171 }
9172 }
9173
9174 static void
9175 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9176 struct intel_initial_plane_config *plane_config)
9177 {
9178 struct drm_device *dev = crtc->base.dev;
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180 u32 val, base, offset, stride_mult, tiling;
9181 int pipe = crtc->pipe;
9182 int fourcc, pixel_format;
9183 unsigned int aligned_height;
9184 struct drm_framebuffer *fb;
9185 struct intel_framebuffer *intel_fb;
9186
9187 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9188 if (!intel_fb) {
9189 DRM_DEBUG_KMS("failed to alloc fb\n");
9190 return;
9191 }
9192
9193 fb = &intel_fb->base;
9194
9195 val = I915_READ(PLANE_CTL(pipe, 0));
9196 if (!(val & PLANE_CTL_ENABLE))
9197 goto error;
9198
9199 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9200 fourcc = skl_format_to_fourcc(pixel_format,
9201 val & PLANE_CTL_ORDER_RGBX,
9202 val & PLANE_CTL_ALPHA_MASK);
9203 fb->pixel_format = fourcc;
9204 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9205
9206 tiling = val & PLANE_CTL_TILED_MASK;
9207 switch (tiling) {
9208 case PLANE_CTL_TILED_LINEAR:
9209 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9210 break;
9211 case PLANE_CTL_TILED_X:
9212 plane_config->tiling = I915_TILING_X;
9213 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9214 break;
9215 case PLANE_CTL_TILED_Y:
9216 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9217 break;
9218 case PLANE_CTL_TILED_YF:
9219 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9220 break;
9221 default:
9222 MISSING_CASE(tiling);
9223 goto error;
9224 }
9225
9226 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9227 plane_config->base = base;
9228
9229 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9230
9231 val = I915_READ(PLANE_SIZE(pipe, 0));
9232 fb->height = ((val >> 16) & 0xfff) + 1;
9233 fb->width = ((val >> 0) & 0x1fff) + 1;
9234
9235 val = I915_READ(PLANE_STRIDE(pipe, 0));
9236 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9237 fb->pixel_format);
9238 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9239
9240 aligned_height = intel_fb_align_height(dev, fb->height,
9241 fb->pixel_format,
9242 fb->modifier[0]);
9243
9244 plane_config->size = fb->pitches[0] * aligned_height;
9245
9246 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9247 pipe_name(pipe), fb->width, fb->height,
9248 fb->bits_per_pixel, base, fb->pitches[0],
9249 plane_config->size);
9250
9251 plane_config->fb = intel_fb;
9252 return;
9253
9254 error:
9255 kfree(fb);
9256 }
9257
9258 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9259 struct intel_crtc_state *pipe_config)
9260 {
9261 struct drm_device *dev = crtc->base.dev;
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 uint32_t tmp;
9264
9265 tmp = I915_READ(PF_CTL(crtc->pipe));
9266
9267 if (tmp & PF_ENABLE) {
9268 pipe_config->pch_pfit.enabled = true;
9269 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9270 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9271
9272 /* We currently do not free assignements of panel fitters on
9273 * ivb/hsw (since we don't use the higher upscaling modes which
9274 * differentiates them) so just WARN about this case for now. */
9275 if (IS_GEN7(dev)) {
9276 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9277 PF_PIPE_SEL_IVB(crtc->pipe));
9278 }
9279 }
9280 }
9281
9282 static void
9283 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9284 struct intel_initial_plane_config *plane_config)
9285 {
9286 struct drm_device *dev = crtc->base.dev;
9287 struct drm_i915_private *dev_priv = dev->dev_private;
9288 u32 val, base, offset;
9289 int pipe = crtc->pipe;
9290 int fourcc, pixel_format;
9291 unsigned int aligned_height;
9292 struct drm_framebuffer *fb;
9293 struct intel_framebuffer *intel_fb;
9294
9295 val = I915_READ(DSPCNTR(pipe));
9296 if (!(val & DISPLAY_PLANE_ENABLE))
9297 return;
9298
9299 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9300 if (!intel_fb) {
9301 DRM_DEBUG_KMS("failed to alloc fb\n");
9302 return;
9303 }
9304
9305 fb = &intel_fb->base;
9306
9307 if (INTEL_INFO(dev)->gen >= 4) {
9308 if (val & DISPPLANE_TILED) {
9309 plane_config->tiling = I915_TILING_X;
9310 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9311 }
9312 }
9313
9314 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9315 fourcc = i9xx_format_to_fourcc(pixel_format);
9316 fb->pixel_format = fourcc;
9317 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9318
9319 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9320 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9321 offset = I915_READ(DSPOFFSET(pipe));
9322 } else {
9323 if (plane_config->tiling)
9324 offset = I915_READ(DSPTILEOFF(pipe));
9325 else
9326 offset = I915_READ(DSPLINOFF(pipe));
9327 }
9328 plane_config->base = base;
9329
9330 val = I915_READ(PIPESRC(pipe));
9331 fb->width = ((val >> 16) & 0xfff) + 1;
9332 fb->height = ((val >> 0) & 0xfff) + 1;
9333
9334 val = I915_READ(DSPSTRIDE(pipe));
9335 fb->pitches[0] = val & 0xffffffc0;
9336
9337 aligned_height = intel_fb_align_height(dev, fb->height,
9338 fb->pixel_format,
9339 fb->modifier[0]);
9340
9341 plane_config->size = fb->pitches[0] * aligned_height;
9342
9343 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9344 pipe_name(pipe), fb->width, fb->height,
9345 fb->bits_per_pixel, base, fb->pitches[0],
9346 plane_config->size);
9347
9348 plane_config->fb = intel_fb;
9349 }
9350
9351 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9352 struct intel_crtc_state *pipe_config)
9353 {
9354 struct drm_device *dev = crtc->base.dev;
9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356 uint32_t tmp;
9357
9358 if (!intel_display_power_is_enabled(dev_priv,
9359 POWER_DOMAIN_PIPE(crtc->pipe)))
9360 return false;
9361
9362 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9363 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9364
9365 tmp = I915_READ(PIPECONF(crtc->pipe));
9366 if (!(tmp & PIPECONF_ENABLE))
9367 return false;
9368
9369 switch (tmp & PIPECONF_BPC_MASK) {
9370 case PIPECONF_6BPC:
9371 pipe_config->pipe_bpp = 18;
9372 break;
9373 case PIPECONF_8BPC:
9374 pipe_config->pipe_bpp = 24;
9375 break;
9376 case PIPECONF_10BPC:
9377 pipe_config->pipe_bpp = 30;
9378 break;
9379 case PIPECONF_12BPC:
9380 pipe_config->pipe_bpp = 36;
9381 break;
9382 default:
9383 break;
9384 }
9385
9386 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9387 pipe_config->limited_color_range = true;
9388
9389 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9390 struct intel_shared_dpll *pll;
9391
9392 pipe_config->has_pch_encoder = true;
9393
9394 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9395 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9396 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9397
9398 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9399
9400 if (HAS_PCH_IBX(dev_priv->dev)) {
9401 pipe_config->shared_dpll =
9402 (enum intel_dpll_id) crtc->pipe;
9403 } else {
9404 tmp = I915_READ(PCH_DPLL_SEL);
9405 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9406 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9407 else
9408 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9409 }
9410
9411 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9412
9413 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9414 &pipe_config->dpll_hw_state));
9415
9416 tmp = pipe_config->dpll_hw_state.dpll;
9417 pipe_config->pixel_multiplier =
9418 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9419 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9420
9421 ironlake_pch_clock_get(crtc, pipe_config);
9422 } else {
9423 pipe_config->pixel_multiplier = 1;
9424 }
9425
9426 intel_get_pipe_timings(crtc, pipe_config);
9427
9428 ironlake_get_pfit_config(crtc, pipe_config);
9429
9430 return true;
9431 }
9432
9433 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9434 {
9435 struct drm_device *dev = dev_priv->dev;
9436 struct intel_crtc *crtc;
9437
9438 for_each_intel_crtc(dev, crtc)
9439 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9440 pipe_name(crtc->pipe));
9441
9442 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9443 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9444 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9445 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9446 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9447 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9448 "CPU PWM1 enabled\n");
9449 if (IS_HASWELL(dev))
9450 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9451 "CPU PWM2 enabled\n");
9452 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9453 "PCH PWM1 enabled\n");
9454 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9455 "Utility pin enabled\n");
9456 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9457
9458 /*
9459 * In theory we can still leave IRQs enabled, as long as only the HPD
9460 * interrupts remain enabled. We used to check for that, but since it's
9461 * gen-specific and since we only disable LCPLL after we fully disable
9462 * the interrupts, the check below should be enough.
9463 */
9464 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9465 }
9466
9467 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9468 {
9469 struct drm_device *dev = dev_priv->dev;
9470
9471 if (IS_HASWELL(dev))
9472 return I915_READ(D_COMP_HSW);
9473 else
9474 return I915_READ(D_COMP_BDW);
9475 }
9476
9477 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9478 {
9479 struct drm_device *dev = dev_priv->dev;
9480
9481 if (IS_HASWELL(dev)) {
9482 mutex_lock(&dev_priv->rps.hw_lock);
9483 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9484 val))
9485 DRM_ERROR("Failed to write to D_COMP\n");
9486 mutex_unlock(&dev_priv->rps.hw_lock);
9487 } else {
9488 I915_WRITE(D_COMP_BDW, val);
9489 POSTING_READ(D_COMP_BDW);
9490 }
9491 }
9492
9493 /*
9494 * This function implements pieces of two sequences from BSpec:
9495 * - Sequence for display software to disable LCPLL
9496 * - Sequence for display software to allow package C8+
9497 * The steps implemented here are just the steps that actually touch the LCPLL
9498 * register. Callers should take care of disabling all the display engine
9499 * functions, doing the mode unset, fixing interrupts, etc.
9500 */
9501 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9502 bool switch_to_fclk, bool allow_power_down)
9503 {
9504 uint32_t val;
9505
9506 assert_can_disable_lcpll(dev_priv);
9507
9508 val = I915_READ(LCPLL_CTL);
9509
9510 if (switch_to_fclk) {
9511 val |= LCPLL_CD_SOURCE_FCLK;
9512 I915_WRITE(LCPLL_CTL, val);
9513
9514 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9515 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9516 DRM_ERROR("Switching to FCLK failed\n");
9517
9518 val = I915_READ(LCPLL_CTL);
9519 }
9520
9521 val |= LCPLL_PLL_DISABLE;
9522 I915_WRITE(LCPLL_CTL, val);
9523 POSTING_READ(LCPLL_CTL);
9524
9525 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9526 DRM_ERROR("LCPLL still locked\n");
9527
9528 val = hsw_read_dcomp(dev_priv);
9529 val |= D_COMP_COMP_DISABLE;
9530 hsw_write_dcomp(dev_priv, val);
9531 ndelay(100);
9532
9533 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9534 1))
9535 DRM_ERROR("D_COMP RCOMP still in progress\n");
9536
9537 if (allow_power_down) {
9538 val = I915_READ(LCPLL_CTL);
9539 val |= LCPLL_POWER_DOWN_ALLOW;
9540 I915_WRITE(LCPLL_CTL, val);
9541 POSTING_READ(LCPLL_CTL);
9542 }
9543 }
9544
9545 /*
9546 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9547 * source.
9548 */
9549 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9550 {
9551 uint32_t val;
9552
9553 val = I915_READ(LCPLL_CTL);
9554
9555 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9556 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9557 return;
9558
9559 /*
9560 * Make sure we're not on PC8 state before disabling PC8, otherwise
9561 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9562 */
9563 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9564
9565 if (val & LCPLL_POWER_DOWN_ALLOW) {
9566 val &= ~LCPLL_POWER_DOWN_ALLOW;
9567 I915_WRITE(LCPLL_CTL, val);
9568 POSTING_READ(LCPLL_CTL);
9569 }
9570
9571 val = hsw_read_dcomp(dev_priv);
9572 val |= D_COMP_COMP_FORCE;
9573 val &= ~D_COMP_COMP_DISABLE;
9574 hsw_write_dcomp(dev_priv, val);
9575
9576 val = I915_READ(LCPLL_CTL);
9577 val &= ~LCPLL_PLL_DISABLE;
9578 I915_WRITE(LCPLL_CTL, val);
9579
9580 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9581 DRM_ERROR("LCPLL not locked yet\n");
9582
9583 if (val & LCPLL_CD_SOURCE_FCLK) {
9584 val = I915_READ(LCPLL_CTL);
9585 val &= ~LCPLL_CD_SOURCE_FCLK;
9586 I915_WRITE(LCPLL_CTL, val);
9587
9588 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9589 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9590 DRM_ERROR("Switching back to LCPLL failed\n");
9591 }
9592
9593 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9594 intel_update_cdclk(dev_priv->dev);
9595 }
9596
9597 /*
9598 * Package states C8 and deeper are really deep PC states that can only be
9599 * reached when all the devices on the system allow it, so even if the graphics
9600 * device allows PC8+, it doesn't mean the system will actually get to these
9601 * states. Our driver only allows PC8+ when going into runtime PM.
9602 *
9603 * The requirements for PC8+ are that all the outputs are disabled, the power
9604 * well is disabled and most interrupts are disabled, and these are also
9605 * requirements for runtime PM. When these conditions are met, we manually do
9606 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9607 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9608 * hang the machine.
9609 *
9610 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9611 * the state of some registers, so when we come back from PC8+ we need to
9612 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9613 * need to take care of the registers kept by RC6. Notice that this happens even
9614 * if we don't put the device in PCI D3 state (which is what currently happens
9615 * because of the runtime PM support).
9616 *
9617 * For more, read "Display Sequences for Package C8" on the hardware
9618 * documentation.
9619 */
9620 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9621 {
9622 struct drm_device *dev = dev_priv->dev;
9623 uint32_t val;
9624
9625 DRM_DEBUG_KMS("Enabling package C8+\n");
9626
9627 if (HAS_PCH_LPT_LP(dev)) {
9628 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9629 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9630 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9631 }
9632
9633 lpt_disable_clkout_dp(dev);
9634 hsw_disable_lcpll(dev_priv, true, true);
9635 }
9636
9637 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9638 {
9639 struct drm_device *dev = dev_priv->dev;
9640 uint32_t val;
9641
9642 DRM_DEBUG_KMS("Disabling package C8+\n");
9643
9644 hsw_restore_lcpll(dev_priv);
9645 lpt_init_pch_refclk(dev);
9646
9647 if (HAS_PCH_LPT_LP(dev)) {
9648 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9649 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9650 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9651 }
9652
9653 intel_prepare_ddi(dev);
9654 }
9655
9656 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9657 {
9658 struct drm_device *dev = old_state->dev;
9659 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9660
9661 broxton_set_cdclk(dev, req_cdclk);
9662 }
9663
9664 /* compute the max rate for new configuration */
9665 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9666 {
9667 struct intel_crtc *intel_crtc;
9668 struct intel_crtc_state *crtc_state;
9669 int max_pixel_rate = 0;
9670
9671 for_each_intel_crtc(state->dev, intel_crtc) {
9672 int pixel_rate;
9673
9674 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9675 if (IS_ERR(crtc_state))
9676 return PTR_ERR(crtc_state);
9677
9678 if (!crtc_state->base.enable)
9679 continue;
9680
9681 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9682
9683 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9684 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9685 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9686
9687 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9688 }
9689
9690 return max_pixel_rate;
9691 }
9692
9693 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9694 {
9695 struct drm_i915_private *dev_priv = dev->dev_private;
9696 uint32_t val, data;
9697 int ret;
9698
9699 if (WARN((I915_READ(LCPLL_CTL) &
9700 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9701 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9702 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9703 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9704 "trying to change cdclk frequency with cdclk not enabled\n"))
9705 return;
9706
9707 mutex_lock(&dev_priv->rps.hw_lock);
9708 ret = sandybridge_pcode_write(dev_priv,
9709 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9710 mutex_unlock(&dev_priv->rps.hw_lock);
9711 if (ret) {
9712 DRM_ERROR("failed to inform pcode about cdclk change\n");
9713 return;
9714 }
9715
9716 val = I915_READ(LCPLL_CTL);
9717 val |= LCPLL_CD_SOURCE_FCLK;
9718 I915_WRITE(LCPLL_CTL, val);
9719
9720 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9721 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9722 DRM_ERROR("Switching to FCLK failed\n");
9723
9724 val = I915_READ(LCPLL_CTL);
9725 val &= ~LCPLL_CLK_FREQ_MASK;
9726
9727 switch (cdclk) {
9728 case 450000:
9729 val |= LCPLL_CLK_FREQ_450;
9730 data = 0;
9731 break;
9732 case 540000:
9733 val |= LCPLL_CLK_FREQ_54O_BDW;
9734 data = 1;
9735 break;
9736 case 337500:
9737 val |= LCPLL_CLK_FREQ_337_5_BDW;
9738 data = 2;
9739 break;
9740 case 675000:
9741 val |= LCPLL_CLK_FREQ_675_BDW;
9742 data = 3;
9743 break;
9744 default:
9745 WARN(1, "invalid cdclk frequency\n");
9746 return;
9747 }
9748
9749 I915_WRITE(LCPLL_CTL, val);
9750
9751 val = I915_READ(LCPLL_CTL);
9752 val &= ~LCPLL_CD_SOURCE_FCLK;
9753 I915_WRITE(LCPLL_CTL, val);
9754
9755 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9756 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9757 DRM_ERROR("Switching back to LCPLL failed\n");
9758
9759 mutex_lock(&dev_priv->rps.hw_lock);
9760 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9761 mutex_unlock(&dev_priv->rps.hw_lock);
9762
9763 intel_update_cdclk(dev);
9764
9765 WARN(cdclk != dev_priv->cdclk_freq,
9766 "cdclk requested %d kHz but got %d kHz\n",
9767 cdclk, dev_priv->cdclk_freq);
9768 }
9769
9770 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9771 {
9772 struct drm_i915_private *dev_priv = to_i915(state->dev);
9773 int max_pixclk = ilk_max_pixel_rate(state);
9774 int cdclk;
9775
9776 /*
9777 * FIXME should also account for plane ratio
9778 * once 64bpp pixel formats are supported.
9779 */
9780 if (max_pixclk > 540000)
9781 cdclk = 675000;
9782 else if (max_pixclk > 450000)
9783 cdclk = 540000;
9784 else if (max_pixclk > 337500)
9785 cdclk = 450000;
9786 else
9787 cdclk = 337500;
9788
9789 if (cdclk > dev_priv->max_cdclk_freq) {
9790 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9791 cdclk, dev_priv->max_cdclk_freq);
9792 return -EINVAL;
9793 }
9794
9795 to_intel_atomic_state(state)->cdclk = cdclk;
9796
9797 return 0;
9798 }
9799
9800 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9801 {
9802 struct drm_device *dev = old_state->dev;
9803 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9804
9805 broadwell_set_cdclk(dev, req_cdclk);
9806 }
9807
9808 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9809 struct intel_crtc_state *crtc_state)
9810 {
9811 if (!intel_ddi_pll_select(crtc, crtc_state))
9812 return -EINVAL;
9813
9814 crtc->lowfreq_avail = false;
9815
9816 return 0;
9817 }
9818
9819 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9820 enum port port,
9821 struct intel_crtc_state *pipe_config)
9822 {
9823 switch (port) {
9824 case PORT_A:
9825 pipe_config->ddi_pll_sel = SKL_DPLL0;
9826 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9827 break;
9828 case PORT_B:
9829 pipe_config->ddi_pll_sel = SKL_DPLL1;
9830 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9831 break;
9832 case PORT_C:
9833 pipe_config->ddi_pll_sel = SKL_DPLL2;
9834 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9835 break;
9836 default:
9837 DRM_ERROR("Incorrect port type\n");
9838 }
9839 }
9840
9841 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9842 enum port port,
9843 struct intel_crtc_state *pipe_config)
9844 {
9845 u32 temp, dpll_ctl1;
9846
9847 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9848 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9849
9850 switch (pipe_config->ddi_pll_sel) {
9851 case SKL_DPLL0:
9852 /*
9853 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9854 * of the shared DPLL framework and thus needs to be read out
9855 * separately
9856 */
9857 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9858 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9859 break;
9860 case SKL_DPLL1:
9861 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9862 break;
9863 case SKL_DPLL2:
9864 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9865 break;
9866 case SKL_DPLL3:
9867 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9868 break;
9869 }
9870 }
9871
9872 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9873 enum port port,
9874 struct intel_crtc_state *pipe_config)
9875 {
9876 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9877
9878 switch (pipe_config->ddi_pll_sel) {
9879 case PORT_CLK_SEL_WRPLL1:
9880 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9881 break;
9882 case PORT_CLK_SEL_WRPLL2:
9883 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9884 break;
9885 case PORT_CLK_SEL_SPLL:
9886 pipe_config->shared_dpll = DPLL_ID_SPLL;
9887 break;
9888 }
9889 }
9890
9891 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9892 struct intel_crtc_state *pipe_config)
9893 {
9894 struct drm_device *dev = crtc->base.dev;
9895 struct drm_i915_private *dev_priv = dev->dev_private;
9896 struct intel_shared_dpll *pll;
9897 enum port port;
9898 uint32_t tmp;
9899
9900 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9901
9902 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9903
9904 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9905 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9906 else if (IS_BROXTON(dev))
9907 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9908 else
9909 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9910
9911 if (pipe_config->shared_dpll >= 0) {
9912 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9913
9914 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9915 &pipe_config->dpll_hw_state));
9916 }
9917
9918 /*
9919 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9920 * DDI E. So just check whether this pipe is wired to DDI E and whether
9921 * the PCH transcoder is on.
9922 */
9923 if (INTEL_INFO(dev)->gen < 9 &&
9924 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9925 pipe_config->has_pch_encoder = true;
9926
9927 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9928 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9929 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9930
9931 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9932 }
9933 }
9934
9935 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9936 struct intel_crtc_state *pipe_config)
9937 {
9938 struct drm_device *dev = crtc->base.dev;
9939 struct drm_i915_private *dev_priv = dev->dev_private;
9940 enum intel_display_power_domain pfit_domain;
9941 uint32_t tmp;
9942
9943 if (!intel_display_power_is_enabled(dev_priv,
9944 POWER_DOMAIN_PIPE(crtc->pipe)))
9945 return false;
9946
9947 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9948 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9949
9950 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9951 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9952 enum pipe trans_edp_pipe;
9953 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9954 default:
9955 WARN(1, "unknown pipe linked to edp transcoder\n");
9956 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9957 case TRANS_DDI_EDP_INPUT_A_ON:
9958 trans_edp_pipe = PIPE_A;
9959 break;
9960 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9961 trans_edp_pipe = PIPE_B;
9962 break;
9963 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9964 trans_edp_pipe = PIPE_C;
9965 break;
9966 }
9967
9968 if (trans_edp_pipe == crtc->pipe)
9969 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9970 }
9971
9972 if (!intel_display_power_is_enabled(dev_priv,
9973 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9974 return false;
9975
9976 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9977 if (!(tmp & PIPECONF_ENABLE))
9978 return false;
9979
9980 haswell_get_ddi_port_state(crtc, pipe_config);
9981
9982 intel_get_pipe_timings(crtc, pipe_config);
9983
9984 if (INTEL_INFO(dev)->gen >= 9) {
9985 skl_init_scalers(dev, crtc, pipe_config);
9986 }
9987
9988 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9989
9990 if (INTEL_INFO(dev)->gen >= 9) {
9991 pipe_config->scaler_state.scaler_id = -1;
9992 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9993 }
9994
9995 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9996 if (INTEL_INFO(dev)->gen >= 9)
9997 skylake_get_pfit_config(crtc, pipe_config);
9998 else
9999 ironlake_get_pfit_config(crtc, pipe_config);
10000 }
10001
10002 if (IS_HASWELL(dev))
10003 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10004 (I915_READ(IPS_CTL) & IPS_ENABLE);
10005
10006 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10007 pipe_config->pixel_multiplier =
10008 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10009 } else {
10010 pipe_config->pixel_multiplier = 1;
10011 }
10012
10013 return true;
10014 }
10015
10016 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10017 {
10018 struct drm_device *dev = crtc->dev;
10019 struct drm_i915_private *dev_priv = dev->dev_private;
10020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10021 uint32_t cntl = 0, size = 0;
10022
10023 if (on) {
10024 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10025 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10026 unsigned int stride = roundup_pow_of_two(width) * 4;
10027
10028 switch (stride) {
10029 default:
10030 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10031 width, stride);
10032 stride = 256;
10033 /* fallthrough */
10034 case 256:
10035 case 512:
10036 case 1024:
10037 case 2048:
10038 break;
10039 }
10040
10041 cntl |= CURSOR_ENABLE |
10042 CURSOR_GAMMA_ENABLE |
10043 CURSOR_FORMAT_ARGB |
10044 CURSOR_STRIDE(stride);
10045
10046 size = (height << 12) | width;
10047 }
10048
10049 if (intel_crtc->cursor_cntl != 0 &&
10050 (intel_crtc->cursor_base != base ||
10051 intel_crtc->cursor_size != size ||
10052 intel_crtc->cursor_cntl != cntl)) {
10053 /* On these chipsets we can only modify the base/size/stride
10054 * whilst the cursor is disabled.
10055 */
10056 I915_WRITE(CURCNTR(PIPE_A), 0);
10057 POSTING_READ(CURCNTR(PIPE_A));
10058 intel_crtc->cursor_cntl = 0;
10059 }
10060
10061 if (intel_crtc->cursor_base != base) {
10062 I915_WRITE(CURBASE(PIPE_A), base);
10063 intel_crtc->cursor_base = base;
10064 }
10065
10066 if (intel_crtc->cursor_size != size) {
10067 I915_WRITE(CURSIZE, size);
10068 intel_crtc->cursor_size = size;
10069 }
10070
10071 if (intel_crtc->cursor_cntl != cntl) {
10072 I915_WRITE(CURCNTR(PIPE_A), cntl);
10073 POSTING_READ(CURCNTR(PIPE_A));
10074 intel_crtc->cursor_cntl = cntl;
10075 }
10076 }
10077
10078 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10079 {
10080 struct drm_device *dev = crtc->dev;
10081 struct drm_i915_private *dev_priv = dev->dev_private;
10082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10083 int pipe = intel_crtc->pipe;
10084 uint32_t cntl = 0;
10085
10086 if (on) {
10087 cntl = MCURSOR_GAMMA_ENABLE;
10088 switch (intel_crtc->base.cursor->state->crtc_w) {
10089 case 64:
10090 cntl |= CURSOR_MODE_64_ARGB_AX;
10091 break;
10092 case 128:
10093 cntl |= CURSOR_MODE_128_ARGB_AX;
10094 break;
10095 case 256:
10096 cntl |= CURSOR_MODE_256_ARGB_AX;
10097 break;
10098 default:
10099 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10100 return;
10101 }
10102 cntl |= pipe << 28; /* Connect to correct pipe */
10103
10104 if (HAS_DDI(dev))
10105 cntl |= CURSOR_PIPE_CSC_ENABLE;
10106 }
10107
10108 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10109 cntl |= CURSOR_ROTATE_180;
10110
10111 if (intel_crtc->cursor_cntl != cntl) {
10112 I915_WRITE(CURCNTR(pipe), cntl);
10113 POSTING_READ(CURCNTR(pipe));
10114 intel_crtc->cursor_cntl = cntl;
10115 }
10116
10117 /* and commit changes on next vblank */
10118 I915_WRITE(CURBASE(pipe), base);
10119 POSTING_READ(CURBASE(pipe));
10120
10121 intel_crtc->cursor_base = base;
10122 }
10123
10124 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10125 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10126 bool on)
10127 {
10128 struct drm_device *dev = crtc->dev;
10129 struct drm_i915_private *dev_priv = dev->dev_private;
10130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10131 int pipe = intel_crtc->pipe;
10132 struct drm_plane_state *cursor_state = crtc->cursor->state;
10133 int x = cursor_state->crtc_x;
10134 int y = cursor_state->crtc_y;
10135 u32 base = 0, pos = 0;
10136
10137 base = intel_crtc->cursor_addr;
10138
10139 if (x >= intel_crtc->config->pipe_src_w)
10140 on = false;
10141
10142 if (y >= intel_crtc->config->pipe_src_h)
10143 on = false;
10144
10145 if (x < 0) {
10146 if (x + cursor_state->crtc_w <= 0)
10147 on = false;
10148
10149 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10150 x = -x;
10151 }
10152 pos |= x << CURSOR_X_SHIFT;
10153
10154 if (y < 0) {
10155 if (y + cursor_state->crtc_h <= 0)
10156 on = false;
10157
10158 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10159 y = -y;
10160 }
10161 pos |= y << CURSOR_Y_SHIFT;
10162
10163 I915_WRITE(CURPOS(pipe), pos);
10164
10165 /* ILK+ do this automagically */
10166 if (HAS_GMCH_DISPLAY(dev) &&
10167 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10168 base += (cursor_state->crtc_h *
10169 cursor_state->crtc_w - 1) * 4;
10170 }
10171
10172 if (IS_845G(dev) || IS_I865G(dev))
10173 i845_update_cursor(crtc, base, on);
10174 else
10175 i9xx_update_cursor(crtc, base, on);
10176 }
10177
10178 static bool cursor_size_ok(struct drm_device *dev,
10179 uint32_t width, uint32_t height)
10180 {
10181 if (width == 0 || height == 0)
10182 return false;
10183
10184 /*
10185 * 845g/865g are special in that they are only limited by
10186 * the width of their cursors, the height is arbitrary up to
10187 * the precision of the register. Everything else requires
10188 * square cursors, limited to a few power-of-two sizes.
10189 */
10190 if (IS_845G(dev) || IS_I865G(dev)) {
10191 if ((width & 63) != 0)
10192 return false;
10193
10194 if (width > (IS_845G(dev) ? 64 : 512))
10195 return false;
10196
10197 if (height > 1023)
10198 return false;
10199 } else {
10200 switch (width | height) {
10201 case 256:
10202 case 128:
10203 if (IS_GEN2(dev))
10204 return false;
10205 case 64:
10206 break;
10207 default:
10208 return false;
10209 }
10210 }
10211
10212 return true;
10213 }
10214
10215 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10216 u16 *blue, uint32_t start, uint32_t size)
10217 {
10218 int end = (start + size > 256) ? 256 : start + size, i;
10219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10220
10221 for (i = start; i < end; i++) {
10222 intel_crtc->lut_r[i] = red[i] >> 8;
10223 intel_crtc->lut_g[i] = green[i] >> 8;
10224 intel_crtc->lut_b[i] = blue[i] >> 8;
10225 }
10226
10227 intel_crtc_load_lut(crtc);
10228 }
10229
10230 /* VESA 640x480x72Hz mode to set on the pipe */
10231 static struct drm_display_mode load_detect_mode = {
10232 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10233 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10234 };
10235
10236 struct drm_framebuffer *
10237 __intel_framebuffer_create(struct drm_device *dev,
10238 struct drm_mode_fb_cmd2 *mode_cmd,
10239 struct drm_i915_gem_object *obj)
10240 {
10241 struct intel_framebuffer *intel_fb;
10242 int ret;
10243
10244 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10245 if (!intel_fb)
10246 return ERR_PTR(-ENOMEM);
10247
10248 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10249 if (ret)
10250 goto err;
10251
10252 return &intel_fb->base;
10253
10254 err:
10255 kfree(intel_fb);
10256 return ERR_PTR(ret);
10257 }
10258
10259 static struct drm_framebuffer *
10260 intel_framebuffer_create(struct drm_device *dev,
10261 struct drm_mode_fb_cmd2 *mode_cmd,
10262 struct drm_i915_gem_object *obj)
10263 {
10264 struct drm_framebuffer *fb;
10265 int ret;
10266
10267 ret = i915_mutex_lock_interruptible(dev);
10268 if (ret)
10269 return ERR_PTR(ret);
10270 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10271 mutex_unlock(&dev->struct_mutex);
10272
10273 return fb;
10274 }
10275
10276 static u32
10277 intel_framebuffer_pitch_for_width(int width, int bpp)
10278 {
10279 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10280 return ALIGN(pitch, 64);
10281 }
10282
10283 static u32
10284 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10285 {
10286 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10287 return PAGE_ALIGN(pitch * mode->vdisplay);
10288 }
10289
10290 static struct drm_framebuffer *
10291 intel_framebuffer_create_for_mode(struct drm_device *dev,
10292 struct drm_display_mode *mode,
10293 int depth, int bpp)
10294 {
10295 struct drm_framebuffer *fb;
10296 struct drm_i915_gem_object *obj;
10297 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10298
10299 obj = i915_gem_alloc_object(dev,
10300 intel_framebuffer_size_for_mode(mode, bpp));
10301 if (obj == NULL)
10302 return ERR_PTR(-ENOMEM);
10303
10304 mode_cmd.width = mode->hdisplay;
10305 mode_cmd.height = mode->vdisplay;
10306 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10307 bpp);
10308 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10309
10310 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10311 if (IS_ERR(fb))
10312 drm_gem_object_unreference_unlocked(&obj->base);
10313
10314 return fb;
10315 }
10316
10317 static struct drm_framebuffer *
10318 mode_fits_in_fbdev(struct drm_device *dev,
10319 struct drm_display_mode *mode)
10320 {
10321 #ifdef CONFIG_DRM_FBDEV_EMULATION
10322 struct drm_i915_private *dev_priv = dev->dev_private;
10323 struct drm_i915_gem_object *obj;
10324 struct drm_framebuffer *fb;
10325
10326 if (!dev_priv->fbdev)
10327 return NULL;
10328
10329 if (!dev_priv->fbdev->fb)
10330 return NULL;
10331
10332 obj = dev_priv->fbdev->fb->obj;
10333 BUG_ON(!obj);
10334
10335 fb = &dev_priv->fbdev->fb->base;
10336 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10337 fb->bits_per_pixel))
10338 return NULL;
10339
10340 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10341 return NULL;
10342
10343 return fb;
10344 #else
10345 return NULL;
10346 #endif
10347 }
10348
10349 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10350 struct drm_crtc *crtc,
10351 struct drm_display_mode *mode,
10352 struct drm_framebuffer *fb,
10353 int x, int y)
10354 {
10355 struct drm_plane_state *plane_state;
10356 int hdisplay, vdisplay;
10357 int ret;
10358
10359 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10360 if (IS_ERR(plane_state))
10361 return PTR_ERR(plane_state);
10362
10363 if (mode)
10364 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10365 else
10366 hdisplay = vdisplay = 0;
10367
10368 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10369 if (ret)
10370 return ret;
10371 drm_atomic_set_fb_for_plane(plane_state, fb);
10372 plane_state->crtc_x = 0;
10373 plane_state->crtc_y = 0;
10374 plane_state->crtc_w = hdisplay;
10375 plane_state->crtc_h = vdisplay;
10376 plane_state->src_x = x << 16;
10377 plane_state->src_y = y << 16;
10378 plane_state->src_w = hdisplay << 16;
10379 plane_state->src_h = vdisplay << 16;
10380
10381 return 0;
10382 }
10383
10384 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10385 struct drm_display_mode *mode,
10386 struct intel_load_detect_pipe *old,
10387 struct drm_modeset_acquire_ctx *ctx)
10388 {
10389 struct intel_crtc *intel_crtc;
10390 struct intel_encoder *intel_encoder =
10391 intel_attached_encoder(connector);
10392 struct drm_crtc *possible_crtc;
10393 struct drm_encoder *encoder = &intel_encoder->base;
10394 struct drm_crtc *crtc = NULL;
10395 struct drm_device *dev = encoder->dev;
10396 struct drm_framebuffer *fb;
10397 struct drm_mode_config *config = &dev->mode_config;
10398 struct drm_atomic_state *state = NULL;
10399 struct drm_connector_state *connector_state;
10400 struct intel_crtc_state *crtc_state;
10401 int ret, i = -1;
10402
10403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10404 connector->base.id, connector->name,
10405 encoder->base.id, encoder->name);
10406
10407 retry:
10408 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10409 if (ret)
10410 goto fail;
10411
10412 /*
10413 * Algorithm gets a little messy:
10414 *
10415 * - if the connector already has an assigned crtc, use it (but make
10416 * sure it's on first)
10417 *
10418 * - try to find the first unused crtc that can drive this connector,
10419 * and use that if we find one
10420 */
10421
10422 /* See if we already have a CRTC for this connector */
10423 if (encoder->crtc) {
10424 crtc = encoder->crtc;
10425
10426 ret = drm_modeset_lock(&crtc->mutex, ctx);
10427 if (ret)
10428 goto fail;
10429 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10430 if (ret)
10431 goto fail;
10432
10433 old->dpms_mode = connector->dpms;
10434 old->load_detect_temp = false;
10435
10436 /* Make sure the crtc and connector are running */
10437 if (connector->dpms != DRM_MODE_DPMS_ON)
10438 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10439
10440 return true;
10441 }
10442
10443 /* Find an unused one (if possible) */
10444 for_each_crtc(dev, possible_crtc) {
10445 i++;
10446 if (!(encoder->possible_crtcs & (1 << i)))
10447 continue;
10448 if (possible_crtc->state->enable)
10449 continue;
10450
10451 crtc = possible_crtc;
10452 break;
10453 }
10454
10455 /*
10456 * If we didn't find an unused CRTC, don't use any.
10457 */
10458 if (!crtc) {
10459 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10460 goto fail;
10461 }
10462
10463 ret = drm_modeset_lock(&crtc->mutex, ctx);
10464 if (ret)
10465 goto fail;
10466 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10467 if (ret)
10468 goto fail;
10469
10470 intel_crtc = to_intel_crtc(crtc);
10471 old->dpms_mode = connector->dpms;
10472 old->load_detect_temp = true;
10473 old->release_fb = NULL;
10474
10475 state = drm_atomic_state_alloc(dev);
10476 if (!state)
10477 return false;
10478
10479 state->acquire_ctx = ctx;
10480
10481 connector_state = drm_atomic_get_connector_state(state, connector);
10482 if (IS_ERR(connector_state)) {
10483 ret = PTR_ERR(connector_state);
10484 goto fail;
10485 }
10486
10487 connector_state->crtc = crtc;
10488 connector_state->best_encoder = &intel_encoder->base;
10489
10490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10491 if (IS_ERR(crtc_state)) {
10492 ret = PTR_ERR(crtc_state);
10493 goto fail;
10494 }
10495
10496 crtc_state->base.active = crtc_state->base.enable = true;
10497
10498 if (!mode)
10499 mode = &load_detect_mode;
10500
10501 /* We need a framebuffer large enough to accommodate all accesses
10502 * that the plane may generate whilst we perform load detection.
10503 * We can not rely on the fbcon either being present (we get called
10504 * during its initialisation to detect all boot displays, or it may
10505 * not even exist) or that it is large enough to satisfy the
10506 * requested mode.
10507 */
10508 fb = mode_fits_in_fbdev(dev, mode);
10509 if (fb == NULL) {
10510 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10511 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10512 old->release_fb = fb;
10513 } else
10514 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10515 if (IS_ERR(fb)) {
10516 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10517 goto fail;
10518 }
10519
10520 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10521 if (ret)
10522 goto fail;
10523
10524 drm_mode_copy(&crtc_state->base.mode, mode);
10525
10526 if (drm_atomic_commit(state)) {
10527 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10528 if (old->release_fb)
10529 old->release_fb->funcs->destroy(old->release_fb);
10530 goto fail;
10531 }
10532 crtc->primary->crtc = crtc;
10533
10534 /* let the connector get through one full cycle before testing */
10535 intel_wait_for_vblank(dev, intel_crtc->pipe);
10536 return true;
10537
10538 fail:
10539 drm_atomic_state_free(state);
10540 state = NULL;
10541
10542 if (ret == -EDEADLK) {
10543 drm_modeset_backoff(ctx);
10544 goto retry;
10545 }
10546
10547 return false;
10548 }
10549
10550 void intel_release_load_detect_pipe(struct drm_connector *connector,
10551 struct intel_load_detect_pipe *old,
10552 struct drm_modeset_acquire_ctx *ctx)
10553 {
10554 struct drm_device *dev = connector->dev;
10555 struct intel_encoder *intel_encoder =
10556 intel_attached_encoder(connector);
10557 struct drm_encoder *encoder = &intel_encoder->base;
10558 struct drm_crtc *crtc = encoder->crtc;
10559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10560 struct drm_atomic_state *state;
10561 struct drm_connector_state *connector_state;
10562 struct intel_crtc_state *crtc_state;
10563 int ret;
10564
10565 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10566 connector->base.id, connector->name,
10567 encoder->base.id, encoder->name);
10568
10569 if (old->load_detect_temp) {
10570 state = drm_atomic_state_alloc(dev);
10571 if (!state)
10572 goto fail;
10573
10574 state->acquire_ctx = ctx;
10575
10576 connector_state = drm_atomic_get_connector_state(state, connector);
10577 if (IS_ERR(connector_state))
10578 goto fail;
10579
10580 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10581 if (IS_ERR(crtc_state))
10582 goto fail;
10583
10584 connector_state->best_encoder = NULL;
10585 connector_state->crtc = NULL;
10586
10587 crtc_state->base.enable = crtc_state->base.active = false;
10588
10589 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10590 0, 0);
10591 if (ret)
10592 goto fail;
10593
10594 ret = drm_atomic_commit(state);
10595 if (ret)
10596 goto fail;
10597
10598 if (old->release_fb) {
10599 drm_framebuffer_unregister_private(old->release_fb);
10600 drm_framebuffer_unreference(old->release_fb);
10601 }
10602
10603 return;
10604 }
10605
10606 /* Switch crtc and encoder back off if necessary */
10607 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10608 connector->funcs->dpms(connector, old->dpms_mode);
10609
10610 return;
10611 fail:
10612 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10613 drm_atomic_state_free(state);
10614 }
10615
10616 static int i9xx_pll_refclk(struct drm_device *dev,
10617 const struct intel_crtc_state *pipe_config)
10618 {
10619 struct drm_i915_private *dev_priv = dev->dev_private;
10620 u32 dpll = pipe_config->dpll_hw_state.dpll;
10621
10622 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10623 return dev_priv->vbt.lvds_ssc_freq;
10624 else if (HAS_PCH_SPLIT(dev))
10625 return 120000;
10626 else if (!IS_GEN2(dev))
10627 return 96000;
10628 else
10629 return 48000;
10630 }
10631
10632 /* Returns the clock of the currently programmed mode of the given pipe. */
10633 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10634 struct intel_crtc_state *pipe_config)
10635 {
10636 struct drm_device *dev = crtc->base.dev;
10637 struct drm_i915_private *dev_priv = dev->dev_private;
10638 int pipe = pipe_config->cpu_transcoder;
10639 u32 dpll = pipe_config->dpll_hw_state.dpll;
10640 u32 fp;
10641 intel_clock_t clock;
10642 int port_clock;
10643 int refclk = i9xx_pll_refclk(dev, pipe_config);
10644
10645 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10646 fp = pipe_config->dpll_hw_state.fp0;
10647 else
10648 fp = pipe_config->dpll_hw_state.fp1;
10649
10650 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10651 if (IS_PINEVIEW(dev)) {
10652 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10653 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10654 } else {
10655 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10656 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10657 }
10658
10659 if (!IS_GEN2(dev)) {
10660 if (IS_PINEVIEW(dev))
10661 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10662 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10663 else
10664 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10665 DPLL_FPA01_P1_POST_DIV_SHIFT);
10666
10667 switch (dpll & DPLL_MODE_MASK) {
10668 case DPLLB_MODE_DAC_SERIAL:
10669 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10670 5 : 10;
10671 break;
10672 case DPLLB_MODE_LVDS:
10673 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10674 7 : 14;
10675 break;
10676 default:
10677 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10678 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10679 return;
10680 }
10681
10682 if (IS_PINEVIEW(dev))
10683 port_clock = pnv_calc_dpll_params(refclk, &clock);
10684 else
10685 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10686 } else {
10687 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10688 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10689
10690 if (is_lvds) {
10691 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10692 DPLL_FPA01_P1_POST_DIV_SHIFT);
10693
10694 if (lvds & LVDS_CLKB_POWER_UP)
10695 clock.p2 = 7;
10696 else
10697 clock.p2 = 14;
10698 } else {
10699 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10700 clock.p1 = 2;
10701 else {
10702 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10703 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10704 }
10705 if (dpll & PLL_P2_DIVIDE_BY_4)
10706 clock.p2 = 4;
10707 else
10708 clock.p2 = 2;
10709 }
10710
10711 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10712 }
10713
10714 /*
10715 * This value includes pixel_multiplier. We will use
10716 * port_clock to compute adjusted_mode.crtc_clock in the
10717 * encoder's get_config() function.
10718 */
10719 pipe_config->port_clock = port_clock;
10720 }
10721
10722 int intel_dotclock_calculate(int link_freq,
10723 const struct intel_link_m_n *m_n)
10724 {
10725 /*
10726 * The calculation for the data clock is:
10727 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10728 * But we want to avoid losing precison if possible, so:
10729 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10730 *
10731 * and the link clock is simpler:
10732 * link_clock = (m * link_clock) / n
10733 */
10734
10735 if (!m_n->link_n)
10736 return 0;
10737
10738 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10739 }
10740
10741 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10742 struct intel_crtc_state *pipe_config)
10743 {
10744 struct drm_device *dev = crtc->base.dev;
10745
10746 /* read out port_clock from the DPLL */
10747 i9xx_crtc_clock_get(crtc, pipe_config);
10748
10749 /*
10750 * This value does not include pixel_multiplier.
10751 * We will check that port_clock and adjusted_mode.crtc_clock
10752 * agree once we know their relationship in the encoder's
10753 * get_config() function.
10754 */
10755 pipe_config->base.adjusted_mode.crtc_clock =
10756 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10757 &pipe_config->fdi_m_n);
10758 }
10759
10760 /** Returns the currently programmed mode of the given pipe. */
10761 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10762 struct drm_crtc *crtc)
10763 {
10764 struct drm_i915_private *dev_priv = dev->dev_private;
10765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10766 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10767 struct drm_display_mode *mode;
10768 struct intel_crtc_state pipe_config;
10769 int htot = I915_READ(HTOTAL(cpu_transcoder));
10770 int hsync = I915_READ(HSYNC(cpu_transcoder));
10771 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10772 int vsync = I915_READ(VSYNC(cpu_transcoder));
10773 enum pipe pipe = intel_crtc->pipe;
10774
10775 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10776 if (!mode)
10777 return NULL;
10778
10779 /*
10780 * Construct a pipe_config sufficient for getting the clock info
10781 * back out of crtc_clock_get.
10782 *
10783 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10784 * to use a real value here instead.
10785 */
10786 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10787 pipe_config.pixel_multiplier = 1;
10788 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10789 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10790 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10791 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10792
10793 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10794 mode->hdisplay = (htot & 0xffff) + 1;
10795 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10796 mode->hsync_start = (hsync & 0xffff) + 1;
10797 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10798 mode->vdisplay = (vtot & 0xffff) + 1;
10799 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10800 mode->vsync_start = (vsync & 0xffff) + 1;
10801 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10802
10803 drm_mode_set_name(mode);
10804
10805 return mode;
10806 }
10807
10808 void intel_mark_busy(struct drm_device *dev)
10809 {
10810 struct drm_i915_private *dev_priv = dev->dev_private;
10811
10812 if (dev_priv->mm.busy)
10813 return;
10814
10815 intel_runtime_pm_get(dev_priv);
10816 i915_update_gfx_val(dev_priv);
10817 if (INTEL_INFO(dev)->gen >= 6)
10818 gen6_rps_busy(dev_priv);
10819 dev_priv->mm.busy = true;
10820 }
10821
10822 void intel_mark_idle(struct drm_device *dev)
10823 {
10824 struct drm_i915_private *dev_priv = dev->dev_private;
10825
10826 if (!dev_priv->mm.busy)
10827 return;
10828
10829 dev_priv->mm.busy = false;
10830
10831 if (INTEL_INFO(dev)->gen >= 6)
10832 gen6_rps_idle(dev->dev_private);
10833
10834 intel_runtime_pm_put(dev_priv);
10835 }
10836
10837 static void intel_crtc_destroy(struct drm_crtc *crtc)
10838 {
10839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10840 struct drm_device *dev = crtc->dev;
10841 struct intel_unpin_work *work;
10842
10843 spin_lock_irq(&dev->event_lock);
10844 work = intel_crtc->unpin_work;
10845 intel_crtc->unpin_work = NULL;
10846 spin_unlock_irq(&dev->event_lock);
10847
10848 if (work) {
10849 cancel_work_sync(&work->work);
10850 kfree(work);
10851 }
10852
10853 drm_crtc_cleanup(crtc);
10854
10855 kfree(intel_crtc);
10856 }
10857
10858 static void intel_unpin_work_fn(struct work_struct *__work)
10859 {
10860 struct intel_unpin_work *work =
10861 container_of(__work, struct intel_unpin_work, work);
10862 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10863 struct drm_device *dev = crtc->base.dev;
10864 struct drm_plane *primary = crtc->base.primary;
10865
10866 mutex_lock(&dev->struct_mutex);
10867 intel_unpin_fb_obj(work->old_fb, primary->state);
10868 drm_gem_object_unreference(&work->pending_flip_obj->base);
10869
10870 if (work->flip_queued_req)
10871 i915_gem_request_assign(&work->flip_queued_req, NULL);
10872 mutex_unlock(&dev->struct_mutex);
10873
10874 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10875 drm_framebuffer_unreference(work->old_fb);
10876
10877 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10878 atomic_dec(&crtc->unpin_work_count);
10879
10880 kfree(work);
10881 }
10882
10883 static void do_intel_finish_page_flip(struct drm_device *dev,
10884 struct drm_crtc *crtc)
10885 {
10886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10887 struct intel_unpin_work *work;
10888 unsigned long flags;
10889
10890 /* Ignore early vblank irqs */
10891 if (intel_crtc == NULL)
10892 return;
10893
10894 /*
10895 * This is called both by irq handlers and the reset code (to complete
10896 * lost pageflips) so needs the full irqsave spinlocks.
10897 */
10898 spin_lock_irqsave(&dev->event_lock, flags);
10899 work = intel_crtc->unpin_work;
10900
10901 /* Ensure we don't miss a work->pending update ... */
10902 smp_rmb();
10903
10904 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10905 spin_unlock_irqrestore(&dev->event_lock, flags);
10906 return;
10907 }
10908
10909 page_flip_completed(intel_crtc);
10910
10911 spin_unlock_irqrestore(&dev->event_lock, flags);
10912 }
10913
10914 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10915 {
10916 struct drm_i915_private *dev_priv = dev->dev_private;
10917 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10918
10919 do_intel_finish_page_flip(dev, crtc);
10920 }
10921
10922 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10923 {
10924 struct drm_i915_private *dev_priv = dev->dev_private;
10925 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10926
10927 do_intel_finish_page_flip(dev, crtc);
10928 }
10929
10930 /* Is 'a' after or equal to 'b'? */
10931 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10932 {
10933 return !((a - b) & 0x80000000);
10934 }
10935
10936 static bool page_flip_finished(struct intel_crtc *crtc)
10937 {
10938 struct drm_device *dev = crtc->base.dev;
10939 struct drm_i915_private *dev_priv = dev->dev_private;
10940
10941 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10942 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10943 return true;
10944
10945 /*
10946 * The relevant registers doen't exist on pre-ctg.
10947 * As the flip done interrupt doesn't trigger for mmio
10948 * flips on gmch platforms, a flip count check isn't
10949 * really needed there. But since ctg has the registers,
10950 * include it in the check anyway.
10951 */
10952 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10953 return true;
10954
10955 /*
10956 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10957 * used the same base address. In that case the mmio flip might
10958 * have completed, but the CS hasn't even executed the flip yet.
10959 *
10960 * A flip count check isn't enough as the CS might have updated
10961 * the base address just after start of vblank, but before we
10962 * managed to process the interrupt. This means we'd complete the
10963 * CS flip too soon.
10964 *
10965 * Combining both checks should get us a good enough result. It may
10966 * still happen that the CS flip has been executed, but has not
10967 * yet actually completed. But in case the base address is the same
10968 * anyway, we don't really care.
10969 */
10970 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10971 crtc->unpin_work->gtt_offset &&
10972 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10973 crtc->unpin_work->flip_count);
10974 }
10975
10976 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10977 {
10978 struct drm_i915_private *dev_priv = dev->dev_private;
10979 struct intel_crtc *intel_crtc =
10980 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10981 unsigned long flags;
10982
10983
10984 /*
10985 * This is called both by irq handlers and the reset code (to complete
10986 * lost pageflips) so needs the full irqsave spinlocks.
10987 *
10988 * NB: An MMIO update of the plane base pointer will also
10989 * generate a page-flip completion irq, i.e. every modeset
10990 * is also accompanied by a spurious intel_prepare_page_flip().
10991 */
10992 spin_lock_irqsave(&dev->event_lock, flags);
10993 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10994 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10995 spin_unlock_irqrestore(&dev->event_lock, flags);
10996 }
10997
10998 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10999 {
11000 /* Ensure that the work item is consistent when activating it ... */
11001 smp_wmb();
11002 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11003 /* and that it is marked active as soon as the irq could fire. */
11004 smp_wmb();
11005 }
11006
11007 static int intel_gen2_queue_flip(struct drm_device *dev,
11008 struct drm_crtc *crtc,
11009 struct drm_framebuffer *fb,
11010 struct drm_i915_gem_object *obj,
11011 struct drm_i915_gem_request *req,
11012 uint32_t flags)
11013 {
11014 struct intel_engine_cs *ring = req->ring;
11015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11016 u32 flip_mask;
11017 int ret;
11018
11019 ret = intel_ring_begin(req, 6);
11020 if (ret)
11021 return ret;
11022
11023 /* Can't queue multiple flips, so wait for the previous
11024 * one to finish before executing the next.
11025 */
11026 if (intel_crtc->plane)
11027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11028 else
11029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11030 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11031 intel_ring_emit(ring, MI_NOOP);
11032 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11033 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11034 intel_ring_emit(ring, fb->pitches[0]);
11035 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11036 intel_ring_emit(ring, 0); /* aux display base address, unused */
11037
11038 intel_mark_page_flip_active(intel_crtc->unpin_work);
11039 return 0;
11040 }
11041
11042 static int intel_gen3_queue_flip(struct drm_device *dev,
11043 struct drm_crtc *crtc,
11044 struct drm_framebuffer *fb,
11045 struct drm_i915_gem_object *obj,
11046 struct drm_i915_gem_request *req,
11047 uint32_t flags)
11048 {
11049 struct intel_engine_cs *ring = req->ring;
11050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051 u32 flip_mask;
11052 int ret;
11053
11054 ret = intel_ring_begin(req, 6);
11055 if (ret)
11056 return ret;
11057
11058 if (intel_crtc->plane)
11059 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11060 else
11061 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11062 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11063 intel_ring_emit(ring, MI_NOOP);
11064 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066 intel_ring_emit(ring, fb->pitches[0]);
11067 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11068 intel_ring_emit(ring, MI_NOOP);
11069
11070 intel_mark_page_flip_active(intel_crtc->unpin_work);
11071 return 0;
11072 }
11073
11074 static int intel_gen4_queue_flip(struct drm_device *dev,
11075 struct drm_crtc *crtc,
11076 struct drm_framebuffer *fb,
11077 struct drm_i915_gem_object *obj,
11078 struct drm_i915_gem_request *req,
11079 uint32_t flags)
11080 {
11081 struct intel_engine_cs *ring = req->ring;
11082 struct drm_i915_private *dev_priv = dev->dev_private;
11083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11084 uint32_t pf, pipesrc;
11085 int ret;
11086
11087 ret = intel_ring_begin(req, 4);
11088 if (ret)
11089 return ret;
11090
11091 /* i965+ uses the linear or tiled offsets from the
11092 * Display Registers (which do not change across a page-flip)
11093 * so we need only reprogram the base address.
11094 */
11095 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11096 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11097 intel_ring_emit(ring, fb->pitches[0]);
11098 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11099 obj->tiling_mode);
11100
11101 /* XXX Enabling the panel-fitter across page-flip is so far
11102 * untested on non-native modes, so ignore it for now.
11103 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11104 */
11105 pf = 0;
11106 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11107 intel_ring_emit(ring, pf | pipesrc);
11108
11109 intel_mark_page_flip_active(intel_crtc->unpin_work);
11110 return 0;
11111 }
11112
11113 static int intel_gen6_queue_flip(struct drm_device *dev,
11114 struct drm_crtc *crtc,
11115 struct drm_framebuffer *fb,
11116 struct drm_i915_gem_object *obj,
11117 struct drm_i915_gem_request *req,
11118 uint32_t flags)
11119 {
11120 struct intel_engine_cs *ring = req->ring;
11121 struct drm_i915_private *dev_priv = dev->dev_private;
11122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11123 uint32_t pf, pipesrc;
11124 int ret;
11125
11126 ret = intel_ring_begin(req, 4);
11127 if (ret)
11128 return ret;
11129
11130 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11131 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11132 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11133 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11134
11135 /* Contrary to the suggestions in the documentation,
11136 * "Enable Panel Fitter" does not seem to be required when page
11137 * flipping with a non-native mode, and worse causes a normal
11138 * modeset to fail.
11139 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11140 */
11141 pf = 0;
11142 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11143 intel_ring_emit(ring, pf | pipesrc);
11144
11145 intel_mark_page_flip_active(intel_crtc->unpin_work);
11146 return 0;
11147 }
11148
11149 static int intel_gen7_queue_flip(struct drm_device *dev,
11150 struct drm_crtc *crtc,
11151 struct drm_framebuffer *fb,
11152 struct drm_i915_gem_object *obj,
11153 struct drm_i915_gem_request *req,
11154 uint32_t flags)
11155 {
11156 struct intel_engine_cs *ring = req->ring;
11157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11158 uint32_t plane_bit = 0;
11159 int len, ret;
11160
11161 switch (intel_crtc->plane) {
11162 case PLANE_A:
11163 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11164 break;
11165 case PLANE_B:
11166 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11167 break;
11168 case PLANE_C:
11169 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11170 break;
11171 default:
11172 WARN_ONCE(1, "unknown plane in flip command\n");
11173 return -ENODEV;
11174 }
11175
11176 len = 4;
11177 if (ring->id == RCS) {
11178 len += 6;
11179 /*
11180 * On Gen 8, SRM is now taking an extra dword to accommodate
11181 * 48bits addresses, and we need a NOOP for the batch size to
11182 * stay even.
11183 */
11184 if (IS_GEN8(dev))
11185 len += 2;
11186 }
11187
11188 /*
11189 * BSpec MI_DISPLAY_FLIP for IVB:
11190 * "The full packet must be contained within the same cache line."
11191 *
11192 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11193 * cacheline, if we ever start emitting more commands before
11194 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11195 * then do the cacheline alignment, and finally emit the
11196 * MI_DISPLAY_FLIP.
11197 */
11198 ret = intel_ring_cacheline_align(req);
11199 if (ret)
11200 return ret;
11201
11202 ret = intel_ring_begin(req, len);
11203 if (ret)
11204 return ret;
11205
11206 /* Unmask the flip-done completion message. Note that the bspec says that
11207 * we should do this for both the BCS and RCS, and that we must not unmask
11208 * more than one flip event at any time (or ensure that one flip message
11209 * can be sent by waiting for flip-done prior to queueing new flips).
11210 * Experimentation says that BCS works despite DERRMR masking all
11211 * flip-done completion events and that unmasking all planes at once
11212 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11213 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11214 */
11215 if (ring->id == RCS) {
11216 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11217 intel_ring_emit_reg(ring, DERRMR);
11218 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11219 DERRMR_PIPEB_PRI_FLIP_DONE |
11220 DERRMR_PIPEC_PRI_FLIP_DONE));
11221 if (IS_GEN8(dev))
11222 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11223 MI_SRM_LRM_GLOBAL_GTT);
11224 else
11225 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11226 MI_SRM_LRM_GLOBAL_GTT);
11227 intel_ring_emit_reg(ring, DERRMR);
11228 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11229 if (IS_GEN8(dev)) {
11230 intel_ring_emit(ring, 0);
11231 intel_ring_emit(ring, MI_NOOP);
11232 }
11233 }
11234
11235 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11236 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11237 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11238 intel_ring_emit(ring, (MI_NOOP));
11239
11240 intel_mark_page_flip_active(intel_crtc->unpin_work);
11241 return 0;
11242 }
11243
11244 static bool use_mmio_flip(struct intel_engine_cs *ring,
11245 struct drm_i915_gem_object *obj)
11246 {
11247 /*
11248 * This is not being used for older platforms, because
11249 * non-availability of flip done interrupt forces us to use
11250 * CS flips. Older platforms derive flip done using some clever
11251 * tricks involving the flip_pending status bits and vblank irqs.
11252 * So using MMIO flips there would disrupt this mechanism.
11253 */
11254
11255 if (ring == NULL)
11256 return true;
11257
11258 if (INTEL_INFO(ring->dev)->gen < 5)
11259 return false;
11260
11261 if (i915.use_mmio_flip < 0)
11262 return false;
11263 else if (i915.use_mmio_flip > 0)
11264 return true;
11265 else if (i915.enable_execlists)
11266 return true;
11267 else if (obj->base.dma_buf &&
11268 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11269 false))
11270 return true;
11271 else
11272 return ring != i915_gem_request_get_ring(obj->last_write_req);
11273 }
11274
11275 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11276 unsigned int rotation,
11277 struct intel_unpin_work *work)
11278 {
11279 struct drm_device *dev = intel_crtc->base.dev;
11280 struct drm_i915_private *dev_priv = dev->dev_private;
11281 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11282 const enum pipe pipe = intel_crtc->pipe;
11283 u32 ctl, stride, tile_height;
11284
11285 ctl = I915_READ(PLANE_CTL(pipe, 0));
11286 ctl &= ~PLANE_CTL_TILED_MASK;
11287 switch (fb->modifier[0]) {
11288 case DRM_FORMAT_MOD_NONE:
11289 break;
11290 case I915_FORMAT_MOD_X_TILED:
11291 ctl |= PLANE_CTL_TILED_X;
11292 break;
11293 case I915_FORMAT_MOD_Y_TILED:
11294 ctl |= PLANE_CTL_TILED_Y;
11295 break;
11296 case I915_FORMAT_MOD_Yf_TILED:
11297 ctl |= PLANE_CTL_TILED_YF;
11298 break;
11299 default:
11300 MISSING_CASE(fb->modifier[0]);
11301 }
11302
11303 /*
11304 * The stride is either expressed as a multiple of 64 bytes chunks for
11305 * linear buffers or in number of tiles for tiled buffers.
11306 */
11307 if (intel_rotation_90_or_270(rotation)) {
11308 /* stride = Surface height in tiles */
11309 tile_height = intel_tile_height(dev, fb->pixel_format,
11310 fb->modifier[0], 0);
11311 stride = DIV_ROUND_UP(fb->height, tile_height);
11312 } else {
11313 stride = fb->pitches[0] /
11314 intel_fb_stride_alignment(dev, fb->modifier[0],
11315 fb->pixel_format);
11316 }
11317
11318 /*
11319 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11320 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11321 */
11322 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11323 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11324
11325 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11326 POSTING_READ(PLANE_SURF(pipe, 0));
11327 }
11328
11329 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11330 struct intel_unpin_work *work)
11331 {
11332 struct drm_device *dev = intel_crtc->base.dev;
11333 struct drm_i915_private *dev_priv = dev->dev_private;
11334 struct intel_framebuffer *intel_fb =
11335 to_intel_framebuffer(intel_crtc->base.primary->fb);
11336 struct drm_i915_gem_object *obj = intel_fb->obj;
11337 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11338 u32 dspcntr;
11339
11340 dspcntr = I915_READ(reg);
11341
11342 if (obj->tiling_mode != I915_TILING_NONE)
11343 dspcntr |= DISPPLANE_TILED;
11344 else
11345 dspcntr &= ~DISPPLANE_TILED;
11346
11347 I915_WRITE(reg, dspcntr);
11348
11349 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11350 POSTING_READ(DSPSURF(intel_crtc->plane));
11351 }
11352
11353 /*
11354 * XXX: This is the temporary way to update the plane registers until we get
11355 * around to using the usual plane update functions for MMIO flips
11356 */
11357 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11358 {
11359 struct intel_crtc *crtc = mmio_flip->crtc;
11360 struct intel_unpin_work *work;
11361
11362 spin_lock_irq(&crtc->base.dev->event_lock);
11363 work = crtc->unpin_work;
11364 spin_unlock_irq(&crtc->base.dev->event_lock);
11365 if (work == NULL)
11366 return;
11367
11368 intel_mark_page_flip_active(work);
11369
11370 intel_pipe_update_start(crtc);
11371
11372 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11373 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11374 else
11375 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11376 ilk_do_mmio_flip(crtc, work);
11377
11378 intel_pipe_update_end(crtc);
11379 }
11380
11381 static void intel_mmio_flip_work_func(struct work_struct *work)
11382 {
11383 struct intel_mmio_flip *mmio_flip =
11384 container_of(work, struct intel_mmio_flip, work);
11385 struct intel_framebuffer *intel_fb =
11386 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11387 struct drm_i915_gem_object *obj = intel_fb->obj;
11388
11389 if (mmio_flip->req) {
11390 WARN_ON(__i915_wait_request(mmio_flip->req,
11391 mmio_flip->crtc->reset_counter,
11392 false, NULL,
11393 &mmio_flip->i915->rps.mmioflips));
11394 i915_gem_request_unreference__unlocked(mmio_flip->req);
11395 }
11396
11397 /* For framebuffer backed by dmabuf, wait for fence */
11398 if (obj->base.dma_buf)
11399 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11400 false, false,
11401 MAX_SCHEDULE_TIMEOUT) < 0);
11402
11403 intel_do_mmio_flip(mmio_flip);
11404 kfree(mmio_flip);
11405 }
11406
11407 static int intel_queue_mmio_flip(struct drm_device *dev,
11408 struct drm_crtc *crtc,
11409 struct drm_i915_gem_object *obj)
11410 {
11411 struct intel_mmio_flip *mmio_flip;
11412
11413 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11414 if (mmio_flip == NULL)
11415 return -ENOMEM;
11416
11417 mmio_flip->i915 = to_i915(dev);
11418 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11419 mmio_flip->crtc = to_intel_crtc(crtc);
11420 mmio_flip->rotation = crtc->primary->state->rotation;
11421
11422 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11423 schedule_work(&mmio_flip->work);
11424
11425 return 0;
11426 }
11427
11428 static int intel_default_queue_flip(struct drm_device *dev,
11429 struct drm_crtc *crtc,
11430 struct drm_framebuffer *fb,
11431 struct drm_i915_gem_object *obj,
11432 struct drm_i915_gem_request *req,
11433 uint32_t flags)
11434 {
11435 return -ENODEV;
11436 }
11437
11438 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11439 struct drm_crtc *crtc)
11440 {
11441 struct drm_i915_private *dev_priv = dev->dev_private;
11442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11443 struct intel_unpin_work *work = intel_crtc->unpin_work;
11444 u32 addr;
11445
11446 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11447 return true;
11448
11449 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11450 return false;
11451
11452 if (!work->enable_stall_check)
11453 return false;
11454
11455 if (work->flip_ready_vblank == 0) {
11456 if (work->flip_queued_req &&
11457 !i915_gem_request_completed(work->flip_queued_req, true))
11458 return false;
11459
11460 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11461 }
11462
11463 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11464 return false;
11465
11466 /* Potential stall - if we see that the flip has happened,
11467 * assume a missed interrupt. */
11468 if (INTEL_INFO(dev)->gen >= 4)
11469 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11470 else
11471 addr = I915_READ(DSPADDR(intel_crtc->plane));
11472
11473 /* There is a potential issue here with a false positive after a flip
11474 * to the same address. We could address this by checking for a
11475 * non-incrementing frame counter.
11476 */
11477 return addr == work->gtt_offset;
11478 }
11479
11480 void intel_check_page_flip(struct drm_device *dev, int pipe)
11481 {
11482 struct drm_i915_private *dev_priv = dev->dev_private;
11483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485 struct intel_unpin_work *work;
11486
11487 WARN_ON(!in_interrupt());
11488
11489 if (crtc == NULL)
11490 return;
11491
11492 spin_lock(&dev->event_lock);
11493 work = intel_crtc->unpin_work;
11494 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11495 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11496 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11497 page_flip_completed(intel_crtc);
11498 work = NULL;
11499 }
11500 if (work != NULL &&
11501 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11502 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11503 spin_unlock(&dev->event_lock);
11504 }
11505
11506 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11507 struct drm_framebuffer *fb,
11508 struct drm_pending_vblank_event *event,
11509 uint32_t page_flip_flags)
11510 {
11511 struct drm_device *dev = crtc->dev;
11512 struct drm_i915_private *dev_priv = dev->dev_private;
11513 struct drm_framebuffer *old_fb = crtc->primary->fb;
11514 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11516 struct drm_plane *primary = crtc->primary;
11517 enum pipe pipe = intel_crtc->pipe;
11518 struct intel_unpin_work *work;
11519 struct intel_engine_cs *ring;
11520 bool mmio_flip;
11521 struct drm_i915_gem_request *request = NULL;
11522 int ret;
11523
11524 /*
11525 * drm_mode_page_flip_ioctl() should already catch this, but double
11526 * check to be safe. In the future we may enable pageflipping from
11527 * a disabled primary plane.
11528 */
11529 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11530 return -EBUSY;
11531
11532 /* Can't change pixel format via MI display flips. */
11533 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11534 return -EINVAL;
11535
11536 /*
11537 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11538 * Note that pitch changes could also affect these register.
11539 */
11540 if (INTEL_INFO(dev)->gen > 3 &&
11541 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11542 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11543 return -EINVAL;
11544
11545 if (i915_terminally_wedged(&dev_priv->gpu_error))
11546 goto out_hang;
11547
11548 work = kzalloc(sizeof(*work), GFP_KERNEL);
11549 if (work == NULL)
11550 return -ENOMEM;
11551
11552 work->event = event;
11553 work->crtc = crtc;
11554 work->old_fb = old_fb;
11555 INIT_WORK(&work->work, intel_unpin_work_fn);
11556
11557 ret = drm_crtc_vblank_get(crtc);
11558 if (ret)
11559 goto free_work;
11560
11561 /* We borrow the event spin lock for protecting unpin_work */
11562 spin_lock_irq(&dev->event_lock);
11563 if (intel_crtc->unpin_work) {
11564 /* Before declaring the flip queue wedged, check if
11565 * the hardware completed the operation behind our backs.
11566 */
11567 if (__intel_pageflip_stall_check(dev, crtc)) {
11568 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11569 page_flip_completed(intel_crtc);
11570 } else {
11571 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11572 spin_unlock_irq(&dev->event_lock);
11573
11574 drm_crtc_vblank_put(crtc);
11575 kfree(work);
11576 return -EBUSY;
11577 }
11578 }
11579 intel_crtc->unpin_work = work;
11580 spin_unlock_irq(&dev->event_lock);
11581
11582 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11583 flush_workqueue(dev_priv->wq);
11584
11585 /* Reference the objects for the scheduled work. */
11586 drm_framebuffer_reference(work->old_fb);
11587 drm_gem_object_reference(&obj->base);
11588
11589 crtc->primary->fb = fb;
11590 update_state_fb(crtc->primary);
11591
11592 work->pending_flip_obj = obj;
11593
11594 ret = i915_mutex_lock_interruptible(dev);
11595 if (ret)
11596 goto cleanup;
11597
11598 atomic_inc(&intel_crtc->unpin_work_count);
11599 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11600
11601 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11602 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11603
11604 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11605 ring = &dev_priv->ring[BCS];
11606 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11607 /* vlv: DISPLAY_FLIP fails to change tiling */
11608 ring = NULL;
11609 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11610 ring = &dev_priv->ring[BCS];
11611 } else if (INTEL_INFO(dev)->gen >= 7) {
11612 ring = i915_gem_request_get_ring(obj->last_write_req);
11613 if (ring == NULL || ring->id != RCS)
11614 ring = &dev_priv->ring[BCS];
11615 } else {
11616 ring = &dev_priv->ring[RCS];
11617 }
11618
11619 mmio_flip = use_mmio_flip(ring, obj);
11620
11621 /* When using CS flips, we want to emit semaphores between rings.
11622 * However, when using mmio flips we will create a task to do the
11623 * synchronisation, so all we want here is to pin the framebuffer
11624 * into the display plane and skip any waits.
11625 */
11626 if (!mmio_flip) {
11627 ret = i915_gem_object_sync(obj, ring, &request);
11628 if (ret)
11629 goto cleanup_pending;
11630 }
11631
11632 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11633 crtc->primary->state);
11634 if (ret)
11635 goto cleanup_pending;
11636
11637 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11638 obj, 0);
11639 work->gtt_offset += intel_crtc->dspaddr_offset;
11640
11641 if (mmio_flip) {
11642 ret = intel_queue_mmio_flip(dev, crtc, obj);
11643 if (ret)
11644 goto cleanup_unpin;
11645
11646 i915_gem_request_assign(&work->flip_queued_req,
11647 obj->last_write_req);
11648 } else {
11649 if (!request) {
11650 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11651 if (ret)
11652 goto cleanup_unpin;
11653 }
11654
11655 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11656 page_flip_flags);
11657 if (ret)
11658 goto cleanup_unpin;
11659
11660 i915_gem_request_assign(&work->flip_queued_req, request);
11661 }
11662
11663 if (request)
11664 i915_add_request_no_flush(request);
11665
11666 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11667 work->enable_stall_check = true;
11668
11669 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11670 to_intel_plane(primary)->frontbuffer_bit);
11671 mutex_unlock(&dev->struct_mutex);
11672
11673 intel_fbc_deactivate(intel_crtc);
11674 intel_frontbuffer_flip_prepare(dev,
11675 to_intel_plane(primary)->frontbuffer_bit);
11676
11677 trace_i915_flip_request(intel_crtc->plane, obj);
11678
11679 return 0;
11680
11681 cleanup_unpin:
11682 intel_unpin_fb_obj(fb, crtc->primary->state);
11683 cleanup_pending:
11684 if (request)
11685 i915_gem_request_cancel(request);
11686 atomic_dec(&intel_crtc->unpin_work_count);
11687 mutex_unlock(&dev->struct_mutex);
11688 cleanup:
11689 crtc->primary->fb = old_fb;
11690 update_state_fb(crtc->primary);
11691
11692 drm_gem_object_unreference_unlocked(&obj->base);
11693 drm_framebuffer_unreference(work->old_fb);
11694
11695 spin_lock_irq(&dev->event_lock);
11696 intel_crtc->unpin_work = NULL;
11697 spin_unlock_irq(&dev->event_lock);
11698
11699 drm_crtc_vblank_put(crtc);
11700 free_work:
11701 kfree(work);
11702
11703 if (ret == -EIO) {
11704 struct drm_atomic_state *state;
11705 struct drm_plane_state *plane_state;
11706
11707 out_hang:
11708 state = drm_atomic_state_alloc(dev);
11709 if (!state)
11710 return -ENOMEM;
11711 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11712
11713 retry:
11714 plane_state = drm_atomic_get_plane_state(state, primary);
11715 ret = PTR_ERR_OR_ZERO(plane_state);
11716 if (!ret) {
11717 drm_atomic_set_fb_for_plane(plane_state, fb);
11718
11719 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11720 if (!ret)
11721 ret = drm_atomic_commit(state);
11722 }
11723
11724 if (ret == -EDEADLK) {
11725 drm_modeset_backoff(state->acquire_ctx);
11726 drm_atomic_state_clear(state);
11727 goto retry;
11728 }
11729
11730 if (ret)
11731 drm_atomic_state_free(state);
11732
11733 if (ret == 0 && event) {
11734 spin_lock_irq(&dev->event_lock);
11735 drm_send_vblank_event(dev, pipe, event);
11736 spin_unlock_irq(&dev->event_lock);
11737 }
11738 }
11739 return ret;
11740 }
11741
11742
11743 /**
11744 * intel_wm_need_update - Check whether watermarks need updating
11745 * @plane: drm plane
11746 * @state: new plane state
11747 *
11748 * Check current plane state versus the new one to determine whether
11749 * watermarks need to be recalculated.
11750 *
11751 * Returns true or false.
11752 */
11753 static bool intel_wm_need_update(struct drm_plane *plane,
11754 struct drm_plane_state *state)
11755 {
11756 struct intel_plane_state *new = to_intel_plane_state(state);
11757 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11758
11759 /* Update watermarks on tiling or size changes. */
11760 if (new->visible != cur->visible)
11761 return true;
11762
11763 if (!cur->base.fb || !new->base.fb)
11764 return false;
11765
11766 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11767 cur->base.rotation != new->base.rotation ||
11768 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11769 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11770 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11771 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11772 return true;
11773
11774 return false;
11775 }
11776
11777 static bool needs_scaling(struct intel_plane_state *state)
11778 {
11779 int src_w = drm_rect_width(&state->src) >> 16;
11780 int src_h = drm_rect_height(&state->src) >> 16;
11781 int dst_w = drm_rect_width(&state->dst);
11782 int dst_h = drm_rect_height(&state->dst);
11783
11784 return (src_w != dst_w || src_h != dst_h);
11785 }
11786
11787 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11788 struct drm_plane_state *plane_state)
11789 {
11790 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11791 struct drm_crtc *crtc = crtc_state->crtc;
11792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11793 struct drm_plane *plane = plane_state->plane;
11794 struct drm_device *dev = crtc->dev;
11795 struct drm_i915_private *dev_priv = dev->dev_private;
11796 struct intel_plane_state *old_plane_state =
11797 to_intel_plane_state(plane->state);
11798 int idx = intel_crtc->base.base.id, ret;
11799 int i = drm_plane_index(plane);
11800 bool mode_changed = needs_modeset(crtc_state);
11801 bool was_crtc_enabled = crtc->state->active;
11802 bool is_crtc_enabled = crtc_state->active;
11803 bool turn_off, turn_on, visible, was_visible;
11804 struct drm_framebuffer *fb = plane_state->fb;
11805
11806 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11807 plane->type != DRM_PLANE_TYPE_CURSOR) {
11808 ret = skl_update_scaler_plane(
11809 to_intel_crtc_state(crtc_state),
11810 to_intel_plane_state(plane_state));
11811 if (ret)
11812 return ret;
11813 }
11814
11815 was_visible = old_plane_state->visible;
11816 visible = to_intel_plane_state(plane_state)->visible;
11817
11818 if (!was_crtc_enabled && WARN_ON(was_visible))
11819 was_visible = false;
11820
11821 if (!is_crtc_enabled && WARN_ON(visible))
11822 visible = false;
11823
11824 if (!was_visible && !visible)
11825 return 0;
11826
11827 turn_off = was_visible && (!visible || mode_changed);
11828 turn_on = visible && (!was_visible || mode_changed);
11829
11830 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11831 plane->base.id, fb ? fb->base.id : -1);
11832
11833 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11834 plane->base.id, was_visible, visible,
11835 turn_off, turn_on, mode_changed);
11836
11837 if (turn_on || turn_off) {
11838 pipe_config->wm_changed = true;
11839
11840 /* must disable cxsr around plane enable/disable */
11841 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11842 if (is_crtc_enabled)
11843 intel_crtc->atomic.wait_vblank = true;
11844 pipe_config->disable_cxsr = true;
11845 }
11846 } else if (intel_wm_need_update(plane, plane_state)) {
11847 pipe_config->wm_changed = true;
11848 }
11849
11850 if (visible || was_visible)
11851 intel_crtc->atomic.fb_bits |=
11852 to_intel_plane(plane)->frontbuffer_bit;
11853
11854 switch (plane->type) {
11855 case DRM_PLANE_TYPE_PRIMARY:
11856 intel_crtc->atomic.pre_disable_primary = turn_off;
11857 intel_crtc->atomic.post_enable_primary = turn_on;
11858
11859 if (turn_off) {
11860 /*
11861 * FIXME: Actually if we will still have any other
11862 * plane enabled on the pipe we could let IPS enabled
11863 * still, but for now lets consider that when we make
11864 * primary invisible by setting DSPCNTR to 0 on
11865 * update_primary_plane function IPS needs to be
11866 * disable.
11867 */
11868 intel_crtc->atomic.disable_ips = true;
11869
11870 intel_crtc->atomic.disable_fbc = true;
11871 }
11872
11873 /*
11874 * FBC does not work on some platforms for rotated
11875 * planes, so disable it when rotation is not 0 and
11876 * update it when rotation is set back to 0.
11877 *
11878 * FIXME: This is redundant with the fbc update done in
11879 * the primary plane enable function except that that
11880 * one is done too late. We eventually need to unify
11881 * this.
11882 */
11883
11884 if (visible &&
11885 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11886 dev_priv->fbc.crtc == intel_crtc &&
11887 plane_state->rotation != BIT(DRM_ROTATE_0))
11888 intel_crtc->atomic.disable_fbc = true;
11889
11890 /*
11891 * BDW signals flip done immediately if the plane
11892 * is disabled, even if the plane enable is already
11893 * armed to occur at the next vblank :(
11894 */
11895 if (turn_on && IS_BROADWELL(dev))
11896 intel_crtc->atomic.wait_vblank = true;
11897
11898 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11899 break;
11900 case DRM_PLANE_TYPE_CURSOR:
11901 break;
11902 case DRM_PLANE_TYPE_OVERLAY:
11903 /*
11904 * WaCxSRDisabledForSpriteScaling:ivb
11905 *
11906 * cstate->update_wm was already set above, so this flag will
11907 * take effect when we commit and program watermarks.
11908 */
11909 if (IS_IVYBRIDGE(dev) &&
11910 needs_scaling(to_intel_plane_state(plane_state)) &&
11911 !needs_scaling(old_plane_state)) {
11912 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11913 } else if (turn_off && !mode_changed) {
11914 intel_crtc->atomic.wait_vblank = true;
11915 intel_crtc->atomic.update_sprite_watermarks |=
11916 1 << i;
11917 }
11918
11919 break;
11920 }
11921 return 0;
11922 }
11923
11924 static bool encoders_cloneable(const struct intel_encoder *a,
11925 const struct intel_encoder *b)
11926 {
11927 /* masks could be asymmetric, so check both ways */
11928 return a == b || (a->cloneable & (1 << b->type) &&
11929 b->cloneable & (1 << a->type));
11930 }
11931
11932 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11933 struct intel_crtc *crtc,
11934 struct intel_encoder *encoder)
11935 {
11936 struct intel_encoder *source_encoder;
11937 struct drm_connector *connector;
11938 struct drm_connector_state *connector_state;
11939 int i;
11940
11941 for_each_connector_in_state(state, connector, connector_state, i) {
11942 if (connector_state->crtc != &crtc->base)
11943 continue;
11944
11945 source_encoder =
11946 to_intel_encoder(connector_state->best_encoder);
11947 if (!encoders_cloneable(encoder, source_encoder))
11948 return false;
11949 }
11950
11951 return true;
11952 }
11953
11954 static bool check_encoder_cloning(struct drm_atomic_state *state,
11955 struct intel_crtc *crtc)
11956 {
11957 struct intel_encoder *encoder;
11958 struct drm_connector *connector;
11959 struct drm_connector_state *connector_state;
11960 int i;
11961
11962 for_each_connector_in_state(state, connector, connector_state, i) {
11963 if (connector_state->crtc != &crtc->base)
11964 continue;
11965
11966 encoder = to_intel_encoder(connector_state->best_encoder);
11967 if (!check_single_encoder_cloning(state, crtc, encoder))
11968 return false;
11969 }
11970
11971 return true;
11972 }
11973
11974 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11975 struct drm_crtc_state *crtc_state)
11976 {
11977 struct drm_device *dev = crtc->dev;
11978 struct drm_i915_private *dev_priv = dev->dev_private;
11979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11980 struct intel_crtc_state *pipe_config =
11981 to_intel_crtc_state(crtc_state);
11982 struct drm_atomic_state *state = crtc_state->state;
11983 int ret;
11984 bool mode_changed = needs_modeset(crtc_state);
11985
11986 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11987 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11988 return -EINVAL;
11989 }
11990
11991 if (mode_changed && !crtc_state->active)
11992 pipe_config->wm_changed = true;
11993
11994 if (mode_changed && crtc_state->enable &&
11995 dev_priv->display.crtc_compute_clock &&
11996 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11997 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11998 pipe_config);
11999 if (ret)
12000 return ret;
12001 }
12002
12003 ret = 0;
12004 if (dev_priv->display.compute_pipe_wm) {
12005 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12006 if (ret)
12007 return ret;
12008 }
12009
12010 if (INTEL_INFO(dev)->gen >= 9) {
12011 if (mode_changed)
12012 ret = skl_update_scaler_crtc(pipe_config);
12013
12014 if (!ret)
12015 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12016 pipe_config);
12017 }
12018
12019 return ret;
12020 }
12021
12022 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12023 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12024 .load_lut = intel_crtc_load_lut,
12025 .atomic_begin = intel_begin_crtc_commit,
12026 .atomic_flush = intel_finish_crtc_commit,
12027 .atomic_check = intel_crtc_atomic_check,
12028 };
12029
12030 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12031 {
12032 struct intel_connector *connector;
12033
12034 for_each_intel_connector(dev, connector) {
12035 if (connector->base.encoder) {
12036 connector->base.state->best_encoder =
12037 connector->base.encoder;
12038 connector->base.state->crtc =
12039 connector->base.encoder->crtc;
12040 } else {
12041 connector->base.state->best_encoder = NULL;
12042 connector->base.state->crtc = NULL;
12043 }
12044 }
12045 }
12046
12047 static void
12048 connected_sink_compute_bpp(struct intel_connector *connector,
12049 struct intel_crtc_state *pipe_config)
12050 {
12051 int bpp = pipe_config->pipe_bpp;
12052
12053 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12054 connector->base.base.id,
12055 connector->base.name);
12056
12057 /* Don't use an invalid EDID bpc value */
12058 if (connector->base.display_info.bpc &&
12059 connector->base.display_info.bpc * 3 < bpp) {
12060 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12061 bpp, connector->base.display_info.bpc*3);
12062 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12063 }
12064
12065 /* Clamp bpp to 8 on screens without EDID 1.4 */
12066 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12067 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12068 bpp);
12069 pipe_config->pipe_bpp = 24;
12070 }
12071 }
12072
12073 static int
12074 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12075 struct intel_crtc_state *pipe_config)
12076 {
12077 struct drm_device *dev = crtc->base.dev;
12078 struct drm_atomic_state *state;
12079 struct drm_connector *connector;
12080 struct drm_connector_state *connector_state;
12081 int bpp, i;
12082
12083 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12084 bpp = 10*3;
12085 else if (INTEL_INFO(dev)->gen >= 5)
12086 bpp = 12*3;
12087 else
12088 bpp = 8*3;
12089
12090
12091 pipe_config->pipe_bpp = bpp;
12092
12093 state = pipe_config->base.state;
12094
12095 /* Clamp display bpp to EDID value */
12096 for_each_connector_in_state(state, connector, connector_state, i) {
12097 if (connector_state->crtc != &crtc->base)
12098 continue;
12099
12100 connected_sink_compute_bpp(to_intel_connector(connector),
12101 pipe_config);
12102 }
12103
12104 return bpp;
12105 }
12106
12107 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12108 {
12109 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12110 "type: 0x%x flags: 0x%x\n",
12111 mode->crtc_clock,
12112 mode->crtc_hdisplay, mode->crtc_hsync_start,
12113 mode->crtc_hsync_end, mode->crtc_htotal,
12114 mode->crtc_vdisplay, mode->crtc_vsync_start,
12115 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12116 }
12117
12118 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12119 struct intel_crtc_state *pipe_config,
12120 const char *context)
12121 {
12122 struct drm_device *dev = crtc->base.dev;
12123 struct drm_plane *plane;
12124 struct intel_plane *intel_plane;
12125 struct intel_plane_state *state;
12126 struct drm_framebuffer *fb;
12127
12128 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12129 context, pipe_config, pipe_name(crtc->pipe));
12130
12131 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12132 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12133 pipe_config->pipe_bpp, pipe_config->dither);
12134 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12135 pipe_config->has_pch_encoder,
12136 pipe_config->fdi_lanes,
12137 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12138 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12139 pipe_config->fdi_m_n.tu);
12140 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12141 pipe_config->has_dp_encoder,
12142 pipe_config->lane_count,
12143 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12144 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12145 pipe_config->dp_m_n.tu);
12146
12147 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12148 pipe_config->has_dp_encoder,
12149 pipe_config->lane_count,
12150 pipe_config->dp_m2_n2.gmch_m,
12151 pipe_config->dp_m2_n2.gmch_n,
12152 pipe_config->dp_m2_n2.link_m,
12153 pipe_config->dp_m2_n2.link_n,
12154 pipe_config->dp_m2_n2.tu);
12155
12156 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12157 pipe_config->has_audio,
12158 pipe_config->has_infoframe);
12159
12160 DRM_DEBUG_KMS("requested mode:\n");
12161 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12162 DRM_DEBUG_KMS("adjusted mode:\n");
12163 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12164 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12165 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12166 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12167 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12168 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12169 crtc->num_scalers,
12170 pipe_config->scaler_state.scaler_users,
12171 pipe_config->scaler_state.scaler_id);
12172 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12173 pipe_config->gmch_pfit.control,
12174 pipe_config->gmch_pfit.pgm_ratios,
12175 pipe_config->gmch_pfit.lvds_border_bits);
12176 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12177 pipe_config->pch_pfit.pos,
12178 pipe_config->pch_pfit.size,
12179 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12180 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12181 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12182
12183 if (IS_BROXTON(dev)) {
12184 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12185 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12186 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12187 pipe_config->ddi_pll_sel,
12188 pipe_config->dpll_hw_state.ebb0,
12189 pipe_config->dpll_hw_state.ebb4,
12190 pipe_config->dpll_hw_state.pll0,
12191 pipe_config->dpll_hw_state.pll1,
12192 pipe_config->dpll_hw_state.pll2,
12193 pipe_config->dpll_hw_state.pll3,
12194 pipe_config->dpll_hw_state.pll6,
12195 pipe_config->dpll_hw_state.pll8,
12196 pipe_config->dpll_hw_state.pll9,
12197 pipe_config->dpll_hw_state.pll10,
12198 pipe_config->dpll_hw_state.pcsdw12);
12199 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12200 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12201 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12202 pipe_config->ddi_pll_sel,
12203 pipe_config->dpll_hw_state.ctrl1,
12204 pipe_config->dpll_hw_state.cfgcr1,
12205 pipe_config->dpll_hw_state.cfgcr2);
12206 } else if (HAS_DDI(dev)) {
12207 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12208 pipe_config->ddi_pll_sel,
12209 pipe_config->dpll_hw_state.wrpll,
12210 pipe_config->dpll_hw_state.spll);
12211 } else {
12212 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12213 "fp0: 0x%x, fp1: 0x%x\n",
12214 pipe_config->dpll_hw_state.dpll,
12215 pipe_config->dpll_hw_state.dpll_md,
12216 pipe_config->dpll_hw_state.fp0,
12217 pipe_config->dpll_hw_state.fp1);
12218 }
12219
12220 DRM_DEBUG_KMS("planes on this crtc\n");
12221 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12222 intel_plane = to_intel_plane(plane);
12223 if (intel_plane->pipe != crtc->pipe)
12224 continue;
12225
12226 state = to_intel_plane_state(plane->state);
12227 fb = state->base.fb;
12228 if (!fb) {
12229 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12230 "disabled, scaler_id = %d\n",
12231 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12232 plane->base.id, intel_plane->pipe,
12233 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12234 drm_plane_index(plane), state->scaler_id);
12235 continue;
12236 }
12237
12238 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12239 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12240 plane->base.id, intel_plane->pipe,
12241 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12242 drm_plane_index(plane));
12243 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12244 fb->base.id, fb->width, fb->height, fb->pixel_format);
12245 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12246 state->scaler_id,
12247 state->src.x1 >> 16, state->src.y1 >> 16,
12248 drm_rect_width(&state->src) >> 16,
12249 drm_rect_height(&state->src) >> 16,
12250 state->dst.x1, state->dst.y1,
12251 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12252 }
12253 }
12254
12255 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12256 {
12257 struct drm_device *dev = state->dev;
12258 struct intel_encoder *encoder;
12259 struct drm_connector *connector;
12260 struct drm_connector_state *connector_state;
12261 unsigned int used_ports = 0;
12262 int i;
12263
12264 /*
12265 * Walk the connector list instead of the encoder
12266 * list to detect the problem on ddi platforms
12267 * where there's just one encoder per digital port.
12268 */
12269 for_each_connector_in_state(state, connector, connector_state, i) {
12270 if (!connector_state->best_encoder)
12271 continue;
12272
12273 encoder = to_intel_encoder(connector_state->best_encoder);
12274
12275 WARN_ON(!connector_state->crtc);
12276
12277 switch (encoder->type) {
12278 unsigned int port_mask;
12279 case INTEL_OUTPUT_UNKNOWN:
12280 if (WARN_ON(!HAS_DDI(dev)))
12281 break;
12282 case INTEL_OUTPUT_DISPLAYPORT:
12283 case INTEL_OUTPUT_HDMI:
12284 case INTEL_OUTPUT_EDP:
12285 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12286
12287 /* the same port mustn't appear more than once */
12288 if (used_ports & port_mask)
12289 return false;
12290
12291 used_ports |= port_mask;
12292 default:
12293 break;
12294 }
12295 }
12296
12297 return true;
12298 }
12299
12300 static void
12301 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12302 {
12303 struct drm_crtc_state tmp_state;
12304 struct intel_crtc_scaler_state scaler_state;
12305 struct intel_dpll_hw_state dpll_hw_state;
12306 enum intel_dpll_id shared_dpll;
12307 uint32_t ddi_pll_sel;
12308 bool force_thru;
12309
12310 /* FIXME: before the switch to atomic started, a new pipe_config was
12311 * kzalloc'd. Code that depends on any field being zero should be
12312 * fixed, so that the crtc_state can be safely duplicated. For now,
12313 * only fields that are know to not cause problems are preserved. */
12314
12315 tmp_state = crtc_state->base;
12316 scaler_state = crtc_state->scaler_state;
12317 shared_dpll = crtc_state->shared_dpll;
12318 dpll_hw_state = crtc_state->dpll_hw_state;
12319 ddi_pll_sel = crtc_state->ddi_pll_sel;
12320 force_thru = crtc_state->pch_pfit.force_thru;
12321
12322 memset(crtc_state, 0, sizeof *crtc_state);
12323
12324 crtc_state->base = tmp_state;
12325 crtc_state->scaler_state = scaler_state;
12326 crtc_state->shared_dpll = shared_dpll;
12327 crtc_state->dpll_hw_state = dpll_hw_state;
12328 crtc_state->ddi_pll_sel = ddi_pll_sel;
12329 crtc_state->pch_pfit.force_thru = force_thru;
12330 }
12331
12332 static int
12333 intel_modeset_pipe_config(struct drm_crtc *crtc,
12334 struct intel_crtc_state *pipe_config)
12335 {
12336 struct drm_atomic_state *state = pipe_config->base.state;
12337 struct intel_encoder *encoder;
12338 struct drm_connector *connector;
12339 struct drm_connector_state *connector_state;
12340 int base_bpp, ret = -EINVAL;
12341 int i;
12342 bool retry = true;
12343
12344 clear_intel_crtc_state(pipe_config);
12345
12346 pipe_config->cpu_transcoder =
12347 (enum transcoder) to_intel_crtc(crtc)->pipe;
12348
12349 /*
12350 * Sanitize sync polarity flags based on requested ones. If neither
12351 * positive or negative polarity is requested, treat this as meaning
12352 * negative polarity.
12353 */
12354 if (!(pipe_config->base.adjusted_mode.flags &
12355 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12357
12358 if (!(pipe_config->base.adjusted_mode.flags &
12359 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12360 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12361
12362 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12363 pipe_config);
12364 if (base_bpp < 0)
12365 goto fail;
12366
12367 /*
12368 * Determine the real pipe dimensions. Note that stereo modes can
12369 * increase the actual pipe size due to the frame doubling and
12370 * insertion of additional space for blanks between the frame. This
12371 * is stored in the crtc timings. We use the requested mode to do this
12372 * computation to clearly distinguish it from the adjusted mode, which
12373 * can be changed by the connectors in the below retry loop.
12374 */
12375 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12376 &pipe_config->pipe_src_w,
12377 &pipe_config->pipe_src_h);
12378
12379 encoder_retry:
12380 /* Ensure the port clock defaults are reset when retrying. */
12381 pipe_config->port_clock = 0;
12382 pipe_config->pixel_multiplier = 1;
12383
12384 /* Fill in default crtc timings, allow encoders to overwrite them. */
12385 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12386 CRTC_STEREO_DOUBLE);
12387
12388 /* Pass our mode to the connectors and the CRTC to give them a chance to
12389 * adjust it according to limitations or connector properties, and also
12390 * a chance to reject the mode entirely.
12391 */
12392 for_each_connector_in_state(state, connector, connector_state, i) {
12393 if (connector_state->crtc != crtc)
12394 continue;
12395
12396 encoder = to_intel_encoder(connector_state->best_encoder);
12397
12398 if (!(encoder->compute_config(encoder, pipe_config))) {
12399 DRM_DEBUG_KMS("Encoder config failure\n");
12400 goto fail;
12401 }
12402 }
12403
12404 /* Set default port clock if not overwritten by the encoder. Needs to be
12405 * done afterwards in case the encoder adjusts the mode. */
12406 if (!pipe_config->port_clock)
12407 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12408 * pipe_config->pixel_multiplier;
12409
12410 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12411 if (ret < 0) {
12412 DRM_DEBUG_KMS("CRTC fixup failed\n");
12413 goto fail;
12414 }
12415
12416 if (ret == RETRY) {
12417 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12418 ret = -EINVAL;
12419 goto fail;
12420 }
12421
12422 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12423 retry = false;
12424 goto encoder_retry;
12425 }
12426
12427 /* Dithering seems to not pass-through bits correctly when it should, so
12428 * only enable it on 6bpc panels. */
12429 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12430 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12431 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12432
12433 fail:
12434 return ret;
12435 }
12436
12437 static void
12438 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12439 {
12440 struct drm_crtc *crtc;
12441 struct drm_crtc_state *crtc_state;
12442 int i;
12443
12444 /* Double check state. */
12445 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12446 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12447
12448 /* Update hwmode for vblank functions */
12449 if (crtc->state->active)
12450 crtc->hwmode = crtc->state->adjusted_mode;
12451 else
12452 crtc->hwmode.crtc_clock = 0;
12453
12454 /*
12455 * Update legacy state to satisfy fbc code. This can
12456 * be removed when fbc uses the atomic state.
12457 */
12458 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12459 struct drm_plane_state *plane_state = crtc->primary->state;
12460
12461 crtc->primary->fb = plane_state->fb;
12462 crtc->x = plane_state->src_x >> 16;
12463 crtc->y = plane_state->src_y >> 16;
12464 }
12465 }
12466 }
12467
12468 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12469 {
12470 int diff;
12471
12472 if (clock1 == clock2)
12473 return true;
12474
12475 if (!clock1 || !clock2)
12476 return false;
12477
12478 diff = abs(clock1 - clock2);
12479
12480 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12481 return true;
12482
12483 return false;
12484 }
12485
12486 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12487 list_for_each_entry((intel_crtc), \
12488 &(dev)->mode_config.crtc_list, \
12489 base.head) \
12490 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12491
12492 static bool
12493 intel_compare_m_n(unsigned int m, unsigned int n,
12494 unsigned int m2, unsigned int n2,
12495 bool exact)
12496 {
12497 if (m == m2 && n == n2)
12498 return true;
12499
12500 if (exact || !m || !n || !m2 || !n2)
12501 return false;
12502
12503 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12504
12505 if (m > m2) {
12506 while (m > m2) {
12507 m2 <<= 1;
12508 n2 <<= 1;
12509 }
12510 } else if (m < m2) {
12511 while (m < m2) {
12512 m <<= 1;
12513 n <<= 1;
12514 }
12515 }
12516
12517 return m == m2 && n == n2;
12518 }
12519
12520 static bool
12521 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12522 struct intel_link_m_n *m2_n2,
12523 bool adjust)
12524 {
12525 if (m_n->tu == m2_n2->tu &&
12526 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12527 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12528 intel_compare_m_n(m_n->link_m, m_n->link_n,
12529 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12530 if (adjust)
12531 *m2_n2 = *m_n;
12532
12533 return true;
12534 }
12535
12536 return false;
12537 }
12538
12539 static bool
12540 intel_pipe_config_compare(struct drm_device *dev,
12541 struct intel_crtc_state *current_config,
12542 struct intel_crtc_state *pipe_config,
12543 bool adjust)
12544 {
12545 bool ret = true;
12546
12547 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12548 do { \
12549 if (!adjust) \
12550 DRM_ERROR(fmt, ##__VA_ARGS__); \
12551 else \
12552 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12553 } while (0)
12554
12555 #define PIPE_CONF_CHECK_X(name) \
12556 if (current_config->name != pipe_config->name) { \
12557 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12558 "(expected 0x%08x, found 0x%08x)\n", \
12559 current_config->name, \
12560 pipe_config->name); \
12561 ret = false; \
12562 }
12563
12564 #define PIPE_CONF_CHECK_I(name) \
12565 if (current_config->name != pipe_config->name) { \
12566 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12567 "(expected %i, found %i)\n", \
12568 current_config->name, \
12569 pipe_config->name); \
12570 ret = false; \
12571 }
12572
12573 #define PIPE_CONF_CHECK_M_N(name) \
12574 if (!intel_compare_link_m_n(&current_config->name, \
12575 &pipe_config->name,\
12576 adjust)) { \
12577 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12578 "(expected tu %i gmch %i/%i link %i/%i, " \
12579 "found tu %i, gmch %i/%i link %i/%i)\n", \
12580 current_config->name.tu, \
12581 current_config->name.gmch_m, \
12582 current_config->name.gmch_n, \
12583 current_config->name.link_m, \
12584 current_config->name.link_n, \
12585 pipe_config->name.tu, \
12586 pipe_config->name.gmch_m, \
12587 pipe_config->name.gmch_n, \
12588 pipe_config->name.link_m, \
12589 pipe_config->name.link_n); \
12590 ret = false; \
12591 }
12592
12593 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12594 if (!intel_compare_link_m_n(&current_config->name, \
12595 &pipe_config->name, adjust) && \
12596 !intel_compare_link_m_n(&current_config->alt_name, \
12597 &pipe_config->name, adjust)) { \
12598 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12599 "(expected tu %i gmch %i/%i link %i/%i, " \
12600 "or tu %i gmch %i/%i link %i/%i, " \
12601 "found tu %i, gmch %i/%i link %i/%i)\n", \
12602 current_config->name.tu, \
12603 current_config->name.gmch_m, \
12604 current_config->name.gmch_n, \
12605 current_config->name.link_m, \
12606 current_config->name.link_n, \
12607 current_config->alt_name.tu, \
12608 current_config->alt_name.gmch_m, \
12609 current_config->alt_name.gmch_n, \
12610 current_config->alt_name.link_m, \
12611 current_config->alt_name.link_n, \
12612 pipe_config->name.tu, \
12613 pipe_config->name.gmch_m, \
12614 pipe_config->name.gmch_n, \
12615 pipe_config->name.link_m, \
12616 pipe_config->name.link_n); \
12617 ret = false; \
12618 }
12619
12620 /* This is required for BDW+ where there is only one set of registers for
12621 * switching between high and low RR.
12622 * This macro can be used whenever a comparison has to be made between one
12623 * hw state and multiple sw state variables.
12624 */
12625 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12626 if ((current_config->name != pipe_config->name) && \
12627 (current_config->alt_name != pipe_config->name)) { \
12628 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12629 "(expected %i or %i, found %i)\n", \
12630 current_config->name, \
12631 current_config->alt_name, \
12632 pipe_config->name); \
12633 ret = false; \
12634 }
12635
12636 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12637 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12638 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12639 "(expected %i, found %i)\n", \
12640 current_config->name & (mask), \
12641 pipe_config->name & (mask)); \
12642 ret = false; \
12643 }
12644
12645 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12646 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12647 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12648 "(expected %i, found %i)\n", \
12649 current_config->name, \
12650 pipe_config->name); \
12651 ret = false; \
12652 }
12653
12654 #define PIPE_CONF_QUIRK(quirk) \
12655 ((current_config->quirks | pipe_config->quirks) & (quirk))
12656
12657 PIPE_CONF_CHECK_I(cpu_transcoder);
12658
12659 PIPE_CONF_CHECK_I(has_pch_encoder);
12660 PIPE_CONF_CHECK_I(fdi_lanes);
12661 PIPE_CONF_CHECK_M_N(fdi_m_n);
12662
12663 PIPE_CONF_CHECK_I(has_dp_encoder);
12664 PIPE_CONF_CHECK_I(lane_count);
12665
12666 if (INTEL_INFO(dev)->gen < 8) {
12667 PIPE_CONF_CHECK_M_N(dp_m_n);
12668
12669 if (current_config->has_drrs)
12670 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12671 } else
12672 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12673
12674 PIPE_CONF_CHECK_I(has_dsi_encoder);
12675
12676 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12677 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12678 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12679 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12680 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12681 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12682
12683 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12684 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12689
12690 PIPE_CONF_CHECK_I(pixel_multiplier);
12691 PIPE_CONF_CHECK_I(has_hdmi_sink);
12692 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12693 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12694 PIPE_CONF_CHECK_I(limited_color_range);
12695 PIPE_CONF_CHECK_I(has_infoframe);
12696
12697 PIPE_CONF_CHECK_I(has_audio);
12698
12699 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12700 DRM_MODE_FLAG_INTERLACE);
12701
12702 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12703 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12704 DRM_MODE_FLAG_PHSYNC);
12705 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12706 DRM_MODE_FLAG_NHSYNC);
12707 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12708 DRM_MODE_FLAG_PVSYNC);
12709 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12710 DRM_MODE_FLAG_NVSYNC);
12711 }
12712
12713 PIPE_CONF_CHECK_X(gmch_pfit.control);
12714 /* pfit ratios are autocomputed by the hw on gen4+ */
12715 if (INTEL_INFO(dev)->gen < 4)
12716 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12717 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12718
12719 if (!adjust) {
12720 PIPE_CONF_CHECK_I(pipe_src_w);
12721 PIPE_CONF_CHECK_I(pipe_src_h);
12722
12723 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12724 if (current_config->pch_pfit.enabled) {
12725 PIPE_CONF_CHECK_X(pch_pfit.pos);
12726 PIPE_CONF_CHECK_X(pch_pfit.size);
12727 }
12728
12729 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12730 }
12731
12732 /* BDW+ don't expose a synchronous way to read the state */
12733 if (IS_HASWELL(dev))
12734 PIPE_CONF_CHECK_I(ips_enabled);
12735
12736 PIPE_CONF_CHECK_I(double_wide);
12737
12738 PIPE_CONF_CHECK_X(ddi_pll_sel);
12739
12740 PIPE_CONF_CHECK_I(shared_dpll);
12741 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12742 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12743 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12744 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12745 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12746 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12747 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12748 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12749 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12750
12751 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12752 PIPE_CONF_CHECK_I(pipe_bpp);
12753
12754 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12755 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12756
12757 #undef PIPE_CONF_CHECK_X
12758 #undef PIPE_CONF_CHECK_I
12759 #undef PIPE_CONF_CHECK_I_ALT
12760 #undef PIPE_CONF_CHECK_FLAGS
12761 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12762 #undef PIPE_CONF_QUIRK
12763 #undef INTEL_ERR_OR_DBG_KMS
12764
12765 return ret;
12766 }
12767
12768 static void check_wm_state(struct drm_device *dev)
12769 {
12770 struct drm_i915_private *dev_priv = dev->dev_private;
12771 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12772 struct intel_crtc *intel_crtc;
12773 int plane;
12774
12775 if (INTEL_INFO(dev)->gen < 9)
12776 return;
12777
12778 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12779 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12780
12781 for_each_intel_crtc(dev, intel_crtc) {
12782 struct skl_ddb_entry *hw_entry, *sw_entry;
12783 const enum pipe pipe = intel_crtc->pipe;
12784
12785 if (!intel_crtc->active)
12786 continue;
12787
12788 /* planes */
12789 for_each_plane(dev_priv, pipe, plane) {
12790 hw_entry = &hw_ddb.plane[pipe][plane];
12791 sw_entry = &sw_ddb->plane[pipe][plane];
12792
12793 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12794 continue;
12795
12796 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12797 "(expected (%u,%u), found (%u,%u))\n",
12798 pipe_name(pipe), plane + 1,
12799 sw_entry->start, sw_entry->end,
12800 hw_entry->start, hw_entry->end);
12801 }
12802
12803 /* cursor */
12804 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12805 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12806
12807 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12808 continue;
12809
12810 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12811 "(expected (%u,%u), found (%u,%u))\n",
12812 pipe_name(pipe),
12813 sw_entry->start, sw_entry->end,
12814 hw_entry->start, hw_entry->end);
12815 }
12816 }
12817
12818 static void
12819 check_connector_state(struct drm_device *dev,
12820 struct drm_atomic_state *old_state)
12821 {
12822 struct drm_connector_state *old_conn_state;
12823 struct drm_connector *connector;
12824 int i;
12825
12826 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12827 struct drm_encoder *encoder = connector->encoder;
12828 struct drm_connector_state *state = connector->state;
12829
12830 /* This also checks the encoder/connector hw state with the
12831 * ->get_hw_state callbacks. */
12832 intel_connector_check_state(to_intel_connector(connector));
12833
12834 I915_STATE_WARN(state->best_encoder != encoder,
12835 "connector's atomic encoder doesn't match legacy encoder\n");
12836 }
12837 }
12838
12839 static void
12840 check_encoder_state(struct drm_device *dev)
12841 {
12842 struct intel_encoder *encoder;
12843 struct intel_connector *connector;
12844
12845 for_each_intel_encoder(dev, encoder) {
12846 bool enabled = false;
12847 enum pipe pipe;
12848
12849 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12850 encoder->base.base.id,
12851 encoder->base.name);
12852
12853 for_each_intel_connector(dev, connector) {
12854 if (connector->base.state->best_encoder != &encoder->base)
12855 continue;
12856 enabled = true;
12857
12858 I915_STATE_WARN(connector->base.state->crtc !=
12859 encoder->base.crtc,
12860 "connector's crtc doesn't match encoder crtc\n");
12861 }
12862
12863 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12864 "encoder's enabled state mismatch "
12865 "(expected %i, found %i)\n",
12866 !!encoder->base.crtc, enabled);
12867
12868 if (!encoder->base.crtc) {
12869 bool active;
12870
12871 active = encoder->get_hw_state(encoder, &pipe);
12872 I915_STATE_WARN(active,
12873 "encoder detached but still enabled on pipe %c.\n",
12874 pipe_name(pipe));
12875 }
12876 }
12877 }
12878
12879 static void
12880 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12881 {
12882 struct drm_i915_private *dev_priv = dev->dev_private;
12883 struct intel_encoder *encoder;
12884 struct drm_crtc_state *old_crtc_state;
12885 struct drm_crtc *crtc;
12886 int i;
12887
12888 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12890 struct intel_crtc_state *pipe_config, *sw_config;
12891 bool active;
12892
12893 if (!needs_modeset(crtc->state) &&
12894 !to_intel_crtc_state(crtc->state)->update_pipe)
12895 continue;
12896
12897 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12898 pipe_config = to_intel_crtc_state(old_crtc_state);
12899 memset(pipe_config, 0, sizeof(*pipe_config));
12900 pipe_config->base.crtc = crtc;
12901 pipe_config->base.state = old_state;
12902
12903 DRM_DEBUG_KMS("[CRTC:%d]\n",
12904 crtc->base.id);
12905
12906 active = dev_priv->display.get_pipe_config(intel_crtc,
12907 pipe_config);
12908
12909 /* hw state is inconsistent with the pipe quirk */
12910 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12911 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12912 active = crtc->state->active;
12913
12914 I915_STATE_WARN(crtc->state->active != active,
12915 "crtc active state doesn't match with hw state "
12916 "(expected %i, found %i)\n", crtc->state->active, active);
12917
12918 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12919 "transitional active state does not match atomic hw state "
12920 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12921
12922 for_each_encoder_on_crtc(dev, crtc, encoder) {
12923 enum pipe pipe;
12924
12925 active = encoder->get_hw_state(encoder, &pipe);
12926 I915_STATE_WARN(active != crtc->state->active,
12927 "[ENCODER:%i] active %i with crtc active %i\n",
12928 encoder->base.base.id, active, crtc->state->active);
12929
12930 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12931 "Encoder connected to wrong pipe %c\n",
12932 pipe_name(pipe));
12933
12934 if (active)
12935 encoder->get_config(encoder, pipe_config);
12936 }
12937
12938 if (!crtc->state->active)
12939 continue;
12940
12941 sw_config = to_intel_crtc_state(crtc->state);
12942 if (!intel_pipe_config_compare(dev, sw_config,
12943 pipe_config, false)) {
12944 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12945 intel_dump_pipe_config(intel_crtc, pipe_config,
12946 "[hw state]");
12947 intel_dump_pipe_config(intel_crtc, sw_config,
12948 "[sw state]");
12949 }
12950 }
12951 }
12952
12953 static void
12954 check_shared_dpll_state(struct drm_device *dev)
12955 {
12956 struct drm_i915_private *dev_priv = dev->dev_private;
12957 struct intel_crtc *crtc;
12958 struct intel_dpll_hw_state dpll_hw_state;
12959 int i;
12960
12961 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12962 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12963 int enabled_crtcs = 0, active_crtcs = 0;
12964 bool active;
12965
12966 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12967
12968 DRM_DEBUG_KMS("%s\n", pll->name);
12969
12970 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12971
12972 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12973 "more active pll users than references: %i vs %i\n",
12974 pll->active, hweight32(pll->config.crtc_mask));
12975 I915_STATE_WARN(pll->active && !pll->on,
12976 "pll in active use but not on in sw tracking\n");
12977 I915_STATE_WARN(pll->on && !pll->active,
12978 "pll in on but not on in use in sw tracking\n");
12979 I915_STATE_WARN(pll->on != active,
12980 "pll on state mismatch (expected %i, found %i)\n",
12981 pll->on, active);
12982
12983 for_each_intel_crtc(dev, crtc) {
12984 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12985 enabled_crtcs++;
12986 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12987 active_crtcs++;
12988 }
12989 I915_STATE_WARN(pll->active != active_crtcs,
12990 "pll active crtcs mismatch (expected %i, found %i)\n",
12991 pll->active, active_crtcs);
12992 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12993 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12994 hweight32(pll->config.crtc_mask), enabled_crtcs);
12995
12996 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12997 sizeof(dpll_hw_state)),
12998 "pll hw state mismatch\n");
12999 }
13000 }
13001
13002 static void
13003 intel_modeset_check_state(struct drm_device *dev,
13004 struct drm_atomic_state *old_state)
13005 {
13006 check_wm_state(dev);
13007 check_connector_state(dev, old_state);
13008 check_encoder_state(dev);
13009 check_crtc_state(dev, old_state);
13010 check_shared_dpll_state(dev);
13011 }
13012
13013 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13014 int dotclock)
13015 {
13016 /*
13017 * FDI already provided one idea for the dotclock.
13018 * Yell if the encoder disagrees.
13019 */
13020 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13021 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13022 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13023 }
13024
13025 static void update_scanline_offset(struct intel_crtc *crtc)
13026 {
13027 struct drm_device *dev = crtc->base.dev;
13028
13029 /*
13030 * The scanline counter increments at the leading edge of hsync.
13031 *
13032 * On most platforms it starts counting from vtotal-1 on the
13033 * first active line. That means the scanline counter value is
13034 * always one less than what we would expect. Ie. just after
13035 * start of vblank, which also occurs at start of hsync (on the
13036 * last active line), the scanline counter will read vblank_start-1.
13037 *
13038 * On gen2 the scanline counter starts counting from 1 instead
13039 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13040 * to keep the value positive), instead of adding one.
13041 *
13042 * On HSW+ the behaviour of the scanline counter depends on the output
13043 * type. For DP ports it behaves like most other platforms, but on HDMI
13044 * there's an extra 1 line difference. So we need to add two instead of
13045 * one to the value.
13046 */
13047 if (IS_GEN2(dev)) {
13048 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13049 int vtotal;
13050
13051 vtotal = adjusted_mode->crtc_vtotal;
13052 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13053 vtotal /= 2;
13054
13055 crtc->scanline_offset = vtotal - 1;
13056 } else if (HAS_DDI(dev) &&
13057 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13058 crtc->scanline_offset = 2;
13059 } else
13060 crtc->scanline_offset = 1;
13061 }
13062
13063 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13064 {
13065 struct drm_device *dev = state->dev;
13066 struct drm_i915_private *dev_priv = to_i915(dev);
13067 struct intel_shared_dpll_config *shared_dpll = NULL;
13068 struct intel_crtc *intel_crtc;
13069 struct intel_crtc_state *intel_crtc_state;
13070 struct drm_crtc *crtc;
13071 struct drm_crtc_state *crtc_state;
13072 int i;
13073
13074 if (!dev_priv->display.crtc_compute_clock)
13075 return;
13076
13077 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13078 int dpll;
13079
13080 intel_crtc = to_intel_crtc(crtc);
13081 intel_crtc_state = to_intel_crtc_state(crtc_state);
13082 dpll = intel_crtc_state->shared_dpll;
13083
13084 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13085 continue;
13086
13087 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13088
13089 if (!shared_dpll)
13090 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13091
13092 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13093 }
13094 }
13095
13096 /*
13097 * This implements the workaround described in the "notes" section of the mode
13098 * set sequence documentation. When going from no pipes or single pipe to
13099 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13100 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13101 */
13102 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13103 {
13104 struct drm_crtc_state *crtc_state;
13105 struct intel_crtc *intel_crtc;
13106 struct drm_crtc *crtc;
13107 struct intel_crtc_state *first_crtc_state = NULL;
13108 struct intel_crtc_state *other_crtc_state = NULL;
13109 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13110 int i;
13111
13112 /* look at all crtc's that are going to be enabled in during modeset */
13113 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13114 intel_crtc = to_intel_crtc(crtc);
13115
13116 if (!crtc_state->active || !needs_modeset(crtc_state))
13117 continue;
13118
13119 if (first_crtc_state) {
13120 other_crtc_state = to_intel_crtc_state(crtc_state);
13121 break;
13122 } else {
13123 first_crtc_state = to_intel_crtc_state(crtc_state);
13124 first_pipe = intel_crtc->pipe;
13125 }
13126 }
13127
13128 /* No workaround needed? */
13129 if (!first_crtc_state)
13130 return 0;
13131
13132 /* w/a possibly needed, check how many crtc's are already enabled. */
13133 for_each_intel_crtc(state->dev, intel_crtc) {
13134 struct intel_crtc_state *pipe_config;
13135
13136 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13137 if (IS_ERR(pipe_config))
13138 return PTR_ERR(pipe_config);
13139
13140 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13141
13142 if (!pipe_config->base.active ||
13143 needs_modeset(&pipe_config->base))
13144 continue;
13145
13146 /* 2 or more enabled crtcs means no need for w/a */
13147 if (enabled_pipe != INVALID_PIPE)
13148 return 0;
13149
13150 enabled_pipe = intel_crtc->pipe;
13151 }
13152
13153 if (enabled_pipe != INVALID_PIPE)
13154 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13155 else if (other_crtc_state)
13156 other_crtc_state->hsw_workaround_pipe = first_pipe;
13157
13158 return 0;
13159 }
13160
13161 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13162 {
13163 struct drm_crtc *crtc;
13164 struct drm_crtc_state *crtc_state;
13165 int ret = 0;
13166
13167 /* add all active pipes to the state */
13168 for_each_crtc(state->dev, crtc) {
13169 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13170 if (IS_ERR(crtc_state))
13171 return PTR_ERR(crtc_state);
13172
13173 if (!crtc_state->active || needs_modeset(crtc_state))
13174 continue;
13175
13176 crtc_state->mode_changed = true;
13177
13178 ret = drm_atomic_add_affected_connectors(state, crtc);
13179 if (ret)
13180 break;
13181
13182 ret = drm_atomic_add_affected_planes(state, crtc);
13183 if (ret)
13184 break;
13185 }
13186
13187 return ret;
13188 }
13189
13190 static int intel_modeset_checks(struct drm_atomic_state *state)
13191 {
13192 struct drm_device *dev = state->dev;
13193 struct drm_i915_private *dev_priv = dev->dev_private;
13194 int ret;
13195
13196 if (!check_digital_port_conflicts(state)) {
13197 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13198 return -EINVAL;
13199 }
13200
13201 /*
13202 * See if the config requires any additional preparation, e.g.
13203 * to adjust global state with pipes off. We need to do this
13204 * here so we can get the modeset_pipe updated config for the new
13205 * mode set on this crtc. For other crtcs we need to use the
13206 * adjusted_mode bits in the crtc directly.
13207 */
13208 if (dev_priv->display.modeset_calc_cdclk) {
13209 unsigned int cdclk;
13210
13211 ret = dev_priv->display.modeset_calc_cdclk(state);
13212
13213 cdclk = to_intel_atomic_state(state)->cdclk;
13214 if (!ret && cdclk != dev_priv->cdclk_freq)
13215 ret = intel_modeset_all_pipes(state);
13216
13217 if (ret < 0)
13218 return ret;
13219 } else
13220 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13221
13222 intel_modeset_clear_plls(state);
13223
13224 if (IS_HASWELL(dev))
13225 return haswell_mode_set_planes_workaround(state);
13226
13227 return 0;
13228 }
13229
13230 /*
13231 * Handle calculation of various watermark data at the end of the atomic check
13232 * phase. The code here should be run after the per-crtc and per-plane 'check'
13233 * handlers to ensure that all derived state has been updated.
13234 */
13235 static void calc_watermark_data(struct drm_atomic_state *state)
13236 {
13237 struct drm_device *dev = state->dev;
13238 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13239 struct drm_crtc *crtc;
13240 struct drm_crtc_state *cstate;
13241 struct drm_plane *plane;
13242 struct drm_plane_state *pstate;
13243
13244 /*
13245 * Calculate watermark configuration details now that derived
13246 * plane/crtc state is all properly updated.
13247 */
13248 drm_for_each_crtc(crtc, dev) {
13249 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13250 crtc->state;
13251
13252 if (cstate->active)
13253 intel_state->wm_config.num_pipes_active++;
13254 }
13255 drm_for_each_legacy_plane(plane, dev) {
13256 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13257 plane->state;
13258
13259 if (!to_intel_plane_state(pstate)->visible)
13260 continue;
13261
13262 intel_state->wm_config.sprites_enabled = true;
13263 if (pstate->crtc_w != pstate->src_w >> 16 ||
13264 pstate->crtc_h != pstate->src_h >> 16)
13265 intel_state->wm_config.sprites_scaled = true;
13266 }
13267 }
13268
13269 /**
13270 * intel_atomic_check - validate state object
13271 * @dev: drm device
13272 * @state: state to validate
13273 */
13274 static int intel_atomic_check(struct drm_device *dev,
13275 struct drm_atomic_state *state)
13276 {
13277 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13278 struct drm_crtc *crtc;
13279 struct drm_crtc_state *crtc_state;
13280 int ret, i;
13281 bool any_ms = false;
13282
13283 ret = drm_atomic_helper_check_modeset(dev, state);
13284 if (ret)
13285 return ret;
13286
13287 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13288 struct intel_crtc_state *pipe_config =
13289 to_intel_crtc_state(crtc_state);
13290
13291 memset(&to_intel_crtc(crtc)->atomic, 0,
13292 sizeof(struct intel_crtc_atomic_commit));
13293
13294 /* Catch I915_MODE_FLAG_INHERITED */
13295 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13296 crtc_state->mode_changed = true;
13297
13298 if (!crtc_state->enable) {
13299 if (needs_modeset(crtc_state))
13300 any_ms = true;
13301 continue;
13302 }
13303
13304 if (!needs_modeset(crtc_state))
13305 continue;
13306
13307 /* FIXME: For only active_changed we shouldn't need to do any
13308 * state recomputation at all. */
13309
13310 ret = drm_atomic_add_affected_connectors(state, crtc);
13311 if (ret)
13312 return ret;
13313
13314 ret = intel_modeset_pipe_config(crtc, pipe_config);
13315 if (ret)
13316 return ret;
13317
13318 if (i915.fastboot &&
13319 intel_pipe_config_compare(state->dev,
13320 to_intel_crtc_state(crtc->state),
13321 pipe_config, true)) {
13322 crtc_state->mode_changed = false;
13323 to_intel_crtc_state(crtc_state)->update_pipe = true;
13324 }
13325
13326 if (needs_modeset(crtc_state)) {
13327 any_ms = true;
13328
13329 ret = drm_atomic_add_affected_planes(state, crtc);
13330 if (ret)
13331 return ret;
13332 }
13333
13334 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13335 needs_modeset(crtc_state) ?
13336 "[modeset]" : "[fastset]");
13337 }
13338
13339 if (any_ms) {
13340 ret = intel_modeset_checks(state);
13341
13342 if (ret)
13343 return ret;
13344 } else
13345 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13346
13347 ret = drm_atomic_helper_check_planes(state->dev, state);
13348 if (ret)
13349 return ret;
13350
13351 calc_watermark_data(state);
13352
13353 return 0;
13354 }
13355
13356 static int intel_atomic_prepare_commit(struct drm_device *dev,
13357 struct drm_atomic_state *state,
13358 bool async)
13359 {
13360 struct drm_i915_private *dev_priv = dev->dev_private;
13361 struct drm_plane_state *plane_state;
13362 struct drm_crtc_state *crtc_state;
13363 struct drm_plane *plane;
13364 struct drm_crtc *crtc;
13365 int i, ret;
13366
13367 if (async) {
13368 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13369 return -EINVAL;
13370 }
13371
13372 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13373 ret = intel_crtc_wait_for_pending_flips(crtc);
13374 if (ret)
13375 return ret;
13376
13377 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13378 flush_workqueue(dev_priv->wq);
13379 }
13380
13381 ret = mutex_lock_interruptible(&dev->struct_mutex);
13382 if (ret)
13383 return ret;
13384
13385 ret = drm_atomic_helper_prepare_planes(dev, state);
13386 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13387 u32 reset_counter;
13388
13389 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13390 mutex_unlock(&dev->struct_mutex);
13391
13392 for_each_plane_in_state(state, plane, plane_state, i) {
13393 struct intel_plane_state *intel_plane_state =
13394 to_intel_plane_state(plane_state);
13395
13396 if (!intel_plane_state->wait_req)
13397 continue;
13398
13399 ret = __i915_wait_request(intel_plane_state->wait_req,
13400 reset_counter, true,
13401 NULL, NULL);
13402
13403 /* Swallow -EIO errors to allow updates during hw lockup. */
13404 if (ret == -EIO)
13405 ret = 0;
13406
13407 if (ret)
13408 break;
13409 }
13410
13411 if (!ret)
13412 return 0;
13413
13414 mutex_lock(&dev->struct_mutex);
13415 drm_atomic_helper_cleanup_planes(dev, state);
13416 }
13417
13418 mutex_unlock(&dev->struct_mutex);
13419 return ret;
13420 }
13421
13422 /**
13423 * intel_atomic_commit - commit validated state object
13424 * @dev: DRM device
13425 * @state: the top-level driver state object
13426 * @async: asynchronous commit
13427 *
13428 * This function commits a top-level state object that has been validated
13429 * with drm_atomic_helper_check().
13430 *
13431 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13432 * we can only handle plane-related operations and do not yet support
13433 * asynchronous commit.
13434 *
13435 * RETURNS
13436 * Zero for success or -errno.
13437 */
13438 static int intel_atomic_commit(struct drm_device *dev,
13439 struct drm_atomic_state *state,
13440 bool async)
13441 {
13442 struct drm_i915_private *dev_priv = dev->dev_private;
13443 struct drm_crtc_state *crtc_state;
13444 struct drm_crtc *crtc;
13445 int ret = 0;
13446 int i;
13447 bool any_ms = false;
13448
13449 ret = intel_atomic_prepare_commit(dev, state, async);
13450 if (ret) {
13451 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13452 return ret;
13453 }
13454
13455 drm_atomic_helper_swap_state(dev, state);
13456 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13457
13458 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13460
13461 if (!needs_modeset(crtc->state))
13462 continue;
13463
13464 any_ms = true;
13465 intel_pre_plane_update(intel_crtc);
13466
13467 if (crtc_state->active) {
13468 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13469 dev_priv->display.crtc_disable(crtc);
13470 intel_crtc->active = false;
13471 intel_disable_shared_dpll(intel_crtc);
13472
13473 /*
13474 * Underruns don't always raise
13475 * interrupts, so check manually.
13476 */
13477 intel_check_cpu_fifo_underruns(dev_priv);
13478 intel_check_pch_fifo_underruns(dev_priv);
13479
13480 if (!crtc->state->active)
13481 intel_update_watermarks(crtc);
13482 }
13483 }
13484
13485 /* Only after disabling all output pipelines that will be changed can we
13486 * update the the output configuration. */
13487 intel_modeset_update_crtc_state(state);
13488
13489 if (any_ms) {
13490 intel_shared_dpll_commit(state);
13491
13492 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13493 modeset_update_crtc_power_domains(state);
13494 }
13495
13496 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13497 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13499 bool modeset = needs_modeset(crtc->state);
13500 bool update_pipe = !modeset &&
13501 to_intel_crtc_state(crtc->state)->update_pipe;
13502 unsigned long put_domains = 0;
13503
13504 if (modeset)
13505 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13506
13507 if (modeset && crtc->state->active) {
13508 update_scanline_offset(to_intel_crtc(crtc));
13509 dev_priv->display.crtc_enable(crtc);
13510 }
13511
13512 if (update_pipe) {
13513 put_domains = modeset_get_crtc_power_domains(crtc);
13514
13515 /* make sure intel_modeset_check_state runs */
13516 any_ms = true;
13517 }
13518
13519 if (!modeset)
13520 intel_pre_plane_update(intel_crtc);
13521
13522 if (crtc->state->active &&
13523 (crtc->state->planes_changed || update_pipe))
13524 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13525
13526 if (put_domains)
13527 modeset_put_power_domains(dev_priv, put_domains);
13528
13529 intel_post_plane_update(intel_crtc);
13530
13531 if (modeset)
13532 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13533 }
13534
13535 /* FIXME: add subpixel order */
13536
13537 drm_atomic_helper_wait_for_vblanks(dev, state);
13538
13539 mutex_lock(&dev->struct_mutex);
13540 drm_atomic_helper_cleanup_planes(dev, state);
13541 mutex_unlock(&dev->struct_mutex);
13542
13543 if (any_ms)
13544 intel_modeset_check_state(dev, state);
13545
13546 drm_atomic_state_free(state);
13547
13548 return 0;
13549 }
13550
13551 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13552 {
13553 struct drm_device *dev = crtc->dev;
13554 struct drm_atomic_state *state;
13555 struct drm_crtc_state *crtc_state;
13556 int ret;
13557
13558 state = drm_atomic_state_alloc(dev);
13559 if (!state) {
13560 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13561 crtc->base.id);
13562 return;
13563 }
13564
13565 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13566
13567 retry:
13568 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13569 ret = PTR_ERR_OR_ZERO(crtc_state);
13570 if (!ret) {
13571 if (!crtc_state->active)
13572 goto out;
13573
13574 crtc_state->mode_changed = true;
13575 ret = drm_atomic_commit(state);
13576 }
13577
13578 if (ret == -EDEADLK) {
13579 drm_atomic_state_clear(state);
13580 drm_modeset_backoff(state->acquire_ctx);
13581 goto retry;
13582 }
13583
13584 if (ret)
13585 out:
13586 drm_atomic_state_free(state);
13587 }
13588
13589 #undef for_each_intel_crtc_masked
13590
13591 static const struct drm_crtc_funcs intel_crtc_funcs = {
13592 .gamma_set = intel_crtc_gamma_set,
13593 .set_config = drm_atomic_helper_set_config,
13594 .destroy = intel_crtc_destroy,
13595 .page_flip = intel_crtc_page_flip,
13596 .atomic_duplicate_state = intel_crtc_duplicate_state,
13597 .atomic_destroy_state = intel_crtc_destroy_state,
13598 };
13599
13600 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13601 struct intel_shared_dpll *pll,
13602 struct intel_dpll_hw_state *hw_state)
13603 {
13604 uint32_t val;
13605
13606 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13607 return false;
13608
13609 val = I915_READ(PCH_DPLL(pll->id));
13610 hw_state->dpll = val;
13611 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13612 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13613
13614 return val & DPLL_VCO_ENABLE;
13615 }
13616
13617 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13618 struct intel_shared_dpll *pll)
13619 {
13620 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13621 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13622 }
13623
13624 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13625 struct intel_shared_dpll *pll)
13626 {
13627 /* PCH refclock must be enabled first */
13628 ibx_assert_pch_refclk_enabled(dev_priv);
13629
13630 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13631
13632 /* Wait for the clocks to stabilize. */
13633 POSTING_READ(PCH_DPLL(pll->id));
13634 udelay(150);
13635
13636 /* The pixel multiplier can only be updated once the
13637 * DPLL is enabled and the clocks are stable.
13638 *
13639 * So write it again.
13640 */
13641 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13642 POSTING_READ(PCH_DPLL(pll->id));
13643 udelay(200);
13644 }
13645
13646 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13647 struct intel_shared_dpll *pll)
13648 {
13649 struct drm_device *dev = dev_priv->dev;
13650 struct intel_crtc *crtc;
13651
13652 /* Make sure no transcoder isn't still depending on us. */
13653 for_each_intel_crtc(dev, crtc) {
13654 if (intel_crtc_to_shared_dpll(crtc) == pll)
13655 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13656 }
13657
13658 I915_WRITE(PCH_DPLL(pll->id), 0);
13659 POSTING_READ(PCH_DPLL(pll->id));
13660 udelay(200);
13661 }
13662
13663 static char *ibx_pch_dpll_names[] = {
13664 "PCH DPLL A",
13665 "PCH DPLL B",
13666 };
13667
13668 static void ibx_pch_dpll_init(struct drm_device *dev)
13669 {
13670 struct drm_i915_private *dev_priv = dev->dev_private;
13671 int i;
13672
13673 dev_priv->num_shared_dpll = 2;
13674
13675 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13676 dev_priv->shared_dplls[i].id = i;
13677 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13678 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13679 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13680 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13681 dev_priv->shared_dplls[i].get_hw_state =
13682 ibx_pch_dpll_get_hw_state;
13683 }
13684 }
13685
13686 static void intel_shared_dpll_init(struct drm_device *dev)
13687 {
13688 struct drm_i915_private *dev_priv = dev->dev_private;
13689
13690 if (HAS_DDI(dev))
13691 intel_ddi_pll_init(dev);
13692 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13693 ibx_pch_dpll_init(dev);
13694 else
13695 dev_priv->num_shared_dpll = 0;
13696
13697 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13698 }
13699
13700 /**
13701 * intel_prepare_plane_fb - Prepare fb for usage on plane
13702 * @plane: drm plane to prepare for
13703 * @fb: framebuffer to prepare for presentation
13704 *
13705 * Prepares a framebuffer for usage on a display plane. Generally this
13706 * involves pinning the underlying object and updating the frontbuffer tracking
13707 * bits. Some older platforms need special physical address handling for
13708 * cursor planes.
13709 *
13710 * Must be called with struct_mutex held.
13711 *
13712 * Returns 0 on success, negative error code on failure.
13713 */
13714 int
13715 intel_prepare_plane_fb(struct drm_plane *plane,
13716 const struct drm_plane_state *new_state)
13717 {
13718 struct drm_device *dev = plane->dev;
13719 struct drm_framebuffer *fb = new_state->fb;
13720 struct intel_plane *intel_plane = to_intel_plane(plane);
13721 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13722 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13723 int ret = 0;
13724
13725 if (!obj && !old_obj)
13726 return 0;
13727
13728 if (old_obj) {
13729 struct drm_crtc_state *crtc_state =
13730 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13731
13732 /* Big Hammer, we also need to ensure that any pending
13733 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13734 * current scanout is retired before unpinning the old
13735 * framebuffer. Note that we rely on userspace rendering
13736 * into the buffer attached to the pipe they are waiting
13737 * on. If not, userspace generates a GPU hang with IPEHR
13738 * point to the MI_WAIT_FOR_EVENT.
13739 *
13740 * This should only fail upon a hung GPU, in which case we
13741 * can safely continue.
13742 */
13743 if (needs_modeset(crtc_state))
13744 ret = i915_gem_object_wait_rendering(old_obj, true);
13745
13746 /* Swallow -EIO errors to allow updates during hw lockup. */
13747 if (ret && ret != -EIO)
13748 return ret;
13749 }
13750
13751 /* For framebuffer backed by dmabuf, wait for fence */
13752 if (obj && obj->base.dma_buf) {
13753 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13754 false, true,
13755 MAX_SCHEDULE_TIMEOUT);
13756 if (ret == -ERESTARTSYS)
13757 return ret;
13758
13759 WARN_ON(ret < 0);
13760 }
13761
13762 if (!obj) {
13763 ret = 0;
13764 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13765 INTEL_INFO(dev)->cursor_needs_physical) {
13766 int align = IS_I830(dev) ? 16 * 1024 : 256;
13767 ret = i915_gem_object_attach_phys(obj, align);
13768 if (ret)
13769 DRM_DEBUG_KMS("failed to attach phys object\n");
13770 } else {
13771 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13772 }
13773
13774 if (ret == 0) {
13775 if (obj) {
13776 struct intel_plane_state *plane_state =
13777 to_intel_plane_state(new_state);
13778
13779 i915_gem_request_assign(&plane_state->wait_req,
13780 obj->last_write_req);
13781 }
13782
13783 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13784 }
13785
13786 return ret;
13787 }
13788
13789 /**
13790 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13791 * @plane: drm plane to clean up for
13792 * @fb: old framebuffer that was on plane
13793 *
13794 * Cleans up a framebuffer that has just been removed from a plane.
13795 *
13796 * Must be called with struct_mutex held.
13797 */
13798 void
13799 intel_cleanup_plane_fb(struct drm_plane *plane,
13800 const struct drm_plane_state *old_state)
13801 {
13802 struct drm_device *dev = plane->dev;
13803 struct intel_plane *intel_plane = to_intel_plane(plane);
13804 struct intel_plane_state *old_intel_state;
13805 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13806 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13807
13808 old_intel_state = to_intel_plane_state(old_state);
13809
13810 if (!obj && !old_obj)
13811 return;
13812
13813 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13814 !INTEL_INFO(dev)->cursor_needs_physical))
13815 intel_unpin_fb_obj(old_state->fb, old_state);
13816
13817 /* prepare_fb aborted? */
13818 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13819 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13820 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13821
13822 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13823
13824 }
13825
13826 int
13827 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13828 {
13829 int max_scale;
13830 struct drm_device *dev;
13831 struct drm_i915_private *dev_priv;
13832 int crtc_clock, cdclk;
13833
13834 if (!intel_crtc || !crtc_state)
13835 return DRM_PLANE_HELPER_NO_SCALING;
13836
13837 dev = intel_crtc->base.dev;
13838 dev_priv = dev->dev_private;
13839 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13840 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13841
13842 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13843 return DRM_PLANE_HELPER_NO_SCALING;
13844
13845 /*
13846 * skl max scale is lower of:
13847 * close to 3 but not 3, -1 is for that purpose
13848 * or
13849 * cdclk/crtc_clock
13850 */
13851 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13852
13853 return max_scale;
13854 }
13855
13856 static int
13857 intel_check_primary_plane(struct drm_plane *plane,
13858 struct intel_crtc_state *crtc_state,
13859 struct intel_plane_state *state)
13860 {
13861 struct drm_crtc *crtc = state->base.crtc;
13862 struct drm_framebuffer *fb = state->base.fb;
13863 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13864 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13865 bool can_position = false;
13866
13867 /* use scaler when colorkey is not required */
13868 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13869 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13870 min_scale = 1;
13871 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13872 can_position = true;
13873 }
13874
13875 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13876 &state->dst, &state->clip,
13877 min_scale, max_scale,
13878 can_position, true,
13879 &state->visible);
13880 }
13881
13882 static void
13883 intel_commit_primary_plane(struct drm_plane *plane,
13884 struct intel_plane_state *state)
13885 {
13886 struct drm_crtc *crtc = state->base.crtc;
13887 struct drm_framebuffer *fb = state->base.fb;
13888 struct drm_device *dev = plane->dev;
13889 struct drm_i915_private *dev_priv = dev->dev_private;
13890
13891 crtc = crtc ? crtc : plane->crtc;
13892
13893 dev_priv->display.update_primary_plane(crtc, fb,
13894 state->src.x1 >> 16,
13895 state->src.y1 >> 16);
13896 }
13897
13898 static void
13899 intel_disable_primary_plane(struct drm_plane *plane,
13900 struct drm_crtc *crtc)
13901 {
13902 struct drm_device *dev = plane->dev;
13903 struct drm_i915_private *dev_priv = dev->dev_private;
13904
13905 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13906 }
13907
13908 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13909 struct drm_crtc_state *old_crtc_state)
13910 {
13911 struct drm_device *dev = crtc->dev;
13912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13913 struct intel_crtc_state *old_intel_state =
13914 to_intel_crtc_state(old_crtc_state);
13915 bool modeset = needs_modeset(crtc->state);
13916
13917 /* Perform vblank evasion around commit operation */
13918 intel_pipe_update_start(intel_crtc);
13919
13920 if (modeset)
13921 return;
13922
13923 if (to_intel_crtc_state(crtc->state)->update_pipe)
13924 intel_update_pipe_config(intel_crtc, old_intel_state);
13925 else if (INTEL_INFO(dev)->gen >= 9)
13926 skl_detach_scalers(intel_crtc);
13927 }
13928
13929 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13930 struct drm_crtc_state *old_crtc_state)
13931 {
13932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13933
13934 intel_pipe_update_end(intel_crtc);
13935 }
13936
13937 /**
13938 * intel_plane_destroy - destroy a plane
13939 * @plane: plane to destroy
13940 *
13941 * Common destruction function for all types of planes (primary, cursor,
13942 * sprite).
13943 */
13944 void intel_plane_destroy(struct drm_plane *plane)
13945 {
13946 struct intel_plane *intel_plane = to_intel_plane(plane);
13947 drm_plane_cleanup(plane);
13948 kfree(intel_plane);
13949 }
13950
13951 const struct drm_plane_funcs intel_plane_funcs = {
13952 .update_plane = drm_atomic_helper_update_plane,
13953 .disable_plane = drm_atomic_helper_disable_plane,
13954 .destroy = intel_plane_destroy,
13955 .set_property = drm_atomic_helper_plane_set_property,
13956 .atomic_get_property = intel_plane_atomic_get_property,
13957 .atomic_set_property = intel_plane_atomic_set_property,
13958 .atomic_duplicate_state = intel_plane_duplicate_state,
13959 .atomic_destroy_state = intel_plane_destroy_state,
13960
13961 };
13962
13963 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13964 int pipe)
13965 {
13966 struct intel_plane *primary;
13967 struct intel_plane_state *state;
13968 const uint32_t *intel_primary_formats;
13969 unsigned int num_formats;
13970
13971 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13972 if (primary == NULL)
13973 return NULL;
13974
13975 state = intel_create_plane_state(&primary->base);
13976 if (!state) {
13977 kfree(primary);
13978 return NULL;
13979 }
13980 primary->base.state = &state->base;
13981
13982 primary->can_scale = false;
13983 primary->max_downscale = 1;
13984 if (INTEL_INFO(dev)->gen >= 9) {
13985 primary->can_scale = true;
13986 state->scaler_id = -1;
13987 }
13988 primary->pipe = pipe;
13989 primary->plane = pipe;
13990 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13991 primary->check_plane = intel_check_primary_plane;
13992 primary->commit_plane = intel_commit_primary_plane;
13993 primary->disable_plane = intel_disable_primary_plane;
13994 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13995 primary->plane = !pipe;
13996
13997 if (INTEL_INFO(dev)->gen >= 9) {
13998 intel_primary_formats = skl_primary_formats;
13999 num_formats = ARRAY_SIZE(skl_primary_formats);
14000 } else if (INTEL_INFO(dev)->gen >= 4) {
14001 intel_primary_formats = i965_primary_formats;
14002 num_formats = ARRAY_SIZE(i965_primary_formats);
14003 } else {
14004 intel_primary_formats = i8xx_primary_formats;
14005 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14006 }
14007
14008 drm_universal_plane_init(dev, &primary->base, 0,
14009 &intel_plane_funcs,
14010 intel_primary_formats, num_formats,
14011 DRM_PLANE_TYPE_PRIMARY);
14012
14013 if (INTEL_INFO(dev)->gen >= 4)
14014 intel_create_rotation_property(dev, primary);
14015
14016 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14017
14018 return &primary->base;
14019 }
14020
14021 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14022 {
14023 if (!dev->mode_config.rotation_property) {
14024 unsigned long flags = BIT(DRM_ROTATE_0) |
14025 BIT(DRM_ROTATE_180);
14026
14027 if (INTEL_INFO(dev)->gen >= 9)
14028 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14029
14030 dev->mode_config.rotation_property =
14031 drm_mode_create_rotation_property(dev, flags);
14032 }
14033 if (dev->mode_config.rotation_property)
14034 drm_object_attach_property(&plane->base.base,
14035 dev->mode_config.rotation_property,
14036 plane->base.state->rotation);
14037 }
14038
14039 static int
14040 intel_check_cursor_plane(struct drm_plane *plane,
14041 struct intel_crtc_state *crtc_state,
14042 struct intel_plane_state *state)
14043 {
14044 struct drm_crtc *crtc = crtc_state->base.crtc;
14045 struct drm_framebuffer *fb = state->base.fb;
14046 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14047 unsigned stride;
14048 int ret;
14049
14050 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14051 &state->dst, &state->clip,
14052 DRM_PLANE_HELPER_NO_SCALING,
14053 DRM_PLANE_HELPER_NO_SCALING,
14054 true, true, &state->visible);
14055 if (ret)
14056 return ret;
14057
14058 /* if we want to turn off the cursor ignore width and height */
14059 if (!obj)
14060 return 0;
14061
14062 /* Check for which cursor types we support */
14063 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14064 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14065 state->base.crtc_w, state->base.crtc_h);
14066 return -EINVAL;
14067 }
14068
14069 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14070 if (obj->base.size < stride * state->base.crtc_h) {
14071 DRM_DEBUG_KMS("buffer is too small\n");
14072 return -ENOMEM;
14073 }
14074
14075 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14076 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14077 return -EINVAL;
14078 }
14079
14080 return 0;
14081 }
14082
14083 static void
14084 intel_disable_cursor_plane(struct drm_plane *plane,
14085 struct drm_crtc *crtc)
14086 {
14087 intel_crtc_update_cursor(crtc, false);
14088 }
14089
14090 static void
14091 intel_commit_cursor_plane(struct drm_plane *plane,
14092 struct intel_plane_state *state)
14093 {
14094 struct drm_crtc *crtc = state->base.crtc;
14095 struct drm_device *dev = plane->dev;
14096 struct intel_crtc *intel_crtc;
14097 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14098 uint32_t addr;
14099
14100 crtc = crtc ? crtc : plane->crtc;
14101 intel_crtc = to_intel_crtc(crtc);
14102
14103 if (!obj)
14104 addr = 0;
14105 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14106 addr = i915_gem_obj_ggtt_offset(obj);
14107 else
14108 addr = obj->phys_handle->busaddr;
14109
14110 intel_crtc->cursor_addr = addr;
14111
14112 intel_crtc_update_cursor(crtc, state->visible);
14113 }
14114
14115 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14116 int pipe)
14117 {
14118 struct intel_plane *cursor;
14119 struct intel_plane_state *state;
14120
14121 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14122 if (cursor == NULL)
14123 return NULL;
14124
14125 state = intel_create_plane_state(&cursor->base);
14126 if (!state) {
14127 kfree(cursor);
14128 return NULL;
14129 }
14130 cursor->base.state = &state->base;
14131
14132 cursor->can_scale = false;
14133 cursor->max_downscale = 1;
14134 cursor->pipe = pipe;
14135 cursor->plane = pipe;
14136 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14137 cursor->check_plane = intel_check_cursor_plane;
14138 cursor->commit_plane = intel_commit_cursor_plane;
14139 cursor->disable_plane = intel_disable_cursor_plane;
14140
14141 drm_universal_plane_init(dev, &cursor->base, 0,
14142 &intel_plane_funcs,
14143 intel_cursor_formats,
14144 ARRAY_SIZE(intel_cursor_formats),
14145 DRM_PLANE_TYPE_CURSOR);
14146
14147 if (INTEL_INFO(dev)->gen >= 4) {
14148 if (!dev->mode_config.rotation_property)
14149 dev->mode_config.rotation_property =
14150 drm_mode_create_rotation_property(dev,
14151 BIT(DRM_ROTATE_0) |
14152 BIT(DRM_ROTATE_180));
14153 if (dev->mode_config.rotation_property)
14154 drm_object_attach_property(&cursor->base.base,
14155 dev->mode_config.rotation_property,
14156 state->base.rotation);
14157 }
14158
14159 if (INTEL_INFO(dev)->gen >=9)
14160 state->scaler_id = -1;
14161
14162 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14163
14164 return &cursor->base;
14165 }
14166
14167 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14168 struct intel_crtc_state *crtc_state)
14169 {
14170 int i;
14171 struct intel_scaler *intel_scaler;
14172 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14173
14174 for (i = 0; i < intel_crtc->num_scalers; i++) {
14175 intel_scaler = &scaler_state->scalers[i];
14176 intel_scaler->in_use = 0;
14177 intel_scaler->mode = PS_SCALER_MODE_DYN;
14178 }
14179
14180 scaler_state->scaler_id = -1;
14181 }
14182
14183 static void intel_crtc_init(struct drm_device *dev, int pipe)
14184 {
14185 struct drm_i915_private *dev_priv = dev->dev_private;
14186 struct intel_crtc *intel_crtc;
14187 struct intel_crtc_state *crtc_state = NULL;
14188 struct drm_plane *primary = NULL;
14189 struct drm_plane *cursor = NULL;
14190 int i, ret;
14191
14192 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14193 if (intel_crtc == NULL)
14194 return;
14195
14196 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14197 if (!crtc_state)
14198 goto fail;
14199 intel_crtc->config = crtc_state;
14200 intel_crtc->base.state = &crtc_state->base;
14201 crtc_state->base.crtc = &intel_crtc->base;
14202
14203 /* initialize shared scalers */
14204 if (INTEL_INFO(dev)->gen >= 9) {
14205 if (pipe == PIPE_C)
14206 intel_crtc->num_scalers = 1;
14207 else
14208 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14209
14210 skl_init_scalers(dev, intel_crtc, crtc_state);
14211 }
14212
14213 primary = intel_primary_plane_create(dev, pipe);
14214 if (!primary)
14215 goto fail;
14216
14217 cursor = intel_cursor_plane_create(dev, pipe);
14218 if (!cursor)
14219 goto fail;
14220
14221 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14222 cursor, &intel_crtc_funcs);
14223 if (ret)
14224 goto fail;
14225
14226 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14227 for (i = 0; i < 256; i++) {
14228 intel_crtc->lut_r[i] = i;
14229 intel_crtc->lut_g[i] = i;
14230 intel_crtc->lut_b[i] = i;
14231 }
14232
14233 /*
14234 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14235 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14236 */
14237 intel_crtc->pipe = pipe;
14238 intel_crtc->plane = pipe;
14239 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14240 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14241 intel_crtc->plane = !pipe;
14242 }
14243
14244 intel_crtc->cursor_base = ~0;
14245 intel_crtc->cursor_cntl = ~0;
14246 intel_crtc->cursor_size = ~0;
14247
14248 intel_crtc->wm.cxsr_allowed = true;
14249
14250 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14251 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14252 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14253 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14254
14255 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14256
14257 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14258 return;
14259
14260 fail:
14261 if (primary)
14262 drm_plane_cleanup(primary);
14263 if (cursor)
14264 drm_plane_cleanup(cursor);
14265 kfree(crtc_state);
14266 kfree(intel_crtc);
14267 }
14268
14269 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14270 {
14271 struct drm_encoder *encoder = connector->base.encoder;
14272 struct drm_device *dev = connector->base.dev;
14273
14274 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14275
14276 if (!encoder || WARN_ON(!encoder->crtc))
14277 return INVALID_PIPE;
14278
14279 return to_intel_crtc(encoder->crtc)->pipe;
14280 }
14281
14282 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14283 struct drm_file *file)
14284 {
14285 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14286 struct drm_crtc *drmmode_crtc;
14287 struct intel_crtc *crtc;
14288
14289 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14290
14291 if (!drmmode_crtc) {
14292 DRM_ERROR("no such CRTC id\n");
14293 return -ENOENT;
14294 }
14295
14296 crtc = to_intel_crtc(drmmode_crtc);
14297 pipe_from_crtc_id->pipe = crtc->pipe;
14298
14299 return 0;
14300 }
14301
14302 static int intel_encoder_clones(struct intel_encoder *encoder)
14303 {
14304 struct drm_device *dev = encoder->base.dev;
14305 struct intel_encoder *source_encoder;
14306 int index_mask = 0;
14307 int entry = 0;
14308
14309 for_each_intel_encoder(dev, source_encoder) {
14310 if (encoders_cloneable(encoder, source_encoder))
14311 index_mask |= (1 << entry);
14312
14313 entry++;
14314 }
14315
14316 return index_mask;
14317 }
14318
14319 static bool has_edp_a(struct drm_device *dev)
14320 {
14321 struct drm_i915_private *dev_priv = dev->dev_private;
14322
14323 if (!IS_MOBILE(dev))
14324 return false;
14325
14326 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14327 return false;
14328
14329 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14330 return false;
14331
14332 return true;
14333 }
14334
14335 static bool intel_crt_present(struct drm_device *dev)
14336 {
14337 struct drm_i915_private *dev_priv = dev->dev_private;
14338
14339 if (INTEL_INFO(dev)->gen >= 9)
14340 return false;
14341
14342 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14343 return false;
14344
14345 if (IS_CHERRYVIEW(dev))
14346 return false;
14347
14348 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14349 return false;
14350
14351 /* DDI E can't be used if DDI A requires 4 lanes */
14352 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14353 return false;
14354
14355 if (!dev_priv->vbt.int_crt_support)
14356 return false;
14357
14358 return true;
14359 }
14360
14361 static void intel_setup_outputs(struct drm_device *dev)
14362 {
14363 struct drm_i915_private *dev_priv = dev->dev_private;
14364 struct intel_encoder *encoder;
14365 bool dpd_is_edp = false;
14366
14367 intel_lvds_init(dev);
14368
14369 if (intel_crt_present(dev))
14370 intel_crt_init(dev);
14371
14372 if (IS_BROXTON(dev)) {
14373 /*
14374 * FIXME: Broxton doesn't support port detection via the
14375 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14376 * detect the ports.
14377 */
14378 intel_ddi_init(dev, PORT_A);
14379 intel_ddi_init(dev, PORT_B);
14380 intel_ddi_init(dev, PORT_C);
14381 } else if (HAS_DDI(dev)) {
14382 int found;
14383
14384 /*
14385 * Haswell uses DDI functions to detect digital outputs.
14386 * On SKL pre-D0 the strap isn't connected, so we assume
14387 * it's there.
14388 */
14389 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14390 /* WaIgnoreDDIAStrap: skl */
14391 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14392 intel_ddi_init(dev, PORT_A);
14393
14394 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14395 * register */
14396 found = I915_READ(SFUSE_STRAP);
14397
14398 if (found & SFUSE_STRAP_DDIB_DETECTED)
14399 intel_ddi_init(dev, PORT_B);
14400 if (found & SFUSE_STRAP_DDIC_DETECTED)
14401 intel_ddi_init(dev, PORT_C);
14402 if (found & SFUSE_STRAP_DDID_DETECTED)
14403 intel_ddi_init(dev, PORT_D);
14404 /*
14405 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14406 */
14407 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14408 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14409 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14410 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14411 intel_ddi_init(dev, PORT_E);
14412
14413 } else if (HAS_PCH_SPLIT(dev)) {
14414 int found;
14415 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14416
14417 if (has_edp_a(dev))
14418 intel_dp_init(dev, DP_A, PORT_A);
14419
14420 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14421 /* PCH SDVOB multiplex with HDMIB */
14422 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14423 if (!found)
14424 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14425 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14426 intel_dp_init(dev, PCH_DP_B, PORT_B);
14427 }
14428
14429 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14430 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14431
14432 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14433 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14434
14435 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14436 intel_dp_init(dev, PCH_DP_C, PORT_C);
14437
14438 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14439 intel_dp_init(dev, PCH_DP_D, PORT_D);
14440 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14441 /*
14442 * The DP_DETECTED bit is the latched state of the DDC
14443 * SDA pin at boot. However since eDP doesn't require DDC
14444 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14445 * eDP ports may have been muxed to an alternate function.
14446 * Thus we can't rely on the DP_DETECTED bit alone to detect
14447 * eDP ports. Consult the VBT as well as DP_DETECTED to
14448 * detect eDP ports.
14449 */
14450 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14451 !intel_dp_is_edp(dev, PORT_B))
14452 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14453 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14454 intel_dp_is_edp(dev, PORT_B))
14455 intel_dp_init(dev, VLV_DP_B, PORT_B);
14456
14457 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14458 !intel_dp_is_edp(dev, PORT_C))
14459 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14460 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14461 intel_dp_is_edp(dev, PORT_C))
14462 intel_dp_init(dev, VLV_DP_C, PORT_C);
14463
14464 if (IS_CHERRYVIEW(dev)) {
14465 /* eDP not supported on port D, so don't check VBT */
14466 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14467 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14468 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14469 intel_dp_init(dev, CHV_DP_D, PORT_D);
14470 }
14471
14472 intel_dsi_init(dev);
14473 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14474 bool found = false;
14475
14476 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14477 DRM_DEBUG_KMS("probing SDVOB\n");
14478 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14479 if (!found && IS_G4X(dev)) {
14480 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14481 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14482 }
14483
14484 if (!found && IS_G4X(dev))
14485 intel_dp_init(dev, DP_B, PORT_B);
14486 }
14487
14488 /* Before G4X SDVOC doesn't have its own detect register */
14489
14490 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14491 DRM_DEBUG_KMS("probing SDVOC\n");
14492 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14493 }
14494
14495 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14496
14497 if (IS_G4X(dev)) {
14498 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14499 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14500 }
14501 if (IS_G4X(dev))
14502 intel_dp_init(dev, DP_C, PORT_C);
14503 }
14504
14505 if (IS_G4X(dev) &&
14506 (I915_READ(DP_D) & DP_DETECTED))
14507 intel_dp_init(dev, DP_D, PORT_D);
14508 } else if (IS_GEN2(dev))
14509 intel_dvo_init(dev);
14510
14511 if (SUPPORTS_TV(dev))
14512 intel_tv_init(dev);
14513
14514 intel_psr_init(dev);
14515
14516 for_each_intel_encoder(dev, encoder) {
14517 encoder->base.possible_crtcs = encoder->crtc_mask;
14518 encoder->base.possible_clones =
14519 intel_encoder_clones(encoder);
14520 }
14521
14522 intel_init_pch_refclk(dev);
14523
14524 drm_helper_move_panel_connectors_to_head(dev);
14525 }
14526
14527 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14528 {
14529 struct drm_device *dev = fb->dev;
14530 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14531
14532 drm_framebuffer_cleanup(fb);
14533 mutex_lock(&dev->struct_mutex);
14534 WARN_ON(!intel_fb->obj->framebuffer_references--);
14535 drm_gem_object_unreference(&intel_fb->obj->base);
14536 mutex_unlock(&dev->struct_mutex);
14537 kfree(intel_fb);
14538 }
14539
14540 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14541 struct drm_file *file,
14542 unsigned int *handle)
14543 {
14544 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14545 struct drm_i915_gem_object *obj = intel_fb->obj;
14546
14547 if (obj->userptr.mm) {
14548 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14549 return -EINVAL;
14550 }
14551
14552 return drm_gem_handle_create(file, &obj->base, handle);
14553 }
14554
14555 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14556 struct drm_file *file,
14557 unsigned flags, unsigned color,
14558 struct drm_clip_rect *clips,
14559 unsigned num_clips)
14560 {
14561 struct drm_device *dev = fb->dev;
14562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14563 struct drm_i915_gem_object *obj = intel_fb->obj;
14564
14565 mutex_lock(&dev->struct_mutex);
14566 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14567 mutex_unlock(&dev->struct_mutex);
14568
14569 return 0;
14570 }
14571
14572 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14573 .destroy = intel_user_framebuffer_destroy,
14574 .create_handle = intel_user_framebuffer_create_handle,
14575 .dirty = intel_user_framebuffer_dirty,
14576 };
14577
14578 static
14579 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14580 uint32_t pixel_format)
14581 {
14582 u32 gen = INTEL_INFO(dev)->gen;
14583
14584 if (gen >= 9) {
14585 /* "The stride in bytes must not exceed the of the size of 8K
14586 * pixels and 32K bytes."
14587 */
14588 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14589 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14590 return 32*1024;
14591 } else if (gen >= 4) {
14592 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14593 return 16*1024;
14594 else
14595 return 32*1024;
14596 } else if (gen >= 3) {
14597 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14598 return 8*1024;
14599 else
14600 return 16*1024;
14601 } else {
14602 /* XXX DSPC is limited to 4k tiled */
14603 return 8*1024;
14604 }
14605 }
14606
14607 static int intel_framebuffer_init(struct drm_device *dev,
14608 struct intel_framebuffer *intel_fb,
14609 struct drm_mode_fb_cmd2 *mode_cmd,
14610 struct drm_i915_gem_object *obj)
14611 {
14612 unsigned int aligned_height;
14613 int ret;
14614 u32 pitch_limit, stride_alignment;
14615
14616 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14617
14618 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14619 /* Enforce that fb modifier and tiling mode match, but only for
14620 * X-tiled. This is needed for FBC. */
14621 if (!!(obj->tiling_mode == I915_TILING_X) !=
14622 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14623 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14624 return -EINVAL;
14625 }
14626 } else {
14627 if (obj->tiling_mode == I915_TILING_X)
14628 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14629 else if (obj->tiling_mode == I915_TILING_Y) {
14630 DRM_DEBUG("No Y tiling for legacy addfb\n");
14631 return -EINVAL;
14632 }
14633 }
14634
14635 /* Passed in modifier sanity checking. */
14636 switch (mode_cmd->modifier[0]) {
14637 case I915_FORMAT_MOD_Y_TILED:
14638 case I915_FORMAT_MOD_Yf_TILED:
14639 if (INTEL_INFO(dev)->gen < 9) {
14640 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14641 mode_cmd->modifier[0]);
14642 return -EINVAL;
14643 }
14644 case DRM_FORMAT_MOD_NONE:
14645 case I915_FORMAT_MOD_X_TILED:
14646 break;
14647 default:
14648 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14649 mode_cmd->modifier[0]);
14650 return -EINVAL;
14651 }
14652
14653 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14654 mode_cmd->pixel_format);
14655 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14656 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14657 mode_cmd->pitches[0], stride_alignment);
14658 return -EINVAL;
14659 }
14660
14661 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14662 mode_cmd->pixel_format);
14663 if (mode_cmd->pitches[0] > pitch_limit) {
14664 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14665 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14666 "tiled" : "linear",
14667 mode_cmd->pitches[0], pitch_limit);
14668 return -EINVAL;
14669 }
14670
14671 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14672 mode_cmd->pitches[0] != obj->stride) {
14673 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14674 mode_cmd->pitches[0], obj->stride);
14675 return -EINVAL;
14676 }
14677
14678 /* Reject formats not supported by any plane early. */
14679 switch (mode_cmd->pixel_format) {
14680 case DRM_FORMAT_C8:
14681 case DRM_FORMAT_RGB565:
14682 case DRM_FORMAT_XRGB8888:
14683 case DRM_FORMAT_ARGB8888:
14684 break;
14685 case DRM_FORMAT_XRGB1555:
14686 if (INTEL_INFO(dev)->gen > 3) {
14687 DRM_DEBUG("unsupported pixel format: %s\n",
14688 drm_get_format_name(mode_cmd->pixel_format));
14689 return -EINVAL;
14690 }
14691 break;
14692 case DRM_FORMAT_ABGR8888:
14693 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14694 INTEL_INFO(dev)->gen < 9) {
14695 DRM_DEBUG("unsupported pixel format: %s\n",
14696 drm_get_format_name(mode_cmd->pixel_format));
14697 return -EINVAL;
14698 }
14699 break;
14700 case DRM_FORMAT_XBGR8888:
14701 case DRM_FORMAT_XRGB2101010:
14702 case DRM_FORMAT_XBGR2101010:
14703 if (INTEL_INFO(dev)->gen < 4) {
14704 DRM_DEBUG("unsupported pixel format: %s\n",
14705 drm_get_format_name(mode_cmd->pixel_format));
14706 return -EINVAL;
14707 }
14708 break;
14709 case DRM_FORMAT_ABGR2101010:
14710 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14711 DRM_DEBUG("unsupported pixel format: %s\n",
14712 drm_get_format_name(mode_cmd->pixel_format));
14713 return -EINVAL;
14714 }
14715 break;
14716 case DRM_FORMAT_YUYV:
14717 case DRM_FORMAT_UYVY:
14718 case DRM_FORMAT_YVYU:
14719 case DRM_FORMAT_VYUY:
14720 if (INTEL_INFO(dev)->gen < 5) {
14721 DRM_DEBUG("unsupported pixel format: %s\n",
14722 drm_get_format_name(mode_cmd->pixel_format));
14723 return -EINVAL;
14724 }
14725 break;
14726 default:
14727 DRM_DEBUG("unsupported pixel format: %s\n",
14728 drm_get_format_name(mode_cmd->pixel_format));
14729 return -EINVAL;
14730 }
14731
14732 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14733 if (mode_cmd->offsets[0] != 0)
14734 return -EINVAL;
14735
14736 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14737 mode_cmd->pixel_format,
14738 mode_cmd->modifier[0]);
14739 /* FIXME drm helper for size checks (especially planar formats)? */
14740 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14741 return -EINVAL;
14742
14743 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14744 intel_fb->obj = obj;
14745 intel_fb->obj->framebuffer_references++;
14746
14747 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14748 if (ret) {
14749 DRM_ERROR("framebuffer init failed %d\n", ret);
14750 return ret;
14751 }
14752
14753 return 0;
14754 }
14755
14756 static struct drm_framebuffer *
14757 intel_user_framebuffer_create(struct drm_device *dev,
14758 struct drm_file *filp,
14759 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14760 {
14761 struct drm_framebuffer *fb;
14762 struct drm_i915_gem_object *obj;
14763 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14764
14765 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14766 mode_cmd.handles[0]));
14767 if (&obj->base == NULL)
14768 return ERR_PTR(-ENOENT);
14769
14770 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14771 if (IS_ERR(fb))
14772 drm_gem_object_unreference_unlocked(&obj->base);
14773
14774 return fb;
14775 }
14776
14777 #ifndef CONFIG_DRM_FBDEV_EMULATION
14778 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14779 {
14780 }
14781 #endif
14782
14783 static const struct drm_mode_config_funcs intel_mode_funcs = {
14784 .fb_create = intel_user_framebuffer_create,
14785 .output_poll_changed = intel_fbdev_output_poll_changed,
14786 .atomic_check = intel_atomic_check,
14787 .atomic_commit = intel_atomic_commit,
14788 .atomic_state_alloc = intel_atomic_state_alloc,
14789 .atomic_state_clear = intel_atomic_state_clear,
14790 };
14791
14792 /* Set up chip specific display functions */
14793 static void intel_init_display(struct drm_device *dev)
14794 {
14795 struct drm_i915_private *dev_priv = dev->dev_private;
14796
14797 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14798 dev_priv->display.find_dpll = g4x_find_best_dpll;
14799 else if (IS_CHERRYVIEW(dev))
14800 dev_priv->display.find_dpll = chv_find_best_dpll;
14801 else if (IS_VALLEYVIEW(dev))
14802 dev_priv->display.find_dpll = vlv_find_best_dpll;
14803 else if (IS_PINEVIEW(dev))
14804 dev_priv->display.find_dpll = pnv_find_best_dpll;
14805 else
14806 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14807
14808 if (INTEL_INFO(dev)->gen >= 9) {
14809 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14810 dev_priv->display.get_initial_plane_config =
14811 skylake_get_initial_plane_config;
14812 dev_priv->display.crtc_compute_clock =
14813 haswell_crtc_compute_clock;
14814 dev_priv->display.crtc_enable = haswell_crtc_enable;
14815 dev_priv->display.crtc_disable = haswell_crtc_disable;
14816 dev_priv->display.update_primary_plane =
14817 skylake_update_primary_plane;
14818 } else if (HAS_DDI(dev)) {
14819 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14820 dev_priv->display.get_initial_plane_config =
14821 ironlake_get_initial_plane_config;
14822 dev_priv->display.crtc_compute_clock =
14823 haswell_crtc_compute_clock;
14824 dev_priv->display.crtc_enable = haswell_crtc_enable;
14825 dev_priv->display.crtc_disable = haswell_crtc_disable;
14826 dev_priv->display.update_primary_plane =
14827 ironlake_update_primary_plane;
14828 } else if (HAS_PCH_SPLIT(dev)) {
14829 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14830 dev_priv->display.get_initial_plane_config =
14831 ironlake_get_initial_plane_config;
14832 dev_priv->display.crtc_compute_clock =
14833 ironlake_crtc_compute_clock;
14834 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14835 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14836 dev_priv->display.update_primary_plane =
14837 ironlake_update_primary_plane;
14838 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14839 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14840 dev_priv->display.get_initial_plane_config =
14841 i9xx_get_initial_plane_config;
14842 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14843 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14844 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14845 dev_priv->display.update_primary_plane =
14846 i9xx_update_primary_plane;
14847 } else {
14848 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14849 dev_priv->display.get_initial_plane_config =
14850 i9xx_get_initial_plane_config;
14851 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14852 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14853 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14854 dev_priv->display.update_primary_plane =
14855 i9xx_update_primary_plane;
14856 }
14857
14858 /* Returns the core display clock speed */
14859 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14860 dev_priv->display.get_display_clock_speed =
14861 skylake_get_display_clock_speed;
14862 else if (IS_BROXTON(dev))
14863 dev_priv->display.get_display_clock_speed =
14864 broxton_get_display_clock_speed;
14865 else if (IS_BROADWELL(dev))
14866 dev_priv->display.get_display_clock_speed =
14867 broadwell_get_display_clock_speed;
14868 else if (IS_HASWELL(dev))
14869 dev_priv->display.get_display_clock_speed =
14870 haswell_get_display_clock_speed;
14871 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14872 dev_priv->display.get_display_clock_speed =
14873 valleyview_get_display_clock_speed;
14874 else if (IS_GEN5(dev))
14875 dev_priv->display.get_display_clock_speed =
14876 ilk_get_display_clock_speed;
14877 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14878 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14879 dev_priv->display.get_display_clock_speed =
14880 i945_get_display_clock_speed;
14881 else if (IS_GM45(dev))
14882 dev_priv->display.get_display_clock_speed =
14883 gm45_get_display_clock_speed;
14884 else if (IS_CRESTLINE(dev))
14885 dev_priv->display.get_display_clock_speed =
14886 i965gm_get_display_clock_speed;
14887 else if (IS_PINEVIEW(dev))
14888 dev_priv->display.get_display_clock_speed =
14889 pnv_get_display_clock_speed;
14890 else if (IS_G33(dev) || IS_G4X(dev))
14891 dev_priv->display.get_display_clock_speed =
14892 g33_get_display_clock_speed;
14893 else if (IS_I915G(dev))
14894 dev_priv->display.get_display_clock_speed =
14895 i915_get_display_clock_speed;
14896 else if (IS_I945GM(dev) || IS_845G(dev))
14897 dev_priv->display.get_display_clock_speed =
14898 i9xx_misc_get_display_clock_speed;
14899 else if (IS_I915GM(dev))
14900 dev_priv->display.get_display_clock_speed =
14901 i915gm_get_display_clock_speed;
14902 else if (IS_I865G(dev))
14903 dev_priv->display.get_display_clock_speed =
14904 i865_get_display_clock_speed;
14905 else if (IS_I85X(dev))
14906 dev_priv->display.get_display_clock_speed =
14907 i85x_get_display_clock_speed;
14908 else { /* 830 */
14909 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14910 dev_priv->display.get_display_clock_speed =
14911 i830_get_display_clock_speed;
14912 }
14913
14914 if (IS_GEN5(dev)) {
14915 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14916 } else if (IS_GEN6(dev)) {
14917 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14918 } else if (IS_IVYBRIDGE(dev)) {
14919 /* FIXME: detect B0+ stepping and use auto training */
14920 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14921 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14922 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14923 if (IS_BROADWELL(dev)) {
14924 dev_priv->display.modeset_commit_cdclk =
14925 broadwell_modeset_commit_cdclk;
14926 dev_priv->display.modeset_calc_cdclk =
14927 broadwell_modeset_calc_cdclk;
14928 }
14929 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14930 dev_priv->display.modeset_commit_cdclk =
14931 valleyview_modeset_commit_cdclk;
14932 dev_priv->display.modeset_calc_cdclk =
14933 valleyview_modeset_calc_cdclk;
14934 } else if (IS_BROXTON(dev)) {
14935 dev_priv->display.modeset_commit_cdclk =
14936 broxton_modeset_commit_cdclk;
14937 dev_priv->display.modeset_calc_cdclk =
14938 broxton_modeset_calc_cdclk;
14939 }
14940
14941 switch (INTEL_INFO(dev)->gen) {
14942 case 2:
14943 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14944 break;
14945
14946 case 3:
14947 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14948 break;
14949
14950 case 4:
14951 case 5:
14952 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14953 break;
14954
14955 case 6:
14956 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14957 break;
14958 case 7:
14959 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14960 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14961 break;
14962 case 9:
14963 /* Drop through - unsupported since execlist only. */
14964 default:
14965 /* Default just returns -ENODEV to indicate unsupported */
14966 dev_priv->display.queue_flip = intel_default_queue_flip;
14967 }
14968
14969 mutex_init(&dev_priv->pps_mutex);
14970 }
14971
14972 /*
14973 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14974 * resume, or other times. This quirk makes sure that's the case for
14975 * affected systems.
14976 */
14977 static void quirk_pipea_force(struct drm_device *dev)
14978 {
14979 struct drm_i915_private *dev_priv = dev->dev_private;
14980
14981 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14982 DRM_INFO("applying pipe a force quirk\n");
14983 }
14984
14985 static void quirk_pipeb_force(struct drm_device *dev)
14986 {
14987 struct drm_i915_private *dev_priv = dev->dev_private;
14988
14989 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14990 DRM_INFO("applying pipe b force quirk\n");
14991 }
14992
14993 /*
14994 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14995 */
14996 static void quirk_ssc_force_disable(struct drm_device *dev)
14997 {
14998 struct drm_i915_private *dev_priv = dev->dev_private;
14999 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15000 DRM_INFO("applying lvds SSC disable quirk\n");
15001 }
15002
15003 /*
15004 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15005 * brightness value
15006 */
15007 static void quirk_invert_brightness(struct drm_device *dev)
15008 {
15009 struct drm_i915_private *dev_priv = dev->dev_private;
15010 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15011 DRM_INFO("applying inverted panel brightness quirk\n");
15012 }
15013
15014 /* Some VBT's incorrectly indicate no backlight is present */
15015 static void quirk_backlight_present(struct drm_device *dev)
15016 {
15017 struct drm_i915_private *dev_priv = dev->dev_private;
15018 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15019 DRM_INFO("applying backlight present quirk\n");
15020 }
15021
15022 struct intel_quirk {
15023 int device;
15024 int subsystem_vendor;
15025 int subsystem_device;
15026 void (*hook)(struct drm_device *dev);
15027 };
15028
15029 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15030 struct intel_dmi_quirk {
15031 void (*hook)(struct drm_device *dev);
15032 const struct dmi_system_id (*dmi_id_list)[];
15033 };
15034
15035 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15036 {
15037 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15038 return 1;
15039 }
15040
15041 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15042 {
15043 .dmi_id_list = &(const struct dmi_system_id[]) {
15044 {
15045 .callback = intel_dmi_reverse_brightness,
15046 .ident = "NCR Corporation",
15047 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15048 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15049 },
15050 },
15051 { } /* terminating entry */
15052 },
15053 .hook = quirk_invert_brightness,
15054 },
15055 };
15056
15057 static struct intel_quirk intel_quirks[] = {
15058 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15059 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15060
15061 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15062 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15063
15064 /* 830 needs to leave pipe A & dpll A up */
15065 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15066
15067 /* 830 needs to leave pipe B & dpll B up */
15068 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15069
15070 /* Lenovo U160 cannot use SSC on LVDS */
15071 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15072
15073 /* Sony Vaio Y cannot use SSC on LVDS */
15074 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15075
15076 /* Acer Aspire 5734Z must invert backlight brightness */
15077 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15078
15079 /* Acer/eMachines G725 */
15080 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15081
15082 /* Acer/eMachines e725 */
15083 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15084
15085 /* Acer/Packard Bell NCL20 */
15086 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15087
15088 /* Acer Aspire 4736Z */
15089 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15090
15091 /* Acer Aspire 5336 */
15092 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15093
15094 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15095 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15096
15097 /* Acer C720 Chromebook (Core i3 4005U) */
15098 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15099
15100 /* Apple Macbook 2,1 (Core 2 T7400) */
15101 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15102
15103 /* Apple Macbook 4,1 */
15104 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15105
15106 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15107 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15108
15109 /* HP Chromebook 14 (Celeron 2955U) */
15110 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15111
15112 /* Dell Chromebook 11 */
15113 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15114
15115 /* Dell Chromebook 11 (2015 version) */
15116 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15117 };
15118
15119 static void intel_init_quirks(struct drm_device *dev)
15120 {
15121 struct pci_dev *d = dev->pdev;
15122 int i;
15123
15124 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15125 struct intel_quirk *q = &intel_quirks[i];
15126
15127 if (d->device == q->device &&
15128 (d->subsystem_vendor == q->subsystem_vendor ||
15129 q->subsystem_vendor == PCI_ANY_ID) &&
15130 (d->subsystem_device == q->subsystem_device ||
15131 q->subsystem_device == PCI_ANY_ID))
15132 q->hook(dev);
15133 }
15134 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15135 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15136 intel_dmi_quirks[i].hook(dev);
15137 }
15138 }
15139
15140 /* Disable the VGA plane that we never use */
15141 static void i915_disable_vga(struct drm_device *dev)
15142 {
15143 struct drm_i915_private *dev_priv = dev->dev_private;
15144 u8 sr1;
15145 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15146
15147 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15148 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15149 outb(SR01, VGA_SR_INDEX);
15150 sr1 = inb(VGA_SR_DATA);
15151 outb(sr1 | 1<<5, VGA_SR_DATA);
15152 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15153 udelay(300);
15154
15155 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15156 POSTING_READ(vga_reg);
15157 }
15158
15159 void intel_modeset_init_hw(struct drm_device *dev)
15160 {
15161 intel_update_cdclk(dev);
15162 intel_prepare_ddi(dev);
15163 intel_init_clock_gating(dev);
15164 intel_enable_gt_powersave(dev);
15165 }
15166
15167 void intel_modeset_init(struct drm_device *dev)
15168 {
15169 struct drm_i915_private *dev_priv = dev->dev_private;
15170 int sprite, ret;
15171 enum pipe pipe;
15172 struct intel_crtc *crtc;
15173
15174 drm_mode_config_init(dev);
15175
15176 dev->mode_config.min_width = 0;
15177 dev->mode_config.min_height = 0;
15178
15179 dev->mode_config.preferred_depth = 24;
15180 dev->mode_config.prefer_shadow = 1;
15181
15182 dev->mode_config.allow_fb_modifiers = true;
15183
15184 dev->mode_config.funcs = &intel_mode_funcs;
15185
15186 intel_init_quirks(dev);
15187
15188 intel_init_pm(dev);
15189
15190 if (INTEL_INFO(dev)->num_pipes == 0)
15191 return;
15192
15193 /*
15194 * There may be no VBT; and if the BIOS enabled SSC we can
15195 * just keep using it to avoid unnecessary flicker. Whereas if the
15196 * BIOS isn't using it, don't assume it will work even if the VBT
15197 * indicates as much.
15198 */
15199 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15200 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15201 DREF_SSC1_ENABLE);
15202
15203 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15204 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15205 bios_lvds_use_ssc ? "en" : "dis",
15206 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15207 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15208 }
15209 }
15210
15211 intel_init_display(dev);
15212 intel_init_audio(dev);
15213
15214 if (IS_GEN2(dev)) {
15215 dev->mode_config.max_width = 2048;
15216 dev->mode_config.max_height = 2048;
15217 } else if (IS_GEN3(dev)) {
15218 dev->mode_config.max_width = 4096;
15219 dev->mode_config.max_height = 4096;
15220 } else {
15221 dev->mode_config.max_width = 8192;
15222 dev->mode_config.max_height = 8192;
15223 }
15224
15225 if (IS_845G(dev) || IS_I865G(dev)) {
15226 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15227 dev->mode_config.cursor_height = 1023;
15228 } else if (IS_GEN2(dev)) {
15229 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15230 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15231 } else {
15232 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15233 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15234 }
15235
15236 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15237
15238 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15239 INTEL_INFO(dev)->num_pipes,
15240 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15241
15242 for_each_pipe(dev_priv, pipe) {
15243 intel_crtc_init(dev, pipe);
15244 for_each_sprite(dev_priv, pipe, sprite) {
15245 ret = intel_plane_init(dev, pipe, sprite);
15246 if (ret)
15247 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15248 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15249 }
15250 }
15251
15252 intel_update_czclk(dev_priv);
15253 intel_update_cdclk(dev);
15254
15255 intel_shared_dpll_init(dev);
15256
15257 /* Just disable it once at startup */
15258 i915_disable_vga(dev);
15259 intel_setup_outputs(dev);
15260
15261 drm_modeset_lock_all(dev);
15262 intel_modeset_setup_hw_state(dev);
15263 drm_modeset_unlock_all(dev);
15264
15265 for_each_intel_crtc(dev, crtc) {
15266 struct intel_initial_plane_config plane_config = {};
15267
15268 if (!crtc->active)
15269 continue;
15270
15271 /*
15272 * Note that reserving the BIOS fb up front prevents us
15273 * from stuffing other stolen allocations like the ring
15274 * on top. This prevents some ugliness at boot time, and
15275 * can even allow for smooth boot transitions if the BIOS
15276 * fb is large enough for the active pipe configuration.
15277 */
15278 dev_priv->display.get_initial_plane_config(crtc,
15279 &plane_config);
15280
15281 /*
15282 * If the fb is shared between multiple heads, we'll
15283 * just get the first one.
15284 */
15285 intel_find_initial_plane_obj(crtc, &plane_config);
15286 }
15287 }
15288
15289 static void intel_enable_pipe_a(struct drm_device *dev)
15290 {
15291 struct intel_connector *connector;
15292 struct drm_connector *crt = NULL;
15293 struct intel_load_detect_pipe load_detect_temp;
15294 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15295
15296 /* We can't just switch on the pipe A, we need to set things up with a
15297 * proper mode and output configuration. As a gross hack, enable pipe A
15298 * by enabling the load detect pipe once. */
15299 for_each_intel_connector(dev, connector) {
15300 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15301 crt = &connector->base;
15302 break;
15303 }
15304 }
15305
15306 if (!crt)
15307 return;
15308
15309 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15310 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15311 }
15312
15313 static bool
15314 intel_check_plane_mapping(struct intel_crtc *crtc)
15315 {
15316 struct drm_device *dev = crtc->base.dev;
15317 struct drm_i915_private *dev_priv = dev->dev_private;
15318 u32 val;
15319
15320 if (INTEL_INFO(dev)->num_pipes == 1)
15321 return true;
15322
15323 val = I915_READ(DSPCNTR(!crtc->plane));
15324
15325 if ((val & DISPLAY_PLANE_ENABLE) &&
15326 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15327 return false;
15328
15329 return true;
15330 }
15331
15332 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15333 {
15334 struct drm_device *dev = crtc->base.dev;
15335 struct intel_encoder *encoder;
15336
15337 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15338 return true;
15339
15340 return false;
15341 }
15342
15343 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15344 {
15345 struct drm_device *dev = crtc->base.dev;
15346 struct drm_i915_private *dev_priv = dev->dev_private;
15347 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15348
15349 /* Clear any frame start delays used for debugging left by the BIOS */
15350 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15351
15352 /* restore vblank interrupts to correct state */
15353 drm_crtc_vblank_reset(&crtc->base);
15354 if (crtc->active) {
15355 struct intel_plane *plane;
15356
15357 drm_crtc_vblank_on(&crtc->base);
15358
15359 /* Disable everything but the primary plane */
15360 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15361 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15362 continue;
15363
15364 plane->disable_plane(&plane->base, &crtc->base);
15365 }
15366 }
15367
15368 /* We need to sanitize the plane -> pipe mapping first because this will
15369 * disable the crtc (and hence change the state) if it is wrong. Note
15370 * that gen4+ has a fixed plane -> pipe mapping. */
15371 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15372 bool plane;
15373
15374 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15375 crtc->base.base.id);
15376
15377 /* Pipe has the wrong plane attached and the plane is active.
15378 * Temporarily change the plane mapping and disable everything
15379 * ... */
15380 plane = crtc->plane;
15381 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15382 crtc->plane = !plane;
15383 intel_crtc_disable_noatomic(&crtc->base);
15384 crtc->plane = plane;
15385 }
15386
15387 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15388 crtc->pipe == PIPE_A && !crtc->active) {
15389 /* BIOS forgot to enable pipe A, this mostly happens after
15390 * resume. Force-enable the pipe to fix this, the update_dpms
15391 * call below we restore the pipe to the right state, but leave
15392 * the required bits on. */
15393 intel_enable_pipe_a(dev);
15394 }
15395
15396 /* Adjust the state of the output pipe according to whether we
15397 * have active connectors/encoders. */
15398 if (!intel_crtc_has_encoders(crtc))
15399 intel_crtc_disable_noatomic(&crtc->base);
15400
15401 if (crtc->active != crtc->base.state->active) {
15402 struct intel_encoder *encoder;
15403
15404 /* This can happen either due to bugs in the get_hw_state
15405 * functions or because of calls to intel_crtc_disable_noatomic,
15406 * or because the pipe is force-enabled due to the
15407 * pipe A quirk. */
15408 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15409 crtc->base.base.id,
15410 crtc->base.state->enable ? "enabled" : "disabled",
15411 crtc->active ? "enabled" : "disabled");
15412
15413 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15414 crtc->base.state->active = crtc->active;
15415 crtc->base.enabled = crtc->active;
15416
15417 /* Because we only establish the connector -> encoder ->
15418 * crtc links if something is active, this means the
15419 * crtc is now deactivated. Break the links. connector
15420 * -> encoder links are only establish when things are
15421 * actually up, hence no need to break them. */
15422 WARN_ON(crtc->active);
15423
15424 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15425 encoder->base.crtc = NULL;
15426 }
15427
15428 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15429 /*
15430 * We start out with underrun reporting disabled to avoid races.
15431 * For correct bookkeeping mark this on active crtcs.
15432 *
15433 * Also on gmch platforms we dont have any hardware bits to
15434 * disable the underrun reporting. Which means we need to start
15435 * out with underrun reporting disabled also on inactive pipes,
15436 * since otherwise we'll complain about the garbage we read when
15437 * e.g. coming up after runtime pm.
15438 *
15439 * No protection against concurrent access is required - at
15440 * worst a fifo underrun happens which also sets this to false.
15441 */
15442 crtc->cpu_fifo_underrun_disabled = true;
15443 crtc->pch_fifo_underrun_disabled = true;
15444 }
15445 }
15446
15447 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15448 {
15449 struct intel_connector *connector;
15450 struct drm_device *dev = encoder->base.dev;
15451 bool active = false;
15452
15453 /* We need to check both for a crtc link (meaning that the
15454 * encoder is active and trying to read from a pipe) and the
15455 * pipe itself being active. */
15456 bool has_active_crtc = encoder->base.crtc &&
15457 to_intel_crtc(encoder->base.crtc)->active;
15458
15459 for_each_intel_connector(dev, connector) {
15460 if (connector->base.encoder != &encoder->base)
15461 continue;
15462
15463 active = true;
15464 break;
15465 }
15466
15467 if (active && !has_active_crtc) {
15468 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15469 encoder->base.base.id,
15470 encoder->base.name);
15471
15472 /* Connector is active, but has no active pipe. This is
15473 * fallout from our resume register restoring. Disable
15474 * the encoder manually again. */
15475 if (encoder->base.crtc) {
15476 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15477 encoder->base.base.id,
15478 encoder->base.name);
15479 encoder->disable(encoder);
15480 if (encoder->post_disable)
15481 encoder->post_disable(encoder);
15482 }
15483 encoder->base.crtc = NULL;
15484
15485 /* Inconsistent output/port/pipe state happens presumably due to
15486 * a bug in one of the get_hw_state functions. Or someplace else
15487 * in our code, like the register restore mess on resume. Clamp
15488 * things to off as a safer default. */
15489 for_each_intel_connector(dev, connector) {
15490 if (connector->encoder != encoder)
15491 continue;
15492 connector->base.dpms = DRM_MODE_DPMS_OFF;
15493 connector->base.encoder = NULL;
15494 }
15495 }
15496 /* Enabled encoders without active connectors will be fixed in
15497 * the crtc fixup. */
15498 }
15499
15500 void i915_redisable_vga_power_on(struct drm_device *dev)
15501 {
15502 struct drm_i915_private *dev_priv = dev->dev_private;
15503 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15504
15505 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15506 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15507 i915_disable_vga(dev);
15508 }
15509 }
15510
15511 void i915_redisable_vga(struct drm_device *dev)
15512 {
15513 struct drm_i915_private *dev_priv = dev->dev_private;
15514
15515 /* This function can be called both from intel_modeset_setup_hw_state or
15516 * at a very early point in our resume sequence, where the power well
15517 * structures are not yet restored. Since this function is at a very
15518 * paranoid "someone might have enabled VGA while we were not looking"
15519 * level, just check if the power well is enabled instead of trying to
15520 * follow the "don't touch the power well if we don't need it" policy
15521 * the rest of the driver uses. */
15522 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15523 return;
15524
15525 i915_redisable_vga_power_on(dev);
15526 }
15527
15528 static bool primary_get_hw_state(struct intel_plane *plane)
15529 {
15530 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15531
15532 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15533 }
15534
15535 /* FIXME read out full plane state for all planes */
15536 static void readout_plane_state(struct intel_crtc *crtc)
15537 {
15538 struct drm_plane *primary = crtc->base.primary;
15539 struct intel_plane_state *plane_state =
15540 to_intel_plane_state(primary->state);
15541
15542 plane_state->visible = crtc->active &&
15543 primary_get_hw_state(to_intel_plane(primary));
15544
15545 if (plane_state->visible)
15546 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15547 }
15548
15549 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15550 {
15551 struct drm_i915_private *dev_priv = dev->dev_private;
15552 enum pipe pipe;
15553 struct intel_crtc *crtc;
15554 struct intel_encoder *encoder;
15555 struct intel_connector *connector;
15556 int i;
15557
15558 for_each_intel_crtc(dev, crtc) {
15559 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15560 memset(crtc->config, 0, sizeof(*crtc->config));
15561 crtc->config->base.crtc = &crtc->base;
15562
15563 crtc->active = dev_priv->display.get_pipe_config(crtc,
15564 crtc->config);
15565
15566 crtc->base.state->active = crtc->active;
15567 crtc->base.enabled = crtc->active;
15568
15569 readout_plane_state(crtc);
15570
15571 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15572 crtc->base.base.id,
15573 crtc->active ? "enabled" : "disabled");
15574 }
15575
15576 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15577 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15578
15579 pll->on = pll->get_hw_state(dev_priv, pll,
15580 &pll->config.hw_state);
15581 pll->active = 0;
15582 pll->config.crtc_mask = 0;
15583 for_each_intel_crtc(dev, crtc) {
15584 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15585 pll->active++;
15586 pll->config.crtc_mask |= 1 << crtc->pipe;
15587 }
15588 }
15589
15590 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15591 pll->name, pll->config.crtc_mask, pll->on);
15592
15593 if (pll->config.crtc_mask)
15594 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15595 }
15596
15597 for_each_intel_encoder(dev, encoder) {
15598 pipe = 0;
15599
15600 if (encoder->get_hw_state(encoder, &pipe)) {
15601 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15602 encoder->base.crtc = &crtc->base;
15603 encoder->get_config(encoder, crtc->config);
15604 } else {
15605 encoder->base.crtc = NULL;
15606 }
15607
15608 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15609 encoder->base.base.id,
15610 encoder->base.name,
15611 encoder->base.crtc ? "enabled" : "disabled",
15612 pipe_name(pipe));
15613 }
15614
15615 for_each_intel_connector(dev, connector) {
15616 if (connector->get_hw_state(connector)) {
15617 connector->base.dpms = DRM_MODE_DPMS_ON;
15618 connector->base.encoder = &connector->encoder->base;
15619 } else {
15620 connector->base.dpms = DRM_MODE_DPMS_OFF;
15621 connector->base.encoder = NULL;
15622 }
15623 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15624 connector->base.base.id,
15625 connector->base.name,
15626 connector->base.encoder ? "enabled" : "disabled");
15627 }
15628
15629 for_each_intel_crtc(dev, crtc) {
15630 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15631
15632 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15633 if (crtc->base.state->active) {
15634 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15635 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15636 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15637
15638 /*
15639 * The initial mode needs to be set in order to keep
15640 * the atomic core happy. It wants a valid mode if the
15641 * crtc's enabled, so we do the above call.
15642 *
15643 * At this point some state updated by the connectors
15644 * in their ->detect() callback has not run yet, so
15645 * no recalculation can be done yet.
15646 *
15647 * Even if we could do a recalculation and modeset
15648 * right now it would cause a double modeset if
15649 * fbdev or userspace chooses a different initial mode.
15650 *
15651 * If that happens, someone indicated they wanted a
15652 * mode change, which means it's safe to do a full
15653 * recalculation.
15654 */
15655 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15656
15657 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15658 update_scanline_offset(crtc);
15659 }
15660 }
15661 }
15662
15663 /* Scan out the current hw modeset state,
15664 * and sanitizes it to the current state
15665 */
15666 static void
15667 intel_modeset_setup_hw_state(struct drm_device *dev)
15668 {
15669 struct drm_i915_private *dev_priv = dev->dev_private;
15670 enum pipe pipe;
15671 struct intel_crtc *crtc;
15672 struct intel_encoder *encoder;
15673 int i;
15674
15675 intel_modeset_readout_hw_state(dev);
15676
15677 /* HW state is read out, now we need to sanitize this mess. */
15678 for_each_intel_encoder(dev, encoder) {
15679 intel_sanitize_encoder(encoder);
15680 }
15681
15682 for_each_pipe(dev_priv, pipe) {
15683 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15684 intel_sanitize_crtc(crtc);
15685 intel_dump_pipe_config(crtc, crtc->config,
15686 "[setup_hw_state]");
15687 }
15688
15689 intel_modeset_update_connector_atomic_state(dev);
15690
15691 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15692 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15693
15694 if (!pll->on || pll->active)
15695 continue;
15696
15697 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15698
15699 pll->disable(dev_priv, pll);
15700 pll->on = false;
15701 }
15702
15703 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15704 vlv_wm_get_hw_state(dev);
15705 else if (IS_GEN9(dev))
15706 skl_wm_get_hw_state(dev);
15707 else if (HAS_PCH_SPLIT(dev))
15708 ilk_wm_get_hw_state(dev);
15709
15710 for_each_intel_crtc(dev, crtc) {
15711 unsigned long put_domains;
15712
15713 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15714 if (WARN_ON(put_domains))
15715 modeset_put_power_domains(dev_priv, put_domains);
15716 }
15717 intel_display_set_init_power(dev_priv, false);
15718 }
15719
15720 void intel_display_resume(struct drm_device *dev)
15721 {
15722 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15723 struct intel_connector *conn;
15724 struct intel_plane *plane;
15725 struct drm_crtc *crtc;
15726 int ret;
15727
15728 if (!state)
15729 return;
15730
15731 state->acquire_ctx = dev->mode_config.acquire_ctx;
15732
15733 /* preserve complete old state, including dpll */
15734 intel_atomic_get_shared_dpll_state(state);
15735
15736 for_each_crtc(dev, crtc) {
15737 struct drm_crtc_state *crtc_state =
15738 drm_atomic_get_crtc_state(state, crtc);
15739
15740 ret = PTR_ERR_OR_ZERO(crtc_state);
15741 if (ret)
15742 goto err;
15743
15744 /* force a restore */
15745 crtc_state->mode_changed = true;
15746 }
15747
15748 for_each_intel_plane(dev, plane) {
15749 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15750 if (ret)
15751 goto err;
15752 }
15753
15754 for_each_intel_connector(dev, conn) {
15755 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15756 if (ret)
15757 goto err;
15758 }
15759
15760 intel_modeset_setup_hw_state(dev);
15761
15762 i915_redisable_vga(dev);
15763 ret = drm_atomic_commit(state);
15764 if (!ret)
15765 return;
15766
15767 err:
15768 DRM_ERROR("Restoring old state failed with %i\n", ret);
15769 drm_atomic_state_free(state);
15770 }
15771
15772 void intel_modeset_gem_init(struct drm_device *dev)
15773 {
15774 struct drm_crtc *c;
15775 struct drm_i915_gem_object *obj;
15776 int ret;
15777
15778 mutex_lock(&dev->struct_mutex);
15779 intel_init_gt_powersave(dev);
15780 mutex_unlock(&dev->struct_mutex);
15781
15782 intel_modeset_init_hw(dev);
15783
15784 intel_setup_overlay(dev);
15785
15786 /*
15787 * Make sure any fbs we allocated at startup are properly
15788 * pinned & fenced. When we do the allocation it's too early
15789 * for this.
15790 */
15791 for_each_crtc(dev, c) {
15792 obj = intel_fb_obj(c->primary->fb);
15793 if (obj == NULL)
15794 continue;
15795
15796 mutex_lock(&dev->struct_mutex);
15797 ret = intel_pin_and_fence_fb_obj(c->primary,
15798 c->primary->fb,
15799 c->primary->state);
15800 mutex_unlock(&dev->struct_mutex);
15801 if (ret) {
15802 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15803 to_intel_crtc(c)->pipe);
15804 drm_framebuffer_unreference(c->primary->fb);
15805 c->primary->fb = NULL;
15806 c->primary->crtc = c->primary->state->crtc = NULL;
15807 update_state_fb(c->primary);
15808 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15809 }
15810 }
15811
15812 intel_backlight_register(dev);
15813 }
15814
15815 void intel_connector_unregister(struct intel_connector *intel_connector)
15816 {
15817 struct drm_connector *connector = &intel_connector->base;
15818
15819 intel_panel_destroy_backlight(connector);
15820 drm_connector_unregister(connector);
15821 }
15822
15823 void intel_modeset_cleanup(struct drm_device *dev)
15824 {
15825 struct drm_i915_private *dev_priv = dev->dev_private;
15826 struct intel_connector *connector;
15827
15828 intel_disable_gt_powersave(dev);
15829
15830 intel_backlight_unregister(dev);
15831
15832 /*
15833 * Interrupts and polling as the first thing to avoid creating havoc.
15834 * Too much stuff here (turning of connectors, ...) would
15835 * experience fancy races otherwise.
15836 */
15837 intel_irq_uninstall(dev_priv);
15838
15839 /*
15840 * Due to the hpd irq storm handling the hotplug work can re-arm the
15841 * poll handlers. Hence disable polling after hpd handling is shut down.
15842 */
15843 drm_kms_helper_poll_fini(dev);
15844
15845 intel_unregister_dsm_handler();
15846
15847 intel_fbc_disable(dev_priv);
15848
15849 /* flush any delayed tasks or pending work */
15850 flush_scheduled_work();
15851
15852 /* destroy the backlight and sysfs files before encoders/connectors */
15853 for_each_intel_connector(dev, connector)
15854 connector->unregister(connector);
15855
15856 drm_mode_config_cleanup(dev);
15857
15858 intel_cleanup_overlay(dev);
15859
15860 mutex_lock(&dev->struct_mutex);
15861 intel_cleanup_gt_powersave(dev);
15862 mutex_unlock(&dev->struct_mutex);
15863 }
15864
15865 /*
15866 * Return which encoder is currently attached for connector.
15867 */
15868 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15869 {
15870 return &intel_attached_encoder(connector)->base;
15871 }
15872
15873 void intel_connector_attach_encoder(struct intel_connector *connector,
15874 struct intel_encoder *encoder)
15875 {
15876 connector->encoder = encoder;
15877 drm_mode_connector_attach_encoder(&connector->base,
15878 &encoder->base);
15879 }
15880
15881 /*
15882 * set vga decode state - true == enable VGA decode
15883 */
15884 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15885 {
15886 struct drm_i915_private *dev_priv = dev->dev_private;
15887 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15888 u16 gmch_ctrl;
15889
15890 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15891 DRM_ERROR("failed to read control word\n");
15892 return -EIO;
15893 }
15894
15895 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15896 return 0;
15897
15898 if (state)
15899 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15900 else
15901 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15902
15903 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15904 DRM_ERROR("failed to write control word\n");
15905 return -EIO;
15906 }
15907
15908 return 0;
15909 }
15910
15911 struct intel_display_error_state {
15912
15913 u32 power_well_driver;
15914
15915 int num_transcoders;
15916
15917 struct intel_cursor_error_state {
15918 u32 control;
15919 u32 position;
15920 u32 base;
15921 u32 size;
15922 } cursor[I915_MAX_PIPES];
15923
15924 struct intel_pipe_error_state {
15925 bool power_domain_on;
15926 u32 source;
15927 u32 stat;
15928 } pipe[I915_MAX_PIPES];
15929
15930 struct intel_plane_error_state {
15931 u32 control;
15932 u32 stride;
15933 u32 size;
15934 u32 pos;
15935 u32 addr;
15936 u32 surface;
15937 u32 tile_offset;
15938 } plane[I915_MAX_PIPES];
15939
15940 struct intel_transcoder_error_state {
15941 bool power_domain_on;
15942 enum transcoder cpu_transcoder;
15943
15944 u32 conf;
15945
15946 u32 htotal;
15947 u32 hblank;
15948 u32 hsync;
15949 u32 vtotal;
15950 u32 vblank;
15951 u32 vsync;
15952 } transcoder[4];
15953 };
15954
15955 struct intel_display_error_state *
15956 intel_display_capture_error_state(struct drm_device *dev)
15957 {
15958 struct drm_i915_private *dev_priv = dev->dev_private;
15959 struct intel_display_error_state *error;
15960 int transcoders[] = {
15961 TRANSCODER_A,
15962 TRANSCODER_B,
15963 TRANSCODER_C,
15964 TRANSCODER_EDP,
15965 };
15966 int i;
15967
15968 if (INTEL_INFO(dev)->num_pipes == 0)
15969 return NULL;
15970
15971 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15972 if (error == NULL)
15973 return NULL;
15974
15975 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15976 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15977
15978 for_each_pipe(dev_priv, i) {
15979 error->pipe[i].power_domain_on =
15980 __intel_display_power_is_enabled(dev_priv,
15981 POWER_DOMAIN_PIPE(i));
15982 if (!error->pipe[i].power_domain_on)
15983 continue;
15984
15985 error->cursor[i].control = I915_READ(CURCNTR(i));
15986 error->cursor[i].position = I915_READ(CURPOS(i));
15987 error->cursor[i].base = I915_READ(CURBASE(i));
15988
15989 error->plane[i].control = I915_READ(DSPCNTR(i));
15990 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15991 if (INTEL_INFO(dev)->gen <= 3) {
15992 error->plane[i].size = I915_READ(DSPSIZE(i));
15993 error->plane[i].pos = I915_READ(DSPPOS(i));
15994 }
15995 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15996 error->plane[i].addr = I915_READ(DSPADDR(i));
15997 if (INTEL_INFO(dev)->gen >= 4) {
15998 error->plane[i].surface = I915_READ(DSPSURF(i));
15999 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16000 }
16001
16002 error->pipe[i].source = I915_READ(PIPESRC(i));
16003
16004 if (HAS_GMCH_DISPLAY(dev))
16005 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16006 }
16007
16008 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16009 if (HAS_DDI(dev_priv->dev))
16010 error->num_transcoders++; /* Account for eDP. */
16011
16012 for (i = 0; i < error->num_transcoders; i++) {
16013 enum transcoder cpu_transcoder = transcoders[i];
16014
16015 error->transcoder[i].power_domain_on =
16016 __intel_display_power_is_enabled(dev_priv,
16017 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16018 if (!error->transcoder[i].power_domain_on)
16019 continue;
16020
16021 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16022
16023 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16024 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16025 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16026 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16027 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16028 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16029 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16030 }
16031
16032 return error;
16033 }
16034
16035 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16036
16037 void
16038 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16039 struct drm_device *dev,
16040 struct intel_display_error_state *error)
16041 {
16042 struct drm_i915_private *dev_priv = dev->dev_private;
16043 int i;
16044
16045 if (!error)
16046 return;
16047
16048 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16049 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16050 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16051 error->power_well_driver);
16052 for_each_pipe(dev_priv, i) {
16053 err_printf(m, "Pipe [%d]:\n", i);
16054 err_printf(m, " Power: %s\n",
16055 error->pipe[i].power_domain_on ? "on" : "off");
16056 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16057 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16058
16059 err_printf(m, "Plane [%d]:\n", i);
16060 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16061 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16062 if (INTEL_INFO(dev)->gen <= 3) {
16063 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16064 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16065 }
16066 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16067 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16068 if (INTEL_INFO(dev)->gen >= 4) {
16069 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16070 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16071 }
16072
16073 err_printf(m, "Cursor [%d]:\n", i);
16074 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16075 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16076 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16077 }
16078
16079 for (i = 0; i < error->num_transcoders; i++) {
16080 err_printf(m, "CPU transcoder: %c\n",
16081 transcoder_name(error->transcoder[i].cpu_transcoder));
16082 err_printf(m, " Power: %s\n",
16083 error->transcoder[i].power_domain_on ? "on" : "off");
16084 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16085 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16086 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16087 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16088 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16089 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16090 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16091 }
16092 }
16093
16094 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16095 {
16096 struct intel_crtc *crtc;
16097
16098 for_each_intel_crtc(dev, crtc) {
16099 struct intel_unpin_work *work;
16100
16101 spin_lock_irq(&dev->event_lock);
16102
16103 work = crtc->unpin_work;
16104
16105 if (work && work->event &&
16106 work->event->base.file_priv == file) {
16107 kfree(work->event);
16108 work->event = NULL;
16109 }
16110
16111 spin_unlock_irq(&dev->event_lock);
16112 }
16113 }
Linux kernel - Deliverables
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