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drm/i915: Enable FBC at Haswell.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80 };
81
82 /* FDI */
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
85 int
86 intel_pch_rawclk(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93 }
94
95 static bool
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99 static bool
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104 static bool
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
111 {
112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
117 }
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131 };
132
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145 };
146
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159 };
160
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173 };
174
175
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
188 },
189 .find_pll = intel_g4x_find_best_PLL,
190 };
191
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204 };
205
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
217 },
218 .find_pll = intel_g4x_find_best_PLL,
219 };
220
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
232 },
233 .find_pll = intel_g4x_find_best_PLL,
234 };
235
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250 };
251
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264 };
265
266 /* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283 };
284
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311 };
312
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340 };
341
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354 };
355
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368 };
369
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382 };
383
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385 {
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
387
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
390 return 0;
391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
398 return 0;
399 }
400
401 return I915_READ(DPIO_DATA);
402 }
403
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
405 {
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
407
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
410 return;
411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
419 }
420
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
423 {
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
439 } else
440 limit = &intel_limits_ironlake_dac;
441
442 return limit;
443 }
444
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446 {
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
453 else
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
462
463 return limit;
464 }
465
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
467 {
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
478 else
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
495 else
496 limit = &intel_limits_i8xx_dvo;
497 }
498 return limit;
499 }
500
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
503 {
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508 }
509
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511 {
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513 }
514
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516 {
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
519 return;
520 }
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525 }
526
527 /**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
531 {
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
534
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
537 return true;
538
539 return false;
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
573
574 return true;
575 }
576
577 static bool
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
581
582 {
583 struct drm_device *dev = crtc->dev;
584 intel_clock_t clock;
585 int err = target;
586
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
604 memset(best_clock, 0, sizeof(*best_clock));
605
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
617 int this_err;
618
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
622 continue;
623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638 }
639
640 static bool
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
644 {
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
647 int max_n;
648 bool found;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 int lvds_reg;
655
656 if (HAS_PCH_SPLIT(dev))
657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
660 if (intel_is_dual_link_lvds(dev))
661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
673 /* based on hardware requirement, prefer smaller n to precision */
674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
675 /* based on hardware requirement, prefere larger m1,m2 */
676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
684 intel_clock(dev, refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
700 return found;
701 }
702
703 static bool
704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
714 flag = 0;
715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770 }
771
772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774 {
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
778 return intel_crtc->config.cpu_transcoder;
779 }
780
781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782 {
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790 }
791
792 /**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
801 {
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 int pipestat_reg = PIPESTAT(pipe);
804
805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
826 /* Wait for vblank interrupt bit to set */
827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
830 DRM_DEBUG_KMS("vblank wait timed out\n");
831 }
832
833 /*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
848 *
849 */
850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
851 {
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
855
856 if (INTEL_INFO(dev)->gen >= 4) {
857 int reg = PIPECONF(cpu_transcoder);
858
859 /* Wait for the Pipe State to go off */
860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
862 WARN(1, "pipe_off wait timed out\n");
863 } else {
864 u32 last_line, line_mask;
865 int reg = PIPEDSL(pipe);
866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
873 /* Wait for the display line to settle */
874 do {
875 last_line = I915_READ(reg) & line_mask;
876 mdelay(5);
877 } while (((I915_READ(reg) & line_mask) != last_line) &&
878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
880 WARN(1, "pipe_off wait timed out\n");
881 }
882 }
883
884 /*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893 {
894 u32 bit;
895
896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
924 }
925
926 return I915_READ(SDEISR) & bit;
927 }
928
929 static const char *state_string(bool enabled)
930 {
931 return enabled ? "on" : "off";
932 }
933
934 /* Only for pre-ILK configs */
935 static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937 {
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948 }
949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
952 /* For ILK+ */
953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
957 {
958 u32 val;
959 bool cur_state;
960
961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
968 return;
969
970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
987 "PLL[%d] not %s on this transcoder %c: %08x\n",
988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
990 pipe_name(crtc->pipe),
991 val);
992 }
993 }
994 }
995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
997
998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000 {
1001 int reg;
1002 u32 val;
1003 bool cur_state;
1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
1006
1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010 val = I915_READ(reg);
1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020 }
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026 {
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037 }
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043 {
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052 if (HAS_DDI(dev_priv->dev))
1053 return;
1054
1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058 }
1059
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062 {
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069 }
1070
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073 {
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
1077 bool locked = true;
1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
1097 pipe_name(pipe));
1098 }
1099
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
1108
1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
1113 if (!intel_display_power_enabled(dev_priv->dev,
1114 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
1124 pipe_name(pipe), state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
1140 }
1141
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147 {
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
1152 /* Planes are fixed to pipes on ILK+ */
1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
1159 return;
1160 }
1161
1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
1171 }
1172 }
1173
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176 {
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
1190 }
1191 }
1192
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194 {
1195 u32 val;
1196 bool enabled;
1197
1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207 }
1208
1209 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = PCH_TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
1222 }
1223
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
1226 {
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240 }
1241
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244 {
1245 if ((val & SDVO_ENABLE) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1253 return false;
1254 }
1255 return true;
1256 }
1257
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260 {
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272 }
1273
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276 {
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287 }
1288
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, int reg, u32 port_sel)
1291 {
1292 u32 val = I915_READ(reg);
1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295 reg, pipe_name(pipe));
1296
1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
1299 "IBX PCH dp port still using transcoder B\n");
1300 }
1301
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304 {
1305 u32 val = I915_READ(reg);
1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308 reg, pipe_name(pipe));
1309
1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311 && (val & SDVO_PIPE_B_SELECT),
1312 "IBX PCH hdmi port still using transcoder B\n");
1313 }
1314
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 int reg;
1319 u32 val;
1320
1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
1329 pipe_name(pipe));
1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1335 pipe_name(pipe));
1336
1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1340 }
1341
1342 /**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1354 */
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359
1360 assert_pipe_disabled(dev_priv, pipe);
1361
1362 /* No really, not for ILK+ */
1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411 }
1412
1413 /* SBI access */
1414 static void
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
1417 {
1418 u32 tmp;
1419
1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
1425 return;
1426 }
1427
1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1436
1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1440 return;
1441 }
1442 }
1443
1444 static u32
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
1447 {
1448 u32 value = 0;
1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1450
1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
1454 return 0;
1455 }
1456
1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1464
1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1468 return 0;
1469 }
1470
1471 return I915_READ(SBI_DATA);
1472 }
1473
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475 {
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486 }
1487
1488 /**
1489 * ironlake_enable_pch_pll - enable PCH PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1497 {
1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499 struct intel_pch_pll *pll;
1500 int reg;
1501 u32 val;
1502
1503 /* PCH PLLs only available on ILK, SNB and IVB */
1504 BUG_ON(dev_priv->info->gen < 5);
1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
1519 if (pll->active++ && pll->on) {
1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
1532
1533 pll->on = true;
1534 }
1535
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1537 {
1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1540 int reg;
1541 u32 val;
1542
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1545 if (pll == NULL)
1546 return;
1547
1548 if (WARN_ON(pll->refcount == 0))
1549 return;
1550
1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
1554
1555 if (WARN_ON(pll->active == 0)) {
1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
1557 return;
1558 }
1559
1560 if (--pll->active) {
1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
1562 return;
1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1569
1570 reg = pll->pll_reg;
1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
1576
1577 pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
1582 {
1583 struct drm_device *dev = dev_priv->dev;
1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585 uint32_t reg, val, pipeconf_val;
1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
1606 }
1607
1608 reg = PCH_TRANSCONF(pipe);
1609 val = I915_READ(reg);
1610 pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619 }
1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637 enum transcoder cpu_transcoder)
1638 {
1639 u32 val, pipeconf_val;
1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653 val = TRANS_ENABLE;
1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
1658 val |= TRANS_INTERLACED;
1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
1669 {
1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
1680 reg = PCH_TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699 u32 val;
1700
1701 val = I915_READ(LPT_TRANSCONF);
1702 val &= ~TRANS_ENABLE;
1703 I915_WRITE(LPT_TRANSCONF, val);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
1730 {
1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1733 enum pipe pch_transcoder;
1734 int reg;
1735 u32 val;
1736
1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
1740 if (HAS_PCH_LPT(dev_priv->dev))
1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
1761
1762 reg = PIPECONF(cpu_transcoder);
1763 val = I915_READ(reg);
1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 /**
1772 * intel_disable_pipe - disable a pipe, asserting requirements
1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785 {
1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
1796 assert_sprites_disabled(dev_priv, pipe);
1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
1802 reg = PIPECONF(cpu_transcoder);
1803 val = I915_READ(reg);
1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane)
1817 {
1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1822 }
1823
1824 /**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834 {
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847 intel_flush_display_plane(dev_priv, plane);
1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861 {
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 static bool need_vtd_wa(struct drm_device *dev)
1876 {
1877 #ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880 #endif
1881 return false;
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886 struct drm_i915_gem_object *obj,
1887 struct intel_ring_buffer *pipelined)
1888 {
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 u32 alignment;
1891 int ret;
1892
1893 switch (obj->tiling_mode) {
1894 case I915_TILING_NONE:
1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
1897 else if (INTEL_INFO(dev)->gen >= 4)
1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
1924 dev_priv->mm.interruptible = false;
1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926 if (ret)
1927 goto err_interruptible;
1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
1934 ret = i915_gem_object_get_fence(obj);
1935 if (ret)
1936 goto err_unpin;
1937
1938 i915_gem_object_pin_fence(obj);
1939
1940 dev_priv->mm.interruptible = true;
1941 return 0;
1942
1943 err_unpin:
1944 i915_gem_object_unpin(obj);
1945 err_interruptible:
1946 dev_priv->mm.interruptible = true;
1947 return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
1962 {
1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968
1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
1981 }
1982
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
1985 {
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
1990 struct drm_i915_gem_object *obj;
1991 int plane = intel_crtc->plane;
1992 unsigned long linear_offset;
1993 u32 dspcntr;
1994 u32 reg;
1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
2007
2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
2019 break;
2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
2038 break;
2039 default:
2040 BUG();
2041 }
2042
2043 if (INTEL_INFO(dev)->gen >= 4) {
2044 if (obj->tiling_mode != I915_TILING_NONE)
2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
2050 I915_WRITE(reg, dspcntr);
2051
2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2053
2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
2061 intel_crtc->dspaddr_offset = linear_offset;
2062 }
2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067 if (INTEL_INFO(dev)->gen >= 4) {
2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
2072 } else
2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2074 POSTING_READ(reg);
2075
2076 return 0;
2077 }
2078
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081 {
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long linear_offset;
2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 case 2:
2096 break;
2097 default:
2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
2115 break;
2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
2131 break;
2132 default:
2133 BUG();
2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147 intel_crtc->dspaddr_offset =
2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
2151 linear_offset -= intel_crtc->dspaddr_offset;
2152
2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
2164 POSTING_READ(reg);
2165
2166 return 0;
2167 }
2168
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2170 static int
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173 {
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
2179 intel_increase_pllclock(crtc);
2180
2181 return dev_priv->display.update_plane(crtc, fb, x, y);
2182 }
2183
2184 void intel_display_handle_reset(struct drm_device *dev)
2185 {
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220 }
2221
2222 static int
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 {
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274 struct drm_framebuffer *fb)
2275 {
2276 struct drm_device *dev = crtc->dev;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279 struct drm_framebuffer *old_fb;
2280 int ret;
2281
2282 /* no fb bound */
2283 if (!fb) {
2284 DRM_ERROR("No FB bound\n");
2285 return 0;
2286 }
2287
2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
2292 return -EINVAL;
2293 }
2294
2295 mutex_lock(&dev->struct_mutex);
2296 ret = intel_pin_and_fence_fb_obj(dev,
2297 to_intel_framebuffer(fb)->obj,
2298 NULL);
2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
2301 DRM_ERROR("pin & fence failed\n");
2302 return ret;
2303 }
2304
2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2306 if (ret) {
2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308 mutex_unlock(&dev->struct_mutex);
2309 DRM_ERROR("failed to update base address\n");
2310 return ret;
2311 }
2312
2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
2315 crtc->x = x;
2316 crtc->y = y;
2317
2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2321 }
2322
2323 intel_update_fbc(dev);
2324 mutex_unlock(&dev->struct_mutex);
2325
2326 intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328 return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 if (IS_IVYBRIDGE(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348 }
2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
2410 int plane = intel_crtc->plane;
2411 u32 reg, temp, tries;
2412
2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
2425 udelay(150);
2426
2427 /* enable CPU FDI TX and PCH FDI RX */
2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
2443 udelay(150);
2444
2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450 reg = FDI_RX_IIR(pipe);
2451 for (tries = 0; tries < 5; tries++) {
2452 temp = I915_READ(reg);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458 break;
2459 }
2460 }
2461 if (tries == 5)
2462 DRM_ERROR("FDI train 1 fail!\n");
2463
2464 /* Train 2 */
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2470
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
2478 udelay(150);
2479
2480 reg = FDI_RX_IIR(pipe);
2481 for (tries = 0; tries < 5; tries++) {
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
2490 }
2491 if (tries == 5)
2492 DRM_ERROR("FDI train 2 fail!\n");
2493
2494 DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
2512 u32 reg, temp, i, retry;
2513
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(150);
2524
2525 /* enable CPU FDI TX and PCH FDI RX */
2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
2554 for (i = 0; i < 4; i++) {
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
2562 udelay(500);
2563
2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
2574 }
2575 if (retry < 5)
2576 break;
2577 }
2578 if (i == 4)
2579 DRM_ERROR("FDI train 1 fail!\n");
2580
2581 /* Train 2 */
2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
2591 I915_WRITE(reg, temp);
2592
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
2605 udelay(150);
2606
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
2615 udelay(500);
2616
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
2627 }
2628 if (retry < 5)
2629 break;
2630 }
2631 if (i == 4)
2632 DRM_ERROR("FDI train 2 fail!\n");
2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2669 temp |= FDI_COMPOSITE_SYNC;
2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2680 temp |= FDI_COMPOSITE_SYNC;
2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
2728 for (i = 0; i < 4; i++) {
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752 }
2753
2754 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2755 {
2756 struct drm_device *dev = intel_crtc->base.dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 int pipe = intel_crtc->pipe;
2759 u32 reg, temp;
2760
2761
2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
2778 udelay(200);
2779
2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
2787 udelay(100);
2788 }
2789 }
2790
2791 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792 {
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818 }
2819
2820 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821 {
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2846 }
2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871 }
2872
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874 {
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 unsigned long flags;
2879 bool pending;
2880
2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2883 return false;
2884
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889 return pending;
2890 }
2891
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893 {
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897 if (crtc->fb == NULL)
2898 return;
2899
2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2904
2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
2908 }
2909
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2912 {
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
2918 mutex_lock(&dev_priv->dpio_lock);
2919
2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2922 */
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928 SBI_SSCCTL_DISABLE,
2929 SBI_ICLK);
2930
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2933 auxdiv = 1;
2934 divsel = 0x41;
2935 phaseinc = 0x20;
2936 } else {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2941 * precision.
2942 */
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2950
2951 auxdiv = 0;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2954 }
2955
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 crtc->mode.clock,
2964 auxdiv,
2965 divsel,
2966 phasedir,
2967 phaseinc);
2968
2969 /* Program SSCDIVINTPHASE6 */
2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2978
2979 /* Program SSCAUXDIV */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2984
2985 /* Enable modulator and associated divider */
2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2987 temp &= ~SBI_SSCCTL_DISABLE;
2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2989
2990 /* Wait for initialization time */
2991 udelay(24);
2992
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2994
2995 mutex_unlock(&dev_priv->dpio_lock);
2996 }
2997
2998 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999 enum pipe pch_transcoder)
3000 {
3001 struct drm_device *dev = crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3004
3005 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006 I915_READ(HTOTAL(cpu_transcoder)));
3007 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008 I915_READ(HBLANK(cpu_transcoder)));
3009 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010 I915_READ(HSYNC(cpu_transcoder)));
3011
3012 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013 I915_READ(VTOTAL(cpu_transcoder)));
3014 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015 I915_READ(VBLANK(cpu_transcoder)));
3016 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017 I915_READ(VSYNC(cpu_transcoder)));
3018 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3020 }
3021
3022 /*
3023 * Enable PCH resources required for PCH ports:
3024 * - PCH PLLs
3025 * - FDI training & RX/TX
3026 * - update transcoder timings
3027 * - DP transcoding bits
3028 * - transcoder
3029 */
3030 static void ironlake_pch_enable(struct drm_crtc *crtc)
3031 {
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
3036 u32 reg, temp;
3037
3038 assert_pch_transcoder_disabled(dev_priv, pipe);
3039
3040 /* Write the TU size bits before fdi link training, so that error
3041 * detection works. */
3042 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
3045 /* For PCH output, training FDI link */
3046 dev_priv->display.fdi_link_train(crtc);
3047
3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3051 *
3052 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053 * unconditionally resets the pll - we need that to have the right LVDS
3054 * enable sequence. */
3055 ironlake_enable_pch_pll(intel_crtc);
3056
3057 if (HAS_PCH_CPT(dev)) {
3058 u32 sel;
3059
3060 temp = I915_READ(PCH_DPLL_SEL);
3061 switch (pipe) {
3062 default:
3063 case 0:
3064 temp |= TRANSA_DPLL_ENABLE;
3065 sel = TRANSA_DPLLB_SEL;
3066 break;
3067 case 1:
3068 temp |= TRANSB_DPLL_ENABLE;
3069 sel = TRANSB_DPLLB_SEL;
3070 break;
3071 case 2:
3072 temp |= TRANSC_DPLL_ENABLE;
3073 sel = TRANSC_DPLLB_SEL;
3074 break;
3075 }
3076 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077 temp |= sel;
3078 else
3079 temp &= ~sel;
3080 I915_WRITE(PCH_DPLL_SEL, temp);
3081 }
3082
3083 /* set transcoder timing, panel must allow it */
3084 assert_panel_unlocked(dev_priv, pipe);
3085 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3086
3087 intel_fdi_normal_train(crtc);
3088
3089 /* For PCH DP, enable TRANS_DP_CTL */
3090 if (HAS_PCH_CPT(dev) &&
3091 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3093 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3094 reg = TRANS_DP_CTL(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3097 TRANS_DP_SYNC_MASK |
3098 TRANS_DP_BPC_MASK);
3099 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100 TRANS_DP_ENH_FRAMING);
3101 temp |= bpc << 9; /* same format but at 11:9 */
3102
3103 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3104 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3105 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3106 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3107
3108 switch (intel_trans_dp_port_sel(crtc)) {
3109 case PCH_DP_B:
3110 temp |= TRANS_DP_PORT_SEL_B;
3111 break;
3112 case PCH_DP_C:
3113 temp |= TRANS_DP_PORT_SEL_C;
3114 break;
3115 case PCH_DP_D:
3116 temp |= TRANS_DP_PORT_SEL_D;
3117 break;
3118 default:
3119 BUG();
3120 }
3121
3122 I915_WRITE(reg, temp);
3123 }
3124
3125 ironlake_enable_pch_transcoder(dev_priv, pipe);
3126 }
3127
3128 static void lpt_pch_enable(struct drm_crtc *crtc)
3129 {
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3134
3135 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3136
3137 lpt_program_iclkip(crtc);
3138
3139 /* Set transcoder timing. */
3140 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3141
3142 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3143 }
3144
3145 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3146 {
3147 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3148
3149 if (pll == NULL)
3150 return;
3151
3152 if (pll->refcount == 0) {
3153 WARN(1, "bad PCH PLL refcount\n");
3154 return;
3155 }
3156
3157 --pll->refcount;
3158 intel_crtc->pch_pll = NULL;
3159 }
3160
3161 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3162 {
3163 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164 struct intel_pch_pll *pll;
3165 int i;
3166
3167 pll = intel_crtc->pch_pll;
3168 if (pll) {
3169 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171 goto prepare;
3172 }
3173
3174 if (HAS_PCH_IBX(dev_priv->dev)) {
3175 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176 i = intel_crtc->pipe;
3177 pll = &dev_priv->pch_plls[i];
3178
3179 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180 intel_crtc->base.base.id, pll->pll_reg);
3181
3182 goto found;
3183 }
3184
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187
3188 /* Only want to check enabled timings first */
3189 if (pll->refcount == 0)
3190 continue;
3191
3192 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193 fp == I915_READ(pll->fp0_reg)) {
3194 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195 intel_crtc->base.base.id,
3196 pll->pll_reg, pll->refcount, pll->active);
3197
3198 goto found;
3199 }
3200 }
3201
3202 /* Ok no matching timings, maybe there's a free one? */
3203 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204 pll = &dev_priv->pch_plls[i];
3205 if (pll->refcount == 0) {
3206 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207 intel_crtc->base.base.id, pll->pll_reg);
3208 goto found;
3209 }
3210 }
3211
3212 return NULL;
3213
3214 found:
3215 intel_crtc->pch_pll = pll;
3216 pll->refcount++;
3217 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3218 prepare: /* separate function? */
3219 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3220
3221 /* Wait for the clocks to stabilize before rewriting the regs */
3222 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3223 POSTING_READ(pll->pll_reg);
3224 udelay(150);
3225
3226 I915_WRITE(pll->fp0_reg, fp);
3227 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3228 pll->on = false;
3229 return pll;
3230 }
3231
3232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3233 {
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 int dslreg = PIPEDSL(pipe);
3236 u32 temp;
3237
3238 temp = I915_READ(dslreg);
3239 udelay(500);
3240 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241 if (wait_for(I915_READ(dslreg) != temp, 5))
3242 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3243 }
3244 }
3245
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3247 {
3248 struct drm_device *dev = crtc->base.dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int pipe = crtc->pipe;
3251
3252 if (crtc->config.pch_pfit.size) {
3253 /* Force use of hard-coded filter coefficients
3254 * as some pre-programmed values are broken,
3255 * e.g. x201.
3256 */
3257 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259 PF_PIPE_SEL_IVB(pipe));
3260 else
3261 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3264 }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272 struct intel_encoder *encoder;
3273 int pipe = intel_crtc->pipe;
3274 int plane = intel_crtc->plane;
3275 u32 temp;
3276
3277 WARN_ON(!crtc->enabled);
3278
3279 if (intel_crtc->active)
3280 return;
3281
3282 intel_crtc->active = true;
3283
3284 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
3287 intel_update_watermarks(dev);
3288
3289 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3290 temp = I915_READ(PCH_LVDS);
3291 if ((temp & LVDS_PORT_EN) == 0)
3292 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3293 }
3294
3295
3296 if (intel_crtc->config.has_pch_encoder) {
3297 /* Note: FDI PLL enabling _must_ be done before we enable the
3298 * cpu pipes, hence this is separate from all the other fdi/pch
3299 * enabling. */
3300 ironlake_fdi_pll_enable(intel_crtc);
3301 } else {
3302 assert_fdi_tx_disabled(dev_priv, pipe);
3303 assert_fdi_rx_disabled(dev_priv, pipe);
3304 }
3305
3306 for_each_encoder_on_crtc(dev, crtc, encoder)
3307 if (encoder->pre_enable)
3308 encoder->pre_enable(encoder);
3309
3310 /* Enable panel fitting for LVDS */
3311 ironlake_pfit_enable(intel_crtc);
3312
3313 /*
3314 * On ILK+ LUT must be loaded before the pipe is running but with
3315 * clocks enabled
3316 */
3317 intel_crtc_load_lut(crtc);
3318
3319 intel_enable_pipe(dev_priv, pipe,
3320 intel_crtc->config.has_pch_encoder);
3321 intel_enable_plane(dev_priv, plane, pipe);
3322
3323 if (intel_crtc->config.has_pch_encoder)
3324 ironlake_pch_enable(crtc);
3325
3326 mutex_lock(&dev->struct_mutex);
3327 intel_update_fbc(dev);
3328 mutex_unlock(&dev->struct_mutex);
3329
3330 intel_crtc_update_cursor(crtc, true);
3331
3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 encoder->enable(encoder);
3334
3335 if (HAS_PCH_CPT(dev))
3336 cpt_verify_modeset(dev, intel_crtc->pipe);
3337
3338 /*
3339 * There seems to be a race in PCH platform hw (at least on some
3340 * outputs) where an enabled pipe still completes any pageflip right
3341 * away (as if the pipe is off) instead of waiting for vblank. As soon
3342 * as the first vblank happend, everything works as expected. Hence just
3343 * wait for one vblank before returning to avoid strange things
3344 * happening.
3345 */
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
3347 }
3348
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 {
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
3357
3358 WARN_ON(!crtc->enabled);
3359
3360 if (intel_crtc->active)
3361 return;
3362
3363 intel_crtc->active = true;
3364
3365 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366 if (intel_crtc->config.has_pch_encoder)
3367 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368
3369 intel_update_watermarks(dev);
3370
3371 if (intel_crtc->config.has_pch_encoder)
3372 dev_priv->display.fdi_link_train(crtc);
3373
3374 for_each_encoder_on_crtc(dev, crtc, encoder)
3375 if (encoder->pre_enable)
3376 encoder->pre_enable(encoder);
3377
3378 intel_ddi_enable_pipe_clock(intel_crtc);
3379
3380 /* Enable panel fitting for eDP */
3381 ironlake_pfit_enable(intel_crtc);
3382
3383 /*
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3385 * clocks enabled
3386 */
3387 intel_crtc_load_lut(crtc);
3388
3389 intel_ddi_set_pipe_settings(crtc);
3390 intel_ddi_enable_transcoder_func(crtc);
3391
3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
3394 intel_enable_plane(dev_priv, plane, pipe);
3395
3396 if (intel_crtc->config.has_pch_encoder)
3397 lpt_pch_enable(crtc);
3398
3399 mutex_lock(&dev->struct_mutex);
3400 intel_update_fbc(dev);
3401 mutex_unlock(&dev->struct_mutex);
3402
3403 intel_crtc_update_cursor(crtc, true);
3404
3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->enable(encoder);
3407
3408 /*
3409 * There seems to be a race in PCH platform hw (at least on some
3410 * outputs) where an enabled pipe still completes any pageflip right
3411 * away (as if the pipe is off) instead of waiting for vblank. As soon
3412 * as the first vblank happend, everything works as expected. Hence just
3413 * wait for one vblank before returning to avoid strange things
3414 * happening.
3415 */
3416 intel_wait_for_vblank(dev, intel_crtc->pipe);
3417 }
3418
3419 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3420 {
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 struct intel_encoder *encoder;
3425 int pipe = intel_crtc->pipe;
3426 int plane = intel_crtc->plane;
3427 u32 reg, temp;
3428
3429
3430 if (!intel_crtc->active)
3431 return;
3432
3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
3435
3436 intel_crtc_wait_for_pending_flips(crtc);
3437 drm_vblank_off(dev, pipe);
3438 intel_crtc_update_cursor(crtc, false);
3439
3440 intel_disable_plane(dev_priv, plane, pipe);
3441
3442 if (dev_priv->cfb_plane == plane)
3443 intel_disable_fbc(dev);
3444
3445 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3446 intel_disable_pipe(dev_priv, pipe);
3447
3448 /* Disable PF */
3449 I915_WRITE(PF_CTL(pipe), 0);
3450 I915_WRITE(PF_WIN_SZ(pipe), 0);
3451
3452 for_each_encoder_on_crtc(dev, crtc, encoder)
3453 if (encoder->post_disable)
3454 encoder->post_disable(encoder);
3455
3456 ironlake_fdi_disable(crtc);
3457
3458 ironlake_disable_pch_transcoder(dev_priv, pipe);
3459 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3460
3461 if (HAS_PCH_CPT(dev)) {
3462 /* disable TRANS_DP_CTL */
3463 reg = TRANS_DP_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3466 temp |= TRANS_DP_PORT_SEL_NONE;
3467 I915_WRITE(reg, temp);
3468
3469 /* disable DPLL_SEL */
3470 temp = I915_READ(PCH_DPLL_SEL);
3471 switch (pipe) {
3472 case 0:
3473 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3474 break;
3475 case 1:
3476 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3477 break;
3478 case 2:
3479 /* C shares PLL A or B */
3480 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3481 break;
3482 default:
3483 BUG(); /* wtf */
3484 }
3485 I915_WRITE(PCH_DPLL_SEL, temp);
3486 }
3487
3488 /* disable PCH DPLL */
3489 intel_disable_pch_pll(intel_crtc);
3490
3491 ironlake_fdi_pll_disable(intel_crtc);
3492
3493 intel_crtc->active = false;
3494 intel_update_watermarks(dev);
3495
3496 mutex_lock(&dev->struct_mutex);
3497 intel_update_fbc(dev);
3498 mutex_unlock(&dev->struct_mutex);
3499 }
3500
3501 static void haswell_crtc_disable(struct drm_crtc *crtc)
3502 {
3503 struct drm_device *dev = crtc->dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506 struct intel_encoder *encoder;
3507 int pipe = intel_crtc->pipe;
3508 int plane = intel_crtc->plane;
3509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3510
3511 if (!intel_crtc->active)
3512 return;
3513
3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3516
3517 intel_crtc_wait_for_pending_flips(crtc);
3518 drm_vblank_off(dev, pipe);
3519 intel_crtc_update_cursor(crtc, false);
3520
3521 /* FBC must be disabled before disabling the plane on HSW. */
3522 if (dev_priv->cfb_plane == plane)
3523 intel_disable_fbc(dev);
3524
3525 intel_disable_plane(dev_priv, plane, pipe);
3526
3527 if (intel_crtc->config.has_pch_encoder)
3528 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3529 intel_disable_pipe(dev_priv, pipe);
3530
3531 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3532
3533 /* XXX: Once we have proper panel fitter state tracking implemented with
3534 * hardware state read/check support we should switch to only disable
3535 * the panel fitter when we know it's used. */
3536 if (intel_display_power_enabled(dev,
3537 POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
3538 I915_WRITE(PF_CTL(pipe), 0);
3539 I915_WRITE(PF_WIN_SZ(pipe), 0);
3540 }
3541
3542 intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
3548 if (intel_crtc->config.has_pch_encoder) {
3549 lpt_disable_pch_transcoder(dev_priv);
3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551 intel_ddi_fdi_disable(crtc);
3552 }
3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 intel_put_pch_pll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571
3572 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573 * start using it. */
3574 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575
3576 intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581 if (!enable && intel_crtc->overlay) {
3582 struct drm_device *dev = intel_crtc->base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 mutex_lock(&dev->struct_mutex);
3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
3589 mutex_unlock(&dev->struct_mutex);
3590 }
3591
3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3594 */
3595 }
3596
3597 /**
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3600 * plane.
3601 * This workaround avoids occasional blank screens when self refresh is
3602 * enabled.
3603 */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618 }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3628 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3629 return;
3630
3631 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3632 assert_pipe_disabled(dev_priv, crtc->pipe);
3633
3634 /*
3635 * Enable automatic panel scaling so that non-native modes
3636 * fill the screen. The panel fitter should only be
3637 * adjusted whilst the pipe is disabled, according to
3638 * register description and PRM.
3639 */
3640 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3641 pipe_config->gmch_pfit.control,
3642 pipe_config->gmch_pfit.pgm_ratios);
3643
3644 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3645 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3646
3647 /* Border color in case we don't scale up to the full screen. Black by
3648 * default, change to something else for debugging. */
3649 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3650 }
3651
3652 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3653 {
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 struct intel_encoder *encoder;
3658 int pipe = intel_crtc->pipe;
3659 int plane = intel_crtc->plane;
3660
3661 WARN_ON(!crtc->enabled);
3662
3663 if (intel_crtc->active)
3664 return;
3665
3666 intel_crtc->active = true;
3667 intel_update_watermarks(dev);
3668
3669 mutex_lock(&dev_priv->dpio_lock);
3670
3671 for_each_encoder_on_crtc(dev, crtc, encoder)
3672 if (encoder->pre_pll_enable)
3673 encoder->pre_pll_enable(encoder);
3674
3675 intel_enable_pll(dev_priv, pipe);
3676
3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 if (encoder->pre_enable)
3679 encoder->pre_enable(encoder);
3680
3681 /* VLV wants encoder enabling _before_ the pipe is up. */
3682 for_each_encoder_on_crtc(dev, crtc, encoder)
3683 encoder->enable(encoder);
3684
3685 /* Enable panel fitting for eDP */
3686 i9xx_pfit_enable(intel_crtc);
3687
3688 intel_enable_pipe(dev_priv, pipe, false);
3689 intel_enable_plane(dev_priv, plane, pipe);
3690
3691 intel_crtc_load_lut(crtc);
3692 intel_update_fbc(dev);
3693
3694 /* Give the overlay scaler a chance to enable if it's on this pipe */
3695 intel_crtc_dpms_overlay(intel_crtc, true);
3696 intel_crtc_update_cursor(crtc, true);
3697
3698 mutex_unlock(&dev_priv->dpio_lock);
3699 }
3700
3701 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3702 {
3703 struct drm_device *dev = crtc->dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3706 struct intel_encoder *encoder;
3707 int pipe = intel_crtc->pipe;
3708 int plane = intel_crtc->plane;
3709
3710 WARN_ON(!crtc->enabled);
3711
3712 if (intel_crtc->active)
3713 return;
3714
3715 intel_crtc->active = true;
3716 intel_update_watermarks(dev);
3717
3718 intel_enable_pll(dev_priv, pipe);
3719
3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->pre_enable)
3722 encoder->pre_enable(encoder);
3723
3724 /* Enable panel fitting for LVDS */
3725 i9xx_pfit_enable(intel_crtc);
3726
3727 intel_enable_pipe(dev_priv, pipe, false);
3728 intel_enable_plane(dev_priv, plane, pipe);
3729 if (IS_G4X(dev))
3730 g4x_fixup_plane(dev_priv, pipe);
3731
3732 intel_crtc_load_lut(crtc);
3733 intel_update_fbc(dev);
3734
3735 /* Give the overlay scaler a chance to enable if it's on this pipe */
3736 intel_crtc_dpms_overlay(intel_crtc, true);
3737 intel_crtc_update_cursor(crtc, true);
3738
3739 for_each_encoder_on_crtc(dev, crtc, encoder)
3740 encoder->enable(encoder);
3741 }
3742
3743 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3744 {
3745 struct drm_device *dev = crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 enum pipe pipe;
3748 uint32_t pctl = I915_READ(PFIT_CONTROL);
3749
3750 assert_pipe_disabled(dev_priv, crtc->pipe);
3751
3752 if (INTEL_INFO(dev)->gen >= 4)
3753 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3754 else
3755 pipe = PIPE_B;
3756
3757 if (pipe == crtc->pipe) {
3758 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3759 I915_WRITE(PFIT_CONTROL, 0);
3760 }
3761 }
3762
3763 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3764 {
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768 struct intel_encoder *encoder;
3769 int pipe = intel_crtc->pipe;
3770 int plane = intel_crtc->plane;
3771
3772 if (!intel_crtc->active)
3773 return;
3774
3775 for_each_encoder_on_crtc(dev, crtc, encoder)
3776 encoder->disable(encoder);
3777
3778 /* Give the overlay scaler a chance to disable if it's on this pipe */
3779 intel_crtc_wait_for_pending_flips(crtc);
3780 drm_vblank_off(dev, pipe);
3781 intel_crtc_dpms_overlay(intel_crtc, false);
3782 intel_crtc_update_cursor(crtc, false);
3783
3784 if (dev_priv->cfb_plane == plane)
3785 intel_disable_fbc(dev);
3786
3787 intel_disable_plane(dev_priv, plane, pipe);
3788 intel_disable_pipe(dev_priv, pipe);
3789
3790 i9xx_pfit_disable(intel_crtc);
3791
3792 for_each_encoder_on_crtc(dev, crtc, encoder)
3793 if (encoder->post_disable)
3794 encoder->post_disable(encoder);
3795
3796 intel_disable_pll(dev_priv, pipe);
3797
3798 intel_crtc->active = false;
3799 intel_update_fbc(dev);
3800 intel_update_watermarks(dev);
3801 }
3802
3803 static void i9xx_crtc_off(struct drm_crtc *crtc)
3804 {
3805 }
3806
3807 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3808 bool enabled)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_master_private *master_priv;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814
3815 if (!dev->primary->master)
3816 return;
3817
3818 master_priv = dev->primary->master->driver_priv;
3819 if (!master_priv->sarea_priv)
3820 return;
3821
3822 switch (pipe) {
3823 case 0:
3824 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3825 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3826 break;
3827 case 1:
3828 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3829 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3830 break;
3831 default:
3832 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3833 break;
3834 }
3835 }
3836
3837 /**
3838 * Sets the power management mode of the pipe and plane.
3839 */
3840 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3841 {
3842 struct drm_device *dev = crtc->dev;
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 struct intel_encoder *intel_encoder;
3845 bool enable = false;
3846
3847 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3848 enable |= intel_encoder->connectors_active;
3849
3850 if (enable)
3851 dev_priv->display.crtc_enable(crtc);
3852 else
3853 dev_priv->display.crtc_disable(crtc);
3854
3855 intel_crtc_update_sarea(crtc, enable);
3856 }
3857
3858 static void intel_crtc_disable(struct drm_crtc *crtc)
3859 {
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_connector *connector;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864
3865 /* crtc should still be enabled when we disable it. */
3866 WARN_ON(!crtc->enabled);
3867
3868 dev_priv->display.crtc_disable(crtc);
3869 intel_crtc->eld_vld = false;
3870 intel_crtc_update_sarea(crtc, false);
3871 dev_priv->display.off(crtc);
3872
3873 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3874 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3875
3876 if (crtc->fb) {
3877 mutex_lock(&dev->struct_mutex);
3878 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3879 mutex_unlock(&dev->struct_mutex);
3880 crtc->fb = NULL;
3881 }
3882
3883 /* Update computed state. */
3884 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3885 if (!connector->encoder || !connector->encoder->crtc)
3886 continue;
3887
3888 if (connector->encoder->crtc != crtc)
3889 continue;
3890
3891 connector->dpms = DRM_MODE_DPMS_OFF;
3892 to_intel_encoder(connector->encoder)->connectors_active = false;
3893 }
3894 }
3895
3896 void intel_modeset_disable(struct drm_device *dev)
3897 {
3898 struct drm_crtc *crtc;
3899
3900 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3901 if (crtc->enabled)
3902 intel_crtc_disable(crtc);
3903 }
3904 }
3905
3906 void intel_encoder_destroy(struct drm_encoder *encoder)
3907 {
3908 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3909
3910 drm_encoder_cleanup(encoder);
3911 kfree(intel_encoder);
3912 }
3913
3914 /* Simple dpms helper for encodres with just one connector, no cloning and only
3915 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3916 * state of the entire output pipe. */
3917 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3918 {
3919 if (mode == DRM_MODE_DPMS_ON) {
3920 encoder->connectors_active = true;
3921
3922 intel_crtc_update_dpms(encoder->base.crtc);
3923 } else {
3924 encoder->connectors_active = false;
3925
3926 intel_crtc_update_dpms(encoder->base.crtc);
3927 }
3928 }
3929
3930 /* Cross check the actual hw state with our own modeset state tracking (and it's
3931 * internal consistency). */
3932 static void intel_connector_check_state(struct intel_connector *connector)
3933 {
3934 if (connector->get_hw_state(connector)) {
3935 struct intel_encoder *encoder = connector->encoder;
3936 struct drm_crtc *crtc;
3937 bool encoder_enabled;
3938 enum pipe pipe;
3939
3940 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3941 connector->base.base.id,
3942 drm_get_connector_name(&connector->base));
3943
3944 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3945 "wrong connector dpms state\n");
3946 WARN(connector->base.encoder != &encoder->base,
3947 "active connector not linked to encoder\n");
3948 WARN(!encoder->connectors_active,
3949 "encoder->connectors_active not set\n");
3950
3951 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3952 WARN(!encoder_enabled, "encoder not enabled\n");
3953 if (WARN_ON(!encoder->base.crtc))
3954 return;
3955
3956 crtc = encoder->base.crtc;
3957
3958 WARN(!crtc->enabled, "crtc not enabled\n");
3959 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3960 WARN(pipe != to_intel_crtc(crtc)->pipe,
3961 "encoder active on the wrong pipe\n");
3962 }
3963 }
3964
3965 /* Even simpler default implementation, if there's really no special case to
3966 * consider. */
3967 void intel_connector_dpms(struct drm_connector *connector, int mode)
3968 {
3969 struct intel_encoder *encoder = intel_attached_encoder(connector);
3970
3971 /* All the simple cases only support two dpms states. */
3972 if (mode != DRM_MODE_DPMS_ON)
3973 mode = DRM_MODE_DPMS_OFF;
3974
3975 if (mode == connector->dpms)
3976 return;
3977
3978 connector->dpms = mode;
3979
3980 /* Only need to change hw state when actually enabled */
3981 if (encoder->base.crtc)
3982 intel_encoder_dpms(encoder, mode);
3983 else
3984 WARN_ON(encoder->connectors_active != false);
3985
3986 intel_modeset_check_state(connector->dev);
3987 }
3988
3989 /* Simple connector->get_hw_state implementation for encoders that support only
3990 * one connector and no cloning and hence the encoder state determines the state
3991 * of the connector. */
3992 bool intel_connector_get_hw_state(struct intel_connector *connector)
3993 {
3994 enum pipe pipe = 0;
3995 struct intel_encoder *encoder = connector->encoder;
3996
3997 return encoder->get_hw_state(encoder, &pipe);
3998 }
3999
4000 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4001 struct intel_crtc_config *pipe_config)
4002 {
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 struct intel_crtc *pipe_B_crtc =
4005 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4006
4007 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4008 pipe_name(pipe), pipe_config->fdi_lanes);
4009 if (pipe_config->fdi_lanes > 4) {
4010 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4011 pipe_name(pipe), pipe_config->fdi_lanes);
4012 return false;
4013 }
4014
4015 if (IS_HASWELL(dev)) {
4016 if (pipe_config->fdi_lanes > 2) {
4017 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4018 pipe_config->fdi_lanes);
4019 return false;
4020 } else {
4021 return true;
4022 }
4023 }
4024
4025 if (INTEL_INFO(dev)->num_pipes == 2)
4026 return true;
4027
4028 /* Ivybridge 3 pipe is really complicated */
4029 switch (pipe) {
4030 case PIPE_A:
4031 return true;
4032 case PIPE_B:
4033 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4034 pipe_config->fdi_lanes > 2) {
4035 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4036 pipe_name(pipe), pipe_config->fdi_lanes);
4037 return false;
4038 }
4039 return true;
4040 case PIPE_C:
4041 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4042 pipe_B_crtc->config.fdi_lanes <= 2) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4045 pipe_name(pipe), pipe_config->fdi_lanes);
4046 return false;
4047 }
4048 } else {
4049 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4050 return false;
4051 }
4052 return true;
4053 default:
4054 BUG();
4055 }
4056 }
4057
4058 #define RETRY 1
4059 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4060 struct intel_crtc_config *pipe_config)
4061 {
4062 struct drm_device *dev = intel_crtc->base.dev;
4063 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4064 int target_clock, lane, link_bw;
4065 bool setup_ok, needs_recompute = false;
4066
4067 retry:
4068 /* FDI is a binary signal running at ~2.7GHz, encoding
4069 * each output octet as 10 bits. The actual frequency
4070 * is stored as a divider into a 100MHz clock, and the
4071 * mode pixel clock is stored in units of 1KHz.
4072 * Hence the bw of each lane in terms of the mode signal
4073 * is:
4074 */
4075 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4076
4077 if (pipe_config->pixel_target_clock)
4078 target_clock = pipe_config->pixel_target_clock;
4079 else
4080 target_clock = adjusted_mode->clock;
4081
4082 lane = ironlake_get_lanes_required(target_clock, link_bw,
4083 pipe_config->pipe_bpp);
4084
4085 pipe_config->fdi_lanes = lane;
4086
4087 if (pipe_config->pixel_multiplier > 1)
4088 link_bw *= pipe_config->pixel_multiplier;
4089 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4090 link_bw, &pipe_config->fdi_m_n);
4091
4092 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4093 intel_crtc->pipe, pipe_config);
4094 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4095 pipe_config->pipe_bpp -= 2*3;
4096 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4097 pipe_config->pipe_bpp);
4098 needs_recompute = true;
4099 pipe_config->bw_constrained = true;
4100
4101 goto retry;
4102 }
4103
4104 if (needs_recompute)
4105 return RETRY;
4106
4107 return setup_ok ? 0 : -EINVAL;
4108 }
4109
4110 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4111 struct intel_crtc_config *pipe_config)
4112 {
4113 struct drm_device *dev = crtc->dev;
4114 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4115
4116 if (HAS_PCH_SPLIT(dev)) {
4117 /* FDI link clock is fixed at 2.7G */
4118 if (pipe_config->requested_mode.clock * 3
4119 > IRONLAKE_FDI_FREQ * 4)
4120 return -EINVAL;
4121 }
4122
4123 /* All interlaced capable intel hw wants timings in frames. Note though
4124 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4125 * timings, so we need to be careful not to clobber these.*/
4126 if (!pipe_config->timings_set)
4127 drm_mode_set_crtcinfo(adjusted_mode, 0);
4128
4129 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4130 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4131 */
4132 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4133 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4134 return -EINVAL;
4135
4136 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4137 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4138 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4139 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4140 * for lvds. */
4141 pipe_config->pipe_bpp = 8*3;
4142 }
4143
4144 if (pipe_config->has_pch_encoder)
4145 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4146
4147 return 0;
4148 }
4149
4150 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4151 {
4152 return 400000; /* FIXME */
4153 }
4154
4155 static int i945_get_display_clock_speed(struct drm_device *dev)
4156 {
4157 return 400000;
4158 }
4159
4160 static int i915_get_display_clock_speed(struct drm_device *dev)
4161 {
4162 return 333000;
4163 }
4164
4165 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4166 {
4167 return 200000;
4168 }
4169
4170 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4171 {
4172 u16 gcfgc = 0;
4173
4174 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4175
4176 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4177 return 133000;
4178 else {
4179 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4180 case GC_DISPLAY_CLOCK_333_MHZ:
4181 return 333000;
4182 default:
4183 case GC_DISPLAY_CLOCK_190_200_MHZ:
4184 return 190000;
4185 }
4186 }
4187 }
4188
4189 static int i865_get_display_clock_speed(struct drm_device *dev)
4190 {
4191 return 266000;
4192 }
4193
4194 static int i855_get_display_clock_speed(struct drm_device *dev)
4195 {
4196 u16 hpllcc = 0;
4197 /* Assume that the hardware is in the high speed state. This
4198 * should be the default.
4199 */
4200 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4201 case GC_CLOCK_133_200:
4202 case GC_CLOCK_100_200:
4203 return 200000;
4204 case GC_CLOCK_166_250:
4205 return 250000;
4206 case GC_CLOCK_100_133:
4207 return 133000;
4208 }
4209
4210 /* Shouldn't happen */
4211 return 0;
4212 }
4213
4214 static int i830_get_display_clock_speed(struct drm_device *dev)
4215 {
4216 return 133000;
4217 }
4218
4219 static void
4220 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4221 {
4222 while (*num > 0xffffff || *den > 0xffffff) {
4223 *num >>= 1;
4224 *den >>= 1;
4225 }
4226 }
4227
4228 void
4229 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4230 int pixel_clock, int link_clock,
4231 struct intel_link_m_n *m_n)
4232 {
4233 m_n->tu = 64;
4234 m_n->gmch_m = bits_per_pixel * pixel_clock;
4235 m_n->gmch_n = link_clock * nlanes * 8;
4236 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4237 m_n->link_m = pixel_clock;
4238 m_n->link_n = link_clock;
4239 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4240 }
4241
4242 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4243 {
4244 if (i915_panel_use_ssc >= 0)
4245 return i915_panel_use_ssc != 0;
4246 return dev_priv->vbt.lvds_use_ssc
4247 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4248 }
4249
4250 static int vlv_get_refclk(struct drm_crtc *crtc)
4251 {
4252 struct drm_device *dev = crtc->dev;
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 int refclk = 27000; /* for DP & HDMI */
4255
4256 return 100000; /* only one validated so far */
4257
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4259 refclk = 96000;
4260 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4261 if (intel_panel_use_ssc(dev_priv))
4262 refclk = 100000;
4263 else
4264 refclk = 96000;
4265 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4266 refclk = 100000;
4267 }
4268
4269 return refclk;
4270 }
4271
4272 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4273 {
4274 struct drm_device *dev = crtc->dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276 int refclk;
4277
4278 if (IS_VALLEYVIEW(dev)) {
4279 refclk = vlv_get_refclk(crtc);
4280 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4281 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4282 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4283 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4284 refclk / 1000);
4285 } else if (!IS_GEN2(dev)) {
4286 refclk = 96000;
4287 } else {
4288 refclk = 48000;
4289 }
4290
4291 return refclk;
4292 }
4293
4294 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4295 {
4296 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4297 }
4298
4299 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4300 {
4301 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4302 }
4303
4304 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4305 intel_clock_t *reduced_clock)
4306 {
4307 struct drm_device *dev = crtc->base.dev;
4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309 int pipe = crtc->pipe;
4310 u32 fp, fp2 = 0;
4311
4312 if (IS_PINEVIEW(dev)) {
4313 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4314 if (reduced_clock)
4315 fp2 = pnv_dpll_compute_fp(reduced_clock);
4316 } else {
4317 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4318 if (reduced_clock)
4319 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4320 }
4321
4322 I915_WRITE(FP0(pipe), fp);
4323
4324 crtc->lowfreq_avail = false;
4325 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4326 reduced_clock && i915_powersave) {
4327 I915_WRITE(FP1(pipe), fp2);
4328 crtc->lowfreq_avail = true;
4329 } else {
4330 I915_WRITE(FP1(pipe), fp);
4331 }
4332 }
4333
4334 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4335 {
4336 u32 reg_val;
4337
4338 /*
4339 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4340 * and set it to a reasonable value instead.
4341 */
4342 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4343 reg_val &= 0xffffff00;
4344 reg_val |= 0x00000030;
4345 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4346
4347 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4348 reg_val &= 0x8cffffff;
4349 reg_val = 0x8c000000;
4350 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4351
4352 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4353 reg_val &= 0xffffff00;
4354 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4355
4356 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4357 reg_val &= 0x00ffffff;
4358 reg_val |= 0xb0000000;
4359 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4360 }
4361
4362 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4363 struct intel_link_m_n *m_n)
4364 {
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
4368
4369 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4370 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4371 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4372 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4373 }
4374
4375 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4376 struct intel_link_m_n *m_n)
4377 {
4378 struct drm_device *dev = crtc->base.dev;
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 int pipe = crtc->pipe;
4381 enum transcoder transcoder = crtc->config.cpu_transcoder;
4382
4383 if (INTEL_INFO(dev)->gen >= 5) {
4384 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4385 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4386 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4387 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4388 } else {
4389 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4390 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4391 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4392 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4393 }
4394 }
4395
4396 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4397 {
4398 if (crtc->config.has_pch_encoder)
4399 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4400 else
4401 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4402 }
4403
4404 static void vlv_update_pll(struct intel_crtc *crtc)
4405 {
4406 struct drm_device *dev = crtc->base.dev;
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 struct drm_display_mode *adjusted_mode =
4409 &crtc->config.adjusted_mode;
4410 struct intel_encoder *encoder;
4411 int pipe = crtc->pipe;
4412 u32 dpll, mdiv;
4413 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4414 bool is_hdmi;
4415 u32 coreclk, reg_val, dpll_md;
4416
4417 mutex_lock(&dev_priv->dpio_lock);
4418
4419 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4420
4421 bestn = crtc->config.dpll.n;
4422 bestm1 = crtc->config.dpll.m1;
4423 bestm2 = crtc->config.dpll.m2;
4424 bestp1 = crtc->config.dpll.p1;
4425 bestp2 = crtc->config.dpll.p2;
4426
4427 /* See eDP HDMI DPIO driver vbios notes doc */
4428
4429 /* PLL B needs special handling */
4430 if (pipe)
4431 vlv_pllb_recal_opamp(dev_priv);
4432
4433 /* Set up Tx target for periodic Rcomp update */
4434 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4435
4436 /* Disable target IRef on PLL */
4437 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4438 reg_val &= 0x00ffffff;
4439 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4440
4441 /* Disable fast lock */
4442 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4443
4444 /* Set idtafcrecal before PLL is enabled */
4445 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4446 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4447 mdiv |= ((bestn << DPIO_N_SHIFT));
4448 mdiv |= (1 << DPIO_K_SHIFT);
4449
4450 /*
4451 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4452 * but we don't support that).
4453 * Note: don't use the DAC post divider as it seems unstable.
4454 */
4455 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4456 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4457
4458 mdiv |= DPIO_ENABLE_CALIBRATION;
4459 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4460
4461 /* Set HBR and RBR LPF coefficients */
4462 if (adjusted_mode->clock == 162000 ||
4463 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4464 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4465 0x005f0021);
4466 else
4467 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4468 0x00d0000f);
4469
4470 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4471 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4472 /* Use SSC source */
4473 if (!pipe)
4474 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4475 0x0df40000);
4476 else
4477 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4478 0x0df70000);
4479 } else { /* HDMI or VGA */
4480 /* Use bend source */
4481 if (!pipe)
4482 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4483 0x0df70000);
4484 else
4485 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4486 0x0df40000);
4487 }
4488
4489 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4490 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4492 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4493 coreclk |= 0x01000000;
4494 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4495
4496 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4497
4498 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4499 if (encoder->pre_pll_enable)
4500 encoder->pre_pll_enable(encoder);
4501
4502 /* Enable DPIO clock input */
4503 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4504 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4505 if (pipe)
4506 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4507
4508 dpll |= DPLL_VCO_ENABLE;
4509 I915_WRITE(DPLL(pipe), dpll);
4510 POSTING_READ(DPLL(pipe));
4511 udelay(150);
4512
4513 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4514 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4515
4516 dpll_md = 0;
4517 if (crtc->config.pixel_multiplier > 1) {
4518 dpll_md = (crtc->config.pixel_multiplier - 1)
4519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4520 }
4521 I915_WRITE(DPLL_MD(pipe), dpll_md);
4522 POSTING_READ(DPLL_MD(pipe));
4523
4524 if (crtc->config.has_dp_encoder)
4525 intel_dp_set_m_n(crtc);
4526
4527 mutex_unlock(&dev_priv->dpio_lock);
4528 }
4529
4530 static void i9xx_update_pll(struct intel_crtc *crtc,
4531 intel_clock_t *reduced_clock,
4532 int num_connectors)
4533 {
4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct intel_encoder *encoder;
4537 int pipe = crtc->pipe;
4538 u32 dpll;
4539 bool is_sdvo;
4540 struct dpll *clock = &crtc->config.dpll;
4541
4542 i9xx_update_pll_dividers(crtc, reduced_clock);
4543
4544 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4545 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4546
4547 dpll = DPLL_VGA_MODE_DIS;
4548
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4550 dpll |= DPLLB_MODE_LVDS;
4551 else
4552 dpll |= DPLLB_MODE_DAC_SERIAL;
4553
4554 if ((crtc->config.pixel_multiplier > 1) &&
4555 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4556 dpll |= (crtc->config.pixel_multiplier - 1)
4557 << SDVO_MULTIPLIER_SHIFT_HIRES;
4558 }
4559
4560 if (is_sdvo)
4561 dpll |= DPLL_DVO_HIGH_SPEED;
4562
4563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4564 dpll |= DPLL_DVO_HIGH_SPEED;
4565
4566 /* compute bitmask from p1 value */
4567 if (IS_PINEVIEW(dev))
4568 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4569 else {
4570 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4571 if (IS_G4X(dev) && reduced_clock)
4572 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4573 }
4574 switch (clock->p2) {
4575 case 5:
4576 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4577 break;
4578 case 7:
4579 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4580 break;
4581 case 10:
4582 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4583 break;
4584 case 14:
4585 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4586 break;
4587 }
4588 if (INTEL_INFO(dev)->gen >= 4)
4589 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4590
4591 if (crtc->config.sdvo_tv_clock)
4592 dpll |= PLL_REF_INPUT_TVCLKINBC;
4593 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4594 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4595 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4596 else
4597 dpll |= PLL_REF_INPUT_DREFCLK;
4598
4599 dpll |= DPLL_VCO_ENABLE;
4600 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4601 POSTING_READ(DPLL(pipe));
4602 udelay(150);
4603
4604 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4605 if (encoder->pre_pll_enable)
4606 encoder->pre_pll_enable(encoder);
4607
4608 if (crtc->config.has_dp_encoder)
4609 intel_dp_set_m_n(crtc);
4610
4611 I915_WRITE(DPLL(pipe), dpll);
4612
4613 /* Wait for the clocks to stabilize. */
4614 POSTING_READ(DPLL(pipe));
4615 udelay(150);
4616
4617 if (INTEL_INFO(dev)->gen >= 4) {
4618 u32 dpll_md = 0;
4619 if (crtc->config.pixel_multiplier > 1) {
4620 dpll_md = (crtc->config.pixel_multiplier - 1)
4621 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4622 }
4623 I915_WRITE(DPLL_MD(pipe), dpll_md);
4624 } else {
4625 /* The pixel multiplier can only be updated once the
4626 * DPLL is enabled and the clocks are stable.
4627 *
4628 * So write it again.
4629 */
4630 I915_WRITE(DPLL(pipe), dpll);
4631 }
4632 }
4633
4634 static void i8xx_update_pll(struct intel_crtc *crtc,
4635 struct drm_display_mode *adjusted_mode,
4636 intel_clock_t *reduced_clock,
4637 int num_connectors)
4638 {
4639 struct drm_device *dev = crtc->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_encoder *encoder;
4642 int pipe = crtc->pipe;
4643 u32 dpll;
4644 struct dpll *clock = &crtc->config.dpll;
4645
4646 i9xx_update_pll_dividers(crtc, reduced_clock);
4647
4648 dpll = DPLL_VGA_MODE_DIS;
4649
4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4651 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4652 } else {
4653 if (clock->p1 == 2)
4654 dpll |= PLL_P1_DIVIDE_BY_TWO;
4655 else
4656 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4657 if (clock->p2 == 4)
4658 dpll |= PLL_P2_DIVIDE_BY_4;
4659 }
4660
4661 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4662 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4663 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4664 else
4665 dpll |= PLL_REF_INPUT_DREFCLK;
4666
4667 dpll |= DPLL_VCO_ENABLE;
4668 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4669 POSTING_READ(DPLL(pipe));
4670 udelay(150);
4671
4672 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4673 if (encoder->pre_pll_enable)
4674 encoder->pre_pll_enable(encoder);
4675
4676 I915_WRITE(DPLL(pipe), dpll);
4677
4678 /* Wait for the clocks to stabilize. */
4679 POSTING_READ(DPLL(pipe));
4680 udelay(150);
4681
4682 /* The pixel multiplier can only be updated once the
4683 * DPLL is enabled and the clocks are stable.
4684 *
4685 * So write it again.
4686 */
4687 I915_WRITE(DPLL(pipe), dpll);
4688 }
4689
4690 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4691 struct drm_display_mode *mode,
4692 struct drm_display_mode *adjusted_mode)
4693 {
4694 struct drm_device *dev = intel_crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum pipe pipe = intel_crtc->pipe;
4697 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4698 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4699
4700 /* We need to be careful not to changed the adjusted mode, for otherwise
4701 * the hw state checker will get angry at the mismatch. */
4702 crtc_vtotal = adjusted_mode->crtc_vtotal;
4703 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4704
4705 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4706 /* the chip adds 2 halflines automatically */
4707 crtc_vtotal -= 1;
4708 crtc_vblank_end -= 1;
4709 vsyncshift = adjusted_mode->crtc_hsync_start
4710 - adjusted_mode->crtc_htotal / 2;
4711 } else {
4712 vsyncshift = 0;
4713 }
4714
4715 if (INTEL_INFO(dev)->gen > 3)
4716 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4717
4718 I915_WRITE(HTOTAL(cpu_transcoder),
4719 (adjusted_mode->crtc_hdisplay - 1) |
4720 ((adjusted_mode->crtc_htotal - 1) << 16));
4721 I915_WRITE(HBLANK(cpu_transcoder),
4722 (adjusted_mode->crtc_hblank_start - 1) |
4723 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4724 I915_WRITE(HSYNC(cpu_transcoder),
4725 (adjusted_mode->crtc_hsync_start - 1) |
4726 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4727
4728 I915_WRITE(VTOTAL(cpu_transcoder),
4729 (adjusted_mode->crtc_vdisplay - 1) |
4730 ((crtc_vtotal - 1) << 16));
4731 I915_WRITE(VBLANK(cpu_transcoder),
4732 (adjusted_mode->crtc_vblank_start - 1) |
4733 ((crtc_vblank_end - 1) << 16));
4734 I915_WRITE(VSYNC(cpu_transcoder),
4735 (adjusted_mode->crtc_vsync_start - 1) |
4736 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4737
4738 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4739 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4740 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4741 * bits. */
4742 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4743 (pipe == PIPE_B || pipe == PIPE_C))
4744 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4745
4746 /* pipesrc controls the size that is scaled from, which should
4747 * always be the user's requested size.
4748 */
4749 I915_WRITE(PIPESRC(pipe),
4750 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4751 }
4752
4753 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4754 struct intel_crtc_config *pipe_config)
4755 {
4756 struct drm_device *dev = crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4759 uint32_t tmp;
4760
4761 tmp = I915_READ(HTOTAL(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(HBLANK(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(HSYNC(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4770
4771 tmp = I915_READ(VTOTAL(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4774 tmp = I915_READ(VBLANK(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(VSYNC(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4780
4781 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4782 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4783 pipe_config->adjusted_mode.crtc_vtotal += 1;
4784 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4785 }
4786
4787 tmp = I915_READ(PIPESRC(crtc->pipe));
4788 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4789 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4790 }
4791
4792 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4793 {
4794 struct drm_device *dev = intel_crtc->base.dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 uint32_t pipeconf;
4797
4798 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4799
4800 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4801 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4802 * core speed.
4803 *
4804 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4805 * pipe == 0 check?
4806 */
4807 if (intel_crtc->config.requested_mode.clock >
4808 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4809 pipeconf |= PIPECONF_DOUBLE_WIDE;
4810 else
4811 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4812 }
4813
4814 /* only g4x and later have fancy bpc/dither controls */
4815 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4816 pipeconf &= ~(PIPECONF_BPC_MASK |
4817 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4818
4819 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4820 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4821 pipeconf |= PIPECONF_DITHER_EN |
4822 PIPECONF_DITHER_TYPE_SP;
4823
4824 switch (intel_crtc->config.pipe_bpp) {
4825 case 18:
4826 pipeconf |= PIPECONF_6BPC;
4827 break;
4828 case 24:
4829 pipeconf |= PIPECONF_8BPC;
4830 break;
4831 case 30:
4832 pipeconf |= PIPECONF_10BPC;
4833 break;
4834 default:
4835 /* Case prevented by intel_choose_pipe_bpp_dither. */
4836 BUG();
4837 }
4838 }
4839
4840 if (HAS_PIPE_CXSR(dev)) {
4841 if (intel_crtc->lowfreq_avail) {
4842 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4843 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4844 } else {
4845 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4846 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4847 }
4848 }
4849
4850 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4851 if (!IS_GEN2(dev) &&
4852 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4853 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4854 else
4855 pipeconf |= PIPECONF_PROGRESSIVE;
4856
4857 if (IS_VALLEYVIEW(dev)) {
4858 if (intel_crtc->config.limited_color_range)
4859 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4860 else
4861 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4862 }
4863
4864 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4865 POSTING_READ(PIPECONF(intel_crtc->pipe));
4866 }
4867
4868 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4869 int x, int y,
4870 struct drm_framebuffer *fb)
4871 {
4872 struct drm_device *dev = crtc->dev;
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875 struct drm_display_mode *adjusted_mode =
4876 &intel_crtc->config.adjusted_mode;
4877 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4878 int pipe = intel_crtc->pipe;
4879 int plane = intel_crtc->plane;
4880 int refclk, num_connectors = 0;
4881 intel_clock_t clock, reduced_clock;
4882 u32 dspcntr;
4883 bool ok, has_reduced_clock = false;
4884 bool is_lvds = false;
4885 struct intel_encoder *encoder;
4886 const intel_limit_t *limit;
4887 int ret;
4888
4889 for_each_encoder_on_crtc(dev, crtc, encoder) {
4890 switch (encoder->type) {
4891 case INTEL_OUTPUT_LVDS:
4892 is_lvds = true;
4893 break;
4894 }
4895
4896 num_connectors++;
4897 }
4898
4899 refclk = i9xx_get_refclk(crtc, num_connectors);
4900
4901 /*
4902 * Returns a set of divisors for the desired target clock with the given
4903 * refclk, or FALSE. The returned values represent the clock equation:
4904 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4905 */
4906 limit = intel_limit(crtc, refclk);
4907 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4908 &clock);
4909 if (!ok) {
4910 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4911 return -EINVAL;
4912 }
4913
4914 /* Ensure that the cursor is valid for the new mode before changing... */
4915 intel_crtc_update_cursor(crtc, true);
4916
4917 if (is_lvds && dev_priv->lvds_downclock_avail) {
4918 /*
4919 * Ensure we match the reduced clock's P to the target clock.
4920 * If the clocks don't match, we can't switch the display clock
4921 * by using the FP0/FP1. In such case we will disable the LVDS
4922 * downclock feature.
4923 */
4924 has_reduced_clock = limit->find_pll(limit, crtc,
4925 dev_priv->lvds_downclock,
4926 refclk,
4927 &clock,
4928 &reduced_clock);
4929 }
4930 /* Compat-code for transition, will disappear. */
4931 if (!intel_crtc->config.clock_set) {
4932 intel_crtc->config.dpll.n = clock.n;
4933 intel_crtc->config.dpll.m1 = clock.m1;
4934 intel_crtc->config.dpll.m2 = clock.m2;
4935 intel_crtc->config.dpll.p1 = clock.p1;
4936 intel_crtc->config.dpll.p2 = clock.p2;
4937 }
4938
4939 if (IS_GEN2(dev))
4940 i8xx_update_pll(intel_crtc, adjusted_mode,
4941 has_reduced_clock ? &reduced_clock : NULL,
4942 num_connectors);
4943 else if (IS_VALLEYVIEW(dev))
4944 vlv_update_pll(intel_crtc);
4945 else
4946 i9xx_update_pll(intel_crtc,
4947 has_reduced_clock ? &reduced_clock : NULL,
4948 num_connectors);
4949
4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
4953 if (!IS_VALLEYVIEW(dev)) {
4954 if (pipe == 0)
4955 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4956 else
4957 dspcntr |= DISPPLANE_SEL_PIPE_B;
4958 }
4959
4960 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4961 drm_mode_debug_printmodeline(mode);
4962
4963 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4964
4965 /* pipesrc and dspsize control the size that is scaled from,
4966 * which should always be the user's requested size.
4967 */
4968 I915_WRITE(DSPSIZE(plane),
4969 ((mode->vdisplay - 1) << 16) |
4970 (mode->hdisplay - 1));
4971 I915_WRITE(DSPPOS(plane), 0);
4972
4973 i9xx_set_pipeconf(intel_crtc);
4974
4975 I915_WRITE(DSPCNTR(plane), dspcntr);
4976 POSTING_READ(DSPCNTR(plane));
4977
4978 ret = intel_pipe_set_base(crtc, x, y, fb);
4979
4980 intel_update_watermarks(dev);
4981
4982 return ret;
4983 }
4984
4985 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4986 struct intel_crtc_config *pipe_config)
4987 {
4988 struct drm_device *dev = crtc->base.dev;
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 uint32_t tmp;
4991
4992 tmp = I915_READ(PIPECONF(crtc->pipe));
4993 if (!(tmp & PIPECONF_ENABLE))
4994 return false;
4995
4996 intel_get_pipe_timings(crtc, pipe_config);
4997
4998 return true;
4999 }
5000
5001 static void ironlake_init_pch_refclk(struct drm_device *dev)
5002 {
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 struct drm_mode_config *mode_config = &dev->mode_config;
5005 struct intel_encoder *encoder;
5006 u32 val, final;
5007 bool has_lvds = false;
5008 bool has_cpu_edp = false;
5009 bool has_panel = false;
5010 bool has_ck505 = false;
5011 bool can_ssc = false;
5012
5013 /* We need to take the global config into account */
5014 list_for_each_entry(encoder, &mode_config->encoder_list,
5015 base.head) {
5016 switch (encoder->type) {
5017 case INTEL_OUTPUT_LVDS:
5018 has_panel = true;
5019 has_lvds = true;
5020 break;
5021 case INTEL_OUTPUT_EDP:
5022 has_panel = true;
5023 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5024 has_cpu_edp = true;
5025 break;
5026 }
5027 }
5028
5029 if (HAS_PCH_IBX(dev)) {
5030 has_ck505 = dev_priv->vbt.display_clock_mode;
5031 can_ssc = has_ck505;
5032 } else {
5033 has_ck505 = false;
5034 can_ssc = true;
5035 }
5036
5037 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5038 has_panel, has_lvds, has_ck505);
5039
5040 /* Ironlake: try to setup display ref clock before DPLL
5041 * enabling. This is only under driver's control after
5042 * PCH B stepping, previous chipset stepping should be
5043 * ignoring this setting.
5044 */
5045 val = I915_READ(PCH_DREF_CONTROL);
5046
5047 /* As we must carefully and slowly disable/enable each source in turn,
5048 * compute the final state we want first and check if we need to
5049 * make any changes at all.
5050 */
5051 final = val;
5052 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5053 if (has_ck505)
5054 final |= DREF_NONSPREAD_CK505_ENABLE;
5055 else
5056 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5057
5058 final &= ~DREF_SSC_SOURCE_MASK;
5059 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5060 final &= ~DREF_SSC1_ENABLE;
5061
5062 if (has_panel) {
5063 final |= DREF_SSC_SOURCE_ENABLE;
5064
5065 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5066 final |= DREF_SSC1_ENABLE;
5067
5068 if (has_cpu_edp) {
5069 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5070 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5071 else
5072 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5073 } else
5074 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5075 } else {
5076 final |= DREF_SSC_SOURCE_DISABLE;
5077 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5078 }
5079
5080 if (final == val)
5081 return;
5082
5083 /* Always enable nonspread source */
5084 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5085
5086 if (has_ck505)
5087 val |= DREF_NONSPREAD_CK505_ENABLE;
5088 else
5089 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5090
5091 if (has_panel) {
5092 val &= ~DREF_SSC_SOURCE_MASK;
5093 val |= DREF_SSC_SOURCE_ENABLE;
5094
5095 /* SSC must be turned on before enabling the CPU output */
5096 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5097 DRM_DEBUG_KMS("Using SSC on panel\n");
5098 val |= DREF_SSC1_ENABLE;
5099 } else
5100 val &= ~DREF_SSC1_ENABLE;
5101
5102 /* Get SSC going before enabling the outputs */
5103 I915_WRITE(PCH_DREF_CONTROL, val);
5104 POSTING_READ(PCH_DREF_CONTROL);
5105 udelay(200);
5106
5107 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5108
5109 /* Enable CPU source on CPU attached eDP */
5110 if (has_cpu_edp) {
5111 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5112 DRM_DEBUG_KMS("Using SSC on eDP\n");
5113 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5114 }
5115 else
5116 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5117 } else
5118 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119
5120 I915_WRITE(PCH_DREF_CONTROL, val);
5121 POSTING_READ(PCH_DREF_CONTROL);
5122 udelay(200);
5123 } else {
5124 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5125
5126 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5127
5128 /* Turn off CPU output */
5129 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5130
5131 I915_WRITE(PCH_DREF_CONTROL, val);
5132 POSTING_READ(PCH_DREF_CONTROL);
5133 udelay(200);
5134
5135 /* Turn off the SSC source */
5136 val &= ~DREF_SSC_SOURCE_MASK;
5137 val |= DREF_SSC_SOURCE_DISABLE;
5138
5139 /* Turn off SSC1 */
5140 val &= ~DREF_SSC1_ENABLE;
5141
5142 I915_WRITE(PCH_DREF_CONTROL, val);
5143 POSTING_READ(PCH_DREF_CONTROL);
5144 udelay(200);
5145 }
5146
5147 BUG_ON(val != final);
5148 }
5149
5150 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5151 static void lpt_init_pch_refclk(struct drm_device *dev)
5152 {
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 struct drm_mode_config *mode_config = &dev->mode_config;
5155 struct intel_encoder *encoder;
5156 bool has_vga = false;
5157 bool is_sdv = false;
5158 u32 tmp;
5159
5160 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5161 switch (encoder->type) {
5162 case INTEL_OUTPUT_ANALOG:
5163 has_vga = true;
5164 break;
5165 }
5166 }
5167
5168 if (!has_vga)
5169 return;
5170
5171 mutex_lock(&dev_priv->dpio_lock);
5172
5173 /* XXX: Rip out SDV support once Haswell ships for real. */
5174 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5175 is_sdv = true;
5176
5177 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5178 tmp &= ~SBI_SSCCTL_DISABLE;
5179 tmp |= SBI_SSCCTL_PATHALT;
5180 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5181
5182 udelay(24);
5183
5184 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5185 tmp &= ~SBI_SSCCTL_PATHALT;
5186 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5187
5188 if (!is_sdv) {
5189 tmp = I915_READ(SOUTH_CHICKEN2);
5190 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5191 I915_WRITE(SOUTH_CHICKEN2, tmp);
5192
5193 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5194 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5195 DRM_ERROR("FDI mPHY reset assert timeout\n");
5196
5197 tmp = I915_READ(SOUTH_CHICKEN2);
5198 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5199 I915_WRITE(SOUTH_CHICKEN2, tmp);
5200
5201 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5202 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5203 100))
5204 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5205 }
5206
5207 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5208 tmp &= ~(0xFF << 24);
5209 tmp |= (0x12 << 24);
5210 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5211
5212 if (is_sdv) {
5213 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5214 tmp |= 0x7FFF;
5215 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5216 }
5217
5218 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5219 tmp |= (1 << 11);
5220 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5221
5222 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5223 tmp |= (1 << 11);
5224 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5225
5226 if (is_sdv) {
5227 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5228 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5229 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5230
5231 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5232 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5233 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5234
5235 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5236 tmp |= (0x3F << 8);
5237 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5240 tmp |= (0x3F << 8);
5241 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5242 }
5243
5244 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5245 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5246 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5247
5248 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5249 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5250 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5251
5252 if (!is_sdv) {
5253 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5254 tmp &= ~(7 << 13);
5255 tmp |= (5 << 13);
5256 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5259 tmp &= ~(7 << 13);
5260 tmp |= (5 << 13);
5261 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5262 }
5263
5264 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5265 tmp &= ~0xFF;
5266 tmp |= 0x1C;
5267 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5270 tmp &= ~0xFF;
5271 tmp |= 0x1C;
5272 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5275 tmp &= ~(0xFF << 16);
5276 tmp |= (0x1C << 16);
5277 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5280 tmp &= ~(0xFF << 16);
5281 tmp |= (0x1C << 16);
5282 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5283
5284 if (!is_sdv) {
5285 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5286 tmp |= (1 << 27);
5287 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5290 tmp |= (1 << 27);
5291 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5294 tmp &= ~(0xF << 28);
5295 tmp |= (4 << 28);
5296 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5297
5298 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5299 tmp &= ~(0xF << 28);
5300 tmp |= (4 << 28);
5301 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5302 }
5303
5304 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5305 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5306 tmp |= SBI_DBUFF0_ENABLE;
5307 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5308
5309 mutex_unlock(&dev_priv->dpio_lock);
5310 }
5311
5312 /*
5313 * Initialize reference clocks when the driver loads
5314 */
5315 void intel_init_pch_refclk(struct drm_device *dev)
5316 {
5317 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5318 ironlake_init_pch_refclk(dev);
5319 else if (HAS_PCH_LPT(dev))
5320 lpt_init_pch_refclk(dev);
5321 }
5322
5323 static int ironlake_get_refclk(struct drm_crtc *crtc)
5324 {
5325 struct drm_device *dev = crtc->dev;
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327 struct intel_encoder *encoder;
5328 int num_connectors = 0;
5329 bool is_lvds = false;
5330
5331 for_each_encoder_on_crtc(dev, crtc, encoder) {
5332 switch (encoder->type) {
5333 case INTEL_OUTPUT_LVDS:
5334 is_lvds = true;
5335 break;
5336 }
5337 num_connectors++;
5338 }
5339
5340 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5341 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5342 dev_priv->vbt.lvds_ssc_freq);
5343 return dev_priv->vbt.lvds_ssc_freq * 1000;
5344 }
5345
5346 return 120000;
5347 }
5348
5349 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5350 {
5351 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353 int pipe = intel_crtc->pipe;
5354 uint32_t val;
5355
5356 val = I915_READ(PIPECONF(pipe));
5357
5358 val &= ~PIPECONF_BPC_MASK;
5359 switch (intel_crtc->config.pipe_bpp) {
5360 case 18:
5361 val |= PIPECONF_6BPC;
5362 break;
5363 case 24:
5364 val |= PIPECONF_8BPC;
5365 break;
5366 case 30:
5367 val |= PIPECONF_10BPC;
5368 break;
5369 case 36:
5370 val |= PIPECONF_12BPC;
5371 break;
5372 default:
5373 /* Case prevented by intel_choose_pipe_bpp_dither. */
5374 BUG();
5375 }
5376
5377 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5378 if (intel_crtc->config.dither)
5379 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5380
5381 val &= ~PIPECONF_INTERLACE_MASK;
5382 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5383 val |= PIPECONF_INTERLACED_ILK;
5384 else
5385 val |= PIPECONF_PROGRESSIVE;
5386
5387 if (intel_crtc->config.limited_color_range)
5388 val |= PIPECONF_COLOR_RANGE_SELECT;
5389 else
5390 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5391
5392 I915_WRITE(PIPECONF(pipe), val);
5393 POSTING_READ(PIPECONF(pipe));
5394 }
5395
5396 /*
5397 * Set up the pipe CSC unit.
5398 *
5399 * Currently only full range RGB to limited range RGB conversion
5400 * is supported, but eventually this should handle various
5401 * RGB<->YCbCr scenarios as well.
5402 */
5403 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5404 {
5405 struct drm_device *dev = crtc->dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408 int pipe = intel_crtc->pipe;
5409 uint16_t coeff = 0x7800; /* 1.0 */
5410
5411 /*
5412 * TODO: Check what kind of values actually come out of the pipe
5413 * with these coeff/postoff values and adjust to get the best
5414 * accuracy. Perhaps we even need to take the bpc value into
5415 * consideration.
5416 */
5417
5418 if (intel_crtc->config.limited_color_range)
5419 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5420
5421 /*
5422 * GY/GU and RY/RU should be the other way around according
5423 * to BSpec, but reality doesn't agree. Just set them up in
5424 * a way that results in the correct picture.
5425 */
5426 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5427 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5428
5429 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5430 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5431
5432 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5433 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5434
5435 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5436 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5437 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5438
5439 if (INTEL_INFO(dev)->gen > 6) {
5440 uint16_t postoff = 0;
5441
5442 if (intel_crtc->config.limited_color_range)
5443 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5444
5445 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5446 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5447 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5448
5449 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5450 } else {
5451 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5452
5453 if (intel_crtc->config.limited_color_range)
5454 mode |= CSC_BLACK_SCREEN_OFFSET;
5455
5456 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5457 }
5458 }
5459
5460 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5461 {
5462 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5465 uint32_t val;
5466
5467 val = I915_READ(PIPECONF(cpu_transcoder));
5468
5469 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5470 if (intel_crtc->config.dither)
5471 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5472
5473 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5474 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5475 val |= PIPECONF_INTERLACED_ILK;
5476 else
5477 val |= PIPECONF_PROGRESSIVE;
5478
5479 I915_WRITE(PIPECONF(cpu_transcoder), val);
5480 POSTING_READ(PIPECONF(cpu_transcoder));
5481 }
5482
5483 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5484 struct drm_display_mode *adjusted_mode,
5485 intel_clock_t *clock,
5486 bool *has_reduced_clock,
5487 intel_clock_t *reduced_clock)
5488 {
5489 struct drm_device *dev = crtc->dev;
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 struct intel_encoder *intel_encoder;
5492 int refclk;
5493 const intel_limit_t *limit;
5494 bool ret, is_lvds = false;
5495
5496 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5497 switch (intel_encoder->type) {
5498 case INTEL_OUTPUT_LVDS:
5499 is_lvds = true;
5500 break;
5501 }
5502 }
5503
5504 refclk = ironlake_get_refclk(crtc);
5505
5506 /*
5507 * Returns a set of divisors for the desired target clock with the given
5508 * refclk, or FALSE. The returned values represent the clock equation:
5509 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5510 */
5511 limit = intel_limit(crtc, refclk);
5512 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5513 clock);
5514 if (!ret)
5515 return false;
5516
5517 if (is_lvds && dev_priv->lvds_downclock_avail) {
5518 /*
5519 * Ensure we match the reduced clock's P to the target clock.
5520 * If the clocks don't match, we can't switch the display clock
5521 * by using the FP0/FP1. In such case we will disable the LVDS
5522 * downclock feature.
5523 */
5524 *has_reduced_clock = limit->find_pll(limit, crtc,
5525 dev_priv->lvds_downclock,
5526 refclk,
5527 clock,
5528 reduced_clock);
5529 }
5530
5531 return true;
5532 }
5533
5534 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5535 {
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537 uint32_t temp;
5538
5539 temp = I915_READ(SOUTH_CHICKEN1);
5540 if (temp & FDI_BC_BIFURCATION_SELECT)
5541 return;
5542
5543 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5544 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5545
5546 temp |= FDI_BC_BIFURCATION_SELECT;
5547 DRM_DEBUG_KMS("enabling fdi C rx\n");
5548 I915_WRITE(SOUTH_CHICKEN1, temp);
5549 POSTING_READ(SOUTH_CHICKEN1);
5550 }
5551
5552 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5553 {
5554 struct drm_device *dev = intel_crtc->base.dev;
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556
5557 switch (intel_crtc->pipe) {
5558 case PIPE_A:
5559 break;
5560 case PIPE_B:
5561 if (intel_crtc->config.fdi_lanes > 2)
5562 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5563 else
5564 cpt_enable_fdi_bc_bifurcation(dev);
5565
5566 break;
5567 case PIPE_C:
5568 cpt_enable_fdi_bc_bifurcation(dev);
5569
5570 break;
5571 default:
5572 BUG();
5573 }
5574 }
5575
5576 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5577 {
5578 /*
5579 * Account for spread spectrum to avoid
5580 * oversubscribing the link. Max center spread
5581 * is 2.5%; use 5% for safety's sake.
5582 */
5583 u32 bps = target_clock * bpp * 21 / 20;
5584 return bps / (link_bw * 8) + 1;
5585 }
5586
5587 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5588 {
5589 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5590 }
5591
5592 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5593 u32 *fp,
5594 intel_clock_t *reduced_clock, u32 *fp2)
5595 {
5596 struct drm_crtc *crtc = &intel_crtc->base;
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_encoder *intel_encoder;
5600 uint32_t dpll;
5601 int factor, num_connectors = 0;
5602 bool is_lvds = false, is_sdvo = false;
5603
5604 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5605 switch (intel_encoder->type) {
5606 case INTEL_OUTPUT_LVDS:
5607 is_lvds = true;
5608 break;
5609 case INTEL_OUTPUT_SDVO:
5610 case INTEL_OUTPUT_HDMI:
5611 is_sdvo = true;
5612 break;
5613 }
5614
5615 num_connectors++;
5616 }
5617
5618 /* Enable autotuning of the PLL clock (if permissible) */
5619 factor = 21;
5620 if (is_lvds) {
5621 if ((intel_panel_use_ssc(dev_priv) &&
5622 dev_priv->vbt.lvds_ssc_freq == 100) ||
5623 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5624 factor = 25;
5625 } else if (intel_crtc->config.sdvo_tv_clock)
5626 factor = 20;
5627
5628 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5629 *fp |= FP_CB_TUNE;
5630
5631 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5632 *fp2 |= FP_CB_TUNE;
5633
5634 dpll = 0;
5635
5636 if (is_lvds)
5637 dpll |= DPLLB_MODE_LVDS;
5638 else
5639 dpll |= DPLLB_MODE_DAC_SERIAL;
5640
5641 if (intel_crtc->config.pixel_multiplier > 1) {
5642 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5643 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5644 }
5645
5646 if (is_sdvo)
5647 dpll |= DPLL_DVO_HIGH_SPEED;
5648 if (intel_crtc->config.has_dp_encoder)
5649 dpll |= DPLL_DVO_HIGH_SPEED;
5650
5651 /* compute bitmask from p1 value */
5652 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5653 /* also FPA1 */
5654 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5655
5656 switch (intel_crtc->config.dpll.p2) {
5657 case 5:
5658 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5659 break;
5660 case 7:
5661 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5662 break;
5663 case 10:
5664 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5665 break;
5666 case 14:
5667 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5668 break;
5669 }
5670
5671 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5672 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5673 else
5674 dpll |= PLL_REF_INPUT_DREFCLK;
5675
5676 return dpll;
5677 }
5678
5679 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5680 int x, int y,
5681 struct drm_framebuffer *fb)
5682 {
5683 struct drm_device *dev = crtc->dev;
5684 struct drm_i915_private *dev_priv = dev->dev_private;
5685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5686 struct drm_display_mode *adjusted_mode =
5687 &intel_crtc->config.adjusted_mode;
5688 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5689 int pipe = intel_crtc->pipe;
5690 int plane = intel_crtc->plane;
5691 int num_connectors = 0;
5692 intel_clock_t clock, reduced_clock;
5693 u32 dpll = 0, fp = 0, fp2 = 0;
5694 bool ok, has_reduced_clock = false;
5695 bool is_lvds = false;
5696 struct intel_encoder *encoder;
5697 int ret;
5698
5699 for_each_encoder_on_crtc(dev, crtc, encoder) {
5700 switch (encoder->type) {
5701 case INTEL_OUTPUT_LVDS:
5702 is_lvds = true;
5703 break;
5704 }
5705
5706 num_connectors++;
5707 }
5708
5709 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5710 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5711
5712 intel_crtc->config.cpu_transcoder = pipe;
5713
5714 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5715 &has_reduced_clock, &reduced_clock);
5716 if (!ok) {
5717 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5718 return -EINVAL;
5719 }
5720 /* Compat-code for transition, will disappear. */
5721 if (!intel_crtc->config.clock_set) {
5722 intel_crtc->config.dpll.n = clock.n;
5723 intel_crtc->config.dpll.m1 = clock.m1;
5724 intel_crtc->config.dpll.m2 = clock.m2;
5725 intel_crtc->config.dpll.p1 = clock.p1;
5726 intel_crtc->config.dpll.p2 = clock.p2;
5727 }
5728
5729 /* Ensure that the cursor is valid for the new mode before changing... */
5730 intel_crtc_update_cursor(crtc, true);
5731
5732 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5733 drm_mode_debug_printmodeline(mode);
5734
5735 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5736 if (intel_crtc->config.has_pch_encoder) {
5737 struct intel_pch_pll *pll;
5738
5739 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5740 if (has_reduced_clock)
5741 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5742
5743 dpll = ironlake_compute_dpll(intel_crtc,
5744 &fp, &reduced_clock,
5745 has_reduced_clock ? &fp2 : NULL);
5746
5747 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5748 if (pll == NULL) {
5749 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5750 pipe_name(pipe));
5751 return -EINVAL;
5752 }
5753 } else
5754 intel_put_pch_pll(intel_crtc);
5755
5756 if (intel_crtc->config.has_dp_encoder)
5757 intel_dp_set_m_n(intel_crtc);
5758
5759 for_each_encoder_on_crtc(dev, crtc, encoder)
5760 if (encoder->pre_pll_enable)
5761 encoder->pre_pll_enable(encoder);
5762
5763 if (intel_crtc->pch_pll) {
5764 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5765
5766 /* Wait for the clocks to stabilize. */
5767 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5768 udelay(150);
5769
5770 /* The pixel multiplier can only be updated once the
5771 * DPLL is enabled and the clocks are stable.
5772 *
5773 * So write it again.
5774 */
5775 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5776 }
5777
5778 intel_crtc->lowfreq_avail = false;
5779 if (intel_crtc->pch_pll) {
5780 if (is_lvds && has_reduced_clock && i915_powersave) {
5781 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5782 intel_crtc->lowfreq_avail = true;
5783 } else {
5784 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5785 }
5786 }
5787
5788 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5789
5790 if (intel_crtc->config.has_pch_encoder) {
5791 intel_cpu_transcoder_set_m_n(intel_crtc,
5792 &intel_crtc->config.fdi_m_n);
5793 }
5794
5795 if (IS_IVYBRIDGE(dev))
5796 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5797
5798 ironlake_set_pipeconf(crtc);
5799
5800 /* Set up the display plane register */
5801 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5802 POSTING_READ(DSPCNTR(plane));
5803
5804 ret = intel_pipe_set_base(crtc, x, y, fb);
5805
5806 intel_update_watermarks(dev);
5807
5808 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5809
5810 return ret;
5811 }
5812
5813 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5814 struct intel_crtc_config *pipe_config)
5815 {
5816 struct drm_device *dev = crtc->base.dev;
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 enum transcoder transcoder = pipe_config->cpu_transcoder;
5819
5820 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5821 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5822 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5823 & ~TU_SIZE_MASK;
5824 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5825 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5826 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5827 }
5828
5829 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5830 struct intel_crtc_config *pipe_config)
5831 {
5832 struct drm_device *dev = crtc->base.dev;
5833 struct drm_i915_private *dev_priv = dev->dev_private;
5834 uint32_t tmp;
5835
5836 tmp = I915_READ(PIPECONF(crtc->pipe));
5837 if (!(tmp & PIPECONF_ENABLE))
5838 return false;
5839
5840 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5841 pipe_config->has_pch_encoder = true;
5842
5843 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5844 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5845 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5846
5847 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5848 }
5849
5850 intel_get_pipe_timings(crtc, pipe_config);
5851
5852 return true;
5853 }
5854
5855 static void haswell_modeset_global_resources(struct drm_device *dev)
5856 {
5857 bool enable = false;
5858 struct intel_crtc *crtc;
5859 struct intel_encoder *encoder;
5860
5861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5862 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5863 enable = true;
5864 /* XXX: Should check for edp transcoder here, but thanks to init
5865 * sequence that's not yet available. Just in case desktop eDP
5866 * on PORT D is possible on haswell, too. */
5867 /* Even the eDP panel fitter is outside the always-on well. */
5868 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5869 enable = true;
5870 }
5871
5872 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5873 base.head) {
5874 if (encoder->type != INTEL_OUTPUT_EDP &&
5875 encoder->connectors_active)
5876 enable = true;
5877 }
5878
5879 intel_set_power_well(dev, enable);
5880 }
5881
5882 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5883 int x, int y,
5884 struct drm_framebuffer *fb)
5885 {
5886 struct drm_device *dev = crtc->dev;
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889 struct drm_display_mode *adjusted_mode =
5890 &intel_crtc->config.adjusted_mode;
5891 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5892 int pipe = intel_crtc->pipe;
5893 int plane = intel_crtc->plane;
5894 int num_connectors = 0;
5895 bool is_cpu_edp = false;
5896 struct intel_encoder *encoder;
5897 int ret;
5898
5899 for_each_encoder_on_crtc(dev, crtc, encoder) {
5900 switch (encoder->type) {
5901 case INTEL_OUTPUT_EDP:
5902 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5903 is_cpu_edp = true;
5904 break;
5905 }
5906
5907 num_connectors++;
5908 }
5909
5910 if (is_cpu_edp)
5911 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5912 else
5913 intel_crtc->config.cpu_transcoder = pipe;
5914
5915 /* We are not sure yet this won't happen. */
5916 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5917 INTEL_PCH_TYPE(dev));
5918
5919 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5920 num_connectors, pipe_name(pipe));
5921
5922 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5923 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5924
5925 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5926
5927 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5928 return -EINVAL;
5929
5930 /* Ensure that the cursor is valid for the new mode before changing... */
5931 intel_crtc_update_cursor(crtc, true);
5932
5933 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5934 drm_mode_debug_printmodeline(mode);
5935
5936 if (intel_crtc->config.has_dp_encoder)
5937 intel_dp_set_m_n(intel_crtc);
5938
5939 intel_crtc->lowfreq_avail = false;
5940
5941 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5942
5943 if (intel_crtc->config.has_pch_encoder) {
5944 intel_cpu_transcoder_set_m_n(intel_crtc,
5945 &intel_crtc->config.fdi_m_n);
5946 }
5947
5948 haswell_set_pipeconf(crtc);
5949
5950 intel_set_pipe_csc(crtc);
5951
5952 /* Set up the display plane register */
5953 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5954 POSTING_READ(DSPCNTR(plane));
5955
5956 ret = intel_pipe_set_base(crtc, x, y, fb);
5957
5958 intel_update_watermarks(dev);
5959
5960 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5961
5962 return ret;
5963 }
5964
5965 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5966 struct intel_crtc_config *pipe_config)
5967 {
5968 struct drm_device *dev = crtc->base.dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5971 uint32_t tmp;
5972
5973 if (!intel_display_power_enabled(dev,
5974 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
5975 return false;
5976
5977 tmp = I915_READ(PIPECONF(cpu_transcoder));
5978 if (!(tmp & PIPECONF_ENABLE))
5979 return false;
5980
5981 /*
5982 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5983 * DDI E. So just check whether this pipe is wired to DDI E and whether
5984 * the PCH transcoder is on.
5985 */
5986 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
5987 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5988 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5989 pipe_config->has_pch_encoder = true;
5990
5991 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5992 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5993 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5994
5995 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5996 }
5997
5998 intel_get_pipe_timings(crtc, pipe_config);
5999
6000 return true;
6001 }
6002
6003 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6004 int x, int y,
6005 struct drm_framebuffer *fb)
6006 {
6007 struct drm_device *dev = crtc->dev;
6008 struct drm_i915_private *dev_priv = dev->dev_private;
6009 struct drm_encoder_helper_funcs *encoder_funcs;
6010 struct intel_encoder *encoder;
6011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6012 struct drm_display_mode *adjusted_mode =
6013 &intel_crtc->config.adjusted_mode;
6014 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6015 int pipe = intel_crtc->pipe;
6016 int ret;
6017
6018 drm_vblank_pre_modeset(dev, pipe);
6019
6020 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6021
6022 drm_vblank_post_modeset(dev, pipe);
6023
6024 if (ret != 0)
6025 return ret;
6026
6027 for_each_encoder_on_crtc(dev, crtc, encoder) {
6028 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6029 encoder->base.base.id,
6030 drm_get_encoder_name(&encoder->base),
6031 mode->base.id, mode->name);
6032 if (encoder->mode_set) {
6033 encoder->mode_set(encoder);
6034 } else {
6035 encoder_funcs = encoder->base.helper_private;
6036 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6037 }
6038 }
6039
6040 return 0;
6041 }
6042
6043 static bool intel_eld_uptodate(struct drm_connector *connector,
6044 int reg_eldv, uint32_t bits_eldv,
6045 int reg_elda, uint32_t bits_elda,
6046 int reg_edid)
6047 {
6048 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6049 uint8_t *eld = connector->eld;
6050 uint32_t i;
6051
6052 i = I915_READ(reg_eldv);
6053 i &= bits_eldv;
6054
6055 if (!eld[0])
6056 return !i;
6057
6058 if (!i)
6059 return false;
6060
6061 i = I915_READ(reg_elda);
6062 i &= ~bits_elda;
6063 I915_WRITE(reg_elda, i);
6064
6065 for (i = 0; i < eld[2]; i++)
6066 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6067 return false;
6068
6069 return true;
6070 }
6071
6072 static void g4x_write_eld(struct drm_connector *connector,
6073 struct drm_crtc *crtc)
6074 {
6075 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6076 uint8_t *eld = connector->eld;
6077 uint32_t eldv;
6078 uint32_t len;
6079 uint32_t i;
6080
6081 i = I915_READ(G4X_AUD_VID_DID);
6082
6083 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6084 eldv = G4X_ELDV_DEVCL_DEVBLC;
6085 else
6086 eldv = G4X_ELDV_DEVCTG;
6087
6088 if (intel_eld_uptodate(connector,
6089 G4X_AUD_CNTL_ST, eldv,
6090 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6091 G4X_HDMIW_HDMIEDID))
6092 return;
6093
6094 i = I915_READ(G4X_AUD_CNTL_ST);
6095 i &= ~(eldv | G4X_ELD_ADDR);
6096 len = (i >> 9) & 0x1f; /* ELD buffer size */
6097 I915_WRITE(G4X_AUD_CNTL_ST, i);
6098
6099 if (!eld[0])
6100 return;
6101
6102 len = min_t(uint8_t, eld[2], len);
6103 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6104 for (i = 0; i < len; i++)
6105 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6106
6107 i = I915_READ(G4X_AUD_CNTL_ST);
6108 i |= eldv;
6109 I915_WRITE(G4X_AUD_CNTL_ST, i);
6110 }
6111
6112 static void haswell_write_eld(struct drm_connector *connector,
6113 struct drm_crtc *crtc)
6114 {
6115 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6116 uint8_t *eld = connector->eld;
6117 struct drm_device *dev = crtc->dev;
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119 uint32_t eldv;
6120 uint32_t i;
6121 int len;
6122 int pipe = to_intel_crtc(crtc)->pipe;
6123 int tmp;
6124
6125 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6126 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6127 int aud_config = HSW_AUD_CFG(pipe);
6128 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6129
6130
6131 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6132
6133 /* Audio output enable */
6134 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6135 tmp = I915_READ(aud_cntrl_st2);
6136 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6137 I915_WRITE(aud_cntrl_st2, tmp);
6138
6139 /* Wait for 1 vertical blank */
6140 intel_wait_for_vblank(dev, pipe);
6141
6142 /* Set ELD valid state */
6143 tmp = I915_READ(aud_cntrl_st2);
6144 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6145 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6146 I915_WRITE(aud_cntrl_st2, tmp);
6147 tmp = I915_READ(aud_cntrl_st2);
6148 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6149
6150 /* Enable HDMI mode */
6151 tmp = I915_READ(aud_config);
6152 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6153 /* clear N_programing_enable and N_value_index */
6154 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6155 I915_WRITE(aud_config, tmp);
6156
6157 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6158
6159 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6160 intel_crtc->eld_vld = true;
6161
6162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6163 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6164 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6165 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6166 } else
6167 I915_WRITE(aud_config, 0);
6168
6169 if (intel_eld_uptodate(connector,
6170 aud_cntrl_st2, eldv,
6171 aud_cntl_st, IBX_ELD_ADDRESS,
6172 hdmiw_hdmiedid))
6173 return;
6174
6175 i = I915_READ(aud_cntrl_st2);
6176 i &= ~eldv;
6177 I915_WRITE(aud_cntrl_st2, i);
6178
6179 if (!eld[0])
6180 return;
6181
6182 i = I915_READ(aud_cntl_st);
6183 i &= ~IBX_ELD_ADDRESS;
6184 I915_WRITE(aud_cntl_st, i);
6185 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6186 DRM_DEBUG_DRIVER("port num:%d\n", i);
6187
6188 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6189 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6190 for (i = 0; i < len; i++)
6191 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6192
6193 i = I915_READ(aud_cntrl_st2);
6194 i |= eldv;
6195 I915_WRITE(aud_cntrl_st2, i);
6196
6197 }
6198
6199 static void ironlake_write_eld(struct drm_connector *connector,
6200 struct drm_crtc *crtc)
6201 {
6202 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6203 uint8_t *eld = connector->eld;
6204 uint32_t eldv;
6205 uint32_t i;
6206 int len;
6207 int hdmiw_hdmiedid;
6208 int aud_config;
6209 int aud_cntl_st;
6210 int aud_cntrl_st2;
6211 int pipe = to_intel_crtc(crtc)->pipe;
6212
6213 if (HAS_PCH_IBX(connector->dev)) {
6214 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6215 aud_config = IBX_AUD_CFG(pipe);
6216 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6217 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6218 } else {
6219 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6220 aud_config = CPT_AUD_CFG(pipe);
6221 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6222 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6223 }
6224
6225 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6226
6227 i = I915_READ(aud_cntl_st);
6228 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6229 if (!i) {
6230 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6231 /* operate blindly on all ports */
6232 eldv = IBX_ELD_VALIDB;
6233 eldv |= IBX_ELD_VALIDB << 4;
6234 eldv |= IBX_ELD_VALIDB << 8;
6235 } else {
6236 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6237 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6238 }
6239
6240 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6241 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6242 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6243 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6244 } else
6245 I915_WRITE(aud_config, 0);
6246
6247 if (intel_eld_uptodate(connector,
6248 aud_cntrl_st2, eldv,
6249 aud_cntl_st, IBX_ELD_ADDRESS,
6250 hdmiw_hdmiedid))
6251 return;
6252
6253 i = I915_READ(aud_cntrl_st2);
6254 i &= ~eldv;
6255 I915_WRITE(aud_cntrl_st2, i);
6256
6257 if (!eld[0])
6258 return;
6259
6260 i = I915_READ(aud_cntl_st);
6261 i &= ~IBX_ELD_ADDRESS;
6262 I915_WRITE(aud_cntl_st, i);
6263
6264 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6265 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6266 for (i = 0; i < len; i++)
6267 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6268
6269 i = I915_READ(aud_cntrl_st2);
6270 i |= eldv;
6271 I915_WRITE(aud_cntrl_st2, i);
6272 }
6273
6274 void intel_write_eld(struct drm_encoder *encoder,
6275 struct drm_display_mode *mode)
6276 {
6277 struct drm_crtc *crtc = encoder->crtc;
6278 struct drm_connector *connector;
6279 struct drm_device *dev = encoder->dev;
6280 struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282 connector = drm_select_eld(encoder, mode);
6283 if (!connector)
6284 return;
6285
6286 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6287 connector->base.id,
6288 drm_get_connector_name(connector),
6289 connector->encoder->base.id,
6290 drm_get_encoder_name(connector->encoder));
6291
6292 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6293
6294 if (dev_priv->display.write_eld)
6295 dev_priv->display.write_eld(connector, crtc);
6296 }
6297
6298 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6299 void intel_crtc_load_lut(struct drm_crtc *crtc)
6300 {
6301 struct drm_device *dev = crtc->dev;
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304 int palreg = PALETTE(intel_crtc->pipe);
6305 int i;
6306
6307 /* The clocks have to be on to load the palette. */
6308 if (!crtc->enabled || !intel_crtc->active)
6309 return;
6310
6311 /* use legacy palette for Ironlake */
6312 if (HAS_PCH_SPLIT(dev))
6313 palreg = LGC_PALETTE(intel_crtc->pipe);
6314
6315 for (i = 0; i < 256; i++) {
6316 I915_WRITE(palreg + 4 * i,
6317 (intel_crtc->lut_r[i] << 16) |
6318 (intel_crtc->lut_g[i] << 8) |
6319 intel_crtc->lut_b[i]);
6320 }
6321 }
6322
6323 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6324 {
6325 struct drm_device *dev = crtc->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 bool visible = base != 0;
6329 u32 cntl;
6330
6331 if (intel_crtc->cursor_visible == visible)
6332 return;
6333
6334 cntl = I915_READ(_CURACNTR);
6335 if (visible) {
6336 /* On these chipsets we can only modify the base whilst
6337 * the cursor is disabled.
6338 */
6339 I915_WRITE(_CURABASE, base);
6340
6341 cntl &= ~(CURSOR_FORMAT_MASK);
6342 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6343 cntl |= CURSOR_ENABLE |
6344 CURSOR_GAMMA_ENABLE |
6345 CURSOR_FORMAT_ARGB;
6346 } else
6347 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6348 I915_WRITE(_CURACNTR, cntl);
6349
6350 intel_crtc->cursor_visible = visible;
6351 }
6352
6353 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6354 {
6355 struct drm_device *dev = crtc->dev;
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 int pipe = intel_crtc->pipe;
6359 bool visible = base != 0;
6360
6361 if (intel_crtc->cursor_visible != visible) {
6362 uint32_t cntl = I915_READ(CURCNTR(pipe));
6363 if (base) {
6364 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6365 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6366 cntl |= pipe << 28; /* Connect to correct pipe */
6367 } else {
6368 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6369 cntl |= CURSOR_MODE_DISABLE;
6370 }
6371 I915_WRITE(CURCNTR(pipe), cntl);
6372
6373 intel_crtc->cursor_visible = visible;
6374 }
6375 /* and commit changes on next vblank */
6376 I915_WRITE(CURBASE(pipe), base);
6377 }
6378
6379 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6380 {
6381 struct drm_device *dev = crtc->dev;
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384 int pipe = intel_crtc->pipe;
6385 bool visible = base != 0;
6386
6387 if (intel_crtc->cursor_visible != visible) {
6388 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6389 if (base) {
6390 cntl &= ~CURSOR_MODE;
6391 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6392 } else {
6393 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6394 cntl |= CURSOR_MODE_DISABLE;
6395 }
6396 if (IS_HASWELL(dev))
6397 cntl |= CURSOR_PIPE_CSC_ENABLE;
6398 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6399
6400 intel_crtc->cursor_visible = visible;
6401 }
6402 /* and commit changes on next vblank */
6403 I915_WRITE(CURBASE_IVB(pipe), base);
6404 }
6405
6406 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6407 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6408 bool on)
6409 {
6410 struct drm_device *dev = crtc->dev;
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6413 int pipe = intel_crtc->pipe;
6414 int x = intel_crtc->cursor_x;
6415 int y = intel_crtc->cursor_y;
6416 u32 base, pos;
6417 bool visible;
6418
6419 pos = 0;
6420
6421 if (on && crtc->enabled && crtc->fb) {
6422 base = intel_crtc->cursor_addr;
6423 if (x > (int) crtc->fb->width)
6424 base = 0;
6425
6426 if (y > (int) crtc->fb->height)
6427 base = 0;
6428 } else
6429 base = 0;
6430
6431 if (x < 0) {
6432 if (x + intel_crtc->cursor_width < 0)
6433 base = 0;
6434
6435 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6436 x = -x;
6437 }
6438 pos |= x << CURSOR_X_SHIFT;
6439
6440 if (y < 0) {
6441 if (y + intel_crtc->cursor_height < 0)
6442 base = 0;
6443
6444 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6445 y = -y;
6446 }
6447 pos |= y << CURSOR_Y_SHIFT;
6448
6449 visible = base != 0;
6450 if (!visible && !intel_crtc->cursor_visible)
6451 return;
6452
6453 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6454 I915_WRITE(CURPOS_IVB(pipe), pos);
6455 ivb_update_cursor(crtc, base);
6456 } else {
6457 I915_WRITE(CURPOS(pipe), pos);
6458 if (IS_845G(dev) || IS_I865G(dev))
6459 i845_update_cursor(crtc, base);
6460 else
6461 i9xx_update_cursor(crtc, base);
6462 }
6463 }
6464
6465 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6466 struct drm_file *file,
6467 uint32_t handle,
6468 uint32_t width, uint32_t height)
6469 {
6470 struct drm_device *dev = crtc->dev;
6471 struct drm_i915_private *dev_priv = dev->dev_private;
6472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473 struct drm_i915_gem_object *obj;
6474 uint32_t addr;
6475 int ret;
6476
6477 /* if we want to turn off the cursor ignore width and height */
6478 if (!handle) {
6479 DRM_DEBUG_KMS("cursor off\n");
6480 addr = 0;
6481 obj = NULL;
6482 mutex_lock(&dev->struct_mutex);
6483 goto finish;
6484 }
6485
6486 /* Currently we only support 64x64 cursors */
6487 if (width != 64 || height != 64) {
6488 DRM_ERROR("we currently only support 64x64 cursors\n");
6489 return -EINVAL;
6490 }
6491
6492 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6493 if (&obj->base == NULL)
6494 return -ENOENT;
6495
6496 if (obj->base.size < width * height * 4) {
6497 DRM_ERROR("buffer is to small\n");
6498 ret = -ENOMEM;
6499 goto fail;
6500 }
6501
6502 /* we only need to pin inside GTT if cursor is non-phy */
6503 mutex_lock(&dev->struct_mutex);
6504 if (!dev_priv->info->cursor_needs_physical) {
6505 unsigned alignment;
6506
6507 if (obj->tiling_mode) {
6508 DRM_ERROR("cursor cannot be tiled\n");
6509 ret = -EINVAL;
6510 goto fail_locked;
6511 }
6512
6513 /* Note that the w/a also requires 2 PTE of padding following
6514 * the bo. We currently fill all unused PTE with the shadow
6515 * page and so we should always have valid PTE following the
6516 * cursor preventing the VT-d warning.
6517 */
6518 alignment = 0;
6519 if (need_vtd_wa(dev))
6520 alignment = 64*1024;
6521
6522 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6523 if (ret) {
6524 DRM_ERROR("failed to move cursor bo into the GTT\n");
6525 goto fail_locked;
6526 }
6527
6528 ret = i915_gem_object_put_fence(obj);
6529 if (ret) {
6530 DRM_ERROR("failed to release fence for cursor");
6531 goto fail_unpin;
6532 }
6533
6534 addr = obj->gtt_offset;
6535 } else {
6536 int align = IS_I830(dev) ? 16 * 1024 : 256;
6537 ret = i915_gem_attach_phys_object(dev, obj,
6538 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6539 align);
6540 if (ret) {
6541 DRM_ERROR("failed to attach phys object\n");
6542 goto fail_locked;
6543 }
6544 addr = obj->phys_obj->handle->busaddr;
6545 }
6546
6547 if (IS_GEN2(dev))
6548 I915_WRITE(CURSIZE, (height << 12) | width);
6549
6550 finish:
6551 if (intel_crtc->cursor_bo) {
6552 if (dev_priv->info->cursor_needs_physical) {
6553 if (intel_crtc->cursor_bo != obj)
6554 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6555 } else
6556 i915_gem_object_unpin(intel_crtc->cursor_bo);
6557 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6558 }
6559
6560 mutex_unlock(&dev->struct_mutex);
6561
6562 intel_crtc->cursor_addr = addr;
6563 intel_crtc->cursor_bo = obj;
6564 intel_crtc->cursor_width = width;
6565 intel_crtc->cursor_height = height;
6566
6567 intel_crtc_update_cursor(crtc, true);
6568
6569 return 0;
6570 fail_unpin:
6571 i915_gem_object_unpin(obj);
6572 fail_locked:
6573 mutex_unlock(&dev->struct_mutex);
6574 fail:
6575 drm_gem_object_unreference_unlocked(&obj->base);
6576 return ret;
6577 }
6578
6579 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6580 {
6581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6582
6583 intel_crtc->cursor_x = x;
6584 intel_crtc->cursor_y = y;
6585
6586 intel_crtc_update_cursor(crtc, true);
6587
6588 return 0;
6589 }
6590
6591 /** Sets the color ramps on behalf of RandR */
6592 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6593 u16 blue, int regno)
6594 {
6595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6596
6597 intel_crtc->lut_r[regno] = red >> 8;
6598 intel_crtc->lut_g[regno] = green >> 8;
6599 intel_crtc->lut_b[regno] = blue >> 8;
6600 }
6601
6602 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6603 u16 *blue, int regno)
6604 {
6605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606
6607 *red = intel_crtc->lut_r[regno] << 8;
6608 *green = intel_crtc->lut_g[regno] << 8;
6609 *blue = intel_crtc->lut_b[regno] << 8;
6610 }
6611
6612 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6613 u16 *blue, uint32_t start, uint32_t size)
6614 {
6615 int end = (start + size > 256) ? 256 : start + size, i;
6616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617
6618 for (i = start; i < end; i++) {
6619 intel_crtc->lut_r[i] = red[i] >> 8;
6620 intel_crtc->lut_g[i] = green[i] >> 8;
6621 intel_crtc->lut_b[i] = blue[i] >> 8;
6622 }
6623
6624 intel_crtc_load_lut(crtc);
6625 }
6626
6627 /* VESA 640x480x72Hz mode to set on the pipe */
6628 static struct drm_display_mode load_detect_mode = {
6629 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6630 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6631 };
6632
6633 static struct drm_framebuffer *
6634 intel_framebuffer_create(struct drm_device *dev,
6635 struct drm_mode_fb_cmd2 *mode_cmd,
6636 struct drm_i915_gem_object *obj)
6637 {
6638 struct intel_framebuffer *intel_fb;
6639 int ret;
6640
6641 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6642 if (!intel_fb) {
6643 drm_gem_object_unreference_unlocked(&obj->base);
6644 return ERR_PTR(-ENOMEM);
6645 }
6646
6647 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6648 if (ret) {
6649 drm_gem_object_unreference_unlocked(&obj->base);
6650 kfree(intel_fb);
6651 return ERR_PTR(ret);
6652 }
6653
6654 return &intel_fb->base;
6655 }
6656
6657 static u32
6658 intel_framebuffer_pitch_for_width(int width, int bpp)
6659 {
6660 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6661 return ALIGN(pitch, 64);
6662 }
6663
6664 static u32
6665 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6666 {
6667 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6668 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6669 }
6670
6671 static struct drm_framebuffer *
6672 intel_framebuffer_create_for_mode(struct drm_device *dev,
6673 struct drm_display_mode *mode,
6674 int depth, int bpp)
6675 {
6676 struct drm_i915_gem_object *obj;
6677 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6678
6679 obj = i915_gem_alloc_object(dev,
6680 intel_framebuffer_size_for_mode(mode, bpp));
6681 if (obj == NULL)
6682 return ERR_PTR(-ENOMEM);
6683
6684 mode_cmd.width = mode->hdisplay;
6685 mode_cmd.height = mode->vdisplay;
6686 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6687 bpp);
6688 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6689
6690 return intel_framebuffer_create(dev, &mode_cmd, obj);
6691 }
6692
6693 static struct drm_framebuffer *
6694 mode_fits_in_fbdev(struct drm_device *dev,
6695 struct drm_display_mode *mode)
6696 {
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 struct drm_i915_gem_object *obj;
6699 struct drm_framebuffer *fb;
6700
6701 if (dev_priv->fbdev == NULL)
6702 return NULL;
6703
6704 obj = dev_priv->fbdev->ifb.obj;
6705 if (obj == NULL)
6706 return NULL;
6707
6708 fb = &dev_priv->fbdev->ifb.base;
6709 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6710 fb->bits_per_pixel))
6711 return NULL;
6712
6713 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6714 return NULL;
6715
6716 return fb;
6717 }
6718
6719 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6720 struct drm_display_mode *mode,
6721 struct intel_load_detect_pipe *old)
6722 {
6723 struct intel_crtc *intel_crtc;
6724 struct intel_encoder *intel_encoder =
6725 intel_attached_encoder(connector);
6726 struct drm_crtc *possible_crtc;
6727 struct drm_encoder *encoder = &intel_encoder->base;
6728 struct drm_crtc *crtc = NULL;
6729 struct drm_device *dev = encoder->dev;
6730 struct drm_framebuffer *fb;
6731 int i = -1;
6732
6733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6734 connector->base.id, drm_get_connector_name(connector),
6735 encoder->base.id, drm_get_encoder_name(encoder));
6736
6737 /*
6738 * Algorithm gets a little messy:
6739 *
6740 * - if the connector already has an assigned crtc, use it (but make
6741 * sure it's on first)
6742 *
6743 * - try to find the first unused crtc that can drive this connector,
6744 * and use that if we find one
6745 */
6746
6747 /* See if we already have a CRTC for this connector */
6748 if (encoder->crtc) {
6749 crtc = encoder->crtc;
6750
6751 mutex_lock(&crtc->mutex);
6752
6753 old->dpms_mode = connector->dpms;
6754 old->load_detect_temp = false;
6755
6756 /* Make sure the crtc and connector are running */
6757 if (connector->dpms != DRM_MODE_DPMS_ON)
6758 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6759
6760 return true;
6761 }
6762
6763 /* Find an unused one (if possible) */
6764 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6765 i++;
6766 if (!(encoder->possible_crtcs & (1 << i)))
6767 continue;
6768 if (!possible_crtc->enabled) {
6769 crtc = possible_crtc;
6770 break;
6771 }
6772 }
6773
6774 /*
6775 * If we didn't find an unused CRTC, don't use any.
6776 */
6777 if (!crtc) {
6778 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6779 return false;
6780 }
6781
6782 mutex_lock(&crtc->mutex);
6783 intel_encoder->new_crtc = to_intel_crtc(crtc);
6784 to_intel_connector(connector)->new_encoder = intel_encoder;
6785
6786 intel_crtc = to_intel_crtc(crtc);
6787 old->dpms_mode = connector->dpms;
6788 old->load_detect_temp = true;
6789 old->release_fb = NULL;
6790
6791 if (!mode)
6792 mode = &load_detect_mode;
6793
6794 /* We need a framebuffer large enough to accommodate all accesses
6795 * that the plane may generate whilst we perform load detection.
6796 * We can not rely on the fbcon either being present (we get called
6797 * during its initialisation to detect all boot displays, or it may
6798 * not even exist) or that it is large enough to satisfy the
6799 * requested mode.
6800 */
6801 fb = mode_fits_in_fbdev(dev, mode);
6802 if (fb == NULL) {
6803 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6804 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6805 old->release_fb = fb;
6806 } else
6807 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6808 if (IS_ERR(fb)) {
6809 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6810 mutex_unlock(&crtc->mutex);
6811 return false;
6812 }
6813
6814 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6815 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6816 if (old->release_fb)
6817 old->release_fb->funcs->destroy(old->release_fb);
6818 mutex_unlock(&crtc->mutex);
6819 return false;
6820 }
6821
6822 /* let the connector get through one full cycle before testing */
6823 intel_wait_for_vblank(dev, intel_crtc->pipe);
6824 return true;
6825 }
6826
6827 void intel_release_load_detect_pipe(struct drm_connector *connector,
6828 struct intel_load_detect_pipe *old)
6829 {
6830 struct intel_encoder *intel_encoder =
6831 intel_attached_encoder(connector);
6832 struct drm_encoder *encoder = &intel_encoder->base;
6833 struct drm_crtc *crtc = encoder->crtc;
6834
6835 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6836 connector->base.id, drm_get_connector_name(connector),
6837 encoder->base.id, drm_get_encoder_name(encoder));
6838
6839 if (old->load_detect_temp) {
6840 to_intel_connector(connector)->new_encoder = NULL;
6841 intel_encoder->new_crtc = NULL;
6842 intel_set_mode(crtc, NULL, 0, 0, NULL);
6843
6844 if (old->release_fb) {
6845 drm_framebuffer_unregister_private(old->release_fb);
6846 drm_framebuffer_unreference(old->release_fb);
6847 }
6848
6849 mutex_unlock(&crtc->mutex);
6850 return;
6851 }
6852
6853 /* Switch crtc and encoder back off if necessary */
6854 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6855 connector->funcs->dpms(connector, old->dpms_mode);
6856
6857 mutex_unlock(&crtc->mutex);
6858 }
6859
6860 /* Returns the clock of the currently programmed mode of the given pipe. */
6861 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6862 {
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6865 int pipe = intel_crtc->pipe;
6866 u32 dpll = I915_READ(DPLL(pipe));
6867 u32 fp;
6868 intel_clock_t clock;
6869
6870 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6871 fp = I915_READ(FP0(pipe));
6872 else
6873 fp = I915_READ(FP1(pipe));
6874
6875 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6876 if (IS_PINEVIEW(dev)) {
6877 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6878 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6879 } else {
6880 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6881 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6882 }
6883
6884 if (!IS_GEN2(dev)) {
6885 if (IS_PINEVIEW(dev))
6886 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6887 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6888 else
6889 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6890 DPLL_FPA01_P1_POST_DIV_SHIFT);
6891
6892 switch (dpll & DPLL_MODE_MASK) {
6893 case DPLLB_MODE_DAC_SERIAL:
6894 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6895 5 : 10;
6896 break;
6897 case DPLLB_MODE_LVDS:
6898 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6899 7 : 14;
6900 break;
6901 default:
6902 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6903 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6904 return 0;
6905 }
6906
6907 /* XXX: Handle the 100Mhz refclk */
6908 intel_clock(dev, 96000, &clock);
6909 } else {
6910 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6911
6912 if (is_lvds) {
6913 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6914 DPLL_FPA01_P1_POST_DIV_SHIFT);
6915 clock.p2 = 14;
6916
6917 if ((dpll & PLL_REF_INPUT_MASK) ==
6918 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6919 /* XXX: might not be 66MHz */
6920 intel_clock(dev, 66000, &clock);
6921 } else
6922 intel_clock(dev, 48000, &clock);
6923 } else {
6924 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6925 clock.p1 = 2;
6926 else {
6927 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6928 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6929 }
6930 if (dpll & PLL_P2_DIVIDE_BY_4)
6931 clock.p2 = 4;
6932 else
6933 clock.p2 = 2;
6934
6935 intel_clock(dev, 48000, &clock);
6936 }
6937 }
6938
6939 /* XXX: It would be nice to validate the clocks, but we can't reuse
6940 * i830PllIsValid() because it relies on the xf86_config connector
6941 * configuration being accurate, which it isn't necessarily.
6942 */
6943
6944 return clock.dot;
6945 }
6946
6947 /** Returns the currently programmed mode of the given pipe. */
6948 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6949 struct drm_crtc *crtc)
6950 {
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6953 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6954 struct drm_display_mode *mode;
6955 int htot = I915_READ(HTOTAL(cpu_transcoder));
6956 int hsync = I915_READ(HSYNC(cpu_transcoder));
6957 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6958 int vsync = I915_READ(VSYNC(cpu_transcoder));
6959
6960 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6961 if (!mode)
6962 return NULL;
6963
6964 mode->clock = intel_crtc_clock_get(dev, crtc);
6965 mode->hdisplay = (htot & 0xffff) + 1;
6966 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6967 mode->hsync_start = (hsync & 0xffff) + 1;
6968 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6969 mode->vdisplay = (vtot & 0xffff) + 1;
6970 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6971 mode->vsync_start = (vsync & 0xffff) + 1;
6972 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6973
6974 drm_mode_set_name(mode);
6975
6976 return mode;
6977 }
6978
6979 static void intel_increase_pllclock(struct drm_crtc *crtc)
6980 {
6981 struct drm_device *dev = crtc->dev;
6982 drm_i915_private_t *dev_priv = dev->dev_private;
6983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6984 int pipe = intel_crtc->pipe;
6985 int dpll_reg = DPLL(pipe);
6986 int dpll;
6987
6988 if (HAS_PCH_SPLIT(dev))
6989 return;
6990
6991 if (!dev_priv->lvds_downclock_avail)
6992 return;
6993
6994 dpll = I915_READ(dpll_reg);
6995 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6996 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6997
6998 assert_panel_unlocked(dev_priv, pipe);
6999
7000 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7001 I915_WRITE(dpll_reg, dpll);
7002 intel_wait_for_vblank(dev, pipe);
7003
7004 dpll = I915_READ(dpll_reg);
7005 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7006 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7007 }
7008 }
7009
7010 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7011 {
7012 struct drm_device *dev = crtc->dev;
7013 drm_i915_private_t *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7015
7016 if (HAS_PCH_SPLIT(dev))
7017 return;
7018
7019 if (!dev_priv->lvds_downclock_avail)
7020 return;
7021
7022 /*
7023 * Since this is called by a timer, we should never get here in
7024 * the manual case.
7025 */
7026 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7027 int pipe = intel_crtc->pipe;
7028 int dpll_reg = DPLL(pipe);
7029 int dpll;
7030
7031 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7032
7033 assert_panel_unlocked(dev_priv, pipe);
7034
7035 dpll = I915_READ(dpll_reg);
7036 dpll |= DISPLAY_RATE_SELECT_FPA1;
7037 I915_WRITE(dpll_reg, dpll);
7038 intel_wait_for_vblank(dev, pipe);
7039 dpll = I915_READ(dpll_reg);
7040 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7041 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7042 }
7043
7044 }
7045
7046 void intel_mark_busy(struct drm_device *dev)
7047 {
7048 i915_update_gfx_val(dev->dev_private);
7049 }
7050
7051 void intel_mark_idle(struct drm_device *dev)
7052 {
7053 struct drm_crtc *crtc;
7054
7055 if (!i915_powersave)
7056 return;
7057
7058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7059 if (!crtc->fb)
7060 continue;
7061
7062 intel_decrease_pllclock(crtc);
7063 }
7064 }
7065
7066 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7067 {
7068 struct drm_device *dev = obj->base.dev;
7069 struct drm_crtc *crtc;
7070
7071 if (!i915_powersave)
7072 return;
7073
7074 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7075 if (!crtc->fb)
7076 continue;
7077
7078 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7079 intel_increase_pllclock(crtc);
7080 }
7081 }
7082
7083 static void intel_crtc_destroy(struct drm_crtc *crtc)
7084 {
7085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7086 struct drm_device *dev = crtc->dev;
7087 struct intel_unpin_work *work;
7088 unsigned long flags;
7089
7090 spin_lock_irqsave(&dev->event_lock, flags);
7091 work = intel_crtc->unpin_work;
7092 intel_crtc->unpin_work = NULL;
7093 spin_unlock_irqrestore(&dev->event_lock, flags);
7094
7095 if (work) {
7096 cancel_work_sync(&work->work);
7097 kfree(work);
7098 }
7099
7100 drm_crtc_cleanup(crtc);
7101
7102 kfree(intel_crtc);
7103 }
7104
7105 static void intel_unpin_work_fn(struct work_struct *__work)
7106 {
7107 struct intel_unpin_work *work =
7108 container_of(__work, struct intel_unpin_work, work);
7109 struct drm_device *dev = work->crtc->dev;
7110
7111 mutex_lock(&dev->struct_mutex);
7112 intel_unpin_fb_obj(work->old_fb_obj);
7113 drm_gem_object_unreference(&work->pending_flip_obj->base);
7114 drm_gem_object_unreference(&work->old_fb_obj->base);
7115
7116 intel_update_fbc(dev);
7117 mutex_unlock(&dev->struct_mutex);
7118
7119 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7120 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7121
7122 kfree(work);
7123 }
7124
7125 static void do_intel_finish_page_flip(struct drm_device *dev,
7126 struct drm_crtc *crtc)
7127 {
7128 drm_i915_private_t *dev_priv = dev->dev_private;
7129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7130 struct intel_unpin_work *work;
7131 unsigned long flags;
7132
7133 /* Ignore early vblank irqs */
7134 if (intel_crtc == NULL)
7135 return;
7136
7137 spin_lock_irqsave(&dev->event_lock, flags);
7138 work = intel_crtc->unpin_work;
7139
7140 /* Ensure we don't miss a work->pending update ... */
7141 smp_rmb();
7142
7143 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7144 spin_unlock_irqrestore(&dev->event_lock, flags);
7145 return;
7146 }
7147
7148 /* and that the unpin work is consistent wrt ->pending. */
7149 smp_rmb();
7150
7151 intel_crtc->unpin_work = NULL;
7152
7153 if (work->event)
7154 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7155
7156 drm_vblank_put(dev, intel_crtc->pipe);
7157
7158 spin_unlock_irqrestore(&dev->event_lock, flags);
7159
7160 wake_up_all(&dev_priv->pending_flip_queue);
7161
7162 queue_work(dev_priv->wq, &work->work);
7163
7164 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7165 }
7166
7167 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7168 {
7169 drm_i915_private_t *dev_priv = dev->dev_private;
7170 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7171
7172 do_intel_finish_page_flip(dev, crtc);
7173 }
7174
7175 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7176 {
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7179
7180 do_intel_finish_page_flip(dev, crtc);
7181 }
7182
7183 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7184 {
7185 drm_i915_private_t *dev_priv = dev->dev_private;
7186 struct intel_crtc *intel_crtc =
7187 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7188 unsigned long flags;
7189
7190 /* NB: An MMIO update of the plane base pointer will also
7191 * generate a page-flip completion irq, i.e. every modeset
7192 * is also accompanied by a spurious intel_prepare_page_flip().
7193 */
7194 spin_lock_irqsave(&dev->event_lock, flags);
7195 if (intel_crtc->unpin_work)
7196 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7197 spin_unlock_irqrestore(&dev->event_lock, flags);
7198 }
7199
7200 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7201 {
7202 /* Ensure that the work item is consistent when activating it ... */
7203 smp_wmb();
7204 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7205 /* and that it is marked active as soon as the irq could fire. */
7206 smp_wmb();
7207 }
7208
7209 static int intel_gen2_queue_flip(struct drm_device *dev,
7210 struct drm_crtc *crtc,
7211 struct drm_framebuffer *fb,
7212 struct drm_i915_gem_object *obj)
7213 {
7214 struct drm_i915_private *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7216 u32 flip_mask;
7217 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7218 int ret;
7219
7220 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7221 if (ret)
7222 goto err;
7223
7224 ret = intel_ring_begin(ring, 6);
7225 if (ret)
7226 goto err_unpin;
7227
7228 /* Can't queue multiple flips, so wait for the previous
7229 * one to finish before executing the next.
7230 */
7231 if (intel_crtc->plane)
7232 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7233 else
7234 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7235 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7236 intel_ring_emit(ring, MI_NOOP);
7237 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7238 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7239 intel_ring_emit(ring, fb->pitches[0]);
7240 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7241 intel_ring_emit(ring, 0); /* aux display base address, unused */
7242
7243 intel_mark_page_flip_active(intel_crtc);
7244 intel_ring_advance(ring);
7245 return 0;
7246
7247 err_unpin:
7248 intel_unpin_fb_obj(obj);
7249 err:
7250 return ret;
7251 }
7252
7253 static int intel_gen3_queue_flip(struct drm_device *dev,
7254 struct drm_crtc *crtc,
7255 struct drm_framebuffer *fb,
7256 struct drm_i915_gem_object *obj)
7257 {
7258 struct drm_i915_private *dev_priv = dev->dev_private;
7259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7260 u32 flip_mask;
7261 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7262 int ret;
7263
7264 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7265 if (ret)
7266 goto err;
7267
7268 ret = intel_ring_begin(ring, 6);
7269 if (ret)
7270 goto err_unpin;
7271
7272 if (intel_crtc->plane)
7273 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7274 else
7275 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7276 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7277 intel_ring_emit(ring, MI_NOOP);
7278 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7279 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7280 intel_ring_emit(ring, fb->pitches[0]);
7281 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7282 intel_ring_emit(ring, MI_NOOP);
7283
7284 intel_mark_page_flip_active(intel_crtc);
7285 intel_ring_advance(ring);
7286 return 0;
7287
7288 err_unpin:
7289 intel_unpin_fb_obj(obj);
7290 err:
7291 return ret;
7292 }
7293
7294 static int intel_gen4_queue_flip(struct drm_device *dev,
7295 struct drm_crtc *crtc,
7296 struct drm_framebuffer *fb,
7297 struct drm_i915_gem_object *obj)
7298 {
7299 struct drm_i915_private *dev_priv = dev->dev_private;
7300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7301 uint32_t pf, pipesrc;
7302 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7303 int ret;
7304
7305 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7306 if (ret)
7307 goto err;
7308
7309 ret = intel_ring_begin(ring, 4);
7310 if (ret)
7311 goto err_unpin;
7312
7313 /* i965+ uses the linear or tiled offsets from the
7314 * Display Registers (which do not change across a page-flip)
7315 * so we need only reprogram the base address.
7316 */
7317 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7319 intel_ring_emit(ring, fb->pitches[0]);
7320 intel_ring_emit(ring,
7321 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7322 obj->tiling_mode);
7323
7324 /* XXX Enabling the panel-fitter across page-flip is so far
7325 * untested on non-native modes, so ignore it for now.
7326 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7327 */
7328 pf = 0;
7329 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7330 intel_ring_emit(ring, pf | pipesrc);
7331
7332 intel_mark_page_flip_active(intel_crtc);
7333 intel_ring_advance(ring);
7334 return 0;
7335
7336 err_unpin:
7337 intel_unpin_fb_obj(obj);
7338 err:
7339 return ret;
7340 }
7341
7342 static int intel_gen6_queue_flip(struct drm_device *dev,
7343 struct drm_crtc *crtc,
7344 struct drm_framebuffer *fb,
7345 struct drm_i915_gem_object *obj)
7346 {
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7349 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7350 uint32_t pf, pipesrc;
7351 int ret;
7352
7353 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7354 if (ret)
7355 goto err;
7356
7357 ret = intel_ring_begin(ring, 4);
7358 if (ret)
7359 goto err_unpin;
7360
7361 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7363 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7364 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7365
7366 /* Contrary to the suggestions in the documentation,
7367 * "Enable Panel Fitter" does not seem to be required when page
7368 * flipping with a non-native mode, and worse causes a normal
7369 * modeset to fail.
7370 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7371 */
7372 pf = 0;
7373 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7374 intel_ring_emit(ring, pf | pipesrc);
7375
7376 intel_mark_page_flip_active(intel_crtc);
7377 intel_ring_advance(ring);
7378 return 0;
7379
7380 err_unpin:
7381 intel_unpin_fb_obj(obj);
7382 err:
7383 return ret;
7384 }
7385
7386 /*
7387 * On gen7 we currently use the blit ring because (in early silicon at least)
7388 * the render ring doesn't give us interrpts for page flip completion, which
7389 * means clients will hang after the first flip is queued. Fortunately the
7390 * blit ring generates interrupts properly, so use it instead.
7391 */
7392 static int intel_gen7_queue_flip(struct drm_device *dev,
7393 struct drm_crtc *crtc,
7394 struct drm_framebuffer *fb,
7395 struct drm_i915_gem_object *obj)
7396 {
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7399 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7400 uint32_t plane_bit = 0;
7401 int ret;
7402
7403 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7404 if (ret)
7405 goto err;
7406
7407 switch(intel_crtc->plane) {
7408 case PLANE_A:
7409 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7410 break;
7411 case PLANE_B:
7412 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7413 break;
7414 case PLANE_C:
7415 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7416 break;
7417 default:
7418 WARN_ONCE(1, "unknown plane in flip command\n");
7419 ret = -ENODEV;
7420 goto err_unpin;
7421 }
7422
7423 ret = intel_ring_begin(ring, 4);
7424 if (ret)
7425 goto err_unpin;
7426
7427 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7428 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7429 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7430 intel_ring_emit(ring, (MI_NOOP));
7431
7432 intel_mark_page_flip_active(intel_crtc);
7433 intel_ring_advance(ring);
7434 return 0;
7435
7436 err_unpin:
7437 intel_unpin_fb_obj(obj);
7438 err:
7439 return ret;
7440 }
7441
7442 static int intel_default_queue_flip(struct drm_device *dev,
7443 struct drm_crtc *crtc,
7444 struct drm_framebuffer *fb,
7445 struct drm_i915_gem_object *obj)
7446 {
7447 return -ENODEV;
7448 }
7449
7450 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7451 struct drm_framebuffer *fb,
7452 struct drm_pending_vblank_event *event)
7453 {
7454 struct drm_device *dev = crtc->dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct drm_framebuffer *old_fb = crtc->fb;
7457 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7459 struct intel_unpin_work *work;
7460 unsigned long flags;
7461 int ret;
7462
7463 /* Can't change pixel format via MI display flips. */
7464 if (fb->pixel_format != crtc->fb->pixel_format)
7465 return -EINVAL;
7466
7467 /*
7468 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7469 * Note that pitch changes could also affect these register.
7470 */
7471 if (INTEL_INFO(dev)->gen > 3 &&
7472 (fb->offsets[0] != crtc->fb->offsets[0] ||
7473 fb->pitches[0] != crtc->fb->pitches[0]))
7474 return -EINVAL;
7475
7476 work = kzalloc(sizeof *work, GFP_KERNEL);
7477 if (work == NULL)
7478 return -ENOMEM;
7479
7480 work->event = event;
7481 work->crtc = crtc;
7482 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7483 INIT_WORK(&work->work, intel_unpin_work_fn);
7484
7485 ret = drm_vblank_get(dev, intel_crtc->pipe);
7486 if (ret)
7487 goto free_work;
7488
7489 /* We borrow the event spin lock for protecting unpin_work */
7490 spin_lock_irqsave(&dev->event_lock, flags);
7491 if (intel_crtc->unpin_work) {
7492 spin_unlock_irqrestore(&dev->event_lock, flags);
7493 kfree(work);
7494 drm_vblank_put(dev, intel_crtc->pipe);
7495
7496 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7497 return -EBUSY;
7498 }
7499 intel_crtc->unpin_work = work;
7500 spin_unlock_irqrestore(&dev->event_lock, flags);
7501
7502 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7503 flush_workqueue(dev_priv->wq);
7504
7505 ret = i915_mutex_lock_interruptible(dev);
7506 if (ret)
7507 goto cleanup;
7508
7509 /* Reference the objects for the scheduled work. */
7510 drm_gem_object_reference(&work->old_fb_obj->base);
7511 drm_gem_object_reference(&obj->base);
7512
7513 crtc->fb = fb;
7514
7515 work->pending_flip_obj = obj;
7516
7517 work->enable_stall_check = true;
7518
7519 atomic_inc(&intel_crtc->unpin_work_count);
7520 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7521
7522 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7523 if (ret)
7524 goto cleanup_pending;
7525
7526 intel_disable_fbc(dev);
7527 intel_mark_fb_busy(obj);
7528 mutex_unlock(&dev->struct_mutex);
7529
7530 trace_i915_flip_request(intel_crtc->plane, obj);
7531
7532 return 0;
7533
7534 cleanup_pending:
7535 atomic_dec(&intel_crtc->unpin_work_count);
7536 crtc->fb = old_fb;
7537 drm_gem_object_unreference(&work->old_fb_obj->base);
7538 drm_gem_object_unreference(&obj->base);
7539 mutex_unlock(&dev->struct_mutex);
7540
7541 cleanup:
7542 spin_lock_irqsave(&dev->event_lock, flags);
7543 intel_crtc->unpin_work = NULL;
7544 spin_unlock_irqrestore(&dev->event_lock, flags);
7545
7546 drm_vblank_put(dev, intel_crtc->pipe);
7547 free_work:
7548 kfree(work);
7549
7550 return ret;
7551 }
7552
7553 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7554 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7555 .load_lut = intel_crtc_load_lut,
7556 };
7557
7558 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7559 {
7560 struct intel_encoder *other_encoder;
7561 struct drm_crtc *crtc = &encoder->new_crtc->base;
7562
7563 if (WARN_ON(!crtc))
7564 return false;
7565
7566 list_for_each_entry(other_encoder,
7567 &crtc->dev->mode_config.encoder_list,
7568 base.head) {
7569
7570 if (&other_encoder->new_crtc->base != crtc ||
7571 encoder == other_encoder)
7572 continue;
7573 else
7574 return true;
7575 }
7576
7577 return false;
7578 }
7579
7580 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7581 struct drm_crtc *crtc)
7582 {
7583 struct drm_device *dev;
7584 struct drm_crtc *tmp;
7585 int crtc_mask = 1;
7586
7587 WARN(!crtc, "checking null crtc?\n");
7588
7589 dev = crtc->dev;
7590
7591 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7592 if (tmp == crtc)
7593 break;
7594 crtc_mask <<= 1;
7595 }
7596
7597 if (encoder->possible_crtcs & crtc_mask)
7598 return true;
7599 return false;
7600 }
7601
7602 /**
7603 * intel_modeset_update_staged_output_state
7604 *
7605 * Updates the staged output configuration state, e.g. after we've read out the
7606 * current hw state.
7607 */
7608 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7609 {
7610 struct intel_encoder *encoder;
7611 struct intel_connector *connector;
7612
7613 list_for_each_entry(connector, &dev->mode_config.connector_list,
7614 base.head) {
7615 connector->new_encoder =
7616 to_intel_encoder(connector->base.encoder);
7617 }
7618
7619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7620 base.head) {
7621 encoder->new_crtc =
7622 to_intel_crtc(encoder->base.crtc);
7623 }
7624 }
7625
7626 /**
7627 * intel_modeset_commit_output_state
7628 *
7629 * This function copies the stage display pipe configuration to the real one.
7630 */
7631 static void intel_modeset_commit_output_state(struct drm_device *dev)
7632 {
7633 struct intel_encoder *encoder;
7634 struct intel_connector *connector;
7635
7636 list_for_each_entry(connector, &dev->mode_config.connector_list,
7637 base.head) {
7638 connector->base.encoder = &connector->new_encoder->base;
7639 }
7640
7641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7642 base.head) {
7643 encoder->base.crtc = &encoder->new_crtc->base;
7644 }
7645 }
7646
7647 static int
7648 pipe_config_set_bpp(struct drm_crtc *crtc,
7649 struct drm_framebuffer *fb,
7650 struct intel_crtc_config *pipe_config)
7651 {
7652 struct drm_device *dev = crtc->dev;
7653 struct drm_connector *connector;
7654 int bpp;
7655
7656 switch (fb->pixel_format) {
7657 case DRM_FORMAT_C8:
7658 bpp = 8*3; /* since we go through a colormap */
7659 break;
7660 case DRM_FORMAT_XRGB1555:
7661 case DRM_FORMAT_ARGB1555:
7662 /* checked in intel_framebuffer_init already */
7663 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7664 return -EINVAL;
7665 case DRM_FORMAT_RGB565:
7666 bpp = 6*3; /* min is 18bpp */
7667 break;
7668 case DRM_FORMAT_XBGR8888:
7669 case DRM_FORMAT_ABGR8888:
7670 /* checked in intel_framebuffer_init already */
7671 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7672 return -EINVAL;
7673 case DRM_FORMAT_XRGB8888:
7674 case DRM_FORMAT_ARGB8888:
7675 bpp = 8*3;
7676 break;
7677 case DRM_FORMAT_XRGB2101010:
7678 case DRM_FORMAT_ARGB2101010:
7679 case DRM_FORMAT_XBGR2101010:
7680 case DRM_FORMAT_ABGR2101010:
7681 /* checked in intel_framebuffer_init already */
7682 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7683 return -EINVAL;
7684 bpp = 10*3;
7685 break;
7686 /* TODO: gen4+ supports 16 bpc floating point, too. */
7687 default:
7688 DRM_DEBUG_KMS("unsupported depth\n");
7689 return -EINVAL;
7690 }
7691
7692 pipe_config->pipe_bpp = bpp;
7693
7694 /* Clamp display bpp to EDID value */
7695 list_for_each_entry(connector, &dev->mode_config.connector_list,
7696 head) {
7697 if (connector->encoder && connector->encoder->crtc != crtc)
7698 continue;
7699
7700 /* Don't use an invalid EDID bpc value */
7701 if (connector->display_info.bpc &&
7702 connector->display_info.bpc * 3 < bpp) {
7703 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7704 bpp, connector->display_info.bpc*3);
7705 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7706 }
7707
7708 /* Clamp bpp to 8 on screens without EDID 1.4 */
7709 if (connector->display_info.bpc == 0 && bpp > 24) {
7710 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7711 bpp);
7712 pipe_config->pipe_bpp = 24;
7713 }
7714 }
7715
7716 return bpp;
7717 }
7718
7719 static struct intel_crtc_config *
7720 intel_modeset_pipe_config(struct drm_crtc *crtc,
7721 struct drm_framebuffer *fb,
7722 struct drm_display_mode *mode)
7723 {
7724 struct drm_device *dev = crtc->dev;
7725 struct drm_encoder_helper_funcs *encoder_funcs;
7726 struct intel_encoder *encoder;
7727 struct intel_crtc_config *pipe_config;
7728 int plane_bpp, ret = -EINVAL;
7729 bool retry = true;
7730
7731 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7732 if (!pipe_config)
7733 return ERR_PTR(-ENOMEM);
7734
7735 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7736 drm_mode_copy(&pipe_config->requested_mode, mode);
7737
7738 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7739 if (plane_bpp < 0)
7740 goto fail;
7741
7742 encoder_retry:
7743 /* Pass our mode to the connectors and the CRTC to give them a chance to
7744 * adjust it according to limitations or connector properties, and also
7745 * a chance to reject the mode entirely.
7746 */
7747 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7748 base.head) {
7749
7750 if (&encoder->new_crtc->base != crtc)
7751 continue;
7752
7753 if (encoder->compute_config) {
7754 if (!(encoder->compute_config(encoder, pipe_config))) {
7755 DRM_DEBUG_KMS("Encoder config failure\n");
7756 goto fail;
7757 }
7758
7759 continue;
7760 }
7761
7762 encoder_funcs = encoder->base.helper_private;
7763 if (!(encoder_funcs->mode_fixup(&encoder->base,
7764 &pipe_config->requested_mode,
7765 &pipe_config->adjusted_mode))) {
7766 DRM_DEBUG_KMS("Encoder fixup failed\n");
7767 goto fail;
7768 }
7769 }
7770
7771 ret = intel_crtc_compute_config(crtc, pipe_config);
7772 if (ret < 0) {
7773 DRM_DEBUG_KMS("CRTC fixup failed\n");
7774 goto fail;
7775 }
7776
7777 if (ret == RETRY) {
7778 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7779 ret = -EINVAL;
7780 goto fail;
7781 }
7782
7783 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7784 retry = false;
7785 goto encoder_retry;
7786 }
7787
7788 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7789
7790 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7791 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7792 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7793
7794 return pipe_config;
7795 fail:
7796 kfree(pipe_config);
7797 return ERR_PTR(ret);
7798 }
7799
7800 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7801 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7802 static void
7803 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7804 unsigned *prepare_pipes, unsigned *disable_pipes)
7805 {
7806 struct intel_crtc *intel_crtc;
7807 struct drm_device *dev = crtc->dev;
7808 struct intel_encoder *encoder;
7809 struct intel_connector *connector;
7810 struct drm_crtc *tmp_crtc;
7811
7812 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7813
7814 /* Check which crtcs have changed outputs connected to them, these need
7815 * to be part of the prepare_pipes mask. We don't (yet) support global
7816 * modeset across multiple crtcs, so modeset_pipes will only have one
7817 * bit set at most. */
7818 list_for_each_entry(connector, &dev->mode_config.connector_list,
7819 base.head) {
7820 if (connector->base.encoder == &connector->new_encoder->base)
7821 continue;
7822
7823 if (connector->base.encoder) {
7824 tmp_crtc = connector->base.encoder->crtc;
7825
7826 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7827 }
7828
7829 if (connector->new_encoder)
7830 *prepare_pipes |=
7831 1 << connector->new_encoder->new_crtc->pipe;
7832 }
7833
7834 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7835 base.head) {
7836 if (encoder->base.crtc == &encoder->new_crtc->base)
7837 continue;
7838
7839 if (encoder->base.crtc) {
7840 tmp_crtc = encoder->base.crtc;
7841
7842 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7843 }
7844
7845 if (encoder->new_crtc)
7846 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7847 }
7848
7849 /* Check for any pipes that will be fully disabled ... */
7850 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7851 base.head) {
7852 bool used = false;
7853
7854 /* Don't try to disable disabled crtcs. */
7855 if (!intel_crtc->base.enabled)
7856 continue;
7857
7858 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7859 base.head) {
7860 if (encoder->new_crtc == intel_crtc)
7861 used = true;
7862 }
7863
7864 if (!used)
7865 *disable_pipes |= 1 << intel_crtc->pipe;
7866 }
7867
7868
7869 /* set_mode is also used to update properties on life display pipes. */
7870 intel_crtc = to_intel_crtc(crtc);
7871 if (crtc->enabled)
7872 *prepare_pipes |= 1 << intel_crtc->pipe;
7873
7874 /*
7875 * For simplicity do a full modeset on any pipe where the output routing
7876 * changed. We could be more clever, but that would require us to be
7877 * more careful with calling the relevant encoder->mode_set functions.
7878 */
7879 if (*prepare_pipes)
7880 *modeset_pipes = *prepare_pipes;
7881
7882 /* ... and mask these out. */
7883 *modeset_pipes &= ~(*disable_pipes);
7884 *prepare_pipes &= ~(*disable_pipes);
7885
7886 /*
7887 * HACK: We don't (yet) fully support global modesets. intel_set_config
7888 * obies this rule, but the modeset restore mode of
7889 * intel_modeset_setup_hw_state does not.
7890 */
7891 *modeset_pipes &= 1 << intel_crtc->pipe;
7892 *prepare_pipes &= 1 << intel_crtc->pipe;
7893
7894 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7895 *modeset_pipes, *prepare_pipes, *disable_pipes);
7896 }
7897
7898 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7899 {
7900 struct drm_encoder *encoder;
7901 struct drm_device *dev = crtc->dev;
7902
7903 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7904 if (encoder->crtc == crtc)
7905 return true;
7906
7907 return false;
7908 }
7909
7910 static void
7911 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7912 {
7913 struct intel_encoder *intel_encoder;
7914 struct intel_crtc *intel_crtc;
7915 struct drm_connector *connector;
7916
7917 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7918 base.head) {
7919 if (!intel_encoder->base.crtc)
7920 continue;
7921
7922 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7923
7924 if (prepare_pipes & (1 << intel_crtc->pipe))
7925 intel_encoder->connectors_active = false;
7926 }
7927
7928 intel_modeset_commit_output_state(dev);
7929
7930 /* Update computed state. */
7931 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7932 base.head) {
7933 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7934 }
7935
7936 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7937 if (!connector->encoder || !connector->encoder->crtc)
7938 continue;
7939
7940 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7941
7942 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7943 struct drm_property *dpms_property =
7944 dev->mode_config.dpms_property;
7945
7946 connector->dpms = DRM_MODE_DPMS_ON;
7947 drm_object_property_set_value(&connector->base,
7948 dpms_property,
7949 DRM_MODE_DPMS_ON);
7950
7951 intel_encoder = to_intel_encoder(connector->encoder);
7952 intel_encoder->connectors_active = true;
7953 }
7954 }
7955
7956 }
7957
7958 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7959 list_for_each_entry((intel_crtc), \
7960 &(dev)->mode_config.crtc_list, \
7961 base.head) \
7962 if (mask & (1 <<(intel_crtc)->pipe))
7963
7964 static bool
7965 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7966 struct intel_crtc_config *pipe_config)
7967 {
7968 #define PIPE_CONF_CHECK_I(name) \
7969 if (current_config->name != pipe_config->name) { \
7970 DRM_ERROR("mismatch in " #name " " \
7971 "(expected %i, found %i)\n", \
7972 current_config->name, \
7973 pipe_config->name); \
7974 return false; \
7975 }
7976
7977 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
7978 if ((current_config->name ^ pipe_config->name) & (mask)) { \
7979 DRM_ERROR("mismatch in " #name " " \
7980 "(expected %i, found %i)\n", \
7981 current_config->name & (mask), \
7982 pipe_config->name & (mask)); \
7983 return false; \
7984 }
7985
7986 PIPE_CONF_CHECK_I(has_pch_encoder);
7987 PIPE_CONF_CHECK_I(fdi_lanes);
7988 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
7989 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
7990 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
7991 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
7992 PIPE_CONF_CHECK_I(fdi_m_n.tu);
7993
7994 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
7995 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
7996 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
7997 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
7998 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
7999 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8000
8001 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8002 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8003 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8004 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8005 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8006 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8007
8008 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8009 DRM_MODE_FLAG_INTERLACE);
8010
8011 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8012 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8013
8014 #undef PIPE_CONF_CHECK_I
8015 #undef PIPE_CONF_CHECK_FLAGS
8016
8017 return true;
8018 }
8019
8020 void
8021 intel_modeset_check_state(struct drm_device *dev)
8022 {
8023 drm_i915_private_t *dev_priv = dev->dev_private;
8024 struct intel_crtc *crtc;
8025 struct intel_encoder *encoder;
8026 struct intel_connector *connector;
8027 struct intel_crtc_config pipe_config;
8028
8029 list_for_each_entry(connector, &dev->mode_config.connector_list,
8030 base.head) {
8031 /* This also checks the encoder/connector hw state with the
8032 * ->get_hw_state callbacks. */
8033 intel_connector_check_state(connector);
8034
8035 WARN(&connector->new_encoder->base != connector->base.encoder,
8036 "connector's staged encoder doesn't match current encoder\n");
8037 }
8038
8039 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8040 base.head) {
8041 bool enabled = false;
8042 bool active = false;
8043 enum pipe pipe, tracked_pipe;
8044
8045 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8046 encoder->base.base.id,
8047 drm_get_encoder_name(&encoder->base));
8048
8049 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8050 "encoder's stage crtc doesn't match current crtc\n");
8051 WARN(encoder->connectors_active && !encoder->base.crtc,
8052 "encoder's active_connectors set, but no crtc\n");
8053
8054 list_for_each_entry(connector, &dev->mode_config.connector_list,
8055 base.head) {
8056 if (connector->base.encoder != &encoder->base)
8057 continue;
8058 enabled = true;
8059 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8060 active = true;
8061 }
8062 WARN(!!encoder->base.crtc != enabled,
8063 "encoder's enabled state mismatch "
8064 "(expected %i, found %i)\n",
8065 !!encoder->base.crtc, enabled);
8066 WARN(active && !encoder->base.crtc,
8067 "active encoder with no crtc\n");
8068
8069 WARN(encoder->connectors_active != active,
8070 "encoder's computed active state doesn't match tracked active state "
8071 "(expected %i, found %i)\n", active, encoder->connectors_active);
8072
8073 active = encoder->get_hw_state(encoder, &pipe);
8074 WARN(active != encoder->connectors_active,
8075 "encoder's hw state doesn't match sw tracking "
8076 "(expected %i, found %i)\n",
8077 encoder->connectors_active, active);
8078
8079 if (!encoder->base.crtc)
8080 continue;
8081
8082 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8083 WARN(active && pipe != tracked_pipe,
8084 "active encoder's pipe doesn't match"
8085 "(expected %i, found %i)\n",
8086 tracked_pipe, pipe);
8087
8088 }
8089
8090 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8091 base.head) {
8092 bool enabled = false;
8093 bool active = false;
8094
8095 DRM_DEBUG_KMS("[CRTC:%d]\n",
8096 crtc->base.base.id);
8097
8098 WARN(crtc->active && !crtc->base.enabled,
8099 "active crtc, but not enabled in sw tracking\n");
8100
8101 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8102 base.head) {
8103 if (encoder->base.crtc != &crtc->base)
8104 continue;
8105 enabled = true;
8106 if (encoder->connectors_active)
8107 active = true;
8108 }
8109 WARN(active != crtc->active,
8110 "crtc's computed active state doesn't match tracked active state "
8111 "(expected %i, found %i)\n", active, crtc->active);
8112 WARN(enabled != crtc->base.enabled,
8113 "crtc's computed enabled state doesn't match tracked enabled state "
8114 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8115
8116 memset(&pipe_config, 0, sizeof(pipe_config));
8117 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8118 active = dev_priv->display.get_pipe_config(crtc,
8119 &pipe_config);
8120 WARN(crtc->active != active,
8121 "crtc active state doesn't match with hw state "
8122 "(expected %i, found %i)\n", crtc->active, active);
8123
8124 WARN(active &&
8125 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8126 "pipe state doesn't match!\n");
8127 }
8128 }
8129
8130 static int __intel_set_mode(struct drm_crtc *crtc,
8131 struct drm_display_mode *mode,
8132 int x, int y, struct drm_framebuffer *fb)
8133 {
8134 struct drm_device *dev = crtc->dev;
8135 drm_i915_private_t *dev_priv = dev->dev_private;
8136 struct drm_display_mode *saved_mode, *saved_hwmode;
8137 struct intel_crtc_config *pipe_config = NULL;
8138 struct intel_crtc *intel_crtc;
8139 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8140 int ret = 0;
8141
8142 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8143 if (!saved_mode)
8144 return -ENOMEM;
8145 saved_hwmode = saved_mode + 1;
8146
8147 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8148 &prepare_pipes, &disable_pipes);
8149
8150 *saved_hwmode = crtc->hwmode;
8151 *saved_mode = crtc->mode;
8152
8153 /* Hack: Because we don't (yet) support global modeset on multiple
8154 * crtcs, we don't keep track of the new mode for more than one crtc.
8155 * Hence simply check whether any bit is set in modeset_pipes in all the
8156 * pieces of code that are not yet converted to deal with mutliple crtcs
8157 * changing their mode at the same time. */
8158 if (modeset_pipes) {
8159 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8160 if (IS_ERR(pipe_config)) {
8161 ret = PTR_ERR(pipe_config);
8162 pipe_config = NULL;
8163
8164 goto out;
8165 }
8166 }
8167
8168 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8169 intel_crtc_disable(&intel_crtc->base);
8170
8171 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8172 if (intel_crtc->base.enabled)
8173 dev_priv->display.crtc_disable(&intel_crtc->base);
8174 }
8175
8176 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8177 * to set it here already despite that we pass it down the callchain.
8178 */
8179 if (modeset_pipes) {
8180 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8181 crtc->mode = *mode;
8182 /* mode_set/enable/disable functions rely on a correct pipe
8183 * config. */
8184 to_intel_crtc(crtc)->config = *pipe_config;
8185 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8186 }
8187
8188 /* Only after disabling all output pipelines that will be changed can we
8189 * update the the output configuration. */
8190 intel_modeset_update_state(dev, prepare_pipes);
8191
8192 if (dev_priv->display.modeset_global_resources)
8193 dev_priv->display.modeset_global_resources(dev);
8194
8195 /* Set up the DPLL and any encoders state that needs to adjust or depend
8196 * on the DPLL.
8197 */
8198 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8199 ret = intel_crtc_mode_set(&intel_crtc->base,
8200 x, y, fb);
8201 if (ret)
8202 goto done;
8203 }
8204
8205 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8206 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8207 dev_priv->display.crtc_enable(&intel_crtc->base);
8208
8209 if (modeset_pipes) {
8210 /* Store real post-adjustment hardware mode. */
8211 crtc->hwmode = pipe_config->adjusted_mode;
8212
8213 /* Calculate and store various constants which
8214 * are later needed by vblank and swap-completion
8215 * timestamping. They are derived from true hwmode.
8216 */
8217 drm_calc_timestamping_constants(crtc);
8218 }
8219
8220 /* FIXME: add subpixel order */
8221 done:
8222 if (ret && crtc->enabled) {
8223 crtc->hwmode = *saved_hwmode;
8224 crtc->mode = *saved_mode;
8225 }
8226
8227 out:
8228 kfree(pipe_config);
8229 kfree(saved_mode);
8230 return ret;
8231 }
8232
8233 int intel_set_mode(struct drm_crtc *crtc,
8234 struct drm_display_mode *mode,
8235 int x, int y, struct drm_framebuffer *fb)
8236 {
8237 int ret;
8238
8239 ret = __intel_set_mode(crtc, mode, x, y, fb);
8240
8241 if (ret == 0)
8242 intel_modeset_check_state(crtc->dev);
8243
8244 return ret;
8245 }
8246
8247 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8248 {
8249 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8250 }
8251
8252 #undef for_each_intel_crtc_masked
8253
8254 static void intel_set_config_free(struct intel_set_config *config)
8255 {
8256 if (!config)
8257 return;
8258
8259 kfree(config->save_connector_encoders);
8260 kfree(config->save_encoder_crtcs);
8261 kfree(config);
8262 }
8263
8264 static int intel_set_config_save_state(struct drm_device *dev,
8265 struct intel_set_config *config)
8266 {
8267 struct drm_encoder *encoder;
8268 struct drm_connector *connector;
8269 int count;
8270
8271 config->save_encoder_crtcs =
8272 kcalloc(dev->mode_config.num_encoder,
8273 sizeof(struct drm_crtc *), GFP_KERNEL);
8274 if (!config->save_encoder_crtcs)
8275 return -ENOMEM;
8276
8277 config->save_connector_encoders =
8278 kcalloc(dev->mode_config.num_connector,
8279 sizeof(struct drm_encoder *), GFP_KERNEL);
8280 if (!config->save_connector_encoders)
8281 return -ENOMEM;
8282
8283 /* Copy data. Note that driver private data is not affected.
8284 * Should anything bad happen only the expected state is
8285 * restored, not the drivers personal bookkeeping.
8286 */
8287 count = 0;
8288 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8289 config->save_encoder_crtcs[count++] = encoder->crtc;
8290 }
8291
8292 count = 0;
8293 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8294 config->save_connector_encoders[count++] = connector->encoder;
8295 }
8296
8297 return 0;
8298 }
8299
8300 static void intel_set_config_restore_state(struct drm_device *dev,
8301 struct intel_set_config *config)
8302 {
8303 struct intel_encoder *encoder;
8304 struct intel_connector *connector;
8305 int count;
8306
8307 count = 0;
8308 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8309 encoder->new_crtc =
8310 to_intel_crtc(config->save_encoder_crtcs[count++]);
8311 }
8312
8313 count = 0;
8314 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8315 connector->new_encoder =
8316 to_intel_encoder(config->save_connector_encoders[count++]);
8317 }
8318 }
8319
8320 static void
8321 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8322 struct intel_set_config *config)
8323 {
8324
8325 /* We should be able to check here if the fb has the same properties
8326 * and then just flip_or_move it */
8327 if (set->crtc->fb != set->fb) {
8328 /* If we have no fb then treat it as a full mode set */
8329 if (set->crtc->fb == NULL) {
8330 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8331 config->mode_changed = true;
8332 } else if (set->fb == NULL) {
8333 config->mode_changed = true;
8334 } else if (set->fb->pixel_format !=
8335 set->crtc->fb->pixel_format) {
8336 config->mode_changed = true;
8337 } else
8338 config->fb_changed = true;
8339 }
8340
8341 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8342 config->fb_changed = true;
8343
8344 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8345 DRM_DEBUG_KMS("modes are different, full mode set\n");
8346 drm_mode_debug_printmodeline(&set->crtc->mode);
8347 drm_mode_debug_printmodeline(set->mode);
8348 config->mode_changed = true;
8349 }
8350 }
8351
8352 static int
8353 intel_modeset_stage_output_state(struct drm_device *dev,
8354 struct drm_mode_set *set,
8355 struct intel_set_config *config)
8356 {
8357 struct drm_crtc *new_crtc;
8358 struct intel_connector *connector;
8359 struct intel_encoder *encoder;
8360 int count, ro;
8361
8362 /* The upper layers ensure that we either disable a crtc or have a list
8363 * of connectors. For paranoia, double-check this. */
8364 WARN_ON(!set->fb && (set->num_connectors != 0));
8365 WARN_ON(set->fb && (set->num_connectors == 0));
8366
8367 count = 0;
8368 list_for_each_entry(connector, &dev->mode_config.connector_list,
8369 base.head) {
8370 /* Otherwise traverse passed in connector list and get encoders
8371 * for them. */
8372 for (ro = 0; ro < set->num_connectors; ro++) {
8373 if (set->connectors[ro] == &connector->base) {
8374 connector->new_encoder = connector->encoder;
8375 break;
8376 }
8377 }
8378
8379 /* If we disable the crtc, disable all its connectors. Also, if
8380 * the connector is on the changing crtc but not on the new
8381 * connector list, disable it. */
8382 if ((!set->fb || ro == set->num_connectors) &&
8383 connector->base.encoder &&
8384 connector->base.encoder->crtc == set->crtc) {
8385 connector->new_encoder = NULL;
8386
8387 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8388 connector->base.base.id,
8389 drm_get_connector_name(&connector->base));
8390 }
8391
8392
8393 if (&connector->new_encoder->base != connector->base.encoder) {
8394 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8395 config->mode_changed = true;
8396 }
8397 }
8398 /* connector->new_encoder is now updated for all connectors. */
8399
8400 /* Update crtc of enabled connectors. */
8401 count = 0;
8402 list_for_each_entry(connector, &dev->mode_config.connector_list,
8403 base.head) {
8404 if (!connector->new_encoder)
8405 continue;
8406
8407 new_crtc = connector->new_encoder->base.crtc;
8408
8409 for (ro = 0; ro < set->num_connectors; ro++) {
8410 if (set->connectors[ro] == &connector->base)
8411 new_crtc = set->crtc;
8412 }
8413
8414 /* Make sure the new CRTC will work with the encoder */
8415 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8416 new_crtc)) {
8417 return -EINVAL;
8418 }
8419 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8420
8421 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8422 connector->base.base.id,
8423 drm_get_connector_name(&connector->base),
8424 new_crtc->base.id);
8425 }
8426
8427 /* Check for any encoders that needs to be disabled. */
8428 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8429 base.head) {
8430 list_for_each_entry(connector,
8431 &dev->mode_config.connector_list,
8432 base.head) {
8433 if (connector->new_encoder == encoder) {
8434 WARN_ON(!connector->new_encoder->new_crtc);
8435
8436 goto next_encoder;
8437 }
8438 }
8439 encoder->new_crtc = NULL;
8440 next_encoder:
8441 /* Only now check for crtc changes so we don't miss encoders
8442 * that will be disabled. */
8443 if (&encoder->new_crtc->base != encoder->base.crtc) {
8444 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8445 config->mode_changed = true;
8446 }
8447 }
8448 /* Now we've also updated encoder->new_crtc for all encoders. */
8449
8450 return 0;
8451 }
8452
8453 static int intel_crtc_set_config(struct drm_mode_set *set)
8454 {
8455 struct drm_device *dev;
8456 struct drm_mode_set save_set;
8457 struct intel_set_config *config;
8458 int ret;
8459
8460 BUG_ON(!set);
8461 BUG_ON(!set->crtc);
8462 BUG_ON(!set->crtc->helper_private);
8463
8464 /* Enforce sane interface api - has been abused by the fb helper. */
8465 BUG_ON(!set->mode && set->fb);
8466 BUG_ON(set->fb && set->num_connectors == 0);
8467
8468 if (set->fb) {
8469 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8470 set->crtc->base.id, set->fb->base.id,
8471 (int)set->num_connectors, set->x, set->y);
8472 } else {
8473 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8474 }
8475
8476 dev = set->crtc->dev;
8477
8478 ret = -ENOMEM;
8479 config = kzalloc(sizeof(*config), GFP_KERNEL);
8480 if (!config)
8481 goto out_config;
8482
8483 ret = intel_set_config_save_state(dev, config);
8484 if (ret)
8485 goto out_config;
8486
8487 save_set.crtc = set->crtc;
8488 save_set.mode = &set->crtc->mode;
8489 save_set.x = set->crtc->x;
8490 save_set.y = set->crtc->y;
8491 save_set.fb = set->crtc->fb;
8492
8493 /* Compute whether we need a full modeset, only an fb base update or no
8494 * change at all. In the future we might also check whether only the
8495 * mode changed, e.g. for LVDS where we only change the panel fitter in
8496 * such cases. */
8497 intel_set_config_compute_mode_changes(set, config);
8498
8499 ret = intel_modeset_stage_output_state(dev, set, config);
8500 if (ret)
8501 goto fail;
8502
8503 if (config->mode_changed) {
8504 if (set->mode) {
8505 DRM_DEBUG_KMS("attempting to set mode from"
8506 " userspace\n");
8507 drm_mode_debug_printmodeline(set->mode);
8508 }
8509
8510 ret = intel_set_mode(set->crtc, set->mode,
8511 set->x, set->y, set->fb);
8512 if (ret) {
8513 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8514 set->crtc->base.id, ret);
8515 goto fail;
8516 }
8517 } else if (config->fb_changed) {
8518 intel_crtc_wait_for_pending_flips(set->crtc);
8519
8520 ret = intel_pipe_set_base(set->crtc,
8521 set->x, set->y, set->fb);
8522 }
8523
8524 intel_set_config_free(config);
8525
8526 return 0;
8527
8528 fail:
8529 intel_set_config_restore_state(dev, config);
8530
8531 /* Try to restore the config */
8532 if (config->mode_changed &&
8533 intel_set_mode(save_set.crtc, save_set.mode,
8534 save_set.x, save_set.y, save_set.fb))
8535 DRM_ERROR("failed to restore config after modeset failure\n");
8536
8537 out_config:
8538 intel_set_config_free(config);
8539 return ret;
8540 }
8541
8542 static const struct drm_crtc_funcs intel_crtc_funcs = {
8543 .cursor_set = intel_crtc_cursor_set,
8544 .cursor_move = intel_crtc_cursor_move,
8545 .gamma_set = intel_crtc_gamma_set,
8546 .set_config = intel_crtc_set_config,
8547 .destroy = intel_crtc_destroy,
8548 .page_flip = intel_crtc_page_flip,
8549 };
8550
8551 static void intel_cpu_pll_init(struct drm_device *dev)
8552 {
8553 if (HAS_DDI(dev))
8554 intel_ddi_pll_init(dev);
8555 }
8556
8557 static void intel_pch_pll_init(struct drm_device *dev)
8558 {
8559 drm_i915_private_t *dev_priv = dev->dev_private;
8560 int i;
8561
8562 if (dev_priv->num_pch_pll == 0) {
8563 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8564 return;
8565 }
8566
8567 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8568 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8569 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8570 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8571 }
8572 }
8573
8574 static void intel_crtc_init(struct drm_device *dev, int pipe)
8575 {
8576 drm_i915_private_t *dev_priv = dev->dev_private;
8577 struct intel_crtc *intel_crtc;
8578 int i;
8579
8580 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8581 if (intel_crtc == NULL)
8582 return;
8583
8584 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8585
8586 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8587 for (i = 0; i < 256; i++) {
8588 intel_crtc->lut_r[i] = i;
8589 intel_crtc->lut_g[i] = i;
8590 intel_crtc->lut_b[i] = i;
8591 }
8592
8593 /* Swap pipes & planes for FBC on pre-965 */
8594 intel_crtc->pipe = pipe;
8595 intel_crtc->plane = pipe;
8596 intel_crtc->config.cpu_transcoder = pipe;
8597 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8598 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8599 intel_crtc->plane = !pipe;
8600 }
8601
8602 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8603 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8604 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8605 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8606
8607 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8608 }
8609
8610 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8611 struct drm_file *file)
8612 {
8613 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8614 struct drm_mode_object *drmmode_obj;
8615 struct intel_crtc *crtc;
8616
8617 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8618 return -ENODEV;
8619
8620 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8621 DRM_MODE_OBJECT_CRTC);
8622
8623 if (!drmmode_obj) {
8624 DRM_ERROR("no such CRTC id\n");
8625 return -EINVAL;
8626 }
8627
8628 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8629 pipe_from_crtc_id->pipe = crtc->pipe;
8630
8631 return 0;
8632 }
8633
8634 static int intel_encoder_clones(struct intel_encoder *encoder)
8635 {
8636 struct drm_device *dev = encoder->base.dev;
8637 struct intel_encoder *source_encoder;
8638 int index_mask = 0;
8639 int entry = 0;
8640
8641 list_for_each_entry(source_encoder,
8642 &dev->mode_config.encoder_list, base.head) {
8643
8644 if (encoder == source_encoder)
8645 index_mask |= (1 << entry);
8646
8647 /* Intel hw has only one MUX where enocoders could be cloned. */
8648 if (encoder->cloneable && source_encoder->cloneable)
8649 index_mask |= (1 << entry);
8650
8651 entry++;
8652 }
8653
8654 return index_mask;
8655 }
8656
8657 static bool has_edp_a(struct drm_device *dev)
8658 {
8659 struct drm_i915_private *dev_priv = dev->dev_private;
8660
8661 if (!IS_MOBILE(dev))
8662 return false;
8663
8664 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8665 return false;
8666
8667 if (IS_GEN5(dev) &&
8668 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8669 return false;
8670
8671 return true;
8672 }
8673
8674 static void intel_setup_outputs(struct drm_device *dev)
8675 {
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 struct intel_encoder *encoder;
8678 bool dpd_is_edp = false;
8679 bool has_lvds;
8680
8681 has_lvds = intel_lvds_init(dev);
8682 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8683 /* disable the panel fitter on everything but LVDS */
8684 I915_WRITE(PFIT_CONTROL, 0);
8685 }
8686
8687 if (!IS_ULT(dev))
8688 intel_crt_init(dev);
8689
8690 if (HAS_DDI(dev)) {
8691 int found;
8692
8693 /* Haswell uses DDI functions to detect digital outputs */
8694 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8695 /* DDI A only supports eDP */
8696 if (found)
8697 intel_ddi_init(dev, PORT_A);
8698
8699 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8700 * register */
8701 found = I915_READ(SFUSE_STRAP);
8702
8703 if (found & SFUSE_STRAP_DDIB_DETECTED)
8704 intel_ddi_init(dev, PORT_B);
8705 if (found & SFUSE_STRAP_DDIC_DETECTED)
8706 intel_ddi_init(dev, PORT_C);
8707 if (found & SFUSE_STRAP_DDID_DETECTED)
8708 intel_ddi_init(dev, PORT_D);
8709 } else if (HAS_PCH_SPLIT(dev)) {
8710 int found;
8711 dpd_is_edp = intel_dpd_is_edp(dev);
8712
8713 if (has_edp_a(dev))
8714 intel_dp_init(dev, DP_A, PORT_A);
8715
8716 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8717 /* PCH SDVOB multiplex with HDMIB */
8718 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8719 if (!found)
8720 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8721 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8722 intel_dp_init(dev, PCH_DP_B, PORT_B);
8723 }
8724
8725 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8726 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8727
8728 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8729 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8730
8731 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8732 intel_dp_init(dev, PCH_DP_C, PORT_C);
8733
8734 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8735 intel_dp_init(dev, PCH_DP_D, PORT_D);
8736 } else if (IS_VALLEYVIEW(dev)) {
8737 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8738 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8739 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8740
8741 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8742 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8743 PORT_B);
8744 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8745 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8746 }
8747 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8748 bool found = false;
8749
8750 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8751 DRM_DEBUG_KMS("probing SDVOB\n");
8752 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8753 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8754 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8755 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8756 }
8757
8758 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8759 intel_dp_init(dev, DP_B, PORT_B);
8760 }
8761
8762 /* Before G4X SDVOC doesn't have its own detect register */
8763
8764 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8765 DRM_DEBUG_KMS("probing SDVOC\n");
8766 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8767 }
8768
8769 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8770
8771 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8772 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8773 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8774 }
8775 if (SUPPORTS_INTEGRATED_DP(dev))
8776 intel_dp_init(dev, DP_C, PORT_C);
8777 }
8778
8779 if (SUPPORTS_INTEGRATED_DP(dev) &&
8780 (I915_READ(DP_D) & DP_DETECTED))
8781 intel_dp_init(dev, DP_D, PORT_D);
8782 } else if (IS_GEN2(dev))
8783 intel_dvo_init(dev);
8784
8785 if (SUPPORTS_TV(dev))
8786 intel_tv_init(dev);
8787
8788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8789 encoder->base.possible_crtcs = encoder->crtc_mask;
8790 encoder->base.possible_clones =
8791 intel_encoder_clones(encoder);
8792 }
8793
8794 intel_init_pch_refclk(dev);
8795
8796 drm_helper_move_panel_connectors_to_head(dev);
8797 }
8798
8799 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8800 {
8801 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8802
8803 drm_framebuffer_cleanup(fb);
8804 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8805
8806 kfree(intel_fb);
8807 }
8808
8809 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8810 struct drm_file *file,
8811 unsigned int *handle)
8812 {
8813 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8814 struct drm_i915_gem_object *obj = intel_fb->obj;
8815
8816 return drm_gem_handle_create(file, &obj->base, handle);
8817 }
8818
8819 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8820 .destroy = intel_user_framebuffer_destroy,
8821 .create_handle = intel_user_framebuffer_create_handle,
8822 };
8823
8824 int intel_framebuffer_init(struct drm_device *dev,
8825 struct intel_framebuffer *intel_fb,
8826 struct drm_mode_fb_cmd2 *mode_cmd,
8827 struct drm_i915_gem_object *obj)
8828 {
8829 int ret;
8830
8831 if (obj->tiling_mode == I915_TILING_Y) {
8832 DRM_DEBUG("hardware does not support tiling Y\n");
8833 return -EINVAL;
8834 }
8835
8836 if (mode_cmd->pitches[0] & 63) {
8837 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8838 mode_cmd->pitches[0]);
8839 return -EINVAL;
8840 }
8841
8842 /* FIXME <= Gen4 stride limits are bit unclear */
8843 if (mode_cmd->pitches[0] > 32768) {
8844 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8845 mode_cmd->pitches[0]);
8846 return -EINVAL;
8847 }
8848
8849 if (obj->tiling_mode != I915_TILING_NONE &&
8850 mode_cmd->pitches[0] != obj->stride) {
8851 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8852 mode_cmd->pitches[0], obj->stride);
8853 return -EINVAL;
8854 }
8855
8856 /* Reject formats not supported by any plane early. */
8857 switch (mode_cmd->pixel_format) {
8858 case DRM_FORMAT_C8:
8859 case DRM_FORMAT_RGB565:
8860 case DRM_FORMAT_XRGB8888:
8861 case DRM_FORMAT_ARGB8888:
8862 break;
8863 case DRM_FORMAT_XRGB1555:
8864 case DRM_FORMAT_ARGB1555:
8865 if (INTEL_INFO(dev)->gen > 3) {
8866 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8867 return -EINVAL;
8868 }
8869 break;
8870 case DRM_FORMAT_XBGR8888:
8871 case DRM_FORMAT_ABGR8888:
8872 case DRM_FORMAT_XRGB2101010:
8873 case DRM_FORMAT_ARGB2101010:
8874 case DRM_FORMAT_XBGR2101010:
8875 case DRM_FORMAT_ABGR2101010:
8876 if (INTEL_INFO(dev)->gen < 4) {
8877 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8878 return -EINVAL;
8879 }
8880 break;
8881 case DRM_FORMAT_YUYV:
8882 case DRM_FORMAT_UYVY:
8883 case DRM_FORMAT_YVYU:
8884 case DRM_FORMAT_VYUY:
8885 if (INTEL_INFO(dev)->gen < 5) {
8886 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8887 return -EINVAL;
8888 }
8889 break;
8890 default:
8891 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8892 return -EINVAL;
8893 }
8894
8895 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8896 if (mode_cmd->offsets[0] != 0)
8897 return -EINVAL;
8898
8899 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8900 intel_fb->obj = obj;
8901
8902 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8903 if (ret) {
8904 DRM_ERROR("framebuffer init failed %d\n", ret);
8905 return ret;
8906 }
8907
8908 return 0;
8909 }
8910
8911 static struct drm_framebuffer *
8912 intel_user_framebuffer_create(struct drm_device *dev,
8913 struct drm_file *filp,
8914 struct drm_mode_fb_cmd2 *mode_cmd)
8915 {
8916 struct drm_i915_gem_object *obj;
8917
8918 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8919 mode_cmd->handles[0]));
8920 if (&obj->base == NULL)
8921 return ERR_PTR(-ENOENT);
8922
8923 return intel_framebuffer_create(dev, mode_cmd, obj);
8924 }
8925
8926 static const struct drm_mode_config_funcs intel_mode_funcs = {
8927 .fb_create = intel_user_framebuffer_create,
8928 .output_poll_changed = intel_fb_output_poll_changed,
8929 };
8930
8931 /* Set up chip specific display functions */
8932 static void intel_init_display(struct drm_device *dev)
8933 {
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935
8936 if (HAS_DDI(dev)) {
8937 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8938 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8939 dev_priv->display.crtc_enable = haswell_crtc_enable;
8940 dev_priv->display.crtc_disable = haswell_crtc_disable;
8941 dev_priv->display.off = haswell_crtc_off;
8942 dev_priv->display.update_plane = ironlake_update_plane;
8943 } else if (HAS_PCH_SPLIT(dev)) {
8944 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8945 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8946 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8947 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8948 dev_priv->display.off = ironlake_crtc_off;
8949 dev_priv->display.update_plane = ironlake_update_plane;
8950 } else if (IS_VALLEYVIEW(dev)) {
8951 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8952 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8953 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8954 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8955 dev_priv->display.off = i9xx_crtc_off;
8956 dev_priv->display.update_plane = i9xx_update_plane;
8957 } else {
8958 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8959 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8960 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8961 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8962 dev_priv->display.off = i9xx_crtc_off;
8963 dev_priv->display.update_plane = i9xx_update_plane;
8964 }
8965
8966 /* Returns the core display clock speed */
8967 if (IS_VALLEYVIEW(dev))
8968 dev_priv->display.get_display_clock_speed =
8969 valleyview_get_display_clock_speed;
8970 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8971 dev_priv->display.get_display_clock_speed =
8972 i945_get_display_clock_speed;
8973 else if (IS_I915G(dev))
8974 dev_priv->display.get_display_clock_speed =
8975 i915_get_display_clock_speed;
8976 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8977 dev_priv->display.get_display_clock_speed =
8978 i9xx_misc_get_display_clock_speed;
8979 else if (IS_I915GM(dev))
8980 dev_priv->display.get_display_clock_speed =
8981 i915gm_get_display_clock_speed;
8982 else if (IS_I865G(dev))
8983 dev_priv->display.get_display_clock_speed =
8984 i865_get_display_clock_speed;
8985 else if (IS_I85X(dev))
8986 dev_priv->display.get_display_clock_speed =
8987 i855_get_display_clock_speed;
8988 else /* 852, 830 */
8989 dev_priv->display.get_display_clock_speed =
8990 i830_get_display_clock_speed;
8991
8992 if (HAS_PCH_SPLIT(dev)) {
8993 if (IS_GEN5(dev)) {
8994 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8995 dev_priv->display.write_eld = ironlake_write_eld;
8996 } else if (IS_GEN6(dev)) {
8997 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8998 dev_priv->display.write_eld = ironlake_write_eld;
8999 } else if (IS_IVYBRIDGE(dev)) {
9000 /* FIXME: detect B0+ stepping and use auto training */
9001 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9002 dev_priv->display.write_eld = ironlake_write_eld;
9003 dev_priv->display.modeset_global_resources =
9004 ivb_modeset_global_resources;
9005 } else if (IS_HASWELL(dev)) {
9006 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9007 dev_priv->display.write_eld = haswell_write_eld;
9008 dev_priv->display.modeset_global_resources =
9009 haswell_modeset_global_resources;
9010 }
9011 } else if (IS_G4X(dev)) {
9012 dev_priv->display.write_eld = g4x_write_eld;
9013 }
9014
9015 /* Default just returns -ENODEV to indicate unsupported */
9016 dev_priv->display.queue_flip = intel_default_queue_flip;
9017
9018 switch (INTEL_INFO(dev)->gen) {
9019 case 2:
9020 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9021 break;
9022
9023 case 3:
9024 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9025 break;
9026
9027 case 4:
9028 case 5:
9029 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9030 break;
9031
9032 case 6:
9033 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9034 break;
9035 case 7:
9036 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9037 break;
9038 }
9039 }
9040
9041 /*
9042 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9043 * resume, or other times. This quirk makes sure that's the case for
9044 * affected systems.
9045 */
9046 static void quirk_pipea_force(struct drm_device *dev)
9047 {
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049
9050 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9051 DRM_INFO("applying pipe a force quirk\n");
9052 }
9053
9054 /*
9055 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9056 */
9057 static void quirk_ssc_force_disable(struct drm_device *dev)
9058 {
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9061 DRM_INFO("applying lvds SSC disable quirk\n");
9062 }
9063
9064 /*
9065 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9066 * brightness value
9067 */
9068 static void quirk_invert_brightness(struct drm_device *dev)
9069 {
9070 struct drm_i915_private *dev_priv = dev->dev_private;
9071 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9072 DRM_INFO("applying inverted panel brightness quirk\n");
9073 }
9074
9075 struct intel_quirk {
9076 int device;
9077 int subsystem_vendor;
9078 int subsystem_device;
9079 void (*hook)(struct drm_device *dev);
9080 };
9081
9082 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9083 struct intel_dmi_quirk {
9084 void (*hook)(struct drm_device *dev);
9085 const struct dmi_system_id (*dmi_id_list)[];
9086 };
9087
9088 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9089 {
9090 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9091 return 1;
9092 }
9093
9094 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9095 {
9096 .dmi_id_list = &(const struct dmi_system_id[]) {
9097 {
9098 .callback = intel_dmi_reverse_brightness,
9099 .ident = "NCR Corporation",
9100 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9101 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9102 },
9103 },
9104 { } /* terminating entry */
9105 },
9106 .hook = quirk_invert_brightness,
9107 },
9108 };
9109
9110 static struct intel_quirk intel_quirks[] = {
9111 /* HP Mini needs pipe A force quirk (LP: #322104) */
9112 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9113
9114 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9115 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9116
9117 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9118 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9119
9120 /* 830/845 need to leave pipe A & dpll A up */
9121 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9122 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9123
9124 /* Lenovo U160 cannot use SSC on LVDS */
9125 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9126
9127 /* Sony Vaio Y cannot use SSC on LVDS */
9128 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9129
9130 /* Acer Aspire 5734Z must invert backlight brightness */
9131 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9132
9133 /* Acer/eMachines G725 */
9134 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9135
9136 /* Acer/eMachines e725 */
9137 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9138
9139 /* Acer/Packard Bell NCL20 */
9140 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9141
9142 /* Acer Aspire 4736Z */
9143 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9144 };
9145
9146 static void intel_init_quirks(struct drm_device *dev)
9147 {
9148 struct pci_dev *d = dev->pdev;
9149 int i;
9150
9151 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9152 struct intel_quirk *q = &intel_quirks[i];
9153
9154 if (d->device == q->device &&
9155 (d->subsystem_vendor == q->subsystem_vendor ||
9156 q->subsystem_vendor == PCI_ANY_ID) &&
9157 (d->subsystem_device == q->subsystem_device ||
9158 q->subsystem_device == PCI_ANY_ID))
9159 q->hook(dev);
9160 }
9161 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9162 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9163 intel_dmi_quirks[i].hook(dev);
9164 }
9165 }
9166
9167 /* Disable the VGA plane that we never use */
9168 static void i915_disable_vga(struct drm_device *dev)
9169 {
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 u8 sr1;
9172 u32 vga_reg = i915_vgacntrl_reg(dev);
9173
9174 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9175 outb(SR01, VGA_SR_INDEX);
9176 sr1 = inb(VGA_SR_DATA);
9177 outb(sr1 | 1<<5, VGA_SR_DATA);
9178 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9179 udelay(300);
9180
9181 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9182 POSTING_READ(vga_reg);
9183 }
9184
9185 void intel_modeset_init_hw(struct drm_device *dev)
9186 {
9187 intel_init_power_well(dev);
9188
9189 intel_prepare_ddi(dev);
9190
9191 intel_init_clock_gating(dev);
9192
9193 mutex_lock(&dev->struct_mutex);
9194 intel_enable_gt_powersave(dev);
9195 mutex_unlock(&dev->struct_mutex);
9196 }
9197
9198 void intel_modeset_suspend_hw(struct drm_device *dev)
9199 {
9200 intel_suspend_hw(dev);
9201 }
9202
9203 void intel_modeset_init(struct drm_device *dev)
9204 {
9205 struct drm_i915_private *dev_priv = dev->dev_private;
9206 int i, j, ret;
9207
9208 drm_mode_config_init(dev);
9209
9210 dev->mode_config.min_width = 0;
9211 dev->mode_config.min_height = 0;
9212
9213 dev->mode_config.preferred_depth = 24;
9214 dev->mode_config.prefer_shadow = 1;
9215
9216 dev->mode_config.funcs = &intel_mode_funcs;
9217
9218 intel_init_quirks(dev);
9219
9220 intel_init_pm(dev);
9221
9222 if (INTEL_INFO(dev)->num_pipes == 0)
9223 return;
9224
9225 intel_init_display(dev);
9226
9227 if (IS_GEN2(dev)) {
9228 dev->mode_config.max_width = 2048;
9229 dev->mode_config.max_height = 2048;
9230 } else if (IS_GEN3(dev)) {
9231 dev->mode_config.max_width = 4096;
9232 dev->mode_config.max_height = 4096;
9233 } else {
9234 dev->mode_config.max_width = 8192;
9235 dev->mode_config.max_height = 8192;
9236 }
9237 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9238
9239 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9240 INTEL_INFO(dev)->num_pipes,
9241 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9242
9243 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9244 intel_crtc_init(dev, i);
9245 for (j = 0; j < dev_priv->num_plane; j++) {
9246 ret = intel_plane_init(dev, i, j);
9247 if (ret)
9248 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9249 pipe_name(i), sprite_name(i, j), ret);
9250 }
9251 }
9252
9253 intel_cpu_pll_init(dev);
9254 intel_pch_pll_init(dev);
9255
9256 /* Just disable it once at startup */
9257 i915_disable_vga(dev);
9258 intel_setup_outputs(dev);
9259
9260 /* Just in case the BIOS is doing something questionable. */
9261 intel_disable_fbc(dev);
9262 }
9263
9264 static void
9265 intel_connector_break_all_links(struct intel_connector *connector)
9266 {
9267 connector->base.dpms = DRM_MODE_DPMS_OFF;
9268 connector->base.encoder = NULL;
9269 connector->encoder->connectors_active = false;
9270 connector->encoder->base.crtc = NULL;
9271 }
9272
9273 static void intel_enable_pipe_a(struct drm_device *dev)
9274 {
9275 struct intel_connector *connector;
9276 struct drm_connector *crt = NULL;
9277 struct intel_load_detect_pipe load_detect_temp;
9278
9279 /* We can't just switch on the pipe A, we need to set things up with a
9280 * proper mode and output configuration. As a gross hack, enable pipe A
9281 * by enabling the load detect pipe once. */
9282 list_for_each_entry(connector,
9283 &dev->mode_config.connector_list,
9284 base.head) {
9285 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9286 crt = &connector->base;
9287 break;
9288 }
9289 }
9290
9291 if (!crt)
9292 return;
9293
9294 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9295 intel_release_load_detect_pipe(crt, &load_detect_temp);
9296
9297
9298 }
9299
9300 static bool
9301 intel_check_plane_mapping(struct intel_crtc *crtc)
9302 {
9303 struct drm_device *dev = crtc->base.dev;
9304 struct drm_i915_private *dev_priv = dev->dev_private;
9305 u32 reg, val;
9306
9307 if (INTEL_INFO(dev)->num_pipes == 1)
9308 return true;
9309
9310 reg = DSPCNTR(!crtc->plane);
9311 val = I915_READ(reg);
9312
9313 if ((val & DISPLAY_PLANE_ENABLE) &&
9314 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9315 return false;
9316
9317 return true;
9318 }
9319
9320 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9321 {
9322 struct drm_device *dev = crtc->base.dev;
9323 struct drm_i915_private *dev_priv = dev->dev_private;
9324 u32 reg;
9325
9326 /* Clear any frame start delays used for debugging left by the BIOS */
9327 reg = PIPECONF(crtc->config.cpu_transcoder);
9328 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9329
9330 /* We need to sanitize the plane -> pipe mapping first because this will
9331 * disable the crtc (and hence change the state) if it is wrong. Note
9332 * that gen4+ has a fixed plane -> pipe mapping. */
9333 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9334 struct intel_connector *connector;
9335 bool plane;
9336
9337 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9338 crtc->base.base.id);
9339
9340 /* Pipe has the wrong plane attached and the plane is active.
9341 * Temporarily change the plane mapping and disable everything
9342 * ... */
9343 plane = crtc->plane;
9344 crtc->plane = !plane;
9345 dev_priv->display.crtc_disable(&crtc->base);
9346 crtc->plane = plane;
9347
9348 /* ... and break all links. */
9349 list_for_each_entry(connector, &dev->mode_config.connector_list,
9350 base.head) {
9351 if (connector->encoder->base.crtc != &crtc->base)
9352 continue;
9353
9354 intel_connector_break_all_links(connector);
9355 }
9356
9357 WARN_ON(crtc->active);
9358 crtc->base.enabled = false;
9359 }
9360
9361 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9362 crtc->pipe == PIPE_A && !crtc->active) {
9363 /* BIOS forgot to enable pipe A, this mostly happens after
9364 * resume. Force-enable the pipe to fix this, the update_dpms
9365 * call below we restore the pipe to the right state, but leave
9366 * the required bits on. */
9367 intel_enable_pipe_a(dev);
9368 }
9369
9370 /* Adjust the state of the output pipe according to whether we
9371 * have active connectors/encoders. */
9372 intel_crtc_update_dpms(&crtc->base);
9373
9374 if (crtc->active != crtc->base.enabled) {
9375 struct intel_encoder *encoder;
9376
9377 /* This can happen either due to bugs in the get_hw_state
9378 * functions or because the pipe is force-enabled due to the
9379 * pipe A quirk. */
9380 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9381 crtc->base.base.id,
9382 crtc->base.enabled ? "enabled" : "disabled",
9383 crtc->active ? "enabled" : "disabled");
9384
9385 crtc->base.enabled = crtc->active;
9386
9387 /* Because we only establish the connector -> encoder ->
9388 * crtc links if something is active, this means the
9389 * crtc is now deactivated. Break the links. connector
9390 * -> encoder links are only establish when things are
9391 * actually up, hence no need to break them. */
9392 WARN_ON(crtc->active);
9393
9394 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9395 WARN_ON(encoder->connectors_active);
9396 encoder->base.crtc = NULL;
9397 }
9398 }
9399 }
9400
9401 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9402 {
9403 struct intel_connector *connector;
9404 struct drm_device *dev = encoder->base.dev;
9405
9406 /* We need to check both for a crtc link (meaning that the
9407 * encoder is active and trying to read from a pipe) and the
9408 * pipe itself being active. */
9409 bool has_active_crtc = encoder->base.crtc &&
9410 to_intel_crtc(encoder->base.crtc)->active;
9411
9412 if (encoder->connectors_active && !has_active_crtc) {
9413 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9414 encoder->base.base.id,
9415 drm_get_encoder_name(&encoder->base));
9416
9417 /* Connector is active, but has no active pipe. This is
9418 * fallout from our resume register restoring. Disable
9419 * the encoder manually again. */
9420 if (encoder->base.crtc) {
9421 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9422 encoder->base.base.id,
9423 drm_get_encoder_name(&encoder->base));
9424 encoder->disable(encoder);
9425 }
9426
9427 /* Inconsistent output/port/pipe state happens presumably due to
9428 * a bug in one of the get_hw_state functions. Or someplace else
9429 * in our code, like the register restore mess on resume. Clamp
9430 * things to off as a safer default. */
9431 list_for_each_entry(connector,
9432 &dev->mode_config.connector_list,
9433 base.head) {
9434 if (connector->encoder != encoder)
9435 continue;
9436
9437 intel_connector_break_all_links(connector);
9438 }
9439 }
9440 /* Enabled encoders without active connectors will be fixed in
9441 * the crtc fixup. */
9442 }
9443
9444 void i915_redisable_vga(struct drm_device *dev)
9445 {
9446 struct drm_i915_private *dev_priv = dev->dev_private;
9447 u32 vga_reg = i915_vgacntrl_reg(dev);
9448
9449 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9450 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9451 i915_disable_vga(dev);
9452 }
9453 }
9454
9455 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9456 * and i915 state tracking structures. */
9457 void intel_modeset_setup_hw_state(struct drm_device *dev,
9458 bool force_restore)
9459 {
9460 struct drm_i915_private *dev_priv = dev->dev_private;
9461 enum pipe pipe;
9462 u32 tmp;
9463 struct drm_plane *plane;
9464 struct intel_crtc *crtc;
9465 struct intel_encoder *encoder;
9466 struct intel_connector *connector;
9467
9468 if (HAS_DDI(dev)) {
9469 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9470
9471 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9472 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9473 case TRANS_DDI_EDP_INPUT_A_ON:
9474 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9475 pipe = PIPE_A;
9476 break;
9477 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9478 pipe = PIPE_B;
9479 break;
9480 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9481 pipe = PIPE_C;
9482 break;
9483 default:
9484 /* A bogus value has been programmed, disable
9485 * the transcoder */
9486 WARN(1, "Bogus eDP source %08x\n", tmp);
9487 intel_ddi_disable_transcoder_func(dev_priv,
9488 TRANSCODER_EDP);
9489 goto setup_pipes;
9490 }
9491
9492 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9493 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9494
9495 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9496 pipe_name(pipe));
9497 }
9498 }
9499
9500 setup_pipes:
9501 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9502 base.head) {
9503 enum transcoder tmp = crtc->config.cpu_transcoder;
9504 memset(&crtc->config, 0, sizeof(crtc->config));
9505 crtc->config.cpu_transcoder = tmp;
9506
9507 crtc->active = dev_priv->display.get_pipe_config(crtc,
9508 &crtc->config);
9509
9510 crtc->base.enabled = crtc->active;
9511
9512 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9513 crtc->base.base.id,
9514 crtc->active ? "enabled" : "disabled");
9515 }
9516
9517 if (HAS_DDI(dev))
9518 intel_ddi_setup_hw_pll_state(dev);
9519
9520 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9521 base.head) {
9522 pipe = 0;
9523
9524 if (encoder->get_hw_state(encoder, &pipe)) {
9525 encoder->base.crtc =
9526 dev_priv->pipe_to_crtc_mapping[pipe];
9527 } else {
9528 encoder->base.crtc = NULL;
9529 }
9530
9531 encoder->connectors_active = false;
9532 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9533 encoder->base.base.id,
9534 drm_get_encoder_name(&encoder->base),
9535 encoder->base.crtc ? "enabled" : "disabled",
9536 pipe);
9537 }
9538
9539 list_for_each_entry(connector, &dev->mode_config.connector_list,
9540 base.head) {
9541 if (connector->get_hw_state(connector)) {
9542 connector->base.dpms = DRM_MODE_DPMS_ON;
9543 connector->encoder->connectors_active = true;
9544 connector->base.encoder = &connector->encoder->base;
9545 } else {
9546 connector->base.dpms = DRM_MODE_DPMS_OFF;
9547 connector->base.encoder = NULL;
9548 }
9549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9550 connector->base.base.id,
9551 drm_get_connector_name(&connector->base),
9552 connector->base.encoder ? "enabled" : "disabled");
9553 }
9554
9555 /* HW state is read out, now we need to sanitize this mess. */
9556 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9557 base.head) {
9558 intel_sanitize_encoder(encoder);
9559 }
9560
9561 for_each_pipe(pipe) {
9562 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9563 intel_sanitize_crtc(crtc);
9564 }
9565
9566 if (force_restore) {
9567 /*
9568 * We need to use raw interfaces for restoring state to avoid
9569 * checking (bogus) intermediate states.
9570 */
9571 for_each_pipe(pipe) {
9572 struct drm_crtc *crtc =
9573 dev_priv->pipe_to_crtc_mapping[pipe];
9574
9575 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9576 crtc->fb);
9577 }
9578 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9579 intel_plane_restore(plane);
9580
9581 i915_redisable_vga(dev);
9582 } else {
9583 intel_modeset_update_staged_output_state(dev);
9584 }
9585
9586 intel_modeset_check_state(dev);
9587
9588 drm_mode_config_reset(dev);
9589 }
9590
9591 void intel_modeset_gem_init(struct drm_device *dev)
9592 {
9593 intel_modeset_init_hw(dev);
9594
9595 intel_setup_overlay(dev);
9596
9597 intel_modeset_setup_hw_state(dev, false);
9598 }
9599
9600 void intel_modeset_cleanup(struct drm_device *dev)
9601 {
9602 struct drm_i915_private *dev_priv = dev->dev_private;
9603 struct drm_crtc *crtc;
9604 struct intel_crtc *intel_crtc;
9605
9606 /*
9607 * Interrupts and polling as the first thing to avoid creating havoc.
9608 * Too much stuff here (turning of rps, connectors, ...) would
9609 * experience fancy races otherwise.
9610 */
9611 drm_irq_uninstall(dev);
9612 cancel_work_sync(&dev_priv->hotplug_work);
9613 /*
9614 * Due to the hpd irq storm handling the hotplug work can re-arm the
9615 * poll handlers. Hence disable polling after hpd handling is shut down.
9616 */
9617 drm_kms_helper_poll_fini(dev);
9618
9619 mutex_lock(&dev->struct_mutex);
9620
9621 intel_unregister_dsm_handler();
9622
9623 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9624 /* Skip inactive CRTCs */
9625 if (!crtc->fb)
9626 continue;
9627
9628 intel_crtc = to_intel_crtc(crtc);
9629 intel_increase_pllclock(crtc);
9630 }
9631
9632 intel_disable_fbc(dev);
9633
9634 intel_disable_gt_powersave(dev);
9635
9636 ironlake_teardown_rc6(dev);
9637
9638 mutex_unlock(&dev->struct_mutex);
9639
9640 /* flush any delayed tasks or pending work */
9641 flush_scheduled_work();
9642
9643 /* destroy backlight, if any, before the connectors */
9644 intel_panel_destroy_backlight(dev);
9645
9646 drm_mode_config_cleanup(dev);
9647
9648 intel_cleanup_overlay(dev);
9649 }
9650
9651 /*
9652 * Return which encoder is currently attached for connector.
9653 */
9654 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9655 {
9656 return &intel_attached_encoder(connector)->base;
9657 }
9658
9659 void intel_connector_attach_encoder(struct intel_connector *connector,
9660 struct intel_encoder *encoder)
9661 {
9662 connector->encoder = encoder;
9663 drm_mode_connector_attach_encoder(&connector->base,
9664 &encoder->base);
9665 }
9666
9667 /*
9668 * set vga decode state - true == enable VGA decode
9669 */
9670 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9671 {
9672 struct drm_i915_private *dev_priv = dev->dev_private;
9673 u16 gmch_ctrl;
9674
9675 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9676 if (state)
9677 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9678 else
9679 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9680 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9681 return 0;
9682 }
9683
9684 #ifdef CONFIG_DEBUG_FS
9685 #include <linux/seq_file.h>
9686
9687 struct intel_display_error_state {
9688
9689 u32 power_well_driver;
9690
9691 struct intel_cursor_error_state {
9692 u32 control;
9693 u32 position;
9694 u32 base;
9695 u32 size;
9696 } cursor[I915_MAX_PIPES];
9697
9698 struct intel_pipe_error_state {
9699 enum transcoder cpu_transcoder;
9700 u32 conf;
9701 u32 source;
9702
9703 u32 htotal;
9704 u32 hblank;
9705 u32 hsync;
9706 u32 vtotal;
9707 u32 vblank;
9708 u32 vsync;
9709 } pipe[I915_MAX_PIPES];
9710
9711 struct intel_plane_error_state {
9712 u32 control;
9713 u32 stride;
9714 u32 size;
9715 u32 pos;
9716 u32 addr;
9717 u32 surface;
9718 u32 tile_offset;
9719 } plane[I915_MAX_PIPES];
9720 };
9721
9722 struct intel_display_error_state *
9723 intel_display_capture_error_state(struct drm_device *dev)
9724 {
9725 drm_i915_private_t *dev_priv = dev->dev_private;
9726 struct intel_display_error_state *error;
9727 enum transcoder cpu_transcoder;
9728 int i;
9729
9730 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9731 if (error == NULL)
9732 return NULL;
9733
9734 if (HAS_POWER_WELL(dev))
9735 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9736
9737 for_each_pipe(i) {
9738 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9739 error->pipe[i].cpu_transcoder = cpu_transcoder;
9740
9741 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9742 error->cursor[i].control = I915_READ(CURCNTR(i));
9743 error->cursor[i].position = I915_READ(CURPOS(i));
9744 error->cursor[i].base = I915_READ(CURBASE(i));
9745 } else {
9746 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9747 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9748 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9749 }
9750
9751 error->plane[i].control = I915_READ(DSPCNTR(i));
9752 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9753 if (INTEL_INFO(dev)->gen <= 3) {
9754 error->plane[i].size = I915_READ(DSPSIZE(i));
9755 error->plane[i].pos = I915_READ(DSPPOS(i));
9756 }
9757 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9758 error->plane[i].addr = I915_READ(DSPADDR(i));
9759 if (INTEL_INFO(dev)->gen >= 4) {
9760 error->plane[i].surface = I915_READ(DSPSURF(i));
9761 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9762 }
9763
9764 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9765 error->pipe[i].source = I915_READ(PIPESRC(i));
9766 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9767 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9768 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9769 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9770 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9771 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9772 }
9773
9774 /* In the code above we read the registers without checking if the power
9775 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9776 * prevent the next I915_WRITE from detecting it and printing an error
9777 * message. */
9778 if (HAS_POWER_WELL(dev))
9779 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9780
9781 return error;
9782 }
9783
9784 void
9785 intel_display_print_error_state(struct seq_file *m,
9786 struct drm_device *dev,
9787 struct intel_display_error_state *error)
9788 {
9789 int i;
9790
9791 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9792 if (HAS_POWER_WELL(dev))
9793 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9794 error->power_well_driver);
9795 for_each_pipe(i) {
9796 seq_printf(m, "Pipe [%d]:\n", i);
9797 seq_printf(m, " CPU transcoder: %c\n",
9798 transcoder_name(error->pipe[i].cpu_transcoder));
9799 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9800 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9801 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9802 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9803 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9804 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9805 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9806 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9807
9808 seq_printf(m, "Plane [%d]:\n", i);
9809 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9810 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9811 if (INTEL_INFO(dev)->gen <= 3) {
9812 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9813 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9814 }
9815 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9816 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9817 if (INTEL_INFO(dev)->gen >= 4) {
9818 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9819 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9820 }
9821
9822 seq_printf(m, "Cursor [%d]:\n", i);
9823 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9824 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9825 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9826 }
9827 }
9828 #endif
Linux kernel - Deliverables
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