2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
40 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
41 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 #define _wait_for(COND, MS, W) ({ \
52 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
55 if (time_after(jiffies, timeout__)) { \
60 if ((W) && drm_can_sleep()) { \
61 usleep_range((W)*1000, (W)*2000); \
69 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
70 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
71 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
72 DIV_ROUND_UP((US), 1000), 0)
74 #define KHz(x) (1000 * (x))
75 #define MHz(x) KHz(1000 * (x))
78 * Display related stuff
81 /* store information about an Ixxx DVO */
82 /* The i830->i865 use multiple DVOs with multiple i2cs */
83 /* the i915, i945 have a single sDVO i2c bus - which is different */
85 /* maximum connectors per crtcs in the mode set */
87 /* Maximum cursor sizes */
88 #define GEN2_CURSOR_WIDTH 64
89 #define GEN2_CURSOR_HEIGHT 64
90 #define MAX_CURSOR_WIDTH 256
91 #define MAX_CURSOR_HEIGHT 256
93 #define INTEL_I2C_BUS_DVO 1
94 #define INTEL_I2C_BUS_SDVO 2
96 /* these are outputs from the chip - integrated only
97 external chips are via DVO or SDVO output */
98 enum intel_output_type
{
99 INTEL_OUTPUT_UNUSED
= 0,
100 INTEL_OUTPUT_ANALOG
= 1,
101 INTEL_OUTPUT_DVO
= 2,
102 INTEL_OUTPUT_SDVO
= 3,
103 INTEL_OUTPUT_LVDS
= 4,
104 INTEL_OUTPUT_TVOUT
= 5,
105 INTEL_OUTPUT_HDMI
= 6,
106 INTEL_OUTPUT_DISPLAYPORT
= 7,
107 INTEL_OUTPUT_EDP
= 8,
108 INTEL_OUTPUT_DSI
= 9,
109 INTEL_OUTPUT_UNKNOWN
= 10,
110 INTEL_OUTPUT_DP_MST
= 11,
113 #define INTEL_DVO_CHIP_NONE 0
114 #define INTEL_DVO_CHIP_LVDS 1
115 #define INTEL_DVO_CHIP_TMDS 2
116 #define INTEL_DVO_CHIP_TVOUT 4
118 #define INTEL_DSI_VIDEO_MODE 0
119 #define INTEL_DSI_COMMAND_MODE 1
121 struct intel_framebuffer
{
122 struct drm_framebuffer base
;
123 struct drm_i915_gem_object
*obj
;
127 struct drm_fb_helper helper
;
128 struct intel_framebuffer
*fb
;
129 struct list_head fbdev_list
;
130 struct drm_display_mode
*our_mode
;
134 struct intel_encoder
{
135 struct drm_encoder base
;
137 * The new crtc this encoder will be driven from. Only differs from
138 * base->crtc while a modeset is in progress.
140 struct intel_crtc
*new_crtc
;
142 enum intel_output_type type
;
143 unsigned int cloneable
;
144 bool connectors_active
;
145 void (*hot_plug
)(struct intel_encoder
*);
146 bool (*compute_config
)(struct intel_encoder
*,
147 struct intel_crtc_state
*);
148 void (*pre_pll_enable
)(struct intel_encoder
*);
149 void (*pre_enable
)(struct intel_encoder
*);
150 void (*enable
)(struct intel_encoder
*);
151 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
152 void (*disable
)(struct intel_encoder
*);
153 void (*post_disable
)(struct intel_encoder
*);
154 /* Read out the current hw state of this connector, returning true if
155 * the encoder is active. If the encoder is enabled it also set the pipe
156 * it is connected to in the pipe parameter. */
157 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
158 /* Reconstructs the equivalent mode flags for the current hardware
159 * state. This must be called _after_ display->get_pipe_config has
160 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
161 * be set correctly before calling this function. */
162 void (*get_config
)(struct intel_encoder
*,
163 struct intel_crtc_state
*pipe_config
);
165 * Called during system suspend after all pending requests for the
166 * encoder are flushed (for example for DP AUX transactions) and
167 * device interrupts are disabled.
169 void (*suspend
)(struct intel_encoder
*);
171 enum hpd_pin hpd_pin
;
175 struct drm_display_mode
*fixed_mode
;
176 struct drm_display_mode
*downclock_mode
;
186 bool combination_mode
; /* gen 2/4 only */
188 struct backlight_device
*device
;
191 void (*backlight_power
)(struct intel_connector
*, bool enable
);
194 struct intel_connector
{
195 struct drm_connector base
;
197 * The fixed encoder this connector is connected to.
199 struct intel_encoder
*encoder
;
202 * The new encoder this connector will be driven. Only differs from
203 * encoder while a modeset is in progress.
205 struct intel_encoder
*new_encoder
;
207 /* Reads out the current hw, returning true if the connector is enabled
208 * and active (i.e. dpms ON state). */
209 bool (*get_hw_state
)(struct intel_connector
*);
212 * Removes all interfaces through which the connector is accessible
213 * - like sysfs, debugfs entries -, so that no new operations can be
214 * started on the connector. Also makes sure all currently pending
215 * operations finish before returing.
217 void (*unregister
)(struct intel_connector
*);
219 /* Panel info for eDP and LVDS */
220 struct intel_panel panel
;
222 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
224 struct edid
*detect_edid
;
226 /* since POLL and HPD connectors may use the same HPD line keep the native
227 state of connector->polled in case hotplug storm detection changes it */
230 void *port
; /* store this opaque as its illegal to dereference it */
232 struct intel_dp
*mst_port
;
235 typedef struct dpll
{
247 struct intel_plane_state
{
248 struct drm_plane_state base
;
251 struct drm_rect clip
;
255 * used only for sprite planes to determine when to implicitly
256 * enable/disable the primary plane
261 struct intel_initial_plane_config
{
262 struct intel_framebuffer
*fb
;
268 struct intel_crtc_state
{
269 struct drm_crtc_state base
;
272 * quirks - bitfield with hw state readout quirks
274 * For various reasons the hw state readout code might not be able to
275 * completely faithfully read out the current state. These cases are
276 * tracked with quirk flags so that fastboot and state checker can act
279 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
280 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
281 unsigned long quirks
;
283 /* Pipe source size (ie. panel fitter input size)
284 * All planes will be positioned inside this space,
285 * and get clipped at the edges. */
286 int pipe_src_w
, pipe_src_h
;
288 /* Whether to set up the PCH/FDI. Note that we never allow sharing
289 * between pch encoders and cpu encoders. */
290 bool has_pch_encoder
;
292 /* Are we sending infoframes on the attached port */
295 /* CPU Transcoder for the pipe. Currently this can only differ from the
296 * pipe on Haswell (where we have a special eDP transcoder). */
297 enum transcoder cpu_transcoder
;
300 * Use reduced/limited/broadcast rbg range, compressing from the full
301 * range fed into the crtcs.
303 bool limited_color_range
;
305 /* DP has a bunch of special case unfortunately, so mark the pipe
309 /* Whether we should send NULL infoframes. Required for audio. */
312 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
313 * has_dp_encoder is set. */
317 * Enable dithering, used when the selected pipe bpp doesn't match the
322 /* Controls for the clock computation, to override various stages. */
325 /* SDVO TV has a bunch of special case. To make multifunction encoders
326 * work correctly, we need to track this at runtime.*/
330 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
331 * required. This is set in the 2nd loop of calling encoder's
332 * ->compute_config if the first pick doesn't work out.
336 /* Settings for the intel dpll used on pretty much everything but
340 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
341 enum intel_dpll_id shared_dpll
;
344 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
345 * - enum skl_dpll on SKL
347 uint32_t ddi_pll_sel
;
349 /* Actual register state of the dpll, for shared dpll cross-checking. */
350 struct intel_dpll_hw_state dpll_hw_state
;
353 struct intel_link_m_n dp_m_n
;
355 /* m2_n2 for eDP downclock */
356 struct intel_link_m_n dp_m2_n2
;
360 * Frequence the dpll for the port should run at. Differs from the
361 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
362 * already multiplied by pixel_multiplier.
366 /* Used by SDVO (and if we ever fix it, HDMI). */
367 unsigned pixel_multiplier
;
369 /* Panel fitter controls for gen2-gen4 + VLV */
373 u32 lvds_border_bits
;
376 /* Panel fitter placement and size for Ironlake+ */
384 /* FDI configuration, only valid if has_pch_encoder is set. */
386 struct intel_link_m_n fdi_m_n
;
392 bool dp_encoder_is_mst
;
396 struct intel_pipe_wm
{
397 struct intel_wm_level wm
[5];
401 bool sprites_enabled
;
405 struct intel_mmio_flip
{
406 struct drm_i915_gem_request
*req
;
407 struct work_struct work
;
411 struct skl_wm_level wm
[8];
412 struct skl_wm_level trans_wm
;
417 * Tracking of operations that need to be performed at the beginning/end of an
418 * atomic commit, outside the atomic section where interrupts are disabled.
419 * These are generally operations that grab mutexes or might otherwise sleep
420 * and thus can't be run with interrupts disabled.
422 struct intel_crtc_atomic_commit
{
425 unsigned start_vbl_count
;
427 /* Sleepable operations to perform before commit */
430 bool pre_disable_primary
;
432 unsigned disabled_planes
;
434 /* Sleepable operations to perform after commit */
438 bool post_enable_primary
;
439 unsigned update_sprite_watermarks
;
443 struct drm_crtc base
;
446 u8 lut_r
[256], lut_g
[256], lut_b
[256];
448 * Whether the crtc and the connected output pipeline is active. Implies
449 * that crtc->enabled is set, i.e. the current mode configuration has
450 * some outputs connected to this crtc.
453 unsigned long enabled_power_domains
;
454 bool primary_enabled
; /* is the primary plane (partially) visible? */
456 struct intel_overlay
*overlay
;
457 struct intel_unpin_work
*unpin_work
;
459 atomic_t unpin_work_count
;
461 /* Display surface base address adjustement for pageflips. Note that on
462 * gen4+ this only adjusts up to a tile, offsets within a tile are
463 * handled in the hw itself (with the TILEOFF register). */
464 unsigned long dspaddr_offset
;
466 struct drm_i915_gem_object
*cursor_bo
;
467 uint32_t cursor_addr
;
468 uint32_t cursor_cntl
;
469 uint32_t cursor_size
;
470 uint32_t cursor_base
;
472 struct intel_initial_plane_config plane_config
;
473 struct intel_crtc_state
*config
;
474 struct intel_crtc_state
*new_config
;
477 /* reset counter value when the last flip was submitted */
478 unsigned int reset_counter
;
480 /* Access to these should be protected by dev_priv->irq_lock. */
481 bool cpu_fifo_underrun_disabled
;
482 bool pch_fifo_underrun_disabled
;
484 /* per-pipe watermark state */
486 /* watermarks currently being used */
487 struct intel_pipe_wm active
;
488 /* SKL wm values currently in use */
489 struct skl_pipe_wm skl_active
;
493 struct intel_mmio_flip mmio_flip
;
495 struct intel_crtc_atomic_commit atomic
;
498 struct intel_plane_wm_parameters
{
499 uint32_t horiz_pixels
;
500 uint32_t vert_pixels
;
501 uint8_t bytes_per_pixel
;
505 unsigned int rotation
;
509 struct drm_plane base
;
515 /* FIXME convert to properties */
516 struct drm_intel_sprite_colorkey ckey
;
518 /* Since we need to change the watermarks before/after
519 * enabling/disabling the planes, we need to store the parameters here
520 * as the other pieces of the struct may not reflect the values we want
521 * for the watermark calculations. Currently only Haswell uses this.
523 struct intel_plane_wm_parameters wm
;
526 * NOTE: Do not place new plane state fields here (e.g., when adding
527 * new plane properties). New runtime state should now be placed in
528 * the intel_plane_state structure and accessed via drm_plane->state.
531 void (*update_plane
)(struct drm_plane
*plane
,
532 struct drm_crtc
*crtc
,
533 struct drm_framebuffer
*fb
,
534 int crtc_x
, int crtc_y
,
535 unsigned int crtc_w
, unsigned int crtc_h
,
536 uint32_t x
, uint32_t y
,
537 uint32_t src_w
, uint32_t src_h
);
538 void (*disable_plane
)(struct drm_plane
*plane
,
539 struct drm_crtc
*crtc
);
540 int (*check_plane
)(struct drm_plane
*plane
,
541 struct intel_plane_state
*state
);
542 void (*commit_plane
)(struct drm_plane
*plane
,
543 struct intel_plane_state
*state
);
546 struct intel_watermark_params
{
547 unsigned long fifo_size
;
548 unsigned long max_wm
;
549 unsigned long default_wm
;
550 unsigned long guard_size
;
551 unsigned long cacheline_size
;
554 struct cxsr_latency
{
557 unsigned long fsb_freq
;
558 unsigned long mem_freq
;
559 unsigned long display_sr
;
560 unsigned long display_hpll_disable
;
561 unsigned long cursor_sr
;
562 unsigned long cursor_hpll_disable
;
565 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
566 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
567 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
568 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
569 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
570 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
571 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
572 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
577 uint32_t color_range
;
578 bool color_range_auto
;
581 enum hdmi_force_audio force_audio
;
582 bool rgb_quant_range_selectable
;
583 enum hdmi_picture_aspect aspect_ratio
;
584 void (*write_infoframe
)(struct drm_encoder
*encoder
,
585 enum hdmi_infoframe_type type
,
586 const void *frame
, ssize_t len
);
587 void (*set_infoframes
)(struct drm_encoder
*encoder
,
589 struct drm_display_mode
*adjusted_mode
);
590 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
);
593 struct intel_dp_mst_encoder
;
594 #define DP_MAX_DOWNSTREAM_PORTS 0x10
598 * When platform provides two set of M_N registers for dp, we can
599 * program them and switch between them incase of DRRS.
600 * But When only one such register is provided, we have to program the
601 * required divider value on that registers itself based on the DRRS state.
603 * M1_N1 : Program dp_m_n on M1_N1 registers
604 * dp_m2_n2 on M2_N2 registers (If supported)
606 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
607 * M2_N2 registers are not supported
611 /* Sets the m1_n1 and m2_n2 */
618 uint32_t aux_ch_ctl_reg
;
621 enum hdmi_force_audio force_audio
;
622 uint32_t color_range
;
623 bool color_range_auto
;
627 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
628 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
629 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
630 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
631 uint8_t num_sink_rates
;
632 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
633 struct drm_dp_aux aux
;
634 uint8_t train_set
[4];
635 int panel_power_up_delay
;
636 int panel_power_down_delay
;
637 int panel_power_cycle_delay
;
638 int backlight_on_delay
;
639 int backlight_off_delay
;
640 struct delayed_work panel_vdd_work
;
642 unsigned long last_power_cycle
;
643 unsigned long last_power_on
;
644 unsigned long last_backlight_off
;
646 struct notifier_block edp_notifier
;
649 * Pipe whose power sequencer is currently locked into
650 * this port. Only relevant on VLV/CHV.
653 struct edp_power_seq pps_delays
;
656 bool can_mst
; /* this port supports mst */
658 int active_mst_links
;
659 /* connector directly attached - won't be use for modeset in mst world */
660 struct intel_connector
*attached_connector
;
662 /* mst connector list */
663 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
664 struct drm_dp_mst_topology_mgr mst_mgr
;
666 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
668 * This function returns the value we have to program the AUX_CTL
669 * register with to kick off an AUX transaction.
671 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
674 uint32_t aux_clock_divider
);
677 struct intel_digital_port
{
678 struct intel_encoder base
;
682 struct intel_hdmi hdmi
;
683 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
686 struct intel_dp_mst_encoder
{
687 struct intel_encoder base
;
689 struct intel_digital_port
*primary
;
690 void *port
; /* store this opaque as its illegal to dereference it */
694 vlv_dport_to_channel(struct intel_digital_port
*dport
)
696 switch (dport
->port
) {
708 vlv_pipe_to_channel(enum pipe pipe
)
721 static inline struct drm_crtc
*
722 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
725 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
728 static inline struct drm_crtc
*
729 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
732 return dev_priv
->plane_to_crtc_mapping
[plane
];
735 struct intel_unpin_work
{
736 struct work_struct work
;
737 struct drm_crtc
*crtc
;
738 struct drm_framebuffer
*old_fb
;
739 struct drm_i915_gem_object
*pending_flip_obj
;
740 struct drm_pending_vblank_event
*event
;
742 #define INTEL_FLIP_INACTIVE 0
743 #define INTEL_FLIP_PENDING 1
744 #define INTEL_FLIP_COMPLETE 2
747 struct drm_i915_gem_request
*flip_queued_req
;
748 int flip_queued_vblank
;
749 int flip_ready_vblank
;
750 bool enable_stall_check
;
753 struct intel_set_config
{
754 struct drm_encoder
**save_connector_encoders
;
755 struct drm_crtc
**save_encoder_crtcs
;
756 bool *save_crtc_enabled
;
762 struct intel_load_detect_pipe
{
763 struct drm_framebuffer
*release_fb
;
764 bool load_detect_temp
;
768 static inline struct intel_encoder
*
769 intel_attached_encoder(struct drm_connector
*connector
)
771 return to_intel_connector(connector
)->encoder
;
774 static inline struct intel_digital_port
*
775 enc_to_dig_port(struct drm_encoder
*encoder
)
777 return container_of(encoder
, struct intel_digital_port
, base
.base
);
780 static inline struct intel_dp_mst_encoder
*
781 enc_to_mst(struct drm_encoder
*encoder
)
783 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
786 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
788 return &enc_to_dig_port(encoder
)->dp
;
791 static inline struct intel_digital_port
*
792 dp_to_dig_port(struct intel_dp
*intel_dp
)
794 return container_of(intel_dp
, struct intel_digital_port
, dp
);
797 static inline struct intel_digital_port
*
798 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
800 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
804 * Returns the number of planes for this pipe, ie the number of sprites + 1
805 * (primary plane). This doesn't count the cursor plane then.
807 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
809 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
812 /* intel_fifo_underrun.c */
813 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
814 enum pipe pipe
, bool enable
);
815 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
816 enum transcoder pch_transcoder
,
818 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
820 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
821 enum transcoder pch_transcoder
);
822 void i9xx_check_fifo_underruns(struct drm_i915_private
*dev_priv
);
825 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
826 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
827 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
828 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
829 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
830 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
831 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
832 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
833 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
834 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
835 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
838 * We only use drm_irq_uninstall() at unload and VT switch, so
839 * this is the only thing we need to check.
841 return dev_priv
->pm
.irqs_enabled
;
844 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
845 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
846 unsigned int pipe_mask
);
849 void intel_crt_init(struct drm_device
*dev
);
853 void intel_prepare_ddi(struct drm_device
*dev
);
854 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
855 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
856 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
857 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
858 void intel_ddi_pll_init(struct drm_device
*dev
);
859 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
860 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
861 enum transcoder cpu_transcoder
);
862 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
863 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
864 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
865 struct intel_crtc_state
*crtc_state
);
866 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
867 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
868 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
869 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
870 void intel_ddi_get_config(struct intel_encoder
*encoder
,
871 struct intel_crtc_state
*pipe_config
);
873 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
874 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
875 struct intel_crtc_state
*pipe_config
);
876 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
878 /* intel_frontbuffer.c */
879 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
880 struct intel_engine_cs
*ring
,
881 enum fb_op_origin origin
);
882 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
883 unsigned frontbuffer_bits
);
884 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
885 unsigned frontbuffer_bits
);
886 void intel_frontbuffer_flush(struct drm_device
*dev
,
887 unsigned frontbuffer_bits
);
889 * intel_frontbuffer_flip - synchronous frontbuffer flip
891 * @frontbuffer_bits: frontbuffer plane tracking bits
893 * This function gets called after scheduling a flip on @obj. This is for
894 * synchronous plane updates which will happen on the next vblank and which will
895 * not get delayed by pending gpu rendering.
897 * Can be called without any locks held.
900 void intel_frontbuffer_flip(struct drm_device
*dev
,
901 unsigned frontbuffer_bits
)
903 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
906 unsigned int intel_fb_align_height(struct drm_device
*dev
,
908 uint32_t pixel_format
,
909 uint64_t fb_format_modifier
);
910 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
);
912 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
913 uint32_t pixel_format
);
916 void intel_init_audio(struct drm_device
*dev
);
917 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
918 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
919 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
920 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
922 /* intel_display.c */
923 extern const struct drm_plane_funcs intel_plane_funcs
;
924 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
925 int intel_pch_rawclk(struct drm_device
*dev
);
926 void intel_mark_busy(struct drm_device
*dev
);
927 void intel_mark_idle(struct drm_device
*dev
);
928 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
929 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
930 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
931 void intel_encoder_destroy(struct drm_encoder
*encoder
);
932 void intel_connector_dpms(struct drm_connector
*, int mode
);
933 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
934 void intel_modeset_check_state(struct drm_device
*dev
);
935 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
936 struct intel_digital_port
*port
);
937 void intel_connector_attach_encoder(struct intel_connector
*connector
,
938 struct intel_encoder
*encoder
);
939 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
940 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
941 struct drm_crtc
*crtc
);
942 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
943 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
944 struct drm_file
*file_priv
);
945 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
947 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
949 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 drm_wait_one_vblank(dev
, pipe
);
953 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
954 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
955 struct intel_digital_port
*dport
);
956 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
957 struct drm_display_mode
*mode
,
958 struct intel_load_detect_pipe
*old
,
959 struct drm_modeset_acquire_ctx
*ctx
);
960 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
961 struct intel_load_detect_pipe
*old
,
962 struct drm_modeset_acquire_ctx
*ctx
);
963 int intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
964 struct drm_framebuffer
*fb
,
965 const struct drm_plane_state
*plane_state
,
966 struct intel_engine_cs
*pipelined
);
967 struct drm_framebuffer
*
968 __intel_framebuffer_create(struct drm_device
*dev
,
969 struct drm_mode_fb_cmd2
*mode_cmd
,
970 struct drm_i915_gem_object
*obj
);
971 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
972 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
973 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
974 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
975 int intel_prepare_plane_fb(struct drm_plane
*plane
,
976 struct drm_framebuffer
*fb
,
977 const struct drm_plane_state
*new_state
);
978 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
979 struct drm_framebuffer
*fb
,
980 const struct drm_plane_state
*old_state
);
981 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
982 const struct drm_plane_state
*state
,
983 struct drm_property
*property
,
985 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
986 struct drm_plane_state
*state
,
987 struct drm_property
*property
,
991 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
992 uint64_t fb_format_modifier
);
995 intel_rotation_90_or_270(unsigned int rotation
)
997 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1000 bool intel_wm_need_update(struct drm_plane
*plane
,
1001 struct drm_plane_state
*state
);
1003 /* shared dpll functions */
1004 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
1005 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1006 struct intel_shared_dpll
*pll
,
1008 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1009 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1010 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
1011 struct intel_crtc_state
*state
);
1012 void intel_put_shared_dpll(struct intel_crtc
*crtc
);
1014 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1015 const struct dpll
*dpll
);
1016 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1018 /* modesetting asserts */
1019 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1021 void assert_pll(struct drm_i915_private
*dev_priv
,
1022 enum pipe pipe
, bool state
);
1023 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1024 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1025 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1026 enum pipe pipe
, bool state
);
1027 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1028 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1029 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1030 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1031 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1032 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1033 unsigned int tiling_mode
,
1035 unsigned int pitch
);
1036 void intel_prepare_reset(struct drm_device
*dev
);
1037 void intel_finish_reset(struct drm_device
*dev
);
1038 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1039 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1040 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1041 struct intel_crtc_state
*pipe_config
);
1042 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1043 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1045 ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
1047 bool intel_crtc_active(struct drm_crtc
*crtc
);
1048 void hsw_enable_ips(struct intel_crtc
*crtc
);
1049 void hsw_disable_ips(struct intel_crtc
*crtc
);
1050 enum intel_display_power_domain
1051 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1052 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1053 struct intel_crtc_state
*pipe_config
);
1054 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
1055 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
1057 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1058 struct drm_i915_gem_object
*obj
);
1061 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
1062 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1063 struct intel_connector
*intel_connector
);
1064 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1065 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
1066 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1067 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1068 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1069 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1070 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1071 struct intel_crtc_state
*pipe_config
);
1072 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1073 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1075 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1076 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1077 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1078 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1079 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1080 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1081 void intel_dp_mst_suspend(struct drm_device
*dev
);
1082 void intel_dp_mst_resume(struct drm_device
*dev
);
1083 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1084 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1085 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1086 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1087 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1088 void intel_plane_destroy(struct drm_plane
*plane
);
1089 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1090 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1091 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1092 unsigned frontbuffer_bits
);
1093 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1095 /* intel_dp_mst.c */
1096 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1097 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1099 void intel_dsi_init(struct drm_device
*dev
);
1103 void intel_dvo_init(struct drm_device
*dev
);
1106 /* legacy fbdev emulation in intel_fbdev.c */
1107 #ifdef CONFIG_DRM_I915_FBDEV
1108 extern int intel_fbdev_init(struct drm_device
*dev
);
1109 extern void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
);
1110 extern void intel_fbdev_fini(struct drm_device
*dev
);
1111 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1112 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1113 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1115 static inline int intel_fbdev_init(struct drm_device
*dev
)
1120 static inline void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
)
1124 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1128 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1132 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1138 bool intel_fbc_enabled(struct drm_device
*dev
);
1139 void intel_fbc_update(struct drm_device
*dev
);
1140 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1141 void intel_fbc_disable(struct drm_device
*dev
);
1142 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1143 unsigned int frontbuffer_bits
,
1144 enum fb_op_origin origin
);
1145 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1146 unsigned int frontbuffer_bits
);
1149 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
1150 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1151 struct intel_connector
*intel_connector
);
1152 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1153 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1154 struct intel_crtc_state
*pipe_config
);
1158 void intel_lvds_init(struct drm_device
*dev
);
1159 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1163 int intel_connector_update_modes(struct drm_connector
*connector
,
1165 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1166 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1167 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1170 /* intel_overlay.c */
1171 void intel_setup_overlay(struct drm_device
*dev
);
1172 void intel_cleanup_overlay(struct drm_device
*dev
);
1173 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1174 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1175 struct drm_file
*file_priv
);
1176 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1177 struct drm_file
*file_priv
);
1178 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1182 int intel_panel_init(struct intel_panel
*panel
,
1183 struct drm_display_mode
*fixed_mode
,
1184 struct drm_display_mode
*downclock_mode
);
1185 void intel_panel_fini(struct intel_panel
*panel
);
1186 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1187 struct drm_display_mode
*adjusted_mode
);
1188 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1189 struct intel_crtc_state
*pipe_config
,
1191 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1192 struct intel_crtc_state
*pipe_config
,
1194 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1195 u32 level
, u32 max
);
1196 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1197 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1198 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1199 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1200 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1201 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1202 extern struct drm_display_mode
*intel_find_panel_downclock(
1203 struct drm_device
*dev
,
1204 struct drm_display_mode
*fixed_mode
,
1205 struct drm_connector
*connector
);
1206 void intel_backlight_register(struct drm_device
*dev
);
1207 void intel_backlight_unregister(struct drm_device
*dev
);
1211 void intel_psr_enable(struct intel_dp
*intel_dp
);
1212 void intel_psr_disable(struct intel_dp
*intel_dp
);
1213 void intel_psr_invalidate(struct drm_device
*dev
,
1214 unsigned frontbuffer_bits
);
1215 void intel_psr_flush(struct drm_device
*dev
,
1216 unsigned frontbuffer_bits
);
1217 void intel_psr_init(struct drm_device
*dev
);
1219 /* intel_runtime_pm.c */
1220 int intel_power_domains_init(struct drm_i915_private
*);
1221 void intel_power_domains_fini(struct drm_i915_private
*);
1222 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1223 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1225 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1226 enum intel_display_power_domain domain
);
1227 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1228 enum intel_display_power_domain domain
);
1229 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1230 enum intel_display_power_domain domain
);
1231 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1232 enum intel_display_power_domain domain
);
1233 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1234 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1235 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1236 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1237 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1239 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1242 void intel_init_clock_gating(struct drm_device
*dev
);
1243 void intel_suspend_hw(struct drm_device
*dev
);
1244 int ilk_wm_max_level(const struct drm_device
*dev
);
1245 void intel_update_watermarks(struct drm_crtc
*crtc
);
1246 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1247 struct drm_crtc
*crtc
,
1248 uint32_t sprite_width
,
1249 uint32_t sprite_height
,
1251 bool enabled
, bool scaled
);
1252 void intel_init_pm(struct drm_device
*dev
);
1253 void intel_pm_setup(struct drm_device
*dev
);
1254 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1255 void intel_gpu_ips_teardown(void);
1256 void intel_init_gt_powersave(struct drm_device
*dev
);
1257 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1258 void intel_enable_gt_powersave(struct drm_device
*dev
);
1259 void intel_disable_gt_powersave(struct drm_device
*dev
);
1260 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1261 void intel_reset_gt_powersave(struct drm_device
*dev
);
1262 void gen6_update_ring_freq(struct drm_device
*dev
);
1263 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1264 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1265 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1266 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
1267 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1268 void skl_wm_get_hw_state(struct drm_device
*dev
);
1269 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1270 struct skl_ddb_allocation
*ddb
/* out */);
1274 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1277 /* intel_sprite.c */
1278 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1279 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1281 int intel_plane_restore(struct drm_plane
*plane
);
1282 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1283 struct drm_file
*file_priv
);
1284 bool intel_pipe_update_start(struct intel_crtc
*crtc
,
1285 uint32_t *start_vbl_count
);
1286 void intel_pipe_update_end(struct intel_crtc
*crtc
, u32 start_vbl_count
);
1287 void intel_post_enable_primary(struct drm_crtc
*crtc
);
1288 void intel_pre_disable_primary(struct drm_crtc
*crtc
);
1291 void intel_tv_init(struct drm_device
*dev
);
1293 /* intel_atomic.c */
1294 int intel_atomic_check(struct drm_device
*dev
,
1295 struct drm_atomic_state
*state
);
1296 int intel_atomic_commit(struct drm_device
*dev
,
1297 struct drm_atomic_state
*state
,
1299 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1300 const struct drm_connector_state
*state
,
1301 struct drm_property
*property
,
1303 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1304 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1305 struct drm_crtc_state
*state
);
1306 static inline struct intel_crtc_state
*
1307 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1308 struct intel_crtc
*crtc
)
1310 struct drm_crtc_state
*crtc_state
;
1311 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1312 if (IS_ERR(crtc_state
))
1313 return ERR_PTR(PTR_ERR(crtc_state
));
1315 return to_intel_crtc_state(crtc_state
);
1318 /* intel_atomic_plane.c */
1319 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1320 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1321 void intel_plane_destroy_state(struct drm_plane
*plane
,
1322 struct drm_plane_state
*state
);
1323 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1325 #endif /* __INTEL_DRV_H__ */