2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
43 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
47 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
49 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
50 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
51 uint32_t enabled_bits
;
53 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
55 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
61 struct intel_digital_port
*intel_dig_port
=
62 container_of(encoder
, struct intel_digital_port
, base
.base
);
63 return &intel_dig_port
->hdmi
;
66 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
71 static u32
g4x_infoframe_index(enum hdmi_infoframe_type type
)
74 case HDMI_INFOFRAME_TYPE_AVI
:
75 return VIDEO_DIP_SELECT_AVI
;
76 case HDMI_INFOFRAME_TYPE_SPD
:
77 return VIDEO_DIP_SELECT_SPD
;
78 case HDMI_INFOFRAME_TYPE_VENDOR
:
79 return VIDEO_DIP_SELECT_VENDOR
;
86 static u32
g4x_infoframe_enable(enum hdmi_infoframe_type type
)
89 case HDMI_INFOFRAME_TYPE_AVI
:
90 return VIDEO_DIP_ENABLE_AVI
;
91 case HDMI_INFOFRAME_TYPE_SPD
:
92 return VIDEO_DIP_ENABLE_SPD
;
93 case HDMI_INFOFRAME_TYPE_VENDOR
:
94 return VIDEO_DIP_ENABLE_VENDOR
;
101 static u32
hsw_infoframe_enable(enum hdmi_infoframe_type type
)
104 case HDMI_INFOFRAME_TYPE_AVI
:
105 return VIDEO_DIP_ENABLE_AVI_HSW
;
106 case HDMI_INFOFRAME_TYPE_SPD
:
107 return VIDEO_DIP_ENABLE_SPD_HSW
;
108 case HDMI_INFOFRAME_TYPE_VENDOR
:
109 return VIDEO_DIP_ENABLE_VS_HSW
;
117 hsw_dip_data_reg(struct drm_i915_private
*dev_priv
,
118 enum transcoder cpu_transcoder
,
119 enum hdmi_infoframe_type type
,
123 case HDMI_INFOFRAME_TYPE_AVI
:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
, i
);
125 case HDMI_INFOFRAME_TYPE_SPD
:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
, i
);
127 case HDMI_INFOFRAME_TYPE_VENDOR
:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
, i
);
131 return INVALID_MMIO_REG
;
135 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
136 enum hdmi_infoframe_type type
,
137 const void *frame
, ssize_t len
)
139 const uint32_t *data
= frame
;
140 struct drm_device
*dev
= encoder
->dev
;
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
142 u32 val
= I915_READ(VIDEO_DIP_CTL
);
145 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
147 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
148 val
|= g4x_infoframe_index(type
);
150 val
&= ~g4x_infoframe_enable(type
);
152 I915_WRITE(VIDEO_DIP_CTL
, val
);
155 for (i
= 0; i
< len
; i
+= 4) {
156 I915_WRITE(VIDEO_DIP_DATA
, *data
);
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
161 I915_WRITE(VIDEO_DIP_DATA
, 0);
164 val
|= g4x_infoframe_enable(type
);
165 val
&= ~VIDEO_DIP_FREQ_MASK
;
166 val
|= VIDEO_DIP_FREQ_VSYNC
;
168 I915_WRITE(VIDEO_DIP_CTL
, val
);
169 POSTING_READ(VIDEO_DIP_CTL
);
172 static bool g4x_infoframe_enabled(struct drm_encoder
*encoder
,
173 const struct intel_crtc_state
*pipe_config
)
175 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
176 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
177 u32 val
= I915_READ(VIDEO_DIP_CTL
);
179 if ((val
& VIDEO_DIP_ENABLE
) == 0)
182 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
185 return val
& (VIDEO_DIP_ENABLE_AVI
|
186 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
189 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
190 enum hdmi_infoframe_type type
,
191 const void *frame
, ssize_t len
)
193 const uint32_t *data
= frame
;
194 struct drm_device
*dev
= encoder
->dev
;
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
197 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
198 u32 val
= I915_READ(reg
);
201 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
203 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
204 val
|= g4x_infoframe_index(type
);
206 val
&= ~g4x_infoframe_enable(type
);
208 I915_WRITE(reg
, val
);
211 for (i
= 0; i
< len
; i
+= 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
220 val
|= g4x_infoframe_enable(type
);
221 val
&= ~VIDEO_DIP_FREQ_MASK
;
222 val
|= VIDEO_DIP_FREQ_VSYNC
;
224 I915_WRITE(reg
, val
);
228 static bool ibx_infoframe_enabled(struct drm_encoder
*encoder
,
229 const struct intel_crtc_state
*pipe_config
)
231 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
232 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
233 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
234 i915_reg_t reg
= TVIDEO_DIP_CTL(pipe
);
235 u32 val
= I915_READ(reg
);
237 if ((val
& VIDEO_DIP_ENABLE
) == 0)
240 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
243 return val
& (VIDEO_DIP_ENABLE_AVI
|
244 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
245 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
248 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
249 enum hdmi_infoframe_type type
,
250 const void *frame
, ssize_t len
)
252 const uint32_t *data
= frame
;
253 struct drm_device
*dev
= encoder
->dev
;
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
256 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
257 u32 val
= I915_READ(reg
);
260 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
262 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
263 val
|= g4x_infoframe_index(type
);
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
268 val
&= ~g4x_infoframe_enable(type
);
270 I915_WRITE(reg
, val
);
273 for (i
= 0; i
< len
; i
+= 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
282 val
|= g4x_infoframe_enable(type
);
283 val
&= ~VIDEO_DIP_FREQ_MASK
;
284 val
|= VIDEO_DIP_FREQ_VSYNC
;
286 I915_WRITE(reg
, val
);
290 static bool cpt_infoframe_enabled(struct drm_encoder
*encoder
,
291 const struct intel_crtc_state
*pipe_config
)
293 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
294 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
295 u32 val
= I915_READ(TVIDEO_DIP_CTL(pipe
));
297 if ((val
& VIDEO_DIP_ENABLE
) == 0)
300 return val
& (VIDEO_DIP_ENABLE_AVI
|
301 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
302 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
305 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
306 enum hdmi_infoframe_type type
,
307 const void *frame
, ssize_t len
)
309 const uint32_t *data
= frame
;
310 struct drm_device
*dev
= encoder
->dev
;
311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
312 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
313 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
314 u32 val
= I915_READ(reg
);
317 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
319 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
320 val
|= g4x_infoframe_index(type
);
322 val
&= ~g4x_infoframe_enable(type
);
324 I915_WRITE(reg
, val
);
327 for (i
= 0; i
< len
; i
+= 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
336 val
|= g4x_infoframe_enable(type
);
337 val
&= ~VIDEO_DIP_FREQ_MASK
;
338 val
|= VIDEO_DIP_FREQ_VSYNC
;
340 I915_WRITE(reg
, val
);
344 static bool vlv_infoframe_enabled(struct drm_encoder
*encoder
,
345 const struct intel_crtc_state
*pipe_config
)
347 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
348 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
349 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
350 u32 val
= I915_READ(VLV_TVIDEO_DIP_CTL(pipe
));
352 if ((val
& VIDEO_DIP_ENABLE
) == 0)
355 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
358 return val
& (VIDEO_DIP_ENABLE_AVI
|
359 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
360 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
363 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
364 enum hdmi_infoframe_type type
,
365 const void *frame
, ssize_t len
)
367 const uint32_t *data
= frame
;
368 struct drm_device
*dev
= encoder
->dev
;
369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
370 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
371 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
372 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
375 u32 val
= I915_READ(ctl_reg
);
377 data_reg
= hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, 0);
379 val
&= ~hsw_infoframe_enable(type
);
380 I915_WRITE(ctl_reg
, val
);
383 for (i
= 0; i
< len
; i
+= 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
385 type
, i
>> 2), *data
);
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
394 val
|= hsw_infoframe_enable(type
);
395 I915_WRITE(ctl_reg
, val
);
396 POSTING_READ(ctl_reg
);
399 static bool hsw_infoframe_enabled(struct drm_encoder
*encoder
,
400 const struct intel_crtc_state
*pipe_config
)
402 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
403 u32 val
= I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config
->cpu_transcoder
));
405 return val
& (VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
406 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
407 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
421 * (HB is Header Byte, DB is Data Byte)
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
427 static void intel_write_infoframe(struct drm_encoder
*encoder
,
428 union hdmi_infoframe
*frame
)
430 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
431 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
434 /* see comment above for the reason for this offset */
435 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer
[0] = buffer
[1];
441 buffer
[1] = buffer
[2];
442 buffer
[2] = buffer
[3];
446 intel_hdmi
->write_infoframe(encoder
, frame
->any
.type
, buffer
, len
);
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
450 const struct drm_display_mode
*adjusted_mode
)
452 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
453 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
454 union hdmi_infoframe frame
;
457 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
460 DRM_ERROR("couldn't fill AVI infoframe\n");
464 if (intel_hdmi
->rgb_quant_range_selectable
) {
465 if (intel_crtc
->config
->limited_color_range
)
466 frame
.avi
.quantization_range
=
467 HDMI_QUANTIZATION_RANGE_LIMITED
;
469 frame
.avi
.quantization_range
=
470 HDMI_QUANTIZATION_RANGE_FULL
;
473 intel_write_infoframe(encoder
, &frame
);
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
478 union hdmi_infoframe frame
;
481 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
483 DRM_ERROR("couldn't fill SPD infoframe\n");
487 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
489 intel_write_infoframe(encoder
, &frame
);
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
494 const struct drm_display_mode
*adjusted_mode
)
496 union hdmi_infoframe frame
;
499 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
504 intel_write_infoframe(encoder
, &frame
);
507 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
509 const struct drm_display_mode
*adjusted_mode
)
511 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
512 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
513 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
514 i915_reg_t reg
= VIDEO_DIP_CTL
;
515 u32 val
= I915_READ(reg
);
516 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
518 assert_hdmi_port_disabled(intel_hdmi
);
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
529 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
532 if (!(val
& VIDEO_DIP_ENABLE
))
534 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
539 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
540 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
541 I915_WRITE(reg
, val
);
546 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
547 if (val
& VIDEO_DIP_ENABLE
) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
552 val
&= ~VIDEO_DIP_PORT_MASK
;
556 val
|= VIDEO_DIP_ENABLE
;
557 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
558 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
560 I915_WRITE(reg
, val
);
563 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
564 intel_hdmi_set_spd_infoframe(encoder
);
565 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
568 static bool hdmi_sink_is_deep_color(struct drm_encoder
*encoder
)
570 struct drm_device
*dev
= encoder
->dev
;
571 struct drm_connector
*connector
;
573 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
580 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
581 if (connector
->encoder
== encoder
)
582 return connector
->display_info
.bpc
> 8;
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
597 static bool gcp_default_phase_possible(int pipe_bpp
,
598 const struct drm_display_mode
*mode
)
600 unsigned int pixels_per_group
;
604 /* 4 pixels in 5 clocks */
605 pixels_per_group
= 4;
608 /* 2 pixels in 3 clocks */
609 pixels_per_group
= 2;
612 /* 1 pixel in 2 clocks */
613 pixels_per_group
= 1;
616 /* phase information not relevant for 8bpc */
620 return mode
->crtc_hdisplay
% pixels_per_group
== 0 &&
621 mode
->crtc_htotal
% pixels_per_group
== 0 &&
622 mode
->crtc_hblank_start
% pixels_per_group
== 0 &&
623 mode
->crtc_hblank_end
% pixels_per_group
== 0 &&
624 mode
->crtc_hsync_start
% pixels_per_group
== 0 &&
625 mode
->crtc_hsync_end
% pixels_per_group
== 0 &&
626 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0 ||
627 mode
->crtc_htotal
/2 % pixels_per_group
== 0);
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder
*encoder
)
632 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
633 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
637 if (HAS_DDI(dev_priv
))
638 reg
= HSW_TVIDEO_DIP_GCP(crtc
->config
->cpu_transcoder
);
639 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
640 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
641 else if (HAS_PCH_SPLIT(dev_priv
->dev
))
642 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder
))
648 val
|= GCP_COLOR_INDICATION
;
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc
->config
->pipe_bpp
,
652 &crtc
->config
->base
.adjusted_mode
))
653 val
|= GCP_DEFAULT_PHASE_ENABLE
;
655 I915_WRITE(reg
, val
);
660 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
662 const struct drm_display_mode
*adjusted_mode
)
664 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
665 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
666 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
667 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
668 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
669 u32 val
= I915_READ(reg
);
670 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
672 assert_hdmi_port_disabled(intel_hdmi
);
674 /* See the big comment in g4x_set_infoframes() */
675 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
678 if (!(val
& VIDEO_DIP_ENABLE
))
680 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
681 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
682 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
683 I915_WRITE(reg
, val
);
688 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
689 WARN(val
& VIDEO_DIP_ENABLE
,
690 "DIP already enabled on port %c\n",
691 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
692 val
&= ~VIDEO_DIP_PORT_MASK
;
696 val
|= VIDEO_DIP_ENABLE
;
697 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
698 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
699 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
701 if (intel_hdmi_set_gcp_infoframe(encoder
))
702 val
|= VIDEO_DIP_ENABLE_GCP
;
704 I915_WRITE(reg
, val
);
707 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
708 intel_hdmi_set_spd_infoframe(encoder
);
709 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
712 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
714 const struct drm_display_mode
*adjusted_mode
)
716 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
717 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
718 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
719 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
720 u32 val
= I915_READ(reg
);
722 assert_hdmi_port_disabled(intel_hdmi
);
724 /* See the big comment in g4x_set_infoframes() */
725 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
728 if (!(val
& VIDEO_DIP_ENABLE
))
730 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
731 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
732 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
733 I915_WRITE(reg
, val
);
738 /* Set both together, unset both together: see the spec. */
739 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
740 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
741 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
743 if (intel_hdmi_set_gcp_infoframe(encoder
))
744 val
|= VIDEO_DIP_ENABLE_GCP
;
746 I915_WRITE(reg
, val
);
749 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
750 intel_hdmi_set_spd_infoframe(encoder
);
751 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
754 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
756 const struct drm_display_mode
*adjusted_mode
)
758 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
759 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
760 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
761 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
762 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
763 u32 val
= I915_READ(reg
);
764 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
766 assert_hdmi_port_disabled(intel_hdmi
);
768 /* See the big comment in g4x_set_infoframes() */
769 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
772 if (!(val
& VIDEO_DIP_ENABLE
))
774 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
775 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
776 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
777 I915_WRITE(reg
, val
);
782 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
783 WARN(val
& VIDEO_DIP_ENABLE
,
784 "DIP already enabled on port %c\n",
785 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
786 val
&= ~VIDEO_DIP_PORT_MASK
;
790 val
|= VIDEO_DIP_ENABLE
;
791 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
792 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
793 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
795 if (intel_hdmi_set_gcp_infoframe(encoder
))
796 val
|= VIDEO_DIP_ENABLE_GCP
;
798 I915_WRITE(reg
, val
);
801 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
802 intel_hdmi_set_spd_infoframe(encoder
);
803 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
806 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
808 const struct drm_display_mode
*adjusted_mode
)
810 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
811 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
812 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
813 i915_reg_t reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
->cpu_transcoder
);
814 u32 val
= I915_READ(reg
);
816 assert_hdmi_port_disabled(intel_hdmi
);
818 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
819 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
820 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
823 I915_WRITE(reg
, val
);
828 if (intel_hdmi_set_gcp_infoframe(encoder
))
829 val
|= VIDEO_DIP_ENABLE_GCP_HSW
;
831 I915_WRITE(reg
, val
);
834 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
835 intel_hdmi_set_spd_infoframe(encoder
);
836 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
839 static void intel_hdmi_prepare(struct intel_encoder
*encoder
)
841 struct drm_device
*dev
= encoder
->base
.dev
;
842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
843 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
844 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
845 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
848 hdmi_val
= SDVO_ENCODING_HDMI
;
849 if (!HAS_PCH_SPLIT(dev
) && crtc
->config
->limited_color_range
)
850 hdmi_val
|= HDMI_COLOR_RANGE_16_235
;
851 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
852 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
853 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
854 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
856 if (crtc
->config
->pipe_bpp
> 24)
857 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
859 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
861 if (crtc
->config
->has_hdmi_sink
)
862 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
864 if (HAS_PCH_CPT(dev
))
865 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
866 else if (IS_CHERRYVIEW(dev
))
867 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
869 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
871 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
872 POSTING_READ(intel_hdmi
->hdmi_reg
);
875 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
878 struct drm_device
*dev
= encoder
->base
.dev
;
879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
880 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
881 enum intel_display_power_domain power_domain
;
884 power_domain
= intel_display_port_power_domain(encoder
);
885 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
888 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
890 if (!(tmp
& SDVO_ENABLE
))
893 if (HAS_PCH_CPT(dev
))
894 *pipe
= PORT_TO_PIPE_CPT(tmp
);
895 else if (IS_CHERRYVIEW(dev
))
896 *pipe
= SDVO_PORT_TO_PIPE_CHV(tmp
);
898 *pipe
= PORT_TO_PIPE(tmp
);
903 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
904 struct intel_crtc_state
*pipe_config
)
906 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
907 struct drm_device
*dev
= encoder
->base
.dev
;
908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
912 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
914 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
915 flags
|= DRM_MODE_FLAG_PHSYNC
;
917 flags
|= DRM_MODE_FLAG_NHSYNC
;
919 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
920 flags
|= DRM_MODE_FLAG_PVSYNC
;
922 flags
|= DRM_MODE_FLAG_NVSYNC
;
924 if (tmp
& HDMI_MODE_SELECT_HDMI
)
925 pipe_config
->has_hdmi_sink
= true;
927 if (intel_hdmi
->infoframe_enabled(&encoder
->base
, pipe_config
))
928 pipe_config
->has_infoframe
= true;
930 if (tmp
& SDVO_AUDIO_ENABLE
)
931 pipe_config
->has_audio
= true;
933 if (!HAS_PCH_SPLIT(dev
) &&
934 tmp
& HDMI_COLOR_RANGE_16_235
)
935 pipe_config
->limited_color_range
= true;
937 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
939 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
940 dotclock
= pipe_config
->port_clock
* 2 / 3;
942 dotclock
= pipe_config
->port_clock
;
944 if (pipe_config
->pixel_multiplier
)
945 dotclock
/= pipe_config
->pixel_multiplier
;
947 if (HAS_PCH_SPLIT(dev_priv
->dev
))
948 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
950 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
953 static void intel_enable_hdmi_audio(struct intel_encoder
*encoder
)
955 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
957 WARN_ON(!crtc
->config
->has_hdmi_sink
);
958 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
959 pipe_name(crtc
->pipe
));
960 intel_audio_codec_enable(encoder
);
963 static void g4x_enable_hdmi(struct intel_encoder
*encoder
)
965 struct drm_device
*dev
= encoder
->base
.dev
;
966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
967 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
968 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
971 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
974 if (crtc
->config
->has_audio
)
975 temp
|= SDVO_AUDIO_ENABLE
;
977 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
978 POSTING_READ(intel_hdmi
->hdmi_reg
);
980 if (crtc
->config
->has_audio
)
981 intel_enable_hdmi_audio(encoder
);
984 static void ibx_enable_hdmi(struct intel_encoder
*encoder
)
986 struct drm_device
*dev
= encoder
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
989 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
992 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
995 if (crtc
->config
->has_audio
)
996 temp
|= SDVO_AUDIO_ENABLE
;
999 * HW workaround, need to write this twice for issue
1000 * that may result in first write getting masked.
1002 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1003 POSTING_READ(intel_hdmi
->hdmi_reg
);
1004 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1005 POSTING_READ(intel_hdmi
->hdmi_reg
);
1008 * HW workaround, need to toggle enable bit off and on
1009 * for 12bpc with pixel repeat.
1011 * FIXME: BSpec says this should be done at the end of
1012 * of the modeset sequence, so not sure if this isn't too soon.
1014 if (crtc
->config
->pipe_bpp
> 24 &&
1015 crtc
->config
->pixel_multiplier
> 1) {
1016 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
1017 POSTING_READ(intel_hdmi
->hdmi_reg
);
1020 * HW workaround, need to write this twice for issue
1021 * that may result in first write getting masked.
1023 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1024 POSTING_READ(intel_hdmi
->hdmi_reg
);
1025 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1026 POSTING_READ(intel_hdmi
->hdmi_reg
);
1029 if (crtc
->config
->has_audio
)
1030 intel_enable_hdmi_audio(encoder
);
1033 static void cpt_enable_hdmi(struct intel_encoder
*encoder
)
1035 struct drm_device
*dev
= encoder
->base
.dev
;
1036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1037 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1038 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1039 enum pipe pipe
= crtc
->pipe
;
1042 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1044 temp
|= SDVO_ENABLE
;
1045 if (crtc
->config
->has_audio
)
1046 temp
|= SDVO_AUDIO_ENABLE
;
1049 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1051 * The procedure for 12bpc is as follows:
1052 * 1. disable HDMI clock gating
1053 * 2. enable HDMI with 8bpc
1054 * 3. enable HDMI with 12bpc
1055 * 4. enable HDMI clock gating
1058 if (crtc
->config
->pipe_bpp
> 24) {
1059 I915_WRITE(TRANS_CHICKEN1(pipe
),
1060 I915_READ(TRANS_CHICKEN1(pipe
)) |
1061 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1063 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1064 temp
|= SDVO_COLOR_FORMAT_8bpc
;
1067 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1068 POSTING_READ(intel_hdmi
->hdmi_reg
);
1070 if (crtc
->config
->pipe_bpp
> 24) {
1071 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1072 temp
|= HDMI_COLOR_FORMAT_12bpc
;
1074 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1075 POSTING_READ(intel_hdmi
->hdmi_reg
);
1077 I915_WRITE(TRANS_CHICKEN1(pipe
),
1078 I915_READ(TRANS_CHICKEN1(pipe
)) &
1079 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1082 if (crtc
->config
->has_audio
)
1083 intel_enable_hdmi_audio(encoder
);
1086 static void vlv_enable_hdmi(struct intel_encoder
*encoder
)
1090 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
1092 struct drm_device
*dev
= encoder
->base
.dev
;
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1095 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1098 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1100 temp
&= ~(SDVO_ENABLE
| SDVO_AUDIO_ENABLE
);
1101 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1102 POSTING_READ(intel_hdmi
->hdmi_reg
);
1105 * HW workaround for IBX, we need to move the port
1106 * to transcoder A after disabling it to allow the
1107 * matching DP port to be enabled on transcoder A.
1109 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
) {
1111 * We get CPU/PCH FIFO underruns on the other pipe when
1112 * doing the workaround. Sweep them under the rug.
1114 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1115 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1117 temp
&= ~SDVO_PIPE_B_SELECT
;
1118 temp
|= SDVO_ENABLE
;
1120 * HW workaround, need to write this twice for issue
1121 * that may result in first write getting masked.
1123 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1124 POSTING_READ(intel_hdmi
->hdmi_reg
);
1125 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1126 POSTING_READ(intel_hdmi
->hdmi_reg
);
1128 temp
&= ~SDVO_ENABLE
;
1129 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1130 POSTING_READ(intel_hdmi
->hdmi_reg
);
1132 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
1133 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1134 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1137 intel_hdmi
->set_infoframes(&encoder
->base
, false, NULL
);
1140 static void g4x_disable_hdmi(struct intel_encoder
*encoder
)
1142 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1144 if (crtc
->config
->has_audio
)
1145 intel_audio_codec_disable(encoder
);
1147 intel_disable_hdmi(encoder
);
1150 static void pch_disable_hdmi(struct intel_encoder
*encoder
)
1152 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1154 if (crtc
->config
->has_audio
)
1155 intel_audio_codec_disable(encoder
);
1158 static void pch_post_disable_hdmi(struct intel_encoder
*encoder
)
1160 intel_disable_hdmi(encoder
);
1163 static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi
, bool respect_dvi_limit
)
1165 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
1167 if ((respect_dvi_limit
&& !hdmi
->has_hdmi_sink
) || IS_G4X(dev
))
1169 else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8)
1175 static enum drm_mode_status
1176 hdmi_port_clock_valid(struct intel_hdmi
*hdmi
,
1177 int clock
, bool respect_dvi_limit
)
1179 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
1182 return MODE_CLOCK_LOW
;
1183 if (clock
> hdmi_port_clock_limit(hdmi
, respect_dvi_limit
))
1184 return MODE_CLOCK_HIGH
;
1186 /* BXT DPLL can't generate 223-240 MHz */
1187 if (IS_BROXTON(dev
) && clock
> 223333 && clock
< 240000)
1188 return MODE_CLOCK_RANGE
;
1190 /* CHV DPLL can't generate 216-240 MHz */
1191 if (IS_CHERRYVIEW(dev
) && clock
> 216000 && clock
< 240000)
1192 return MODE_CLOCK_RANGE
;
1197 static enum drm_mode_status
1198 intel_hdmi_mode_valid(struct drm_connector
*connector
,
1199 struct drm_display_mode
*mode
)
1201 struct intel_hdmi
*hdmi
= intel_attached_hdmi(connector
);
1202 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
1203 enum drm_mode_status status
;
1206 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1207 return MODE_NO_DBLESCAN
;
1209 clock
= mode
->clock
;
1210 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1213 /* check if we can do 8bpc */
1214 status
= hdmi_port_clock_valid(hdmi
, clock
, true);
1216 /* if we can't do 8bpc we may still be able to do 12bpc */
1217 if (!HAS_GMCH_DISPLAY(dev
) && status
!= MODE_OK
)
1218 status
= hdmi_port_clock_valid(hdmi
, clock
* 3 / 2, true);
1223 static bool hdmi_12bpc_possible(struct intel_crtc_state
*crtc_state
)
1225 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
1226 struct drm_atomic_state
*state
;
1227 struct intel_encoder
*encoder
;
1228 struct drm_connector
*connector
;
1229 struct drm_connector_state
*connector_state
;
1230 int count
= 0, count_hdmi
= 0;
1233 if (HAS_GMCH_DISPLAY(dev
))
1236 state
= crtc_state
->base
.state
;
1238 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
1239 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
1242 encoder
= to_intel_encoder(connector_state
->best_encoder
);
1244 count_hdmi
+= encoder
->type
== INTEL_OUTPUT_HDMI
;
1249 * HDMI 12bpc affects the clocks, so it's only possible
1250 * when not cloning with other encoder types.
1252 return count_hdmi
> 0 && count_hdmi
== count
;
1255 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1256 struct intel_crtc_state
*pipe_config
)
1258 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1259 struct drm_device
*dev
= encoder
->base
.dev
;
1260 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1261 int clock_8bpc
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1262 int clock_12bpc
= clock_8bpc
* 3 / 2;
1265 pipe_config
->has_hdmi_sink
= intel_hdmi
->has_hdmi_sink
;
1267 if (pipe_config
->has_hdmi_sink
)
1268 pipe_config
->has_infoframe
= true;
1270 if (intel_hdmi
->color_range_auto
) {
1271 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1272 pipe_config
->limited_color_range
=
1273 pipe_config
->has_hdmi_sink
&&
1274 drm_match_cea_mode(adjusted_mode
) > 1;
1276 pipe_config
->limited_color_range
=
1277 intel_hdmi
->limited_color_range
;
1280 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
) {
1281 pipe_config
->pixel_multiplier
= 2;
1286 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
1287 pipe_config
->has_pch_encoder
= true;
1289 if (pipe_config
->has_hdmi_sink
&& intel_hdmi
->has_audio
)
1290 pipe_config
->has_audio
= true;
1293 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1294 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1295 * outputs. We also need to check that the higher clock still fits
1298 if (pipe_config
->pipe_bpp
> 8*3 && pipe_config
->has_hdmi_sink
&&
1299 hdmi_port_clock_valid(intel_hdmi
, clock_12bpc
, false) == MODE_OK
&&
1300 hdmi_12bpc_possible(pipe_config
)) {
1301 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1304 /* Need to adjust the port link by 1.5x for 12bpc. */
1305 pipe_config
->port_clock
= clock_12bpc
;
1307 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1310 pipe_config
->port_clock
= clock_8bpc
;
1313 if (!pipe_config
->bw_constrained
) {
1314 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
1315 pipe_config
->pipe_bpp
= desired_bpp
;
1318 if (hdmi_port_clock_valid(intel_hdmi
, pipe_config
->port_clock
,
1319 false) != MODE_OK
) {
1320 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1324 /* Set user selected PAR to incoming mode's member */
1325 adjusted_mode
->picture_aspect_ratio
= intel_hdmi
->aspect_ratio
;
1331 intel_hdmi_unset_edid(struct drm_connector
*connector
)
1333 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1335 intel_hdmi
->has_hdmi_sink
= false;
1336 intel_hdmi
->has_audio
= false;
1337 intel_hdmi
->rgb_quant_range_selectable
= false;
1339 kfree(to_intel_connector(connector
)->detect_edid
);
1340 to_intel_connector(connector
)->detect_edid
= NULL
;
1344 intel_hdmi_set_edid(struct drm_connector
*connector
, bool force
)
1346 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1347 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1348 struct edid
*edid
= NULL
;
1349 bool connected
= false;
1352 intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
1354 edid
= drm_get_edid(connector
,
1355 intel_gmbus_get_adapter(dev_priv
,
1356 intel_hdmi
->ddc_bus
));
1358 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
);
1361 to_intel_connector(connector
)->detect_edid
= edid
;
1362 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
1363 intel_hdmi
->rgb_quant_range_selectable
=
1364 drm_rgb_quant_range_selectable(edid
);
1366 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
1367 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
1368 intel_hdmi
->has_audio
=
1369 intel_hdmi
->force_audio
== HDMI_AUDIO_ON
;
1371 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
1372 intel_hdmi
->has_hdmi_sink
=
1373 drm_detect_hdmi_monitor(edid
);
1381 static enum drm_connector_status
1382 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
1384 enum drm_connector_status status
;
1385 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1386 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1387 bool live_status
= false;
1390 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1391 connector
->base
.id
, connector
->name
);
1393 intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
1395 for (try = 0; !live_status
&& try < 9; try++) {
1398 live_status
= intel_digital_port_connected(dev_priv
,
1399 hdmi_to_dig_port(intel_hdmi
));
1403 DRM_DEBUG_KMS("Live status not up!");
1405 intel_hdmi_unset_edid(connector
);
1407 if (intel_hdmi_set_edid(connector
, live_status
)) {
1408 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1410 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1411 status
= connector_status_connected
;
1413 status
= connector_status_disconnected
;
1415 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
);
1421 intel_hdmi_force(struct drm_connector
*connector
)
1423 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1425 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1426 connector
->base
.id
, connector
->name
);
1428 intel_hdmi_unset_edid(connector
);
1430 if (connector
->status
!= connector_status_connected
)
1433 intel_hdmi_set_edid(connector
, true);
1434 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1437 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
1441 edid
= to_intel_connector(connector
)->detect_edid
;
1445 return intel_connector_update_modes(connector
, edid
);
1449 intel_hdmi_detect_audio(struct drm_connector
*connector
)
1451 bool has_audio
= false;
1454 edid
= to_intel_connector(connector
)->detect_edid
;
1455 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
)
1456 has_audio
= drm_detect_monitor_audio(edid
);
1462 intel_hdmi_set_property(struct drm_connector
*connector
,
1463 struct drm_property
*property
,
1466 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1467 struct intel_digital_port
*intel_dig_port
=
1468 hdmi_to_dig_port(intel_hdmi
);
1469 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1472 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1476 if (property
== dev_priv
->force_audio_property
) {
1477 enum hdmi_force_audio i
= val
;
1480 if (i
== intel_hdmi
->force_audio
)
1483 intel_hdmi
->force_audio
= i
;
1485 if (i
== HDMI_AUDIO_AUTO
)
1486 has_audio
= intel_hdmi_detect_audio(connector
);
1488 has_audio
= (i
== HDMI_AUDIO_ON
);
1490 if (i
== HDMI_AUDIO_OFF_DVI
)
1491 intel_hdmi
->has_hdmi_sink
= 0;
1493 intel_hdmi
->has_audio
= has_audio
;
1497 if (property
== dev_priv
->broadcast_rgb_property
) {
1498 bool old_auto
= intel_hdmi
->color_range_auto
;
1499 bool old_range
= intel_hdmi
->limited_color_range
;
1502 case INTEL_BROADCAST_RGB_AUTO
:
1503 intel_hdmi
->color_range_auto
= true;
1505 case INTEL_BROADCAST_RGB_FULL
:
1506 intel_hdmi
->color_range_auto
= false;
1507 intel_hdmi
->limited_color_range
= false;
1509 case INTEL_BROADCAST_RGB_LIMITED
:
1510 intel_hdmi
->color_range_auto
= false;
1511 intel_hdmi
->limited_color_range
= true;
1517 if (old_auto
== intel_hdmi
->color_range_auto
&&
1518 old_range
== intel_hdmi
->limited_color_range
)
1524 if (property
== connector
->dev
->mode_config
.aspect_ratio_property
) {
1526 case DRM_MODE_PICTURE_ASPECT_NONE
:
1527 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1529 case DRM_MODE_PICTURE_ASPECT_4_3
:
1530 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
;
1532 case DRM_MODE_PICTURE_ASPECT_16_9
:
1533 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
;
1544 if (intel_dig_port
->base
.base
.crtc
)
1545 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1550 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1552 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1553 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1554 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1556 intel_hdmi_prepare(encoder
);
1558 intel_hdmi
->set_infoframes(&encoder
->base
,
1559 intel_crtc
->config
->has_hdmi_sink
,
1563 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1565 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1566 struct intel_hdmi
*intel_hdmi
= &dport
->hdmi
;
1567 struct drm_device
*dev
= encoder
->base
.dev
;
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 struct intel_crtc
*intel_crtc
=
1570 to_intel_crtc(encoder
->base
.crtc
);
1571 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1572 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1573 int pipe
= intel_crtc
->pipe
;
1576 /* Enable clock channels for this port */
1577 mutex_lock(&dev_priv
->sb_lock
);
1578 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1585 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1588 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0);
1589 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), 0x2b245f5f);
1590 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
), 0x5578b83a);
1591 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0c782040);
1592 vlv_dpio_write(dev_priv
, pipe
, VLV_TX3_DW4(port
), 0x2b247878);
1593 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
1594 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1595 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1597 /* Program lane clock */
1598 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1599 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1600 mutex_unlock(&dev_priv
->sb_lock
);
1602 intel_hdmi
->set_infoframes(&encoder
->base
,
1603 intel_crtc
->config
->has_hdmi_sink
,
1606 g4x_enable_hdmi(encoder
);
1608 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
1611 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1613 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1614 struct drm_device
*dev
= encoder
->base
.dev
;
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1616 struct intel_crtc
*intel_crtc
=
1617 to_intel_crtc(encoder
->base
.crtc
);
1618 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1619 int pipe
= intel_crtc
->pipe
;
1621 intel_hdmi_prepare(encoder
);
1623 /* Program Tx lane resets to default */
1624 mutex_lock(&dev_priv
->sb_lock
);
1625 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1626 DPIO_PCS_TX_LANE2_RESET
|
1627 DPIO_PCS_TX_LANE1_RESET
);
1628 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1629 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1630 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1631 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1632 DPIO_PCS_CLK_SOFT_RESET
);
1634 /* Fix up inter-pair skew failure */
1635 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1636 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1637 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1639 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1640 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1641 mutex_unlock(&dev_priv
->sb_lock
);
1644 static void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
1647 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1648 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
1649 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1650 enum pipe pipe
= crtc
->pipe
;
1653 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1655 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1657 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
1658 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1660 if (crtc
->config
->lane_count
> 2) {
1661 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1663 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1665 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
1666 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1669 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1670 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1672 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
1674 val
|= DPIO_PCS_CLK_SOFT_RESET
;
1675 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1677 if (crtc
->config
->lane_count
> 2) {
1678 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1679 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1681 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
1683 val
|= DPIO_PCS_CLK_SOFT_RESET
;
1684 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1688 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1690 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1691 struct drm_device
*dev
= encoder
->base
.dev
;
1692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1693 struct intel_crtc
*intel_crtc
=
1694 to_intel_crtc(encoder
->base
.crtc
);
1695 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1696 enum pipe pipe
= intel_crtc
->pipe
;
1699 intel_hdmi_prepare(encoder
);
1702 * Must trick the second common lane into life.
1703 * Otherwise we can't even access the PLL.
1705 if (ch
== DPIO_CH0
&& pipe
== PIPE_B
)
1706 dport
->release_cl2_override
=
1707 !chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, true);
1709 chv_phy_powergate_lanes(encoder
, true, 0x0);
1711 mutex_lock(&dev_priv
->sb_lock
);
1713 /* Assert data lane reset */
1714 chv_data_lane_soft_reset(encoder
, true);
1716 /* program left/right clock distribution */
1717 if (pipe
!= PIPE_B
) {
1718 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1719 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1721 val
|= CHV_BUFLEFTENA1_FORCE
;
1723 val
|= CHV_BUFRIGHTENA1_FORCE
;
1724 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1726 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1727 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1729 val
|= CHV_BUFLEFTENA2_FORCE
;
1731 val
|= CHV_BUFRIGHTENA2_FORCE
;
1732 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1735 /* program clock channel usage */
1736 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
1737 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1739 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1741 val
|= CHV_PCS_USEDCLKCHANNEL
;
1742 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
1744 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
1745 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1747 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1749 val
|= CHV_PCS_USEDCLKCHANNEL
;
1750 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
1753 * This a a bit weird since generally CL
1754 * matches the pipe, but here we need to
1755 * pick the CL based on the port.
1757 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
1759 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
1761 val
|= CHV_CMN_USEDCLKCHANNEL
;
1762 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
1764 mutex_unlock(&dev_priv
->sb_lock
);
1767 static void chv_hdmi_post_pll_disable(struct intel_encoder
*encoder
)
1769 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1770 enum pipe pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
1773 mutex_lock(&dev_priv
->sb_lock
);
1775 /* disable left/right clock distribution */
1776 if (pipe
!= PIPE_B
) {
1777 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1778 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1779 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1781 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1782 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1783 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1786 mutex_unlock(&dev_priv
->sb_lock
);
1789 * Leave the power down bit cleared for at least one
1790 * lane so that chv_powergate_phy_ch() will power
1791 * on something when the channel is otherwise unused.
1792 * When the port is off and the override is removed
1793 * the lanes power down anyway, so otherwise it doesn't
1794 * really matter what the state of power down bits is
1797 chv_phy_powergate_lanes(encoder
, false, 0x0);
1800 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
)
1802 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1803 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1804 struct intel_crtc
*intel_crtc
=
1805 to_intel_crtc(encoder
->base
.crtc
);
1806 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1807 int pipe
= intel_crtc
->pipe
;
1809 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1810 mutex_lock(&dev_priv
->sb_lock
);
1811 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
), 0x00000000);
1812 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
), 0x00e00060);
1813 mutex_unlock(&dev_priv
->sb_lock
);
1816 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
)
1818 struct drm_device
*dev
= encoder
->base
.dev
;
1819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1821 mutex_lock(&dev_priv
->sb_lock
);
1823 /* Assert data lane reset */
1824 chv_data_lane_soft_reset(encoder
, true);
1826 mutex_unlock(&dev_priv
->sb_lock
);
1829 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1831 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1832 struct intel_hdmi
*intel_hdmi
= &dport
->hdmi
;
1833 struct drm_device
*dev
= encoder
->base
.dev
;
1834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1835 struct intel_crtc
*intel_crtc
=
1836 to_intel_crtc(encoder
->base
.crtc
);
1837 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1838 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1839 int pipe
= intel_crtc
->pipe
;
1840 int data
, i
, stagger
;
1843 mutex_lock(&dev_priv
->sb_lock
);
1845 /* allow hardware to manage TX FIFO reset source */
1846 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
1847 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
1848 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
1850 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
1851 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
1852 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
1854 /* Program Tx latency optimal setting */
1855 for (i
= 0; i
< 4; i
++) {
1856 /* Set the upar bit */
1857 data
= (i
== 1) ? 0x0 : 0x1;
1858 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
1859 data
<< DPIO_UPAR_SHIFT
);
1862 /* Data lane stagger programming */
1863 if (intel_crtc
->config
->port_clock
> 270000)
1865 else if (intel_crtc
->config
->port_clock
> 135000)
1867 else if (intel_crtc
->config
->port_clock
> 67500)
1869 else if (intel_crtc
->config
->port_clock
> 33750)
1874 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
1875 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
1876 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
1878 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
1879 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
1880 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
1882 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
1883 DPIO_LANESTAGGER_STRAP(stagger
) |
1884 DPIO_LANESTAGGER_STRAP_OVRD
|
1885 DPIO_TX1_STAGGER_MASK(0x1f) |
1886 DPIO_TX1_STAGGER_MULT(6) |
1887 DPIO_TX2_STAGGER_MULT(0));
1889 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
1890 DPIO_LANESTAGGER_STRAP(stagger
) |
1891 DPIO_LANESTAGGER_STRAP_OVRD
|
1892 DPIO_TX1_STAGGER_MASK(0x1f) |
1893 DPIO_TX1_STAGGER_MULT(7) |
1894 DPIO_TX2_STAGGER_MULT(5));
1896 /* Deassert data lane reset */
1897 chv_data_lane_soft_reset(encoder
, false);
1899 /* Clear calc init */
1900 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1901 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1902 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
1903 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
1904 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1906 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1907 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1908 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
1909 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
1910 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1912 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
1913 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
1914 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
1915 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
1917 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
1918 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
1919 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
1920 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
1922 /* FIXME: Program the support xxx V-dB */
1924 for (i
= 0; i
< 4; i
++) {
1925 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
1926 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
1927 val
|= 128 << DPIO_SWING_DEEMPH9P5_SHIFT
;
1928 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
1931 for (i
= 0; i
< 4; i
++) {
1932 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
1934 val
&= ~DPIO_SWING_MARGIN000_MASK
;
1935 val
|= 102 << DPIO_SWING_MARGIN000_SHIFT
;
1938 * Supposedly this value shouldn't matter when unique transition
1939 * scale is disabled, but in fact it does matter. Let's just
1940 * always program the same value and hope it's OK.
1942 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
1943 val
|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
;
1945 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
1949 * The document said it needs to set bit 27 for ch0 and bit 26
1950 * for ch1. Might be a typo in the doc.
1951 * For now, for this unique transition scale selection, set bit
1952 * 27 for ch0 and ch1.
1954 for (i
= 0; i
< 4; i
++) {
1955 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
1956 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
1957 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
1960 /* Start swing calculation */
1961 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1962 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1963 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1965 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1966 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1967 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1969 mutex_unlock(&dev_priv
->sb_lock
);
1971 intel_hdmi
->set_infoframes(&encoder
->base
,
1972 intel_crtc
->config
->has_hdmi_sink
,
1975 g4x_enable_hdmi(encoder
);
1977 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
1979 /* Second common lane will stay alive on its own now */
1980 if (dport
->release_cl2_override
) {
1981 chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, false);
1982 dport
->release_cl2_override
= false;
1986 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1988 kfree(to_intel_connector(connector
)->detect_edid
);
1989 drm_connector_cleanup(connector
);
1993 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1994 .dpms
= drm_atomic_helper_connector_dpms
,
1995 .detect
= intel_hdmi_detect
,
1996 .force
= intel_hdmi_force
,
1997 .fill_modes
= drm_helper_probe_single_connector_modes
,
1998 .set_property
= intel_hdmi_set_property
,
1999 .atomic_get_property
= intel_connector_atomic_get_property
,
2000 .destroy
= intel_hdmi_destroy
,
2001 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2002 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
2005 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
2006 .get_modes
= intel_hdmi_get_modes
,
2007 .mode_valid
= intel_hdmi_mode_valid
,
2008 .best_encoder
= intel_best_encoder
,
2011 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
2012 .destroy
= intel_encoder_destroy
,
2016 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
2018 intel_attach_force_audio_property(connector
);
2019 intel_attach_broadcast_rgb_property(connector
);
2020 intel_hdmi
->color_range_auto
= true;
2021 intel_attach_aspect_ratio_property(connector
);
2022 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
2025 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
2026 struct intel_connector
*intel_connector
)
2028 struct drm_connector
*connector
= &intel_connector
->base
;
2029 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
2030 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2031 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2033 enum port port
= intel_dig_port
->port
;
2034 uint8_t alternate_ddc_pin
;
2036 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
2037 DRM_MODE_CONNECTOR_HDMIA
);
2038 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
2040 connector
->interlace_allowed
= 1;
2041 connector
->doublescan_allowed
= 0;
2042 connector
->stereo_allowed
= 1;
2046 if (IS_BROXTON(dev_priv
))
2047 intel_hdmi
->ddc_bus
= GMBUS_PIN_1_BXT
;
2049 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPB
;
2051 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2052 * interrupts to check the external panel connection.
2054 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
2055 intel_encoder
->hpd_pin
= HPD_PORT_A
;
2057 intel_encoder
->hpd_pin
= HPD_PORT_B
;
2060 if (IS_BROXTON(dev_priv
))
2061 intel_hdmi
->ddc_bus
= GMBUS_PIN_2_BXT
;
2063 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPC
;
2064 intel_encoder
->hpd_pin
= HPD_PORT_C
;
2067 if (WARN_ON(IS_BROXTON(dev_priv
)))
2068 intel_hdmi
->ddc_bus
= GMBUS_PIN_DISABLED
;
2069 else if (IS_CHERRYVIEW(dev_priv
))
2070 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPD_CHV
;
2072 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPD
;
2073 intel_encoder
->hpd_pin
= HPD_PORT_D
;
2076 /* On SKL PORT E doesn't have seperate GMBUS pin
2077 * We rely on VBT to set a proper alternate GMBUS pin. */
2079 dev_priv
->vbt
.ddi_port_info
[PORT_E
].alternate_ddc_pin
;
2080 switch (alternate_ddc_pin
) {
2082 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPB
;
2085 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPC
;
2088 intel_hdmi
->ddc_bus
= GMBUS_PIN_DPD
;
2091 MISSING_CASE(alternate_ddc_pin
);
2093 intel_encoder
->hpd_pin
= HPD_PORT_E
;
2096 intel_encoder
->hpd_pin
= HPD_PORT_A
;
2097 /* Internal port only for eDP. */
2102 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2103 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
2104 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
2105 intel_hdmi
->infoframe_enabled
= vlv_infoframe_enabled
;
2106 } else if (IS_G4X(dev
)) {
2107 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
2108 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
2109 intel_hdmi
->infoframe_enabled
= g4x_infoframe_enabled
;
2110 } else if (HAS_DDI(dev
)) {
2111 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
2112 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
2113 intel_hdmi
->infoframe_enabled
= hsw_infoframe_enabled
;
2114 } else if (HAS_PCH_IBX(dev
)) {
2115 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
2116 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
2117 intel_hdmi
->infoframe_enabled
= ibx_infoframe_enabled
;
2119 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
2120 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
2121 intel_hdmi
->infoframe_enabled
= cpt_infoframe_enabled
;
2125 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2127 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2128 intel_connector
->unregister
= intel_connector_unregister
;
2130 intel_hdmi_add_properties(intel_hdmi
, connector
);
2132 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2133 drm_connector_register(connector
);
2134 intel_hdmi
->attached_connector
= intel_connector
;
2136 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2137 * 0xd. Failure to do so will result in spurious interrupts being
2138 * generated on the port when a cable is not attached.
2140 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2141 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2142 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2146 void intel_hdmi_init(struct drm_device
*dev
,
2147 i915_reg_t hdmi_reg
, enum port port
)
2149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2150 struct intel_digital_port
*intel_dig_port
;
2151 struct intel_encoder
*intel_encoder
;
2152 struct intel_connector
*intel_connector
;
2154 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2155 if (!intel_dig_port
)
2158 intel_connector
= intel_connector_alloc();
2159 if (!intel_connector
) {
2160 kfree(intel_dig_port
);
2164 intel_encoder
= &intel_dig_port
->base
;
2166 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
2167 DRM_MODE_ENCODER_TMDS
, NULL
);
2169 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
2170 if (HAS_PCH_SPLIT(dev
)) {
2171 intel_encoder
->disable
= pch_disable_hdmi
;
2172 intel_encoder
->post_disable
= pch_post_disable_hdmi
;
2174 intel_encoder
->disable
= g4x_disable_hdmi
;
2176 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
2177 intel_encoder
->get_config
= intel_hdmi_get_config
;
2178 if (IS_CHERRYVIEW(dev
)) {
2179 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
2180 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
2181 intel_encoder
->enable
= vlv_enable_hdmi
;
2182 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
2183 intel_encoder
->post_pll_disable
= chv_hdmi_post_pll_disable
;
2184 } else if (IS_VALLEYVIEW(dev
)) {
2185 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
2186 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
2187 intel_encoder
->enable
= vlv_enable_hdmi
;
2188 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
2190 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
2191 if (HAS_PCH_CPT(dev
))
2192 intel_encoder
->enable
= cpt_enable_hdmi
;
2193 else if (HAS_PCH_IBX(dev
))
2194 intel_encoder
->enable
= ibx_enable_hdmi
;
2196 intel_encoder
->enable
= g4x_enable_hdmi
;
2199 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
2200 if (IS_CHERRYVIEW(dev
)) {
2202 intel_encoder
->crtc_mask
= 1 << 2;
2204 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
2206 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2208 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
2210 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2211 * to work on real hardware. And since g4x can send infoframes to
2212 * only one port anyway, nothing is lost by allowing it.
2215 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
2217 intel_dig_port
->port
= port
;
2218 dev_priv
->dig_port_map
[port
] = intel_encoder
;
2219 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
2220 intel_dig_port
->dp
.output_reg
= INVALID_MMIO_REG
;
2222 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);