2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
33 * These expanded contexts enable a number of new abilities, especially
34 * "Execlists" (also implemented in this file).
36 * Execlists are the new method by which, on gen8+ hardware, workloads are
37 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
41 #include <drm/i915_drm.h>
44 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
45 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
47 #define GEN8_LR_CONTEXT_ALIGN 4096
49 #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
50 #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
52 #define CTX_LRI_HEADER_0 0x01
53 #define CTX_CONTEXT_CONTROL 0x02
54 #define CTX_RING_HEAD 0x04
55 #define CTX_RING_TAIL 0x06
56 #define CTX_RING_BUFFER_START 0x08
57 #define CTX_RING_BUFFER_CONTROL 0x0a
58 #define CTX_BB_HEAD_U 0x0c
59 #define CTX_BB_HEAD_L 0x0e
60 #define CTX_BB_STATE 0x10
61 #define CTX_SECOND_BB_HEAD_U 0x12
62 #define CTX_SECOND_BB_HEAD_L 0x14
63 #define CTX_SECOND_BB_STATE 0x16
64 #define CTX_BB_PER_CTX_PTR 0x18
65 #define CTX_RCS_INDIRECT_CTX 0x1a
66 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
67 #define CTX_LRI_HEADER_1 0x21
68 #define CTX_CTX_TIMESTAMP 0x22
69 #define CTX_PDP3_UDW 0x24
70 #define CTX_PDP3_LDW 0x26
71 #define CTX_PDP2_UDW 0x28
72 #define CTX_PDP2_LDW 0x2a
73 #define CTX_PDP1_UDW 0x2c
74 #define CTX_PDP1_LDW 0x2e
75 #define CTX_PDP0_UDW 0x30
76 #define CTX_PDP0_LDW 0x32
77 #define CTX_LRI_HEADER_2 0x41
78 #define CTX_R_PWR_CLK_STATE 0x42
79 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
81 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
83 WARN_ON(i915
.enable_ppgtt
== -1);
85 if (enable_execlists
== 0)
88 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
))
94 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
95 struct intel_engine_cs
*ring
,
96 struct intel_context
*ctx
,
97 struct drm_i915_gem_execbuffer2
*args
,
98 struct list_head
*vmas
,
99 struct drm_i915_gem_object
*batch_obj
,
100 u64 exec_start
, u32 flags
)
106 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
111 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
)
113 intel_logical_ring_advance(ringbuf
);
115 if (intel_ring_stopped(ringbuf
->ring
))
118 /* TODO: how to submit a context to the ELSP is not here yet */
121 static int logical_ring_alloc_seqno(struct intel_engine_cs
*ring
)
123 if (ring
->outstanding_lazy_seqno
)
126 if (ring
->preallocated_lazy_request
== NULL
) {
127 struct drm_i915_gem_request
*request
;
129 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
133 ring
->preallocated_lazy_request
= request
;
136 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
139 static int logical_ring_wait_request(struct intel_ringbuffer
*ringbuf
,
142 struct intel_engine_cs
*ring
= ringbuf
->ring
;
143 struct drm_i915_gem_request
*request
;
147 if (ringbuf
->last_retired_head
!= -1) {
148 ringbuf
->head
= ringbuf
->last_retired_head
;
149 ringbuf
->last_retired_head
= -1;
151 ringbuf
->space
= intel_ring_space(ringbuf
);
152 if (ringbuf
->space
>= bytes
)
156 list_for_each_entry(request
, &ring
->request_list
, list
) {
157 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
158 ringbuf
->size
) >= bytes
) {
159 seqno
= request
->seqno
;
167 ret
= i915_wait_seqno(ring
, seqno
);
171 /* TODO: make sure we update the right ringbuffer's last_retired_head
172 * when retiring requests */
173 i915_gem_retire_requests_ring(ring
);
174 ringbuf
->head
= ringbuf
->last_retired_head
;
175 ringbuf
->last_retired_head
= -1;
177 ringbuf
->space
= intel_ring_space(ringbuf
);
181 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
184 struct intel_engine_cs
*ring
= ringbuf
->ring
;
185 struct drm_device
*dev
= ring
->dev
;
186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 ret
= logical_ring_wait_request(ringbuf
, bytes
);
194 /* Force the context submission in case we have been skipping it */
195 intel_logical_ring_advance_and_submit(ringbuf
);
197 /* With GEM the hangcheck timer should kick us out of the loop,
198 * leaving it early runs the risk of corrupting GEM state (due
199 * to running on almost untested codepaths). But on resume
200 * timers don't work yet, so prevent a complete hang in that
201 * case by choosing an insanely large timeout. */
202 end
= jiffies
+ 60 * HZ
;
205 ringbuf
->head
= I915_READ_HEAD(ring
);
206 ringbuf
->space
= intel_ring_space(ringbuf
);
207 if (ringbuf
->space
>= bytes
) {
214 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
219 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
220 dev_priv
->mm
.interruptible
);
224 if (time_after(jiffies
, end
)) {
233 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
)
235 uint32_t __iomem
*virt
;
236 int rem
= ringbuf
->size
- ringbuf
->tail
;
238 if (ringbuf
->space
< rem
) {
239 int ret
= logical_ring_wait_for_space(ringbuf
, rem
);
245 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
248 iowrite32(MI_NOOP
, virt
++);
251 ringbuf
->space
= intel_ring_space(ringbuf
);
256 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
, int bytes
)
260 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
261 ret
= logical_ring_wrap_buffer(ringbuf
);
266 if (unlikely(ringbuf
->space
< bytes
)) {
267 ret
= logical_ring_wait_for_space(ringbuf
, bytes
);
275 int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
, int num_dwords
)
277 struct intel_engine_cs
*ring
= ringbuf
->ring
;
278 struct drm_device
*dev
= ring
->dev
;
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
282 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
283 dev_priv
->mm
.interruptible
);
287 ret
= logical_ring_prepare(ringbuf
, num_dwords
* sizeof(uint32_t));
291 /* Preallocate the olr before touching the ring */
292 ret
= logical_ring_alloc_seqno(ring
);
296 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
300 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
302 struct drm_device
*dev
= ring
->dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
305 I915_WRITE(RING_MODE_GEN7(ring
),
306 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
307 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
308 POSTING_READ(RING_MODE_GEN7(ring
));
309 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
311 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
316 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
318 struct drm_device
*dev
= ring
->dev
;
319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
322 ret
= gen8_init_common_ring(ring
);
326 /* We need to disable the AsyncFlip performance optimisations in order
327 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
328 * programmed to '1' on all products.
330 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
332 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
334 ret
= intel_init_pipe_control(ring
);
338 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
343 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
345 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
348 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
350 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
353 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
355 if (!intel_ring_initialized(ring
))
358 /* TODO: make sure the ring is stopped */
359 ring
->preallocated_lazy_request
= NULL
;
360 ring
->outstanding_lazy_seqno
= 0;
365 i915_cmd_parser_fini_ring(ring
);
367 if (ring
->status_page
.obj
) {
368 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
369 ring
->status_page
.obj
= NULL
;
373 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
376 struct intel_context
*dctx
= ring
->default_context
;
377 struct drm_i915_gem_object
*dctx_obj
;
379 /* Intentionally left blank. */
383 INIT_LIST_HEAD(&ring
->active_list
);
384 INIT_LIST_HEAD(&ring
->request_list
);
385 init_waitqueue_head(&ring
->irq_queue
);
387 ret
= intel_lr_context_deferred_create(dctx
, ring
);
391 /* The status page is offset 0 from the context object in LRCs. */
392 dctx_obj
= dctx
->engine
[ring
->id
].state
;
393 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
);
394 ring
->status_page
.page_addr
= kmap(sg_page(dctx_obj
->pages
->sgl
));
395 if (ring
->status_page
.page_addr
== NULL
)
397 ring
->status_page
.obj
= dctx_obj
;
399 ret
= i915_cmd_parser_init_ring(ring
);
404 ret
= ring
->init(ring
);
412 static int logical_render_ring_init(struct drm_device
*dev
)
414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
417 ring
->name
= "render ring";
419 ring
->mmio_base
= RENDER_RING_BASE
;
420 ring
->irq_enable_mask
=
421 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
423 ring
->init
= gen8_init_render_ring
;
424 ring
->cleanup
= intel_fini_pipe_control
;
425 ring
->get_seqno
= gen8_get_seqno
;
426 ring
->set_seqno
= gen8_set_seqno
;
428 return logical_ring_init(dev
, ring
);
431 static int logical_bsd_ring_init(struct drm_device
*dev
)
433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
434 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
436 ring
->name
= "bsd ring";
438 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
439 ring
->irq_enable_mask
=
440 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
442 ring
->init
= gen8_init_common_ring
;
443 ring
->get_seqno
= gen8_get_seqno
;
444 ring
->set_seqno
= gen8_set_seqno
;
446 return logical_ring_init(dev
, ring
);
449 static int logical_bsd2_ring_init(struct drm_device
*dev
)
451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
452 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
454 ring
->name
= "bds2 ring";
456 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
457 ring
->irq_enable_mask
=
458 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
460 ring
->init
= gen8_init_common_ring
;
461 ring
->get_seqno
= gen8_get_seqno
;
462 ring
->set_seqno
= gen8_set_seqno
;
464 return logical_ring_init(dev
, ring
);
467 static int logical_blt_ring_init(struct drm_device
*dev
)
469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
472 ring
->name
= "blitter ring";
474 ring
->mmio_base
= BLT_RING_BASE
;
475 ring
->irq_enable_mask
=
476 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
478 ring
->init
= gen8_init_common_ring
;
479 ring
->get_seqno
= gen8_get_seqno
;
480 ring
->set_seqno
= gen8_set_seqno
;
482 return logical_ring_init(dev
, ring
);
485 static int logical_vebox_ring_init(struct drm_device
*dev
)
487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
488 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
490 ring
->name
= "video enhancement ring";
492 ring
->mmio_base
= VEBOX_RING_BASE
;
493 ring
->irq_enable_mask
=
494 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
496 ring
->init
= gen8_init_common_ring
;
497 ring
->get_seqno
= gen8_get_seqno
;
498 ring
->set_seqno
= gen8_set_seqno
;
500 return logical_ring_init(dev
, ring
);
503 int intel_logical_rings_init(struct drm_device
*dev
)
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 ret
= logical_render_ring_init(dev
);
513 ret
= logical_bsd_ring_init(dev
);
515 goto cleanup_render_ring
;
519 ret
= logical_blt_ring_init(dev
);
521 goto cleanup_bsd_ring
;
524 if (HAS_VEBOX(dev
)) {
525 ret
= logical_vebox_ring_init(dev
);
527 goto cleanup_blt_ring
;
531 ret
= logical_bsd2_ring_init(dev
);
533 goto cleanup_vebox_ring
;
536 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
538 goto cleanup_bsd2_ring
;
543 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
545 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
547 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
549 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
551 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
557 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
558 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
560 struct drm_i915_gem_object
*ring_obj
= ringbuf
->obj
;
561 struct i915_hw_ppgtt
*ppgtt
= ctx_to_ppgtt(ctx
);
566 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
568 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
572 ret
= i915_gem_object_get_pages(ctx_obj
);
574 DRM_DEBUG_DRIVER("Could not get object pages\n");
578 i915_gem_object_pin_pages(ctx_obj
);
580 /* The second page of the context object contains some fields which must
581 * be set up prior to the first execution. */
582 page
= i915_gem_object_get_page(ctx_obj
, 1);
583 reg_state
= kmap_atomic(page
);
585 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
586 * commands followed by (reg, value) pairs. The values we are setting here are
587 * only for the first context restore: on a subsequent save, the GPU will
588 * recreate this batchbuffer with new values (including all the missing
589 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
591 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
593 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
594 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
595 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
596 reg_state
[CTX_CONTEXT_CONTROL
+1] =
597 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT
);
598 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
599 reg_state
[CTX_RING_HEAD
+1] = 0;
600 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
601 reg_state
[CTX_RING_TAIL
+1] = 0;
602 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
603 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
604 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
605 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
606 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
607 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
608 reg_state
[CTX_BB_HEAD_U
+1] = 0;
609 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
610 reg_state
[CTX_BB_HEAD_L
+1] = 0;
611 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
612 reg_state
[CTX_BB_STATE
+1] = (1<<5);
613 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
614 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
615 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
616 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
617 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
618 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
619 if (ring
->id
== RCS
) {
620 /* TODO: according to BSpec, the register state context
621 * for CHV does not have these. OTOH, these registers do
622 * exist in CHV. I'm waiting for a clarification */
623 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
624 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
625 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
626 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
627 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
628 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
630 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
631 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
632 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
633 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
634 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
635 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
636 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
637 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
638 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
639 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
640 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
641 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
642 reg_state
[CTX_PDP3_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[3]);
643 reg_state
[CTX_PDP3_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[3]);
644 reg_state
[CTX_PDP2_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[2]);
645 reg_state
[CTX_PDP2_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[2]);
646 reg_state
[CTX_PDP1_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[1]);
647 reg_state
[CTX_PDP1_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[1]);
648 reg_state
[CTX_PDP0_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[0]);
649 reg_state
[CTX_PDP0_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[0]);
650 if (ring
->id
== RCS
) {
651 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
652 reg_state
[CTX_R_PWR_CLK_STATE
] = 0x20c8;
653 reg_state
[CTX_R_PWR_CLK_STATE
+1] = 0;
656 kunmap_atomic(reg_state
);
659 set_page_dirty(page
);
660 i915_gem_object_unpin_pages(ctx_obj
);
665 void intel_lr_context_free(struct intel_context
*ctx
)
669 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
670 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
671 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
674 intel_destroy_ringbuffer_obj(ringbuf
);
676 i915_gem_object_ggtt_unpin(ctx_obj
);
677 drm_gem_object_unreference(&ctx_obj
->base
);
682 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
686 WARN_ON(INTEL_INFO(ring
->dev
)->gen
!= 8);
690 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
696 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
703 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
704 struct intel_engine_cs
*ring
)
706 struct drm_device
*dev
= ring
->dev
;
707 struct drm_i915_gem_object
*ctx_obj
;
708 uint32_t context_size
;
709 struct intel_ringbuffer
*ringbuf
;
712 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
713 if (ctx
->engine
[ring
->id
].state
)
716 context_size
= round_up(get_lr_context_size(ring
), 4096);
718 ctx_obj
= i915_gem_alloc_context_obj(dev
, context_size
);
719 if (IS_ERR(ctx_obj
)) {
720 ret
= PTR_ERR(ctx_obj
);
721 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
725 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
727 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret
);
728 drm_gem_object_unreference(&ctx_obj
->base
);
732 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
734 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
736 i915_gem_object_ggtt_unpin(ctx_obj
);
737 drm_gem_object_unreference(&ctx_obj
->base
);
742 ringbuf
->ring
= ring
;
743 ringbuf
->size
= 32 * PAGE_SIZE
;
744 ringbuf
->effective_size
= ringbuf
->size
;
747 ringbuf
->space
= ringbuf
->size
;
748 ringbuf
->last_retired_head
= -1;
750 /* TODO: For now we put this in the mappable region so that we can reuse
751 * the existing ringbuffer code which ioremaps it. When we start
752 * creating many contexts, this will no longer work and we must switch
753 * to a kmapish interface.
755 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
757 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
762 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
764 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
765 intel_destroy_ringbuffer_obj(ringbuf
);
769 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
770 ctx
->engine
[ring
->id
].state
= ctx_obj
;
776 i915_gem_object_ggtt_unpin(ctx_obj
);
777 drm_gem_object_unreference(&ctx_obj
->base
);