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drm/i915: kill per-ring macros
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static u32 i915_gem_get_seqno(struct drm_device *dev)
38 {
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 u32 seqno;
41
42 seqno = dev_priv->next_seqno;
43
44 /* reserve 0 for non-seqno */
45 if (++dev_priv->next_seqno == 0)
46 dev_priv->next_seqno = 1;
47
48 return seqno;
49 }
50
51 static void
52 render_ring_flush(struct drm_device *dev,
53 struct intel_ring_buffer *ring,
54 u32 invalidate_domains,
55 u32 flush_domains)
56 {
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 cmd;
59
60 #if WATCH_EXEC
61 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62 invalidate_domains, flush_domains);
63 #endif
64
65 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
66 invalidate_domains, flush_domains);
67
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69 /*
70 * read/write caches:
71 *
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */
96
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112 #if WATCH_EXEC
113 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
114 #endif
115 intel_ring_begin(dev, ring, 2);
116 intel_ring_emit(dev, ring, cmd);
117 intel_ring_emit(dev, ring, MI_NOOP);
118 intel_ring_advance(dev, ring);
119 }
120 }
121
122 static void ring_set_tail(struct drm_device *dev,
123 struct intel_ring_buffer *ring,
124 u32 value)
125 {
126 drm_i915_private_t *dev_priv = dev->dev_private;
127 I915_WRITE_TAIL(ring, ring->tail);
128 }
129
130 static unsigned int render_ring_get_active_head(struct drm_device *dev,
131 struct intel_ring_buffer *ring)
132 {
133 drm_i915_private_t *dev_priv = dev->dev_private;
134 u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ?
135 RING_ACTHD(ring->mmio_base) : ACTHD;
136
137 return I915_READ(acthd_reg);
138 }
139
140 static int init_ring_common(struct drm_device *dev,
141 struct intel_ring_buffer *ring)
142 {
143 u32 head;
144 drm_i915_private_t *dev_priv = dev->dev_private;
145 struct drm_i915_gem_object *obj_priv;
146 obj_priv = to_intel_bo(ring->gem_object);
147
148 /* Stop the ring if it's running. */
149 I915_WRITE_CTL(ring, 0);
150 I915_WRITE_HEAD(ring, 0);
151 ring->set_tail(dev, ring, 0);
152
153 /* Initialize the ring. */
154 I915_WRITE_START(ring, obj_priv->gtt_offset);
155 head = I915_READ_HEAD(ring) & HEAD_ADDR;
156
157 /* G45 ring initialization fails to reset head to zero */
158 if (head != 0) {
159 DRM_ERROR("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n",
161 ring->name,
162 I915_READ_CTL(ring),
163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring),
165 I915_READ_START(ring));
166
167 I915_WRITE_HEAD(ring, 0);
168
169 DRM_ERROR("%s head forced to zero "
170 "ctl %08x head %08x tail %08x start %08x\n",
171 ring->name,
172 I915_READ_CTL(ring),
173 I915_READ_HEAD(ring),
174 I915_READ_TAIL(ring),
175 I915_READ_START(ring));
176 }
177
178 I915_WRITE_CTL(ring,
179 ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
180 | RING_NO_REPORT | RING_VALID);
181
182 head = I915_READ_HEAD(ring) & HEAD_ADDR;
183 /* If the head is still not zero, the ring is dead */
184 if (head != 0) {
185 DRM_ERROR("%s initialization failed "
186 "ctl %08x head %08x tail %08x start %08x\n",
187 ring->name,
188 I915_READ_CTL(ring),
189 I915_READ_HEAD(ring),
190 I915_READ_TAIL(ring),
191 I915_READ_START(ring));
192 return -EIO;
193 }
194
195 if (!drm_core_check_feature(dev, DRIVER_MODESET))
196 i915_kernel_lost_context(dev);
197 else {
198 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
199 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
200 ring->space = ring->head - (ring->tail + 8);
201 if (ring->space < 0)
202 ring->space += ring->size;
203 }
204 return 0;
205 }
206
207 static int init_render_ring(struct drm_device *dev,
208 struct intel_ring_buffer *ring)
209 {
210 drm_i915_private_t *dev_priv = dev->dev_private;
211 int ret = init_ring_common(dev, ring);
212 int mode;
213
214 if (INTEL_INFO(dev)->gen > 3) {
215 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
216 if (IS_GEN6(dev))
217 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
218 I915_WRITE(MI_MODE, mode);
219 }
220 return ret;
221 }
222
223 #define PIPE_CONTROL_FLUSH(addr) \
224 do { \
225 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
226 PIPE_CONTROL_DEPTH_STALL | 2); \
227 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
228 OUT_RING(0); \
229 OUT_RING(0); \
230 } while (0)
231
232 /**
233 * Creates a new sequence number, emitting a write of it to the status page
234 * plus an interrupt, which will trigger i915_user_interrupt_handler.
235 *
236 * Must be called with struct_lock held.
237 *
238 * Returned sequence numbers are nonzero on success.
239 */
240 static u32
241 render_ring_add_request(struct drm_device *dev,
242 struct intel_ring_buffer *ring,
243 u32 flush_domains)
244 {
245 drm_i915_private_t *dev_priv = dev->dev_private;
246 u32 seqno;
247
248 seqno = i915_gem_get_seqno(dev);
249
250 if (IS_GEN6(dev)) {
251 BEGIN_LP_RING(6);
252 OUT_RING(GFX_OP_PIPE_CONTROL | 3);
253 OUT_RING(PIPE_CONTROL_QW_WRITE |
254 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
255 PIPE_CONTROL_NOTIFY);
256 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
257 OUT_RING(seqno);
258 OUT_RING(0);
259 OUT_RING(0);
260 ADVANCE_LP_RING();
261 } else if (HAS_PIPE_CONTROL(dev)) {
262 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
263
264 /*
265 * Workaround qword write incoherence by flushing the
266 * PIPE_NOTIFY buffers out to memory before requesting
267 * an interrupt.
268 */
269 BEGIN_LP_RING(32);
270 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
271 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
272 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
273 OUT_RING(seqno);
274 OUT_RING(0);
275 PIPE_CONTROL_FLUSH(scratch_addr);
276 scratch_addr += 128; /* write to separate cachelines */
277 PIPE_CONTROL_FLUSH(scratch_addr);
278 scratch_addr += 128;
279 PIPE_CONTROL_FLUSH(scratch_addr);
280 scratch_addr += 128;
281 PIPE_CONTROL_FLUSH(scratch_addr);
282 scratch_addr += 128;
283 PIPE_CONTROL_FLUSH(scratch_addr);
284 scratch_addr += 128;
285 PIPE_CONTROL_FLUSH(scratch_addr);
286 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
287 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
288 PIPE_CONTROL_NOTIFY);
289 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
290 OUT_RING(seqno);
291 OUT_RING(0);
292 ADVANCE_LP_RING();
293 } else {
294 BEGIN_LP_RING(4);
295 OUT_RING(MI_STORE_DWORD_INDEX);
296 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
297 OUT_RING(seqno);
298
299 OUT_RING(MI_USER_INTERRUPT);
300 ADVANCE_LP_RING();
301 }
302 return seqno;
303 }
304
305 static u32
306 render_ring_get_seqno(struct drm_device *dev,
307 struct intel_ring_buffer *ring)
308 {
309 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
310 if (HAS_PIPE_CONTROL(dev))
311 return ((volatile u32 *)(dev_priv->seqno_page))[0];
312 else
313 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
314 }
315
316 static void
317 render_ring_get_user_irq(struct drm_device *dev,
318 struct intel_ring_buffer *ring)
319 {
320 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
321 unsigned long irqflags;
322
323 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
324 if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
325 if (HAS_PCH_SPLIT(dev))
326 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
327 else
328 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
329 }
330 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
331 }
332
333 static void
334 render_ring_put_user_irq(struct drm_device *dev,
335 struct intel_ring_buffer *ring)
336 {
337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
338 unsigned long irqflags;
339
340 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
341 BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
342 if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
343 if (HAS_PCH_SPLIT(dev))
344 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
345 else
346 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
347 }
348 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
349 }
350
351 static void render_setup_status_page(struct drm_device *dev,
352 struct intel_ring_buffer *ring)
353 {
354 drm_i915_private_t *dev_priv = dev->dev_private;
355 if (IS_GEN6(dev)) {
356 I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base),
357 ring->status_page.gfx_addr);
358 I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */
359 } else {
360 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
361 ring->status_page.gfx_addr);
362 I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */
363 }
364
365 }
366
367 static void
368 bsd_ring_flush(struct drm_device *dev,
369 struct intel_ring_buffer *ring,
370 u32 invalidate_domains,
371 u32 flush_domains)
372 {
373 intel_ring_begin(dev, ring, 2);
374 intel_ring_emit(dev, ring, MI_FLUSH);
375 intel_ring_emit(dev, ring, MI_NOOP);
376 intel_ring_advance(dev, ring);
377 }
378
379 static unsigned int bsd_ring_get_active_head(struct drm_device *dev,
380 struct intel_ring_buffer *ring)
381 {
382 drm_i915_private_t *dev_priv = dev->dev_private;
383 return I915_READ(RING_ACTHD(ring->mmio_base));
384 }
385
386 static int init_bsd_ring(struct drm_device *dev,
387 struct intel_ring_buffer *ring)
388 {
389 return init_ring_common(dev, ring);
390 }
391
392 static u32
393 bsd_ring_add_request(struct drm_device *dev,
394 struct intel_ring_buffer *ring,
395 u32 flush_domains)
396 {
397 u32 seqno;
398
399 seqno = i915_gem_get_seqno(dev);
400
401 intel_ring_begin(dev, ring, 4);
402 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
403 intel_ring_emit(dev, ring,
404 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
405 intel_ring_emit(dev, ring, seqno);
406 intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
407 intel_ring_advance(dev, ring);
408
409 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
410
411 return seqno;
412 }
413
414 static void bsd_setup_status_page(struct drm_device *dev,
415 struct intel_ring_buffer *ring)
416 {
417 drm_i915_private_t *dev_priv = dev->dev_private;
418 I915_WRITE(RING_HWS_PGA(ring->mmio_base), ring->status_page.gfx_addr);
419 I915_READ(RING_HWS_PGA(ring->mmio_base));
420 }
421
422 static void
423 bsd_ring_get_user_irq(struct drm_device *dev,
424 struct intel_ring_buffer *ring)
425 {
426 /* do nothing */
427 }
428 static void
429 bsd_ring_put_user_irq(struct drm_device *dev,
430 struct intel_ring_buffer *ring)
431 {
432 /* do nothing */
433 }
434
435 static u32
436 bsd_ring_get_seqno(struct drm_device *dev,
437 struct intel_ring_buffer *ring)
438 {
439 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
440 }
441
442 static int
443 bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
444 struct intel_ring_buffer *ring,
445 struct drm_i915_gem_execbuffer2 *exec,
446 struct drm_clip_rect *cliprects,
447 uint64_t exec_offset)
448 {
449 uint32_t exec_start;
450 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
451 intel_ring_begin(dev, ring, 2);
452 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
453 (2 << 6) | MI_BATCH_NON_SECURE_I965);
454 intel_ring_emit(dev, ring, exec_start);
455 intel_ring_advance(dev, ring);
456 return 0;
457 }
458
459
460 static int
461 render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
462 struct intel_ring_buffer *ring,
463 struct drm_i915_gem_execbuffer2 *exec,
464 struct drm_clip_rect *cliprects,
465 uint64_t exec_offset)
466 {
467 drm_i915_private_t *dev_priv = dev->dev_private;
468 int nbox = exec->num_cliprects;
469 int i = 0, count;
470 uint32_t exec_start, exec_len;
471 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
472 exec_len = (uint32_t) exec->batch_len;
473
474 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
475
476 count = nbox ? nbox : 1;
477
478 for (i = 0; i < count; i++) {
479 if (i < nbox) {
480 int ret = i915_emit_box(dev, cliprects, i,
481 exec->DR1, exec->DR4);
482 if (ret)
483 return ret;
484 }
485
486 if (IS_I830(dev) || IS_845G(dev)) {
487 intel_ring_begin(dev, ring, 4);
488 intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
489 intel_ring_emit(dev, ring,
490 exec_start | MI_BATCH_NON_SECURE);
491 intel_ring_emit(dev, ring, exec_start + exec_len - 4);
492 intel_ring_emit(dev, ring, 0);
493 } else {
494 intel_ring_begin(dev, ring, 4);
495 if (INTEL_INFO(dev)->gen >= 4) {
496 intel_ring_emit(dev, ring,
497 MI_BATCH_BUFFER_START | (2 << 6)
498 | MI_BATCH_NON_SECURE_I965);
499 intel_ring_emit(dev, ring, exec_start);
500 } else {
501 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
502 | (2 << 6));
503 intel_ring_emit(dev, ring, exec_start |
504 MI_BATCH_NON_SECURE);
505 }
506 }
507 intel_ring_advance(dev, ring);
508 }
509
510 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
511 intel_ring_begin(dev, ring, 2);
512 intel_ring_emit(dev, ring, MI_FLUSH |
513 MI_NO_WRITE_FLUSH |
514 MI_INVALIDATE_ISP );
515 intel_ring_emit(dev, ring, MI_NOOP);
516 intel_ring_advance(dev, ring);
517 }
518 /* XXX breadcrumb */
519
520 return 0;
521 }
522
523 static void cleanup_status_page(struct drm_device *dev,
524 struct intel_ring_buffer *ring)
525 {
526 drm_i915_private_t *dev_priv = dev->dev_private;
527 struct drm_gem_object *obj;
528 struct drm_i915_gem_object *obj_priv;
529
530 obj = ring->status_page.obj;
531 if (obj == NULL)
532 return;
533 obj_priv = to_intel_bo(obj);
534
535 kunmap(obj_priv->pages[0]);
536 i915_gem_object_unpin(obj);
537 drm_gem_object_unreference(obj);
538 ring->status_page.obj = NULL;
539
540 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
541 }
542
543 static int init_status_page(struct drm_device *dev,
544 struct intel_ring_buffer *ring)
545 {
546 drm_i915_private_t *dev_priv = dev->dev_private;
547 struct drm_gem_object *obj;
548 struct drm_i915_gem_object *obj_priv;
549 int ret;
550
551 obj = i915_gem_alloc_object(dev, 4096);
552 if (obj == NULL) {
553 DRM_ERROR("Failed to allocate status page\n");
554 ret = -ENOMEM;
555 goto err;
556 }
557 obj_priv = to_intel_bo(obj);
558 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
559
560 ret = i915_gem_object_pin(obj, 4096);
561 if (ret != 0) {
562 goto err_unref;
563 }
564
565 ring->status_page.gfx_addr = obj_priv->gtt_offset;
566 ring->status_page.page_addr = kmap(obj_priv->pages[0]);
567 if (ring->status_page.page_addr == NULL) {
568 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
569 goto err_unpin;
570 }
571 ring->status_page.obj = obj;
572 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
573
574 ring->setup_status_page(dev, ring);
575 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
576 ring->name, ring->status_page.gfx_addr);
577
578 return 0;
579
580 err_unpin:
581 i915_gem_object_unpin(obj);
582 err_unref:
583 drm_gem_object_unreference(obj);
584 err:
585 return ret;
586 }
587
588 int intel_init_ring_buffer(struct drm_device *dev,
589 struct intel_ring_buffer *ring)
590 {
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 struct drm_i915_gem_object *obj_priv;
593 struct drm_gem_object *obj;
594 int ret;
595
596 ring->dev = dev;
597
598 if (I915_NEED_GFX_HWS(dev)) {
599 ret = init_status_page(dev, ring);
600 if (ret)
601 return ret;
602 }
603
604 obj = i915_gem_alloc_object(dev, ring->size);
605 if (obj == NULL) {
606 DRM_ERROR("Failed to allocate ringbuffer\n");
607 ret = -ENOMEM;
608 goto err_hws;
609 }
610
611 ring->gem_object = obj;
612
613 ret = i915_gem_object_pin(obj, PAGE_SIZE);
614 if (ret)
615 goto err_unref;
616
617 obj_priv = to_intel_bo(obj);
618 ring->map.size = ring->size;
619 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
620 ring->map.type = 0;
621 ring->map.flags = 0;
622 ring->map.mtrr = 0;
623
624 drm_core_ioremap_wc(&ring->map, dev);
625 if (ring->map.handle == NULL) {
626 DRM_ERROR("Failed to map ringbuffer.\n");
627 ret = -EINVAL;
628 goto err_unpin;
629 }
630
631 ring->virtual_start = ring->map.handle;
632 ret = ring->init(dev, ring);
633 if (ret)
634 goto err_unmap;
635
636 if (!drm_core_check_feature(dev, DRIVER_MODESET))
637 i915_kernel_lost_context(dev);
638 else {
639 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
640 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
641 ring->space = ring->head - (ring->tail + 8);
642 if (ring->space < 0)
643 ring->space += ring->size;
644 }
645 INIT_LIST_HEAD(&ring->active_list);
646 INIT_LIST_HEAD(&ring->request_list);
647 return ret;
648
649 err_unmap:
650 drm_core_ioremapfree(&ring->map, dev);
651 err_unpin:
652 i915_gem_object_unpin(obj);
653 err_unref:
654 drm_gem_object_unreference(obj);
655 ring->gem_object = NULL;
656 err_hws:
657 cleanup_status_page(dev, ring);
658 return ret;
659 }
660
661 void intel_cleanup_ring_buffer(struct drm_device *dev,
662 struct intel_ring_buffer *ring)
663 {
664 if (ring->gem_object == NULL)
665 return;
666
667 drm_core_ioremapfree(&ring->map, dev);
668
669 i915_gem_object_unpin(ring->gem_object);
670 drm_gem_object_unreference(ring->gem_object);
671 ring->gem_object = NULL;
672 cleanup_status_page(dev, ring);
673 }
674
675 static int intel_wrap_ring_buffer(struct drm_device *dev,
676 struct intel_ring_buffer *ring)
677 {
678 unsigned int *virt;
679 int rem;
680 rem = ring->size - ring->tail;
681
682 if (ring->space < rem) {
683 int ret = intel_wait_ring_buffer(dev, ring, rem);
684 if (ret)
685 return ret;
686 }
687
688 virt = (unsigned int *)(ring->virtual_start + ring->tail);
689 rem /= 8;
690 while (rem--) {
691 *virt++ = MI_NOOP;
692 *virt++ = MI_NOOP;
693 }
694
695 ring->tail = 0;
696 ring->space = ring->head - 8;
697
698 return 0;
699 }
700
701 int intel_wait_ring_buffer(struct drm_device *dev,
702 struct intel_ring_buffer *ring, int n)
703 {
704 unsigned long end;
705 drm_i915_private_t *dev_priv = dev->dev_private;
706
707 trace_i915_ring_wait_begin (dev);
708 end = jiffies + 3 * HZ;
709 do {
710 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
711 ring->space = ring->head - (ring->tail + 8);
712 if (ring->space < 0)
713 ring->space += ring->size;
714 if (ring->space >= n) {
715 trace_i915_ring_wait_end (dev);
716 return 0;
717 }
718
719 if (dev->primary->master) {
720 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
721 if (master_priv->sarea_priv)
722 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
723 }
724
725 yield();
726 } while (!time_after(jiffies, end));
727 trace_i915_ring_wait_end (dev);
728 return -EBUSY;
729 }
730
731 void intel_ring_begin(struct drm_device *dev,
732 struct intel_ring_buffer *ring,
733 int num_dwords)
734 {
735 int n = 4*num_dwords;
736 if (unlikely(ring->tail + n > ring->size))
737 intel_wrap_ring_buffer(dev, ring);
738 if (unlikely(ring->space < n))
739 intel_wait_ring_buffer(dev, ring, n);
740
741 ring->space -= n;
742 }
743
744 void intel_ring_advance(struct drm_device *dev,
745 struct intel_ring_buffer *ring)
746 {
747 ring->tail &= ring->size - 1;
748 ring->set_tail(dev, ring, ring->tail);
749 }
750
751 void intel_fill_struct(struct drm_device *dev,
752 struct intel_ring_buffer *ring,
753 void *data,
754 unsigned int len)
755 {
756 unsigned int *virt = ring->virtual_start + ring->tail;
757 BUG_ON((len&~(4-1)) != 0);
758 intel_ring_begin(dev, ring, len/4);
759 memcpy(virt, data, len);
760 ring->tail += len;
761 ring->tail &= ring->size - 1;
762 ring->space -= len;
763 intel_ring_advance(dev, ring);
764 }
765
766 static const struct intel_ring_buffer render_ring = {
767 .name = "render ring",
768 .id = RING_RENDER,
769 .mmio_base = RENDER_RING_BASE,
770 .size = 32 * PAGE_SIZE,
771 .setup_status_page = render_setup_status_page,
772 .init = init_render_ring,
773 .set_tail = ring_set_tail,
774 .get_active_head = render_ring_get_active_head,
775 .flush = render_ring_flush,
776 .add_request = render_ring_add_request,
777 .get_seqno = render_ring_get_seqno,
778 .user_irq_get = render_ring_get_user_irq,
779 .user_irq_put = render_ring_put_user_irq,
780 .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
781 };
782
783 /* ring buffer for bit-stream decoder */
784
785 static const struct intel_ring_buffer bsd_ring = {
786 .name = "bsd ring",
787 .id = RING_BSD,
788 .mmio_base = BSD_RING_BASE,
789 .size = 32 * PAGE_SIZE,
790 .setup_status_page = bsd_setup_status_page,
791 .init = init_bsd_ring,
792 .set_tail = ring_set_tail,
793 .get_active_head = bsd_ring_get_active_head,
794 .flush = bsd_ring_flush,
795 .add_request = bsd_ring_add_request,
796 .get_seqno = bsd_ring_get_seqno,
797 .user_irq_get = bsd_ring_get_user_irq,
798 .user_irq_put = bsd_ring_put_user_irq,
799 .dispatch_gem_execbuffer = bsd_ring_dispatch_gem_execbuffer,
800 };
801
802
803 static void gen6_bsd_setup_status_page(struct drm_device *dev,
804 struct intel_ring_buffer *ring)
805 {
806 drm_i915_private_t *dev_priv = dev->dev_private;
807 I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), ring->status_page.gfx_addr);
808 I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base));
809 }
810
811 static void gen6_bsd_ring_set_tail(struct drm_device *dev,
812 struct intel_ring_buffer *ring,
813 u32 value)
814 {
815 drm_i915_private_t *dev_priv = dev->dev_private;
816
817 /* Every tail move must follow the sequence below */
818 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
819 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
820 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
821 I915_WRITE(GEN6_BSD_RNCID, 0x0);
822
823 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
824 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
825 50))
826 DRM_ERROR("timed out waiting for IDLE Indicator\n");
827
828 I915_WRITE_TAIL(ring, value);
829 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
830 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
831 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
832 }
833
834 static unsigned int gen6_bsd_ring_get_active_head(struct drm_device *dev,
835 struct intel_ring_buffer *ring)
836 {
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 return I915_READ(RING_ACTHD(ring->mmio_base));
839 }
840
841 static void gen6_bsd_ring_flush(struct drm_device *dev,
842 struct intel_ring_buffer *ring,
843 u32 invalidate_domains,
844 u32 flush_domains)
845 {
846 intel_ring_begin(dev, ring, 4);
847 intel_ring_emit(dev, ring, MI_FLUSH_DW);
848 intel_ring_emit(dev, ring, 0);
849 intel_ring_emit(dev, ring, 0);
850 intel_ring_emit(dev, ring, 0);
851 intel_ring_advance(dev, ring);
852 }
853
854 static int
855 gen6_bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
856 struct intel_ring_buffer *ring,
857 struct drm_i915_gem_execbuffer2 *exec,
858 struct drm_clip_rect *cliprects,
859 uint64_t exec_offset)
860 {
861 uint32_t exec_start;
862
863 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
864
865 intel_ring_begin(dev, ring, 2);
866 intel_ring_emit(dev, ring,
867 MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
868 /* bit0-7 is the length on GEN6+ */
869 intel_ring_emit(dev, ring, exec_start);
870 intel_ring_advance(dev, ring);
871
872 return 0;
873 }
874
875 /* ring buffer for Video Codec for Gen6+ */
876 static const struct intel_ring_buffer gen6_bsd_ring = {
877 .name = "gen6 bsd ring",
878 .id = RING_BSD,
879 .mmio_base = GEN6_BSD_RING_BASE,
880 .size = 32 * PAGE_SIZE,
881 .setup_status_page = gen6_bsd_setup_status_page,
882 .init = init_bsd_ring,
883 .set_tail = gen6_bsd_ring_set_tail,
884 .get_active_head = gen6_bsd_ring_get_active_head,
885 .flush = gen6_bsd_ring_flush,
886 .add_request = bsd_ring_add_request,
887 .get_seqno = bsd_ring_get_seqno,
888 .user_irq_get = bsd_ring_get_user_irq,
889 .user_irq_put = bsd_ring_put_user_irq,
890 .dispatch_gem_execbuffer = gen6_bsd_ring_dispatch_gem_execbuffer,
891 };
892
893 int intel_init_render_ring_buffer(struct drm_device *dev)
894 {
895 drm_i915_private_t *dev_priv = dev->dev_private;
896
897 dev_priv->render_ring = render_ring;
898
899 if (!I915_NEED_GFX_HWS(dev)) {
900 dev_priv->render_ring.status_page.page_addr
901 = dev_priv->status_page_dmah->vaddr;
902 memset(dev_priv->render_ring.status_page.page_addr,
903 0, PAGE_SIZE);
904 }
905
906 return intel_init_ring_buffer(dev, &dev_priv->render_ring);
907 }
908
909 int intel_init_bsd_ring_buffer(struct drm_device *dev)
910 {
911 drm_i915_private_t *dev_priv = dev->dev_private;
912
913 if (IS_GEN6(dev))
914 dev_priv->bsd_ring = gen6_bsd_ring;
915 else
916 dev_priv->bsd_ring = bsd_ring;
917
918 return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
919 }
Linux kernel - Deliverables
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