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drm/i915: i8xx interrupt handler
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
235
236 ret = intel_ring_begin(ring, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static void ring_write_tail(struct intel_ring_buffer *ring,
252 u32 value)
253 {
254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
255 I915_WRITE_TAIL(ring, value);
256 }
257
258 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
259 {
260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
262 RING_ACTHD(ring->mmio_base) : ACTHD;
263
264 return I915_READ(acthd_reg);
265 }
266
267 static int init_ring_common(struct intel_ring_buffer *ring)
268 {
269 drm_i915_private_t *dev_priv = ring->dev->dev_private;
270 struct drm_i915_gem_object *obj = ring->obj;
271 u32 head;
272
273 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring, 0);
275 I915_WRITE_HEAD(ring, 0);
276 ring->write_tail(ring, 0);
277
278 /* Initialize the ring. */
279 I915_WRITE_START(ring, obj->gtt_offset);
280 head = I915_READ_HEAD(ring) & HEAD_ADDR;
281
282 /* G45 ring initialization fails to reset head to zero */
283 if (head != 0) {
284 DRM_DEBUG_KMS("%s head not reset to zero "
285 "ctl %08x head %08x tail %08x start %08x\n",
286 ring->name,
287 I915_READ_CTL(ring),
288 I915_READ_HEAD(ring),
289 I915_READ_TAIL(ring),
290 I915_READ_START(ring));
291
292 I915_WRITE_HEAD(ring, 0);
293
294 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
295 DRM_ERROR("failed to set %s head to zero "
296 "ctl %08x head %08x tail %08x start %08x\n",
297 ring->name,
298 I915_READ_CTL(ring),
299 I915_READ_HEAD(ring),
300 I915_READ_TAIL(ring),
301 I915_READ_START(ring));
302 }
303 }
304
305 I915_WRITE_CTL(ring,
306 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
307 | RING_VALID);
308
309 /* If the head is still not zero, the ring is dead */
310 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
311 I915_READ_START(ring) == obj->gtt_offset &&
312 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
313 DRM_ERROR("%s initialization failed "
314 "ctl %08x head %08x tail %08x start %08x\n",
315 ring->name,
316 I915_READ_CTL(ring),
317 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring),
319 I915_READ_START(ring));
320 return -EIO;
321 }
322
323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
324 i915_kernel_lost_context(ring->dev);
325 else {
326 ring->head = I915_READ_HEAD(ring);
327 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
328 ring->space = ring_space(ring);
329 }
330
331 return 0;
332 }
333
334 static int
335 init_pipe_control(struct intel_ring_buffer *ring)
336 {
337 struct pipe_control *pc;
338 struct drm_i915_gem_object *obj;
339 int ret;
340
341 if (ring->private)
342 return 0;
343
344 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
345 if (!pc)
346 return -ENOMEM;
347
348 obj = i915_gem_alloc_object(ring->dev, 4096);
349 if (obj == NULL) {
350 DRM_ERROR("Failed to allocate seqno page\n");
351 ret = -ENOMEM;
352 goto err;
353 }
354
355 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
356
357 ret = i915_gem_object_pin(obj, 4096, true);
358 if (ret)
359 goto err_unref;
360
361 pc->gtt_offset = obj->gtt_offset;
362 pc->cpu_page = kmap(obj->pages[0]);
363 if (pc->cpu_page == NULL)
364 goto err_unpin;
365
366 pc->obj = obj;
367 ring->private = pc;
368 return 0;
369
370 err_unpin:
371 i915_gem_object_unpin(obj);
372 err_unref:
373 drm_gem_object_unreference(&obj->base);
374 err:
375 kfree(pc);
376 return ret;
377 }
378
379 static void
380 cleanup_pipe_control(struct intel_ring_buffer *ring)
381 {
382 struct pipe_control *pc = ring->private;
383 struct drm_i915_gem_object *obj;
384
385 if (!ring->private)
386 return;
387
388 obj = pc->obj;
389 kunmap(obj->pages[0]);
390 i915_gem_object_unpin(obj);
391 drm_gem_object_unreference(&obj->base);
392
393 kfree(pc);
394 ring->private = NULL;
395 }
396
397 static int init_render_ring(struct intel_ring_buffer *ring)
398 {
399 struct drm_device *dev = ring->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 int ret = init_ring_common(ring);
402
403 if (INTEL_INFO(dev)->gen > 3) {
404 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
405 I915_WRITE(MI_MODE, mode);
406 if (IS_GEN7(dev))
407 I915_WRITE(GFX_MODE_GEN7,
408 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
409 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
410 }
411
412 if (INTEL_INFO(dev)->gen >= 5) {
413 ret = init_pipe_control(ring);
414 if (ret)
415 return ret;
416 }
417
418 if (INTEL_INFO(dev)->gen >= 6) {
419 I915_WRITE(INSTPM,
420 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
421 }
422
423 return ret;
424 }
425
426 static void render_ring_cleanup(struct intel_ring_buffer *ring)
427 {
428 if (!ring->private)
429 return;
430
431 cleanup_pipe_control(ring);
432 }
433
434 static void
435 update_mboxes(struct intel_ring_buffer *ring,
436 u32 seqno,
437 u32 mmio_offset)
438 {
439 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
440 MI_SEMAPHORE_GLOBAL_GTT |
441 MI_SEMAPHORE_REGISTER |
442 MI_SEMAPHORE_UPDATE);
443 intel_ring_emit(ring, seqno);
444 intel_ring_emit(ring, mmio_offset);
445 }
446
447 /**
448 * gen6_add_request - Update the semaphore mailbox registers
449 *
450 * @ring - ring that is adding a request
451 * @seqno - return seqno stuck into the ring
452 *
453 * Update the mailbox registers in the *other* rings with the current seqno.
454 * This acts like a signal in the canonical semaphore.
455 */
456 static int
457 gen6_add_request(struct intel_ring_buffer *ring,
458 u32 *seqno)
459 {
460 u32 mbox1_reg;
461 u32 mbox2_reg;
462 int ret;
463
464 ret = intel_ring_begin(ring, 10);
465 if (ret)
466 return ret;
467
468 mbox1_reg = ring->signal_mbox[0];
469 mbox2_reg = ring->signal_mbox[1];
470
471 *seqno = i915_gem_next_request_seqno(ring);
472
473 update_mboxes(ring, *seqno, mbox1_reg);
474 update_mboxes(ring, *seqno, mbox2_reg);
475 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
476 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
477 intel_ring_emit(ring, *seqno);
478 intel_ring_emit(ring, MI_USER_INTERRUPT);
479 intel_ring_advance(ring);
480
481 return 0;
482 }
483
484 /**
485 * intel_ring_sync - sync the waiter to the signaller on seqno
486 *
487 * @waiter - ring that is waiting
488 * @signaller - ring which has, or will signal
489 * @seqno - seqno which the waiter will block on
490 */
491 static int
492 gen6_ring_sync(struct intel_ring_buffer *waiter,
493 struct intel_ring_buffer *signaller,
494 u32 seqno)
495 {
496 int ret;
497 u32 dw1 = MI_SEMAPHORE_MBOX |
498 MI_SEMAPHORE_COMPARE |
499 MI_SEMAPHORE_REGISTER;
500
501 /* Throughout all of the GEM code, seqno passed implies our current
502 * seqno is >= the last seqno executed. However for hardware the
503 * comparison is strictly greater than.
504 */
505 seqno -= 1;
506
507 WARN_ON(signaller->semaphore_register[waiter->id] ==
508 MI_SEMAPHORE_SYNC_INVALID);
509
510 ret = intel_ring_begin(waiter, 4);
511 if (ret)
512 return ret;
513
514 intel_ring_emit(waiter,
515 dw1 | signaller->semaphore_register[waiter->id]);
516 intel_ring_emit(waiter, seqno);
517 intel_ring_emit(waiter, 0);
518 intel_ring_emit(waiter, MI_NOOP);
519 intel_ring_advance(waiter);
520
521 return 0;
522 }
523
524 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
525 do { \
526 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
527 PIPE_CONTROL_DEPTH_STALL); \
528 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
529 intel_ring_emit(ring__, 0); \
530 intel_ring_emit(ring__, 0); \
531 } while (0)
532
533 static int
534 pc_render_add_request(struct intel_ring_buffer *ring,
535 u32 *result)
536 {
537 u32 seqno = i915_gem_next_request_seqno(ring);
538 struct pipe_control *pc = ring->private;
539 u32 scratch_addr = pc->gtt_offset + 128;
540 int ret;
541
542 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
543 * incoherent with writes to memory, i.e. completely fubar,
544 * so we need to use PIPE_NOTIFY instead.
545 *
546 * However, we also need to workaround the qword write
547 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
548 * memory before requesting an interrupt.
549 */
550 ret = intel_ring_begin(ring, 32);
551 if (ret)
552 return ret;
553
554 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
555 PIPE_CONTROL_WRITE_FLUSH |
556 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
557 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
558 intel_ring_emit(ring, seqno);
559 intel_ring_emit(ring, 0);
560 PIPE_CONTROL_FLUSH(ring, scratch_addr);
561 scratch_addr += 128; /* write to separate cachelines */
562 PIPE_CONTROL_FLUSH(ring, scratch_addr);
563 scratch_addr += 128;
564 PIPE_CONTROL_FLUSH(ring, scratch_addr);
565 scratch_addr += 128;
566 PIPE_CONTROL_FLUSH(ring, scratch_addr);
567 scratch_addr += 128;
568 PIPE_CONTROL_FLUSH(ring, scratch_addr);
569 scratch_addr += 128;
570 PIPE_CONTROL_FLUSH(ring, scratch_addr);
571
572 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
573 PIPE_CONTROL_WRITE_FLUSH |
574 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
575 PIPE_CONTROL_NOTIFY);
576 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
577 intel_ring_emit(ring, seqno);
578 intel_ring_emit(ring, 0);
579 intel_ring_advance(ring);
580
581 *result = seqno;
582 return 0;
583 }
584
585 static u32
586 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
587 {
588 struct drm_device *dev = ring->dev;
589
590 /* Workaround to force correct ordering between irq and seqno writes on
591 * ivb (and maybe also on snb) by reading from a CS register (like
592 * ACTHD) before reading the status page. */
593 if (IS_GEN6(dev) || IS_GEN7(dev))
594 intel_ring_get_active_head(ring);
595 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
596 }
597
598 static u32
599 ring_get_seqno(struct intel_ring_buffer *ring)
600 {
601 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
602 }
603
604 static u32
605 pc_render_get_seqno(struct intel_ring_buffer *ring)
606 {
607 struct pipe_control *pc = ring->private;
608 return pc->cpu_page[0];
609 }
610
611 static bool
612 gen5_ring_get_irq(struct intel_ring_buffer *ring)
613 {
614 struct drm_device *dev = ring->dev;
615 drm_i915_private_t *dev_priv = dev->dev_private;
616
617 if (!dev->irq_enabled)
618 return false;
619
620 spin_lock(&ring->irq_lock);
621 if (ring->irq_refcount++ == 0) {
622 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
623 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
624 POSTING_READ(GTIMR);
625 }
626 spin_unlock(&ring->irq_lock);
627
628 return true;
629 }
630
631 static void
632 gen5_ring_put_irq(struct intel_ring_buffer *ring)
633 {
634 struct drm_device *dev = ring->dev;
635 drm_i915_private_t *dev_priv = dev->dev_private;
636
637 spin_lock(&ring->irq_lock);
638 if (--ring->irq_refcount == 0) {
639 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
640 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
641 POSTING_READ(GTIMR);
642 }
643 spin_unlock(&ring->irq_lock);
644 }
645
646 static bool
647 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
648 {
649 struct drm_device *dev = ring->dev;
650 drm_i915_private_t *dev_priv = dev->dev_private;
651
652 if (!dev->irq_enabled)
653 return false;
654
655 spin_lock(&ring->irq_lock);
656 if (ring->irq_refcount++ == 0) {
657 dev_priv->irq_mask &= ~ring->irq_enable_mask;
658 I915_WRITE(IMR, dev_priv->irq_mask);
659 POSTING_READ(IMR);
660 }
661 spin_unlock(&ring->irq_lock);
662
663 return true;
664 }
665
666 static void
667 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
668 {
669 struct drm_device *dev = ring->dev;
670 drm_i915_private_t *dev_priv = dev->dev_private;
671
672 spin_lock(&ring->irq_lock);
673 if (--ring->irq_refcount == 0) {
674 dev_priv->irq_mask |= ring->irq_enable_mask;
675 I915_WRITE(IMR, dev_priv->irq_mask);
676 POSTING_READ(IMR);
677 }
678 spin_unlock(&ring->irq_lock);
679 }
680
681 static bool
682 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
683 {
684 struct drm_device *dev = ring->dev;
685 drm_i915_private_t *dev_priv = dev->dev_private;
686
687 if (!dev->irq_enabled)
688 return false;
689
690 spin_lock(&ring->irq_lock);
691 if (ring->irq_refcount++ == 0) {
692 dev_priv->irq_mask &= ~ring->irq_enable_mask;
693 I915_WRITE16(IMR, dev_priv->irq_mask);
694 POSTING_READ16(IMR);
695 }
696 spin_unlock(&ring->irq_lock);
697
698 return true;
699 }
700
701 static void
702 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
703 {
704 struct drm_device *dev = ring->dev;
705 drm_i915_private_t *dev_priv = dev->dev_private;
706
707 spin_lock(&ring->irq_lock);
708 if (--ring->irq_refcount == 0) {
709 dev_priv->irq_mask |= ring->irq_enable_mask;
710 I915_WRITE16(IMR, dev_priv->irq_mask);
711 POSTING_READ16(IMR);
712 }
713 spin_unlock(&ring->irq_lock);
714 }
715
716 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
717 {
718 struct drm_device *dev = ring->dev;
719 drm_i915_private_t *dev_priv = ring->dev->dev_private;
720 u32 mmio = 0;
721
722 /* The ring status page addresses are no longer next to the rest of
723 * the ring registers as of gen7.
724 */
725 if (IS_GEN7(dev)) {
726 switch (ring->id) {
727 case RCS:
728 mmio = RENDER_HWS_PGA_GEN7;
729 break;
730 case BCS:
731 mmio = BLT_HWS_PGA_GEN7;
732 break;
733 case VCS:
734 mmio = BSD_HWS_PGA_GEN7;
735 break;
736 }
737 } else if (IS_GEN6(ring->dev)) {
738 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
739 } else {
740 mmio = RING_HWS_PGA(ring->mmio_base);
741 }
742
743 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
744 POSTING_READ(mmio);
745 }
746
747 static int
748 bsd_ring_flush(struct intel_ring_buffer *ring,
749 u32 invalidate_domains,
750 u32 flush_domains)
751 {
752 int ret;
753
754 ret = intel_ring_begin(ring, 2);
755 if (ret)
756 return ret;
757
758 intel_ring_emit(ring, MI_FLUSH);
759 intel_ring_emit(ring, MI_NOOP);
760 intel_ring_advance(ring);
761 return 0;
762 }
763
764 static int
765 i9xx_add_request(struct intel_ring_buffer *ring,
766 u32 *result)
767 {
768 u32 seqno;
769 int ret;
770
771 ret = intel_ring_begin(ring, 4);
772 if (ret)
773 return ret;
774
775 seqno = i915_gem_next_request_seqno(ring);
776
777 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
778 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
779 intel_ring_emit(ring, seqno);
780 intel_ring_emit(ring, MI_USER_INTERRUPT);
781 intel_ring_advance(ring);
782
783 *result = seqno;
784 return 0;
785 }
786
787 static bool
788 gen6_ring_get_irq(struct intel_ring_buffer *ring)
789 {
790 struct drm_device *dev = ring->dev;
791 drm_i915_private_t *dev_priv = dev->dev_private;
792
793 if (!dev->irq_enabled)
794 return false;
795
796 /* It looks like we need to prevent the gt from suspending while waiting
797 * for an notifiy irq, otherwise irqs seem to get lost on at least the
798 * blt/bsd rings on ivb. */
799 gen6_gt_force_wake_get(dev_priv);
800
801 spin_lock(&ring->irq_lock);
802 if (ring->irq_refcount++ == 0) {
803 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
804 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
805 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
806 POSTING_READ(GTIMR);
807 }
808 spin_unlock(&ring->irq_lock);
809
810 return true;
811 }
812
813 static void
814 gen6_ring_put_irq(struct intel_ring_buffer *ring)
815 {
816 struct drm_device *dev = ring->dev;
817 drm_i915_private_t *dev_priv = dev->dev_private;
818
819 spin_lock(&ring->irq_lock);
820 if (--ring->irq_refcount == 0) {
821 I915_WRITE_IMR(ring, ~0);
822 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
823 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
824 POSTING_READ(GTIMR);
825 }
826 spin_unlock(&ring->irq_lock);
827
828 gen6_gt_force_wake_put(dev_priv);
829 }
830
831 static int
832 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
833 {
834 int ret;
835
836 ret = intel_ring_begin(ring, 2);
837 if (ret)
838 return ret;
839
840 intel_ring_emit(ring,
841 MI_BATCH_BUFFER_START |
842 MI_BATCH_GTT |
843 MI_BATCH_NON_SECURE_I965);
844 intel_ring_emit(ring, offset);
845 intel_ring_advance(ring);
846
847 return 0;
848 }
849
850 static int
851 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
852 u32 offset, u32 len)
853 {
854 int ret;
855
856 ret = intel_ring_begin(ring, 4);
857 if (ret)
858 return ret;
859
860 intel_ring_emit(ring, MI_BATCH_BUFFER);
861 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
862 intel_ring_emit(ring, offset + len - 8);
863 intel_ring_emit(ring, 0);
864 intel_ring_advance(ring);
865
866 return 0;
867 }
868
869 static int
870 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
871 u32 offset, u32 len)
872 {
873 int ret;
874
875 ret = intel_ring_begin(ring, 2);
876 if (ret)
877 return ret;
878
879 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
880 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
881 intel_ring_advance(ring);
882
883 return 0;
884 }
885
886 static void cleanup_status_page(struct intel_ring_buffer *ring)
887 {
888 drm_i915_private_t *dev_priv = ring->dev->dev_private;
889 struct drm_i915_gem_object *obj;
890
891 obj = ring->status_page.obj;
892 if (obj == NULL)
893 return;
894
895 kunmap(obj->pages[0]);
896 i915_gem_object_unpin(obj);
897 drm_gem_object_unreference(&obj->base);
898 ring->status_page.obj = NULL;
899
900 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
901 }
902
903 static int init_status_page(struct intel_ring_buffer *ring)
904 {
905 struct drm_device *dev = ring->dev;
906 drm_i915_private_t *dev_priv = dev->dev_private;
907 struct drm_i915_gem_object *obj;
908 int ret;
909
910 obj = i915_gem_alloc_object(dev, 4096);
911 if (obj == NULL) {
912 DRM_ERROR("Failed to allocate status page\n");
913 ret = -ENOMEM;
914 goto err;
915 }
916
917 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
918
919 ret = i915_gem_object_pin(obj, 4096, true);
920 if (ret != 0) {
921 goto err_unref;
922 }
923
924 ring->status_page.gfx_addr = obj->gtt_offset;
925 ring->status_page.page_addr = kmap(obj->pages[0]);
926 if (ring->status_page.page_addr == NULL) {
927 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
928 goto err_unpin;
929 }
930 ring->status_page.obj = obj;
931 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
932
933 intel_ring_setup_status_page(ring);
934 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
935 ring->name, ring->status_page.gfx_addr);
936
937 return 0;
938
939 err_unpin:
940 i915_gem_object_unpin(obj);
941 err_unref:
942 drm_gem_object_unreference(&obj->base);
943 err:
944 return ret;
945 }
946
947 static int intel_init_ring_buffer(struct drm_device *dev,
948 struct intel_ring_buffer *ring)
949 {
950 struct drm_i915_gem_object *obj;
951 int ret;
952
953 ring->dev = dev;
954 INIT_LIST_HEAD(&ring->active_list);
955 INIT_LIST_HEAD(&ring->request_list);
956 INIT_LIST_HEAD(&ring->gpu_write_list);
957 ring->size = 32 * PAGE_SIZE;
958
959 init_waitqueue_head(&ring->irq_queue);
960 spin_lock_init(&ring->irq_lock);
961
962 if (I915_NEED_GFX_HWS(dev)) {
963 ret = init_status_page(ring);
964 if (ret)
965 return ret;
966 }
967
968 obj = i915_gem_alloc_object(dev, ring->size);
969 if (obj == NULL) {
970 DRM_ERROR("Failed to allocate ringbuffer\n");
971 ret = -ENOMEM;
972 goto err_hws;
973 }
974
975 ring->obj = obj;
976
977 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
978 if (ret)
979 goto err_unref;
980
981 ring->map.size = ring->size;
982 ring->map.offset = dev->agp->base + obj->gtt_offset;
983 ring->map.type = 0;
984 ring->map.flags = 0;
985 ring->map.mtrr = 0;
986
987 drm_core_ioremap_wc(&ring->map, dev);
988 if (ring->map.handle == NULL) {
989 DRM_ERROR("Failed to map ringbuffer.\n");
990 ret = -EINVAL;
991 goto err_unpin;
992 }
993
994 ring->virtual_start = ring->map.handle;
995 ret = ring->init(ring);
996 if (ret)
997 goto err_unmap;
998
999 /* Workaround an erratum on the i830 which causes a hang if
1000 * the TAIL pointer points to within the last 2 cachelines
1001 * of the buffer.
1002 */
1003 ring->effective_size = ring->size;
1004 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1005 ring->effective_size -= 128;
1006
1007 return 0;
1008
1009 err_unmap:
1010 drm_core_ioremapfree(&ring->map, dev);
1011 err_unpin:
1012 i915_gem_object_unpin(obj);
1013 err_unref:
1014 drm_gem_object_unreference(&obj->base);
1015 ring->obj = NULL;
1016 err_hws:
1017 cleanup_status_page(ring);
1018 return ret;
1019 }
1020
1021 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1022 {
1023 struct drm_i915_private *dev_priv;
1024 int ret;
1025
1026 if (ring->obj == NULL)
1027 return;
1028
1029 /* Disable the ring buffer. The ring must be idle at this point */
1030 dev_priv = ring->dev->dev_private;
1031 ret = intel_wait_ring_idle(ring);
1032 if (ret)
1033 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1034 ring->name, ret);
1035
1036 I915_WRITE_CTL(ring, 0);
1037
1038 drm_core_ioremapfree(&ring->map, ring->dev);
1039
1040 i915_gem_object_unpin(ring->obj);
1041 drm_gem_object_unreference(&ring->obj->base);
1042 ring->obj = NULL;
1043
1044 if (ring->cleanup)
1045 ring->cleanup(ring);
1046
1047 cleanup_status_page(ring);
1048 }
1049
1050 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1051 {
1052 unsigned int *virt;
1053 int rem = ring->size - ring->tail;
1054
1055 if (ring->space < rem) {
1056 int ret = intel_wait_ring_buffer(ring, rem);
1057 if (ret)
1058 return ret;
1059 }
1060
1061 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1062 rem /= 8;
1063 while (rem--) {
1064 *virt++ = MI_NOOP;
1065 *virt++ = MI_NOOP;
1066 }
1067
1068 ring->tail = 0;
1069 ring->space = ring_space(ring);
1070
1071 return 0;
1072 }
1073
1074 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1075 {
1076 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1077 bool was_interruptible;
1078 int ret;
1079
1080 /* XXX As we have not yet audited all the paths to check that
1081 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1082 * allow us to be interruptible by a signal.
1083 */
1084 was_interruptible = dev_priv->mm.interruptible;
1085 dev_priv->mm.interruptible = false;
1086
1087 ret = i915_wait_request(ring, seqno, true);
1088
1089 dev_priv->mm.interruptible = was_interruptible;
1090
1091 return ret;
1092 }
1093
1094 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1095 {
1096 struct drm_i915_gem_request *request;
1097 u32 seqno = 0;
1098 int ret;
1099
1100 i915_gem_retire_requests_ring(ring);
1101
1102 if (ring->last_retired_head != -1) {
1103 ring->head = ring->last_retired_head;
1104 ring->last_retired_head = -1;
1105 ring->space = ring_space(ring);
1106 if (ring->space >= n)
1107 return 0;
1108 }
1109
1110 list_for_each_entry(request, &ring->request_list, list) {
1111 int space;
1112
1113 if (request->tail == -1)
1114 continue;
1115
1116 space = request->tail - (ring->tail + 8);
1117 if (space < 0)
1118 space += ring->size;
1119 if (space >= n) {
1120 seqno = request->seqno;
1121 break;
1122 }
1123
1124 /* Consume this request in case we need more space than
1125 * is available and so need to prevent a race between
1126 * updating last_retired_head and direct reads of
1127 * I915_RING_HEAD. It also provides a nice sanity check.
1128 */
1129 request->tail = -1;
1130 }
1131
1132 if (seqno == 0)
1133 return -ENOSPC;
1134
1135 ret = intel_ring_wait_seqno(ring, seqno);
1136 if (ret)
1137 return ret;
1138
1139 if (WARN_ON(ring->last_retired_head == -1))
1140 return -ENOSPC;
1141
1142 ring->head = ring->last_retired_head;
1143 ring->last_retired_head = -1;
1144 ring->space = ring_space(ring);
1145 if (WARN_ON(ring->space < n))
1146 return -ENOSPC;
1147
1148 return 0;
1149 }
1150
1151 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1152 {
1153 struct drm_device *dev = ring->dev;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1155 unsigned long end;
1156 int ret;
1157
1158 ret = intel_ring_wait_request(ring, n);
1159 if (ret != -ENOSPC)
1160 return ret;
1161
1162 trace_i915_ring_wait_begin(ring);
1163 if (drm_core_check_feature(dev, DRIVER_GEM))
1164 /* With GEM the hangcheck timer should kick us out of the loop,
1165 * leaving it early runs the risk of corrupting GEM state (due
1166 * to running on almost untested codepaths). But on resume
1167 * timers don't work yet, so prevent a complete hang in that
1168 * case by choosing an insanely large timeout. */
1169 end = jiffies + 60 * HZ;
1170 else
1171 end = jiffies + 3 * HZ;
1172
1173 do {
1174 ring->head = I915_READ_HEAD(ring);
1175 ring->space = ring_space(ring);
1176 if (ring->space >= n) {
1177 trace_i915_ring_wait_end(ring);
1178 return 0;
1179 }
1180
1181 if (dev->primary->master) {
1182 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1183 if (master_priv->sarea_priv)
1184 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1185 }
1186
1187 msleep(1);
1188 if (atomic_read(&dev_priv->mm.wedged))
1189 return -EAGAIN;
1190 } while (!time_after(jiffies, end));
1191 trace_i915_ring_wait_end(ring);
1192 return -EBUSY;
1193 }
1194
1195 int intel_ring_begin(struct intel_ring_buffer *ring,
1196 int num_dwords)
1197 {
1198 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1199 int n = 4*num_dwords;
1200 int ret;
1201
1202 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1203 return -EIO;
1204
1205 if (unlikely(ring->tail + n > ring->effective_size)) {
1206 ret = intel_wrap_ring_buffer(ring);
1207 if (unlikely(ret))
1208 return ret;
1209 }
1210
1211 if (unlikely(ring->space < n)) {
1212 ret = intel_wait_ring_buffer(ring, n);
1213 if (unlikely(ret))
1214 return ret;
1215 }
1216
1217 ring->space -= n;
1218 return 0;
1219 }
1220
1221 void intel_ring_advance(struct intel_ring_buffer *ring)
1222 {
1223 ring->tail &= ring->size - 1;
1224 ring->write_tail(ring, ring->tail);
1225 }
1226
1227
1228 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1229 u32 value)
1230 {
1231 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1232
1233 /* Every tail move must follow the sequence below */
1234 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1235 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1236 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1237 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1238
1239 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1240 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1241 50))
1242 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1243
1244 I915_WRITE_TAIL(ring, value);
1245 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1246 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1247 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1248 }
1249
1250 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1251 u32 invalidate, u32 flush)
1252 {
1253 uint32_t cmd;
1254 int ret;
1255
1256 ret = intel_ring_begin(ring, 4);
1257 if (ret)
1258 return ret;
1259
1260 cmd = MI_FLUSH_DW;
1261 if (invalidate & I915_GEM_GPU_DOMAINS)
1262 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1263 intel_ring_emit(ring, cmd);
1264 intel_ring_emit(ring, 0);
1265 intel_ring_emit(ring, 0);
1266 intel_ring_emit(ring, MI_NOOP);
1267 intel_ring_advance(ring);
1268 return 0;
1269 }
1270
1271 static int
1272 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1273 u32 offset, u32 len)
1274 {
1275 int ret;
1276
1277 ret = intel_ring_begin(ring, 2);
1278 if (ret)
1279 return ret;
1280
1281 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1282 /* bit0-7 is the length on GEN6+ */
1283 intel_ring_emit(ring, offset);
1284 intel_ring_advance(ring);
1285
1286 return 0;
1287 }
1288
1289 /* Blitter support (SandyBridge+) */
1290
1291 static int blt_ring_flush(struct intel_ring_buffer *ring,
1292 u32 invalidate, u32 flush)
1293 {
1294 uint32_t cmd;
1295 int ret;
1296
1297 ret = intel_ring_begin(ring, 4);
1298 if (ret)
1299 return ret;
1300
1301 cmd = MI_FLUSH_DW;
1302 if (invalidate & I915_GEM_DOMAIN_RENDER)
1303 cmd |= MI_INVALIDATE_TLB;
1304 intel_ring_emit(ring, cmd);
1305 intel_ring_emit(ring, 0);
1306 intel_ring_emit(ring, 0);
1307 intel_ring_emit(ring, MI_NOOP);
1308 intel_ring_advance(ring);
1309 return 0;
1310 }
1311
1312 int intel_init_render_ring_buffer(struct drm_device *dev)
1313 {
1314 drm_i915_private_t *dev_priv = dev->dev_private;
1315 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1316
1317 ring->name = "render ring";
1318 ring->id = RCS;
1319 ring->mmio_base = RENDER_RING_BASE;
1320
1321 if (INTEL_INFO(dev)->gen >= 6) {
1322 ring->add_request = gen6_add_request;
1323 ring->flush = gen6_render_ring_flush;
1324 ring->irq_get = gen6_ring_get_irq;
1325 ring->irq_put = gen6_ring_put_irq;
1326 ring->irq_enable_mask = GT_USER_INTERRUPT;
1327 ring->get_seqno = gen6_ring_get_seqno;
1328 ring->sync_to = gen6_ring_sync;
1329 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1330 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1331 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1332 ring->signal_mbox[0] = GEN6_VRSYNC;
1333 ring->signal_mbox[1] = GEN6_BRSYNC;
1334 } else if (IS_GEN5(dev)) {
1335 ring->add_request = pc_render_add_request;
1336 ring->flush = gen4_render_ring_flush;
1337 ring->get_seqno = pc_render_get_seqno;
1338 ring->irq_get = gen5_ring_get_irq;
1339 ring->irq_put = gen5_ring_put_irq;
1340 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1341 } else {
1342 ring->add_request = i9xx_add_request;
1343 if (INTEL_INFO(dev)->gen < 4)
1344 ring->flush = gen2_render_ring_flush;
1345 else
1346 ring->flush = gen4_render_ring_flush;
1347 ring->get_seqno = ring_get_seqno;
1348 if (IS_GEN2(dev)) {
1349 ring->irq_get = i8xx_ring_get_irq;
1350 ring->irq_put = i8xx_ring_put_irq;
1351 } else {
1352 ring->irq_get = i9xx_ring_get_irq;
1353 ring->irq_put = i9xx_ring_put_irq;
1354 }
1355 ring->irq_enable_mask = I915_USER_INTERRUPT;
1356 }
1357 ring->write_tail = ring_write_tail;
1358 if (INTEL_INFO(dev)->gen >= 6)
1359 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1360 else if (INTEL_INFO(dev)->gen >= 4)
1361 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1362 else if (IS_I830(dev) || IS_845G(dev))
1363 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1364 else
1365 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1366 ring->init = init_render_ring;
1367 ring->cleanup = render_ring_cleanup;
1368
1369
1370 if (!I915_NEED_GFX_HWS(dev)) {
1371 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1372 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1373 }
1374
1375 return intel_init_ring_buffer(dev, ring);
1376 }
1377
1378 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1379 {
1380 drm_i915_private_t *dev_priv = dev->dev_private;
1381 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1382
1383 ring->name = "render ring";
1384 ring->id = RCS;
1385 ring->mmio_base = RENDER_RING_BASE;
1386
1387 if (INTEL_INFO(dev)->gen >= 6) {
1388 /* non-kms not supported on gen6+ */
1389 return -ENODEV;
1390 }
1391
1392 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1393 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1394 * the special gen5 functions. */
1395 ring->add_request = i9xx_add_request;
1396 if (INTEL_INFO(dev)->gen < 4)
1397 ring->flush = gen2_render_ring_flush;
1398 else
1399 ring->flush = gen4_render_ring_flush;
1400 ring->get_seqno = ring_get_seqno;
1401 if (IS_GEN2(dev)) {
1402 ring->irq_get = i8xx_ring_get_irq;
1403 ring->irq_put = i8xx_ring_put_irq;
1404 } else {
1405 ring->irq_get = i9xx_ring_get_irq;
1406 ring->irq_put = i9xx_ring_put_irq;
1407 }
1408 ring->irq_enable_mask = I915_USER_INTERRUPT;
1409 ring->write_tail = ring_write_tail;
1410 if (INTEL_INFO(dev)->gen >= 4)
1411 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1412 else if (IS_I830(dev) || IS_845G(dev))
1413 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1414 else
1415 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1416 ring->init = init_render_ring;
1417 ring->cleanup = render_ring_cleanup;
1418
1419 if (!I915_NEED_GFX_HWS(dev))
1420 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1421
1422 ring->dev = dev;
1423 INIT_LIST_HEAD(&ring->active_list);
1424 INIT_LIST_HEAD(&ring->request_list);
1425 INIT_LIST_HEAD(&ring->gpu_write_list);
1426
1427 ring->size = size;
1428 ring->effective_size = ring->size;
1429 if (IS_I830(ring->dev))
1430 ring->effective_size -= 128;
1431
1432 ring->map.offset = start;
1433 ring->map.size = size;
1434 ring->map.type = 0;
1435 ring->map.flags = 0;
1436 ring->map.mtrr = 0;
1437
1438 drm_core_ioremap_wc(&ring->map, dev);
1439 if (ring->map.handle == NULL) {
1440 DRM_ERROR("can not ioremap virtual address for"
1441 " ring buffer\n");
1442 return -ENOMEM;
1443 }
1444
1445 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1446 return 0;
1447 }
1448
1449 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1450 {
1451 drm_i915_private_t *dev_priv = dev->dev_private;
1452 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1453
1454 ring->name = "bsd ring";
1455 ring->id = VCS;
1456
1457 ring->write_tail = ring_write_tail;
1458 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1459 ring->mmio_base = GEN6_BSD_RING_BASE;
1460 /* gen6 bsd needs a special wa for tail updates */
1461 if (IS_GEN6(dev))
1462 ring->write_tail = gen6_bsd_ring_write_tail;
1463 ring->flush = gen6_ring_flush;
1464 ring->add_request = gen6_add_request;
1465 ring->get_seqno = gen6_ring_get_seqno;
1466 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1467 ring->irq_get = gen6_ring_get_irq;
1468 ring->irq_put = gen6_ring_put_irq;
1469 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1470 ring->sync_to = gen6_ring_sync;
1471 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1472 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1473 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1474 ring->signal_mbox[0] = GEN6_RVSYNC;
1475 ring->signal_mbox[1] = GEN6_BVSYNC;
1476 } else {
1477 ring->mmio_base = BSD_RING_BASE;
1478 ring->flush = bsd_ring_flush;
1479 ring->add_request = i9xx_add_request;
1480 ring->get_seqno = ring_get_seqno;
1481 if (IS_GEN5(dev)) {
1482 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1483 ring->irq_get = gen5_ring_get_irq;
1484 ring->irq_put = gen5_ring_put_irq;
1485 } else {
1486 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1487 ring->irq_get = i9xx_ring_get_irq;
1488 ring->irq_put = i9xx_ring_put_irq;
1489 }
1490 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1491 }
1492 ring->init = init_ring_common;
1493
1494
1495 return intel_init_ring_buffer(dev, ring);
1496 }
1497
1498 int intel_init_blt_ring_buffer(struct drm_device *dev)
1499 {
1500 drm_i915_private_t *dev_priv = dev->dev_private;
1501 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1502
1503 ring->name = "blitter ring";
1504 ring->id = BCS;
1505
1506 ring->mmio_base = BLT_RING_BASE;
1507 ring->write_tail = ring_write_tail;
1508 ring->flush = blt_ring_flush;
1509 ring->add_request = gen6_add_request;
1510 ring->get_seqno = gen6_ring_get_seqno;
1511 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1512 ring->irq_get = gen6_ring_get_irq;
1513 ring->irq_put = gen6_ring_put_irq;
1514 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1515 ring->sync_to = gen6_ring_sync;
1516 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1517 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1518 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1519 ring->signal_mbox[0] = GEN6_RBSYNC;
1520 ring->signal_mbox[1] = GEN6_VBSYNC;
1521 ring->init = init_ring_common;
1522
1523 return intel_init_ring_buffer(dev, ring);
1524 }
Linux kernel - Deliverables
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