drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/clock.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/pll.h>
  28
  29 #include "pll.h"
  30
  31 struct nv40_clock_priv {
  32         struct nouveau_clock base;
  33         u32 ctrl;
  34         u32 npll_ctrl;
  35         u32 npll_coef;
  36         u32 spll;
  37 };
  38
  39 static struct nouveau_clocks
  40 nv40_domain[] = {
  41         { nv_clk_src_crystal, 0xff },
  42         { nv_clk_src_href   , 0xff },
  43         { nv_clk_src_core   , 0xff, 0, "core", 1000 },
  44         { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
  45         { nv_clk_src_mem    , 0xff, 0, "memory", 1000 },
  46         { nv_clk_src_max }
  47 };
  48
  49 static u32
  50 read_pll_1(struct nv40_clock_priv *priv, u32 reg)
  51 {
  52         u32 ctrl = nv_rd32(priv, reg + 0x00);
  53         int P = (ctrl & 0x00070000) >> 16;
  54         int N = (ctrl & 0x0000ff00) >> 8;
  55         int M = (ctrl & 0x000000ff) >> 0;
  56         u32 ref = 27000, clk = 0;
  57
  58         if (ctrl & 0x80000000)
  59                 clk = ref * N / M;
  60
  61         return clk >> P;
  62 }
  63
  64 static u32
  65 read_pll_2(struct nv40_clock_priv *priv, u32 reg)
  66 {
  67         u32 ctrl = nv_rd32(priv, reg + 0x00);
  68         u32 coef = nv_rd32(priv, reg + 0x04);
  69         int N2 = (coef & 0xff000000) >> 24;
  70         int M2 = (coef & 0x00ff0000) >> 16;
  71         int N1 = (coef & 0x0000ff00) >> 8;
  72         int M1 = (coef & 0x000000ff) >> 0;
  73         int P = (ctrl & 0x00070000) >> 16;
  74         u32 ref = 27000, clk = 0;
  75
  76         if ((ctrl & 0x80000000) && M1) {
  77                 clk = ref * N1 / M1;
  78                 if ((ctrl & 0x40000100) == 0x40000000) {
  79                         if (M2)
  80                                 clk = clk * N2 / M2;
  81                         else
  82                                 clk = 0;
  83                 }
  84         }
  85
  86         return clk >> P;
  87 }
  88
  89 static u32
  90 read_clk(struct nv40_clock_priv *priv, u32 src)
  91 {
  92         switch (src) {
  93         case 3:
  94                 return read_pll_2(priv, 0x004000);
  95         case 2:
  96                 return read_pll_1(priv, 0x004008);
  97         default:
  98                 break;
  99         }
 100
 101         return 0;
 102 }
 103
 104 static int
 105 nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
 106 {
 107         struct nv40_clock_priv *priv = (void *)clk;
 108         u32 mast = nv_rd32(priv, 0x00c040);
 109
 110         switch (src) {
 111         case nv_clk_src_crystal:
 112                 return nv_device(priv)->crystal;
 113         case nv_clk_src_href:
 114                 return 100000; /*XXX: PCIE/AGP differ*/
 115         case nv_clk_src_core:
 116                 return read_clk(priv, (mast & 0x00000003) >> 0);
 117         case nv_clk_src_shader:
 118                 return read_clk(priv, (mast & 0x00000030) >> 4);
 119         case nv_clk_src_mem:
 120                 return read_pll_2(priv, 0x4020);
 121         default:
 122                 break;
 123         }
 124
 125         nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
 126         return -EINVAL;
 127 }
 128
 129 static int
 130 nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
 131                     int *N1, int *M1, int *N2, int *M2, int *log2P)
 132 {
 133         struct nouveau_bios *bios = nouveau_bios(priv);
 134         struct nvbios_pll pll;
 135         int ret;
 136
 137         ret = nvbios_pll_parse(bios, reg, &pll);
 138         if (ret)
 139                 return ret;
 140
 141         if (clk < pll.vco1.max_freq)
 142                 pll.vco2.max_freq = 0;
 143
 144         ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
 145         if (ret == 0)
 146                 return -ERANGE;
 147         return ret;
 148 }
 149
 150 static int
 151 nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
 152 {
 153         struct nv40_clock_priv *priv = (void *)clk;
 154         int gclk = cstate->domain[nv_clk_src_core];
 155         int sclk = cstate->domain[nv_clk_src_shader];
 156         int N1, M1, N2, M2, log2P;
 157         int ret;
 158
 159         /* core/geometric clock */
 160         ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
 161                                  &N1, &M1, &N2, &M2, &log2P);
 162         if (ret < 0)
 163                 return ret;
 164
 165         if (N2 == M2) {
 166                 priv->npll_ctrl = 0x80000100 | (log2P << 16);
 167                 priv->npll_coef = (N1 << 8) | M1;
 168         } else {
 169                 priv->npll_ctrl = 0xc0000000 | (log2P << 16);
 170                 priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
 171         }
 172
 173         /* use the second pll for shader/rop clock, if it differs from core */
 174         if (sclk && sclk != gclk) {
 175                 ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
 176                                          &N1, &M1, NULL, NULL, &log2P);
 177                 if (ret < 0)
 178                         return ret;
 179
 180                 priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
 181                 priv->ctrl = 0x00000223;
 182         } else {
 183                 priv->spll = 0x00000000;
 184                 priv->ctrl = 0x00000333;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int
 191 nv40_clock_prog(struct nouveau_clock *clk)
 192 {
 193         struct nv40_clock_priv *priv = (void *)clk;
 194         nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
 195         nv_wr32(priv, 0x004004, priv->npll_coef);
 196         nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
 197         nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
 198         mdelay(5);
 199         nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl);
 200         return 0;
 201 }
 202
 203 static void
 204 nv40_clock_tidy(struct nouveau_clock *clk)
 205 {
 206 }
 207
 208 static int
 209 nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 210                 struct nouveau_oclass *oclass, void *data, u32 size,
 211                 struct nouveau_object **pobject)
 212 {
 213         struct nv40_clock_priv *priv;
 214         int ret;
 215
 216         ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0,
 217                                    true, &priv);
 218         *pobject = nv_object(priv);
 219         if (ret)
 220                 return ret;
 221
 222         priv->base.pll_calc = nv04_clock_pll_calc;
 223         priv->base.pll_prog = nv04_clock_pll_prog;
 224         priv->base.read = nv40_clock_read;
 225         priv->base.calc = nv40_clock_calc;
 226         priv->base.prog = nv40_clock_prog;
 227         priv->base.tidy = nv40_clock_tidy;
 228         return 0;
 229 }
 230
 231 struct nouveau_oclass
 232 nv40_clock_oclass = {
 233         .handle = NV_SUBDEV(CLOCK, 0x40),
 234         .ofuncs = &(struct nouveau_ofuncs) {
 235                 .ctor = nv40_clock_ctor,
 236                 .dtor = _nouveau_clock_dtor,
 237                 .init = _nouveau_clock_init,
 238                 .fini = _nouveau_clock_fini,
 239         },
 240 };