drivers/gpu/drm/nouveau/include/nvkm/core/device.h

   1 #ifndef __NOUVEAU_DEVICE_H__
   2 #define __NOUVEAU_DEVICE_H__
   3
   4 #include <core/object.h>
   5 #include <core/subdev.h>
   6 #include <core/engine.h>
   7 #include <core/event.h>
   8
   9 enum nv_subdev_type {
  10         NVDEV_ENGINE_DEVICE,
  11         NVDEV_SUBDEV_VBIOS,
  12
  13         /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
  14          * *any* of them are initialised.  This subdev category is used
  15          * for any subdevs that the VBIOS init table parsing may call out
  16          * to during POST.
  17          */
  18         NVDEV_SUBDEV_DEVINIT,
  19         NVDEV_SUBDEV_IBUS,
  20         NVDEV_SUBDEV_GPIO,
  21         NVDEV_SUBDEV_I2C,
  22         NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
  23
  24         /* This grouping of subdevs are initialised right after they've
  25          * been created, and are allowed to assume any subdevs in the
  26          * list above them exist and have been initialised.
  27          */
  28         NVDEV_SUBDEV_FUSE,
  29         NVDEV_SUBDEV_MXM,
  30         NVDEV_SUBDEV_MC,
  31         NVDEV_SUBDEV_BUS,
  32         NVDEV_SUBDEV_TIMER,
  33         NVDEV_SUBDEV_FB,
  34         NVDEV_SUBDEV_LTC,
  35         NVDEV_SUBDEV_INSTMEM,
  36         NVDEV_SUBDEV_MMU,
  37         NVDEV_SUBDEV_BAR,
  38         NVDEV_SUBDEV_PMU,
  39         NVDEV_SUBDEV_VOLT,
  40         NVDEV_SUBDEV_THERM,
  41         NVDEV_SUBDEV_CLK,
  42
  43         NVDEV_ENGINE_FIRST,
  44         NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
  45         NVDEV_ENGINE_IFB,
  46         NVDEV_ENGINE_FIFO,
  47         NVDEV_ENGINE_SW,
  48         NVDEV_ENGINE_GR,
  49         NVDEV_ENGINE_MPEG,
  50         NVDEV_ENGINE_ME,
  51         NVDEV_ENGINE_VP,
  52         NVDEV_ENGINE_CIPHER,
  53         NVDEV_ENGINE_BSP,
  54         NVDEV_ENGINE_MSPPP,
  55         NVDEV_ENGINE_CE0,
  56         NVDEV_ENGINE_CE1,
  57         NVDEV_ENGINE_CE2,
  58         NVDEV_ENGINE_VIC,
  59         NVDEV_ENGINE_MSENC,
  60         NVDEV_ENGINE_DISP,
  61         NVDEV_ENGINE_PM,
  62         NVDEV_ENGINE_MSVLD,
  63         NVDEV_ENGINE_SEC,
  64         NVDEV_ENGINE_MSPDEC,
  65
  66         NVDEV_SUBDEV_NR,
  67 };
  68
  69 struct nouveau_device {
  70         struct nouveau_engine engine;
  71         struct list_head head;
  72
  73         struct pci_dev *pdev;
  74         struct platform_device *platformdev;
  75         u64 handle;
  76
  77         struct nvkm_event event;
  78
  79         const char *cfgopt;
  80         const char *dbgopt;
  81         const char *name;
  82         const char *cname;
  83         u64 disable_mask;
  84
  85         enum {
  86                 NV_04    = 0x04,
  87                 NV_10    = 0x10,
  88                 NV_11    = 0x11,
  89                 NV_20    = 0x20,
  90                 NV_30    = 0x30,
  91                 NV_40    = 0x40,
  92                 NV_50    = 0x50,
  93                 NV_C0    = 0xc0,
  94                 NV_E0    = 0xe0,
  95                 GM100    = 0x110,
  96         } card_type;
  97         u32 chipset;
  98         u8  chiprev;
  99         u32 crystal;
 100
 101         struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR];
 102         struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
 103
 104         struct {
 105                 struct notifier_block nb;
 106         } acpi;
 107 };
 108
 109 int nouveau_device_list(u64 *name, int size);
 110
 111 struct nouveau_device *nv_device(void *obj);
 112
 113 static inline bool
 114 nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
 115 {
 116         struct nouveau_device *device = nv_device(object);
 117         return device->pdev->device == dev &&
 118                device->pdev->subsystem_vendor == ven &&
 119                device->pdev->subsystem_device == sub;
 120 }
 121
 122 static inline bool
 123 nv_device_is_pci(struct nouveau_device *device)
 124 {
 125         return device->pdev != NULL;
 126 }
 127
 128 static inline bool
 129 nv_device_is_cpu_coherent(struct nouveau_device *device)
 130 {
 131         return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
 132 }
 133
 134 static inline struct device *
 135 nv_device_base(struct nouveau_device *device)
 136 {
 137         return nv_device_is_pci(device) ? &device->pdev->dev :
 138                                           &device->platformdev->dev;
 139 }
 140
 141 resource_size_t
 142 nv_device_resource_start(struct nouveau_device *device, unsigned int bar);
 143
 144 resource_size_t
 145 nv_device_resource_len(struct nouveau_device *device, unsigned int bar);
 146
 147 int
 148 nv_device_get_irq(struct nouveau_device *device, bool stall);
 149
 150 #endif