drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bios.h>
  26 #include <subdev/bus.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/fuse.h>
  30 #include <subdev/clk.h>
  31 #include <subdev/therm.h>
  32 #include <subdev/mxm.h>
  33 #include <subdev/devinit.h>
  34 #include <subdev/mc.h>
  35 #include <subdev/timer.h>
  36 #include <subdev/fb.h>
  37 #include <subdev/ltc.h>
  38 #include <subdev/ibus.h>
  39 #include <subdev/instmem.h>
  40 #include <subdev/mmu.h>
  41 #include <subdev/bar.h>
  42 #include <subdev/pmu.h>
  43 #include <subdev/volt.h>
  44
  45 #include <engine/device.h>
  46 #include <engine/dmaobj.h>
  47 #include <engine/fifo.h>
  48 #include <engine/sw.h>
  49 #include <engine/gr.h>
  50 #include <engine/disp.h>
  51 #include <engine/ce.h>
  52 #include <engine/bsp.h>
  53 #include <engine/msvld.h>
  54 #include <engine/mspdec.h>
  55 #include <engine/msppp.h>
  56 #include <engine/pm.h>
  57
  58 int
  59 gm100_identify(struct nouveau_device *device)
  60 {
  61         switch (device->chipset) {
  62         case 0x117:
  63                 device->cname = "GM107";
  64                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  65                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
  66                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
  67                 device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
  68                 device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;
  69                 device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
  70                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  71                 device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
  72                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
  73                 device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
  74                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
  75                 device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
  76                 device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
  77                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
  78                 device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
  79                 device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
  80                 device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
  81                 device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
  82
  83 #if 0
  84                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  85 #endif
  86                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
  87                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
  88                 device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
  89                 device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
  90                 device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
  91                 device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
  92 #if 0
  93                 device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
  94 #endif
  95                 device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
  96 #if 0
  97                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
  98                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
  99                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 100 #endif
 101                 break;
 102         case 0x124:
 103                 device->cname = "GM204";
 104                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 105                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
 106                 device->oclass[NVDEV_SUBDEV_I2C    ] =  gm204_i2c_oclass;
 107                 device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
 108 #if 0
 109                 /* looks to be some non-trivial changes */
 110                 device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;
 111                 /* priv ring says no to 0x10eb14 writes */
 112                 device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
 113 #endif
 114                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 115                 device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;
 116                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
 117                 device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
 118                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
 119                 device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
 120                 device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
 121                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 122                 device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
 123                 device->oclass[NVDEV_SUBDEV_MMU    ] = &nvc0_mmu_oclass;
 124                 device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
 125                 device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;
 126 #if 0
 127                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 128 #endif
 129                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 130 #if 0
 131                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 132                 device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 133                 device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 134 #endif
 135                 device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
 136 #if 0
 137                 device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;
 138                 device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;
 139                 device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
 140                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 141                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
 142                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 143 #endif
 144                 break;
 145         default:
 146                 nv_fatal(device, "unknown Maxwell chipset\n");
 147                 return -EINVAL;
 148         }
 149
 150         return 0;
 151 }