drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "priv.h"
  26
  27 static void
  28 pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
  29                  struct nouveau_perfctr *ctr)
  30 {
  31         u32 mask = 0x00000000;
  32         u32 ctrl = 0x00000001;
  33         int i;
  34
  35         for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
  36                 mask |= 1 << (ctr->signal[i] - dom->signal);
  37
  38         nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
  39         nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
  40         nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
  41 }
  42
  43 static void
  44 pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
  45                  struct nouveau_perfctr *ctr)
  46 {
  47         ctr->ctr = ppm->pwr[ctr->slot];
  48         ctr->clk = ppm->pwr[ppm->last];
  49 }
  50
  51 static void
  52 pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
  53 {
  54         int i;
  55
  56         for (i = 0; i <= ppm->last; i++) {
  57                 ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
  58                 nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
  59         }
  60 }
  61
  62 static const struct nouveau_funcdom
  63 pwr_perfctr_func = {
  64         .init = pwr_perfctr_init,
  65         .read = pwr_perfctr_read,
  66         .next = pwr_perfctr_next,
  67 };
  68
  69 const struct nouveau_specdom
  70 nva3_perfmon_pwr[] = {
  71         { 0x20, (const struct nouveau_specsig[]) {
  72                         { 0x00, "pwr_gr_idle" },
  73                         { 0x04, "pwr_bsp_idle" },
  74                         { 0x05, "pwr_vp_idle" },
  75                         { 0x06, "pwr_ppp_idle" },
  76                         { 0x13, "pwr_ce0_idle" },
  77                         {}
  78                 }, &pwr_perfctr_func },
  79         {}
  80 };
  81
  82 const struct nouveau_specdom
  83 nvc0_perfmon_pwr[] = {
  84         { 0x20, (const struct nouveau_specsig[]) {
  85                         { 0x00, "pwr_gr_idle" },
  86                         { 0x04, "pwr_bsp_idle" },
  87                         { 0x05, "pwr_vp_idle" },
  88                         { 0x06, "pwr_ppp_idle" },
  89                         { 0x13, "pwr_ce0_idle" },
  90                         { 0x14, "pwr_ce1_idle" },
  91                         {}
  92                 }, &pwr_perfctr_func },
  93         {}
  94 };
  95
  96 const struct nouveau_specdom
  97 nve0_perfmon_pwr[] = {
  98         { 0x20, (const struct nouveau_specsig[]) {
  99                         { 0x00, "pwr_gr_idle" },
 100                         { 0x04, "pwr_bsp_idle" },
 101                         { 0x05, "pwr_vp_idle" },
 102                         { 0x06, "pwr_ppp_idle" },
 103                         { 0x13, "pwr_ce0_idle" },
 104                         { 0x14, "pwr_ce1_idle" },
 105                         { 0x15, "pwr_ce2_idle" },
 106                         {}
 107                 }, &pwr_perfctr_func },
 108         {}
 109 };