drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nv04.h"
  26
  27 const struct nouveau_mc_intr
  28 nvc0_mc_intr[] = {
  29         { 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work. */
  30         { 0x00000001, NVDEV_ENGINE_MSPPP },
  31         { 0x00000020, NVDEV_ENGINE_CE0 },
  32         { 0x00000040, NVDEV_ENGINE_CE1 },
  33         { 0x00000080, NVDEV_ENGINE_CE2 },
  34         { 0x00000100, NVDEV_ENGINE_FIFO },
  35         { 0x00001000, NVDEV_ENGINE_GR },
  36         { 0x00002000, NVDEV_SUBDEV_FB },
  37         { 0x00008000, NVDEV_ENGINE_MSVLD },
  38         { 0x00040000, NVDEV_SUBDEV_THERM },
  39         { 0x00020000, NVDEV_ENGINE_MSPDEC },
  40         { 0x00100000, NVDEV_SUBDEV_TIMER },
  41         { 0x00200000, NVDEV_SUBDEV_GPIO },      /* PMGR->GPIO */
  42         { 0x00200000, NVDEV_SUBDEV_I2C },       /* PMGR->I2C/AUX */
  43         { 0x01000000, NVDEV_SUBDEV_PMU },
  44         { 0x02000000, NVDEV_SUBDEV_LTC },
  45         { 0x08000000, NVDEV_SUBDEV_FB },
  46         { 0x10000000, NVDEV_SUBDEV_BUS },
  47         { 0x40000000, NVDEV_SUBDEV_IBUS },
  48         { 0x80000000, NVDEV_ENGINE_SW },
  49         {},
  50 };
  51
  52 static void
  53 nvc0_mc_msi_rearm(struct nouveau_mc *pmc)
  54 {
  55         struct nv04_mc_priv *priv = (void *)pmc;
  56         nv_wr32(priv, 0x088704, 0x00000000);
  57 }
  58
  59 void
  60 nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data)
  61 {
  62         nv_wr32(pmc, 0x000260, data);
  63 }
  64
  65 struct nouveau_oclass *
  66 nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
  67         .base.handle = NV_SUBDEV(MC, 0xc0),
  68         .base.ofuncs = &(struct nouveau_ofuncs) {
  69                 .ctor = nv04_mc_ctor,
  70                 .dtor = _nouveau_mc_dtor,
  71                 .init = nv50_mc_init,
  72                 .fini = _nouveau_mc_fini,
  73         },
  74         .intr = nvc0_mc_intr,
  75         .msi_rearm = nvc0_mc_msi_rearm,
  76         .unk260 = nvc0_mc_unk260,
  77 }.base;