1 /**************************************************************************
3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "vmwgfx_drv.h"
31 #define VMW_FENCE_WRAP (1 << 24)
33 irqreturn_t
vmw_irq_handler(int irq
, void *arg
)
35 struct drm_device
*dev
= (struct drm_device
*)arg
;
36 struct vmw_private
*dev_priv
= vmw_priv(dev
);
37 uint32_t status
, masked_status
;
39 spin_lock(&dev_priv
->irq_lock
);
40 status
= inl(dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
41 masked_status
= status
& dev_priv
->irq_mask
;
42 spin_unlock(&dev_priv
->irq_lock
);
45 outl(status
, dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
50 if (masked_status
& (SVGA_IRQFLAG_ANY_FENCE
|
51 SVGA_IRQFLAG_FENCE_GOAL
)) {
52 vmw_fences_update(dev_priv
->fman
);
53 wake_up_all(&dev_priv
->fence_queue
);
56 if (masked_status
& SVGA_IRQFLAG_FIFO_PROGRESS
)
57 wake_up_all(&dev_priv
->fifo_queue
);
59 if (masked_status
& (SVGA_IRQFLAG_COMMAND_BUFFER
|
61 vmw_cmdbuf_tasklet_schedule(dev_priv
->cman
);
66 static bool vmw_fifo_idle(struct vmw_private
*dev_priv
, uint32_t seqno
)
69 return (vmw_read(dev_priv
, SVGA_REG_BUSY
) == 0);
72 void vmw_update_seqno(struct vmw_private
*dev_priv
,
73 struct vmw_fifo_state
*fifo_state
)
75 u32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
76 uint32_t seqno
= ioread32(fifo_mem
+ SVGA_FIFO_FENCE
);
78 if (dev_priv
->last_read_seqno
!= seqno
) {
79 dev_priv
->last_read_seqno
= seqno
;
80 vmw_marker_pull(&fifo_state
->marker_queue
, seqno
);
81 vmw_fences_update(dev_priv
->fman
);
85 bool vmw_seqno_passed(struct vmw_private
*dev_priv
,
88 struct vmw_fifo_state
*fifo_state
;
91 if (likely(dev_priv
->last_read_seqno
- seqno
< VMW_FENCE_WRAP
))
94 fifo_state
= &dev_priv
->fifo
;
95 vmw_update_seqno(dev_priv
, fifo_state
);
96 if (likely(dev_priv
->last_read_seqno
- seqno
< VMW_FENCE_WRAP
))
99 if (!(fifo_state
->capabilities
& SVGA_FIFO_CAP_FENCE
) &&
100 vmw_fifo_idle(dev_priv
, seqno
))
104 * Then check if the seqno is higher than what we've actually
105 * emitted. Then the fence is stale and signaled.
108 ret
= ((atomic_read(&dev_priv
->marker_seq
) - seqno
)
114 int vmw_fallback_wait(struct vmw_private
*dev_priv
,
119 unsigned long timeout
)
121 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
126 unsigned long end_jiffies
= jiffies
+ timeout
;
127 bool (*wait_condition
)(struct vmw_private
*, uint32_t);
130 wait_condition
= (fifo_idle
) ? &vmw_fifo_idle
:
134 * Block command submission while waiting for idle.
138 down_read(&fifo_state
->rwsem
);
139 if (dev_priv
->cman
) {
140 ret
= vmw_cmdbuf_idle(dev_priv
->cman
, interruptible
,
147 signal_seq
= atomic_read(&dev_priv
->marker_seq
);
151 prepare_to_wait(&dev_priv
->fence_queue
, &__wait
,
153 TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
154 if (wait_condition(dev_priv
, seqno
))
156 if (time_after_eq(jiffies
, end_jiffies
)) {
157 DRM_ERROR("SVGA device lockup.\n");
162 else if ((++count
& 0x0F) == 0) {
164 * FIXME: Use schedule_hr_timeout here for
165 * newer kernels and lower CPU utilization.
168 __set_current_state(TASK_RUNNING
);
170 __set_current_state((interruptible
) ?
172 TASK_UNINTERRUPTIBLE
);
174 if (interruptible
&& signal_pending(current
)) {
179 finish_wait(&dev_priv
->fence_queue
, &__wait
);
180 if (ret
== 0 && fifo_idle
) {
181 u32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
182 iowrite32(signal_seq
, fifo_mem
+ SVGA_FIFO_FENCE
);
184 wake_up_all(&dev_priv
->fence_queue
);
187 up_read(&fifo_state
->rwsem
);
192 void vmw_seqno_waiter_add(struct vmw_private
*dev_priv
)
194 spin_lock(&dev_priv
->waiter_lock
);
195 if (dev_priv
->fence_queue_waiters
++ == 0) {
196 unsigned long irq_flags
;
198 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
199 outl(SVGA_IRQFLAG_ANY_FENCE
,
200 dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
201 dev_priv
->irq_mask
|= SVGA_IRQFLAG_ANY_FENCE
;
202 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
203 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
205 spin_unlock(&dev_priv
->waiter_lock
);
208 void vmw_seqno_waiter_remove(struct vmw_private
*dev_priv
)
210 spin_lock(&dev_priv
->waiter_lock
);
211 if (--dev_priv
->fence_queue_waiters
== 0) {
212 unsigned long irq_flags
;
214 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
215 dev_priv
->irq_mask
&= ~SVGA_IRQFLAG_ANY_FENCE
;
216 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
217 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
219 spin_unlock(&dev_priv
->waiter_lock
);
223 void vmw_goal_waiter_add(struct vmw_private
*dev_priv
)
225 spin_lock(&dev_priv
->waiter_lock
);
226 if (dev_priv
->goal_queue_waiters
++ == 0) {
227 unsigned long irq_flags
;
229 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
230 outl(SVGA_IRQFLAG_FENCE_GOAL
,
231 dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
232 dev_priv
->irq_mask
|= SVGA_IRQFLAG_FENCE_GOAL
;
233 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
234 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
236 spin_unlock(&dev_priv
->waiter_lock
);
239 void vmw_goal_waiter_remove(struct vmw_private
*dev_priv
)
241 spin_lock(&dev_priv
->waiter_lock
);
242 if (--dev_priv
->goal_queue_waiters
== 0) {
243 unsigned long irq_flags
;
245 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
246 dev_priv
->irq_mask
&= ~SVGA_IRQFLAG_FENCE_GOAL
;
247 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
248 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
250 spin_unlock(&dev_priv
->waiter_lock
);
253 int vmw_wait_seqno(struct vmw_private
*dev_priv
,
254 bool lazy
, uint32_t seqno
,
255 bool interruptible
, unsigned long timeout
)
258 struct vmw_fifo_state
*fifo
= &dev_priv
->fifo
;
260 if (likely(dev_priv
->last_read_seqno
- seqno
< VMW_FENCE_WRAP
))
263 if (likely(vmw_seqno_passed(dev_priv
, seqno
)))
266 vmw_fifo_ping_host(dev_priv
, SVGA_SYNC_GENERIC
);
268 if (!(fifo
->capabilities
& SVGA_FIFO_CAP_FENCE
))
269 return vmw_fallback_wait(dev_priv
, lazy
, true, seqno
,
270 interruptible
, timeout
);
272 if (!(dev_priv
->capabilities
& SVGA_CAP_IRQMASK
))
273 return vmw_fallback_wait(dev_priv
, lazy
, false, seqno
,
274 interruptible
, timeout
);
276 vmw_seqno_waiter_add(dev_priv
);
279 ret
= wait_event_interruptible_timeout
280 (dev_priv
->fence_queue
,
281 vmw_seqno_passed(dev_priv
, seqno
),
284 ret
= wait_event_timeout
285 (dev_priv
->fence_queue
,
286 vmw_seqno_passed(dev_priv
, seqno
),
289 vmw_seqno_waiter_remove(dev_priv
);
291 if (unlikely(ret
== 0))
293 else if (likely(ret
> 0))
299 void vmw_irq_preinstall(struct drm_device
*dev
)
301 struct vmw_private
*dev_priv
= vmw_priv(dev
);
304 if (!(dev_priv
->capabilities
& SVGA_CAP_IRQMASK
))
307 spin_lock_init(&dev_priv
->irq_lock
);
308 status
= inl(dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
309 outl(status
, dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
312 int vmw_irq_postinstall(struct drm_device
*dev
)
317 void vmw_irq_uninstall(struct drm_device
*dev
)
319 struct vmw_private
*dev_priv
= vmw_priv(dev
);
322 if (!(dev_priv
->capabilities
& SVGA_CAP_IRQMASK
))
325 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, 0);
327 status
= inl(dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
328 outl(status
, dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
331 void vmw_generic_waiter_add(struct vmw_private
*dev_priv
,
332 u32 flag
, int *waiter_count
)
334 unsigned long irq_flags
;
336 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
337 if ((*waiter_count
)++ == 0) {
338 outl(flag
, dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
339 dev_priv
->irq_mask
|= flag
;
340 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
342 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
345 void vmw_generic_waiter_remove(struct vmw_private
*dev_priv
,
346 u32 flag
, int *waiter_count
)
348 unsigned long irq_flags
;
350 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
351 if (--(*waiter_count
) == 0) {
352 dev_priv
->irq_mask
&= ~flag
;
353 vmw_write(dev_priv
, SVGA_REG_IRQMASK
, dev_priv
->irq_mask
);
355 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);