2 * Copyright (C) 2004 Red Hat
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
63 #include <linux/types.h>
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/ide.h>
67 #include <linux/init.h>
69 #define DRV_NAME "it821x"
73 unsigned int smart
:1, /* Are we in smart raid mode */
74 timing10
:1; /* Rev 0x10 */
75 u8 clock_mode
; /* 0, ATA_50 or ATA_66 */
76 u8 want
[2][2]; /* Mode/Pri log for master slave */
77 /* We need these for switching the clock when DMA goes on/off
78 The high byte is the 66Mhz timing */
79 u16 pio
[2]; /* Cached PIO values */
80 u16 mwdma
[2]; /* Cached MWDMA values */
81 u16 udma
[2]; /* Cached UDMA values (per drive) */
92 * We allow users to force the card into non raid mode without
93 * flashing the alternative BIOS. This is also necessary right now
94 * for embedded platforms that cannot run a PC BIOS but are using this
98 static int it8212_noraid
;
101 * it821x_program - program the PIO/MWDMA registers
102 * @drive: drive to tune
103 * @timing: timing info
105 * Program the PIO/MWDMA timing for this channel according to the
109 static void it821x_program(ide_drive_t
*drive
, u16 timing
)
111 ide_hwif_t
*hwif
= drive
->hwif
;
112 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
113 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
114 int channel
= hwif
->channel
;
117 /* Program PIO/MWDMA timing bits */
118 if(itdev
->clock_mode
== ATA_66
)
121 conf
= timing
& 0xFF;
123 pci_write_config_byte(dev
, 0x54 + 4 * channel
, conf
);
127 * it821x_program_udma - program the UDMA registers
128 * @drive: drive to tune
129 * @timing: timing info
131 * Program the UDMA timing for this drive according to the
135 static void it821x_program_udma(ide_drive_t
*drive
, u16 timing
)
137 ide_hwif_t
*hwif
= drive
->hwif
;
138 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
139 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
140 int channel
= hwif
->channel
;
141 u8 unit
= drive
->dn
& 1, conf
;
143 /* Program UDMA timing bits */
144 if(itdev
->clock_mode
== ATA_66
)
147 conf
= timing
& 0xFF;
149 if (itdev
->timing10
== 0)
150 pci_write_config_byte(dev
, 0x56 + 4 * channel
+ unit
, conf
);
152 pci_write_config_byte(dev
, 0x56 + 4 * channel
, conf
);
153 pci_write_config_byte(dev
, 0x56 + 4 * channel
+ 1, conf
);
158 * it821x_clock_strategy
159 * @drive: drive to set up
161 * Select between the 50 and 66Mhz base clocks to get the best
162 * results for this interface.
165 static void it821x_clock_strategy(ide_drive_t
*drive
)
167 ide_hwif_t
*hwif
= drive
->hwif
;
168 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
169 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
170 ide_drive_t
*pair
= ide_get_pair_dev(drive
);
171 int clock
, altclock
, sel
= 0;
172 u8 unit
= drive
->dn
& 1, v
;
174 if(itdev
->want
[0][0] > itdev
->want
[1][0]) {
175 clock
= itdev
->want
[0][1];
176 altclock
= itdev
->want
[1][1];
178 clock
= itdev
->want
[1][1];
179 altclock
= itdev
->want
[0][1];
183 * if both clocks can be used for the mode with the higher priority
184 * use the clock needed by the mode with the lower priority
186 if (clock
== ATA_ANY
)
189 /* Nobody cares - keep the same clock */
193 if(clock
== itdev
->clock_mode
)
196 /* Load this into the controller ? */
198 itdev
->clock_mode
= ATA_66
;
200 itdev
->clock_mode
= ATA_50
;
204 pci_read_config_byte(dev
, 0x50, &v
);
205 v
&= ~(1 << (1 + hwif
->channel
));
206 v
|= sel
<< (1 + hwif
->channel
);
207 pci_write_config_byte(dev
, 0x50, v
);
210 * Reprogram the UDMA/PIO of the pair drive for the switch
211 * MWDMA will be dealt with by the dma switcher
213 if(pair
&& itdev
->udma
[1-unit
] != UDMA_OFF
) {
214 it821x_program_udma(pair
, itdev
->udma
[1-unit
]);
215 it821x_program(pair
, itdev
->pio
[1-unit
]);
218 * Reprogram the UDMA/PIO of our drive for the switch.
219 * MWDMA will be dealt with by the dma switcher
221 if(itdev
->udma
[unit
] != UDMA_OFF
) {
222 it821x_program_udma(drive
, itdev
->udma
[unit
]);
223 it821x_program(drive
, itdev
->pio
[unit
]);
228 * it821x_set_pio_mode - set host controller for PIO mode
230 * @pio: PIO mode number
232 * Tune the host to the desired PIO mode taking into the consideration
233 * the maximum PIO mode supported by the other device on the cable.
236 static void it821x_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
238 ide_hwif_t
*hwif
= drive
->hwif
;
239 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
240 ide_drive_t
*pair
= ide_get_pair_dev(drive
);
241 u8 unit
= drive
->dn
& 1, set_pio
= pio
;
243 /* Spec says 89 ref driver uses 88 */
244 static u16 pio_timings
[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
245 static u8 pio_want
[] = { ATA_66
, ATA_66
, ATA_66
, ATA_66
, ATA_ANY
};
248 * Compute the best PIO mode we can for a given device. We must
249 * pick a speed that does not cause problems with the other device
253 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
254 /* trim PIO to the slowest of the master/slave */
255 if (pair_pio
< set_pio
)
259 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
260 itdev
->want
[unit
][1] = pio_want
[set_pio
];
261 itdev
->want
[unit
][0] = 1; /* PIO is lowest priority */
262 itdev
->pio
[unit
] = pio_timings
[set_pio
];
263 it821x_clock_strategy(drive
);
264 it821x_program(drive
, itdev
->pio
[unit
]);
268 * it821x_tune_mwdma - tune a channel for MWDMA
269 * @drive: drive to set up
270 * @mode_wanted: the target operating mode
272 * Load the timing settings for this device mode into the
273 * controller when doing MWDMA in pass through mode. The caller
274 * must manage the whole lack of per device MWDMA/PIO timings and
275 * the shared MWDMA/PIO timing register.
278 static void it821x_tune_mwdma(ide_drive_t
*drive
, u8 mode_wanted
)
280 ide_hwif_t
*hwif
= drive
->hwif
;
281 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
282 struct it821x_dev
*itdev
= (void *)ide_get_hwifdata(hwif
);
283 u8 unit
= drive
->dn
& 1, channel
= hwif
->channel
, conf
;
285 static u16 dma
[] = { 0x8866, 0x3222, 0x3121 };
286 static u8 mwdma_want
[] = { ATA_ANY
, ATA_66
, ATA_ANY
};
288 itdev
->want
[unit
][1] = mwdma_want
[mode_wanted
];
289 itdev
->want
[unit
][0] = 2; /* MWDMA is low priority */
290 itdev
->mwdma
[unit
] = dma
[mode_wanted
];
291 itdev
->udma
[unit
] = UDMA_OFF
;
293 /* UDMA bits off - Revision 0x10 do them in pairs */
294 pci_read_config_byte(dev
, 0x50, &conf
);
296 conf
|= channel
? 0x60: 0x18;
298 conf
|= 1 << (3 + 2 * channel
+ unit
);
299 pci_write_config_byte(dev
, 0x50, conf
);
301 it821x_clock_strategy(drive
);
302 /* FIXME: do we need to program this ? */
303 /* it821x_program(drive, itdev->mwdma[unit]); */
307 * it821x_tune_udma - tune a channel for UDMA
308 * @drive: drive to set up
309 * @mode_wanted: the target operating mode
311 * Load the timing settings for this device mode into the
312 * controller when doing UDMA modes in pass through.
315 static void it821x_tune_udma(ide_drive_t
*drive
, u8 mode_wanted
)
317 ide_hwif_t
*hwif
= drive
->hwif
;
318 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
319 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
320 u8 unit
= drive
->dn
& 1, channel
= hwif
->channel
, conf
;
322 static u16 udma
[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
323 static u8 udma_want
[] = { ATA_ANY
, ATA_50
, ATA_ANY
, ATA_66
, ATA_66
, ATA_50
, ATA_66
};
325 itdev
->want
[unit
][1] = udma_want
[mode_wanted
];
326 itdev
->want
[unit
][0] = 3; /* UDMA is high priority */
327 itdev
->mwdma
[unit
] = MWDMA_OFF
;
328 itdev
->udma
[unit
] = udma
[mode_wanted
];
330 itdev
->udma
[unit
] |= 0x8080; /* UDMA 5/6 select on */
332 /* UDMA on. Again revision 0x10 must do the pair */
333 pci_read_config_byte(dev
, 0x50, &conf
);
335 conf
&= channel
? 0x9F: 0xE7;
337 conf
&= ~ (1 << (3 + 2 * channel
+ unit
));
338 pci_write_config_byte(dev
, 0x50, conf
);
340 it821x_clock_strategy(drive
);
341 it821x_program_udma(drive
, itdev
->udma
[unit
]);
346 * it821x_dma_read - DMA hook
347 * @drive: drive for DMA
349 * The IT821x has a single timing register for MWDMA and for PIO
350 * operations. As we flip back and forth we have to reload the
351 * clock. In addition the rev 0x10 device only works if the same
352 * timing value is loaded into the master and slave UDMA clock
353 * so we must also reload that.
355 * FIXME: we could figure out in advance if we need to do reloads
358 static void it821x_dma_start(ide_drive_t
*drive
)
360 ide_hwif_t
*hwif
= drive
->hwif
;
361 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
362 u8 unit
= drive
->dn
& 1;
364 if(itdev
->mwdma
[unit
] != MWDMA_OFF
)
365 it821x_program(drive
, itdev
->mwdma
[unit
]);
366 else if(itdev
->udma
[unit
] != UDMA_OFF
&& itdev
->timing10
)
367 it821x_program_udma(drive
, itdev
->udma
[unit
]);
368 ide_dma_start(drive
);
372 * it821x_dma_write - DMA hook
373 * @drive: drive for DMA stop
375 * The IT821x has a single timing register for MWDMA and for PIO
376 * operations. As we flip back and forth we have to reload the
380 static int it821x_dma_end(ide_drive_t
*drive
)
382 ide_hwif_t
*hwif
= drive
->hwif
;
383 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
384 int ret
= ide_dma_end(drive
);
385 u8 unit
= drive
->dn
& 1;
387 if(itdev
->mwdma
[unit
] != MWDMA_OFF
)
388 it821x_program(drive
, itdev
->pio
[unit
]);
393 * it821x_set_dma_mode - set host controller for DMA mode
397 * Tune the ITE chipset for the desired DMA mode.
400 static void it821x_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
403 * MWDMA tuning is really hard because our MWDMA and PIO
404 * timings are kept in the same place. We can switch in the
405 * host dma on/off callbacks.
407 if (speed
>= XFER_UDMA_0
&& speed
<= XFER_UDMA_6
)
408 it821x_tune_udma(drive
, speed
- XFER_UDMA_0
);
409 else if (speed
>= XFER_MW_DMA_0
&& speed
<= XFER_MW_DMA_2
)
410 it821x_tune_mwdma(drive
, speed
- XFER_MW_DMA_0
);
414 * it821x_cable_detect - cable detection
415 * @hwif: interface to check
417 * Check for the presence of an ATA66 capable cable on the
418 * interface. Problematic as it seems some cards don't have
419 * the needed logic onboard.
422 static u8
it821x_cable_detect(ide_hwif_t
*hwif
)
424 /* The reference driver also only does disk side */
425 return ATA_CBL_PATA80
;
429 * it821x_quirkproc - post init callback
432 * This callback is run after the drive has been probed but
433 * before anything gets attached. It allows drivers to do any
434 * final tuning that is needed, or fixups to work around bugs.
437 static void it821x_quirkproc(ide_drive_t
*drive
)
439 struct it821x_dev
*itdev
= ide_get_hwifdata(drive
->hwif
);
444 * If we are in pass through mode then not much
445 * needs to be done, but we do bother to clear the
446 * IRQ mask as we may well be in PIO (eg rev 0x10)
447 * for now and we know unmasking is safe on this chipset.
449 drive
->dev_flags
|= IDE_DFLAG_UNMASK
;
452 * Perform fixups on smart mode. We need to "lose" some
453 * capabilities the firmware lacks but does not filter, and
454 * also patch up some capability bits that it forgets to set
458 /* Check for RAID v native */
459 if (strstr((char *)&id
[ATA_ID_PROD
],
460 "Integrated Technology Express")) {
461 /* In raid mode the ident block is slightly buggy
462 We need to set the bits so that the IDE layer knows
463 LBA28. LBA48 and DMA ar valid */
464 id
[ATA_ID_CAPABILITY
] |= (3 << 8); /* LBA28, DMA */
465 id
[ATA_ID_COMMAND_SET_2
] |= 0x0400; /* LBA48 valid */
466 id
[ATA_ID_CFS_ENABLE_2
] |= 0x0400; /* LBA48 on */
467 /* Reporting logic */
468 printk(KERN_INFO
"%s: IT8212 %sRAID %d volume",
469 drive
->name
, id
[147] ? "Bootable " : "",
471 if (id
[ATA_ID_CSFO
] != 1)
472 printk(KERN_CONT
"(%dK stripe)", id
[146]);
473 printk(KERN_CONT
".\n");
475 /* Non RAID volume. Fixups to stop the core code
476 doing unsupported things */
477 id
[ATA_ID_FIELD_VALID
] &= 3;
478 id
[ATA_ID_QUEUE_DEPTH
] = 0;
479 id
[ATA_ID_COMMAND_SET_1
] = 0;
480 id
[ATA_ID_COMMAND_SET_2
] &= 0xC400;
481 id
[ATA_ID_CFSSE
] &= 0xC000;
482 id
[ATA_ID_CFS_ENABLE_1
] = 0;
483 id
[ATA_ID_CFS_ENABLE_2
] &= 0xC400;
484 id
[ATA_ID_CSF_DEFAULT
] &= 0xC000;
488 id
[ATA_ID_CFA_POWER
] = 0;
489 printk(KERN_INFO
"%s: Performing identify fixups.\n",
494 * Set MWDMA0 mode as enabled/support - just to tell
495 * IDE core that DMA is supported (it821x hardware
496 * takes care of DMA mode programming).
498 if (ata_id_has_dma(id
)) {
499 id
[ATA_ID_MWDMA_MODES
] |= 0x0101;
500 drive
->current_speed
= XFER_MW_DMA_0
;
506 static struct ide_dma_ops it821x_pass_through_dma_ops
= {
507 .dma_host_set
= ide_dma_host_set
,
508 .dma_setup
= ide_dma_setup
,
509 .dma_exec_cmd
= ide_dma_exec_cmd
,
510 .dma_start
= it821x_dma_start
,
511 .dma_end
= it821x_dma_end
,
512 .dma_test_irq
= ide_dma_test_irq
,
513 .dma_timeout
= ide_dma_timeout
,
514 .dma_lost_irq
= ide_dma_lost_irq
,
515 .dma_sff_read_status
= ide_dma_sff_read_status
,
519 * init_hwif_it821x - set up hwif structs
520 * @hwif: interface to set up
522 * We do the basic set up of the interface structure. The IT8212
523 * requires several custom handlers so we override the default
524 * ide DMA handlers appropriately
527 static void __devinit
init_hwif_it821x(ide_hwif_t
*hwif
)
529 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
530 struct ide_host
*host
= pci_get_drvdata(dev
);
531 struct it821x_dev
*itdevs
= host
->host_priv
;
532 struct it821x_dev
*idev
= itdevs
+ hwif
->channel
;
535 ide_set_hwifdata(hwif
, idev
);
537 pci_read_config_byte(dev
, 0x50, &conf
);
540 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
541 /* Long I/O's although allowed in LBA48 space cause the
542 onboard firmware to enter the twighlight zone */
546 /* Pull the current clocks from 0x50 also */
547 if (conf
& (1 << (1 + hwif
->channel
)))
548 idev
->clock_mode
= ATA_50
;
550 idev
->clock_mode
= ATA_66
;
552 idev
->want
[0][1] = ATA_ANY
;
553 idev
->want
[1][1] = ATA_ANY
;
556 * Not in the docs but according to the reference driver
560 pci_read_config_byte(dev
, 0x08, &conf
);
563 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
564 if (idev
->smart
== 0)
565 printk(KERN_WARNING DRV_NAME
" %s: revision 0x10, "
566 "workarounds activated\n", pci_name(dev
));
569 if (idev
->smart
== 0) {
570 /* MWDMA/PIO clock switching for pass through mode */
571 hwif
->dma_ops
= &it821x_pass_through_dma_ops
;
573 hwif
->host_flags
|= IDE_HFLAG_NO_SET_MODE
;
575 if (hwif
->dma_base
== 0)
578 hwif
->ultra_mask
= ATA_UDMA6
;
579 hwif
->mwdma_mask
= ATA_MWDMA2
;
582 static void it8212_disable_raid(struct pci_dev
*dev
)
584 /* Reset local CPU, and set BIOS not ready */
585 pci_write_config_byte(dev
, 0x5E, 0x01);
587 /* Set to bypass mode, and reset PCI bus */
588 pci_write_config_byte(dev
, 0x50, 0x00);
589 pci_write_config_word(dev
, PCI_COMMAND
,
590 PCI_COMMAND_PARITY
| PCI_COMMAND_IO
|
591 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
592 pci_write_config_word(dev
, 0x40, 0xA0F3);
594 pci_write_config_dword(dev
,0x4C, 0x02040204);
595 pci_write_config_byte(dev
, 0x42, 0x36);
596 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x20);
599 static unsigned int init_chipset_it821x(struct pci_dev
*dev
)
602 static char *mode
[2] = { "pass through", "smart" };
604 /* Force the card into bypass mode if so requested */
606 printk(KERN_INFO DRV_NAME
" %s: forcing bypass mode\n",
608 it8212_disable_raid(dev
);
610 pci_read_config_byte(dev
, 0x50, &conf
);
611 printk(KERN_INFO DRV_NAME
" %s: controller in %s mode\n",
612 pci_name(dev
), mode
[conf
& 1]);
616 static const struct ide_port_ops it821x_port_ops
= {
617 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
618 .set_pio_mode
= it821x_set_pio_mode
,
619 .set_dma_mode
= it821x_set_dma_mode
,
620 .quirkproc
= it821x_quirkproc
,
621 .cable_detect
= it821x_cable_detect
,
624 static const struct ide_port_info it821x_chipset __devinitdata
= {
626 .init_chipset
= init_chipset_it821x
,
627 .init_hwif
= init_hwif_it821x
,
628 .port_ops
= &it821x_port_ops
,
629 .pio_mask
= ATA_PIO4
,
633 * it821x_init_one - pci layer discovery entry
635 * @id: ident table entry
637 * Called by the PCI code when it finds an ITE821x controller.
638 * We then use the IDE PCI generic helper to do most of the work.
641 static int __devinit
it821x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
643 struct it821x_dev
*itdevs
;
646 itdevs
= kzalloc(2 * sizeof(*itdevs
), GFP_KERNEL
);
647 if (itdevs
== NULL
) {
648 printk(KERN_ERR DRV_NAME
" %s: out of memory\n", pci_name(dev
));
652 rc
= ide_pci_init_one(dev
, &it821x_chipset
, itdevs
);
659 static void __devexit
it821x_remove(struct pci_dev
*dev
)
661 struct ide_host
*host
= pci_get_drvdata(dev
);
662 struct it821x_dev
*itdevs
= host
->host_priv
;
668 static const struct pci_device_id it821x_pci_tbl
[] = {
669 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8211
), 0 },
670 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8212
), 0 },
674 MODULE_DEVICE_TABLE(pci
, it821x_pci_tbl
);
676 static struct pci_driver it821x_pci_driver
= {
677 .name
= "ITE821x IDE",
678 .id_table
= it821x_pci_tbl
,
679 .probe
= it821x_init_one
,
680 .remove
= __devexit_p(it821x_remove
),
681 .suspend
= ide_pci_suspend
,
682 .resume
= ide_pci_resume
,
685 static int __init
it821x_ide_init(void)
687 return ide_pci_register_driver(&it821x_pci_driver
);
690 static void __exit
it821x_ide_exit(void)
692 pci_unregister_driver(&it821x_pci_driver
);
695 module_init(it821x_ide_init
);
696 module_exit(it821x_ide_exit
);
698 module_param_named(noraid
, it8212_noraid
, int, S_IRUGO
);
699 MODULE_PARM_DESC(noraid
, "Force card into bypass mode");
701 MODULE_AUTHOR("Alan Cox");
702 MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
703 MODULE_LICENSE("GPL");