2 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * May be copied or modified under the terms of the GNU General Public License
8 * Development of this chipset driver was funded
9 * by the nice folks at National Semiconductor.
12 * CS5530 documentation available from National Semiconductor.
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/hdreg.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/ide.h>
25 #define DRV_NAME "cs5530"
28 * Here are the standard PIO mode 0-4 timings for each "format".
29 * Format-0 uses fast data reg timings, with slower command reg timings.
30 * Format-1 uses fast timings for all registers, but won't work with all drives.
32 static unsigned int cs5530_pio_timings
[2][5] = {
33 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
34 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
38 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
40 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
41 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
44 * cs5530_set_pio_mode - set host controller for PIO mode
46 * @pio: PIO mode number
48 * Handles setting of PIO mode for the chipset.
50 * The init_hwif_cs5530() routine guarantees that all drives
51 * will have valid default PIO timings set up before we get here.
54 static void cs5530_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
56 unsigned long basereg
= CS5530_BASEREG(drive
->hwif
);
57 unsigned int format
= (inl(basereg
+ 4) >> 31) & 1;
59 outl(cs5530_pio_timings
[format
][pio
], basereg
+ ((drive
->dn
& 1)<<3));
63 * cs5530_udma_filter - UDMA filter
66 * cs5530_udma_filter() does UDMA mask filtering for the given drive
67 * taking into the consideration capabilities of the mate device.
69 * The CS5530 specifies that two drives sharing a cable cannot mix
70 * UDMA/MDMA. It has to be one or the other, for the pair, though
71 * different timings can still be chosen for each drive. We could
72 * set the appropriate timing bits on the fly, but that might be
73 * a bit confusing. So, for now we statically handle this requirement
74 * by looking at our mate drive to see what it is capable of, before
75 * choosing a mode for our own drive.
77 * Note: This relies on the fact we never fail from UDMA to MWDMA2
78 * but instead drop to PIO.
81 static u8
cs5530_udma_filter(ide_drive_t
*drive
)
83 ide_hwif_t
*hwif
= drive
->hwif
;
84 ide_drive_t
*mate
= &hwif
->drives
[(drive
->dn
& 1) ^ 1];
85 struct hd_driveid
*mateid
= mate
->id
;
86 u8 mask
= hwif
->ultra_mask
;
88 if (mate
->present
== 0)
91 if ((mateid
->capability
& 1) && __ide_dma_bad_drive(mate
) == 0) {
92 if ((mateid
->field_valid
& 4) && (mateid
->dma_ultra
& 7))
94 if ((mateid
->field_valid
& 2) && (mateid
->dma_mword
& 7))
101 static void cs5530_set_dma_mode(ide_drive_t
*drive
, const u8 mode
)
103 unsigned long basereg
;
104 unsigned int reg
, timings
= 0;
107 case XFER_UDMA_0
: timings
= 0x00921250; break;
108 case XFER_UDMA_1
: timings
= 0x00911140; break;
109 case XFER_UDMA_2
: timings
= 0x00911030; break;
110 case XFER_MW_DMA_0
: timings
= 0x00077771; break;
111 case XFER_MW_DMA_1
: timings
= 0x00012121; break;
112 case XFER_MW_DMA_2
: timings
= 0x00002020; break;
114 basereg
= CS5530_BASEREG(drive
->hwif
);
115 reg
= inl(basereg
+ 4); /* get drive0 config register */
116 timings
|= reg
& 0x80000000; /* preserve PIO format bit */
117 if ((drive
-> dn
& 1) == 0) { /* are we configuring drive0? */
118 outl(timings
, basereg
+ 4); /* write drive0 config register */
120 if (timings
& 0x00100000)
121 reg
|= 0x00100000; /* enable UDMA timings for both drives */
123 reg
&= ~0x00100000; /* disable UDMA timings for both drives */
124 outl(reg
, basereg
+ 4); /* write drive0 config register */
125 outl(timings
, basereg
+ 12); /* write drive1 config register */
130 * init_chipset_5530 - set up 5530 bridge
133 * Initialize the cs5530 bridge for reliable IDE DMA operation.
136 static unsigned int __devinit
init_chipset_cs5530(struct pci_dev
*dev
)
138 struct pci_dev
*master_0
= NULL
, *cs5530_0
= NULL
;
140 if (pci_resource_start(dev
, 4) == 0)
144 while ((dev
= pci_get_device(PCI_VENDOR_ID_CYRIX
, PCI_ANY_ID
, dev
)) != NULL
) {
145 switch (dev
->device
) {
146 case PCI_DEVICE_ID_CYRIX_PCI_MASTER
:
147 master_0
= pci_dev_get(dev
);
149 case PCI_DEVICE_ID_CYRIX_5530_LEGACY
:
150 cs5530_0
= pci_dev_get(dev
);
155 printk(KERN_ERR DRV_NAME
": unable to locate PCI MASTER function\n");
159 printk(KERN_ERR DRV_NAME
": unable to locate CS5530 LEGACY function\n");
164 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
165 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
168 pci_set_master(cs5530_0
);
169 pci_try_set_mwi(cs5530_0
);
172 * Set PCI CacheLineSize to 16-bytes:
173 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
176 pci_write_config_byte(cs5530_0
, PCI_CACHE_LINE_SIZE
, 0x04);
179 * Disable trapping of UDMA register accesses (Win98 hack):
180 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
183 pci_write_config_word(cs5530_0
, 0xd0, 0x5006);
186 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
187 * The other settings are what is necessary to get the register
188 * into a sane state for IDE DMA operation.
191 pci_write_config_byte(master_0
, 0x40, 0x1e);
194 * Set max PCI burst size (16-bytes seems to work best):
195 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
196 * all others: clear bit-1 at 0x41, and do:
197 * 128bytes: OR 0x00 at 0x41
198 * 256bytes: OR 0x04 at 0x41
199 * 512bytes: OR 0x08 at 0x41
200 * 1024bytes: OR 0x0c at 0x41
203 pci_write_config_byte(master_0
, 0x41, 0x14);
206 * These settings are necessary to get the chip
207 * into a sane state for IDE DMA operation.
210 pci_write_config_byte(master_0
, 0x42, 0x00);
211 pci_write_config_byte(master_0
, 0x43, 0xc1);
214 pci_dev_put(master_0
);
215 pci_dev_put(cs5530_0
);
220 * init_hwif_cs5530 - initialise an IDE channel
221 * @hwif: IDE to initialize
223 * This gets invoked by the IDE driver once for each channel. It
224 * performs channel-specific pre-initialization before drive probing.
227 static void __devinit
init_hwif_cs5530 (ide_hwif_t
*hwif
)
229 unsigned long basereg
;
232 basereg
= CS5530_BASEREG(hwif
);
233 d0_timings
= inl(basereg
+ 0);
234 if (CS5530_BAD_PIO(d0_timings
))
235 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 0);
236 if (CS5530_BAD_PIO(inl(basereg
+ 8)))
237 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 8);
240 static const struct ide_port_ops cs5530_port_ops
= {
241 .set_pio_mode
= cs5530_set_pio_mode
,
242 .set_dma_mode
= cs5530_set_dma_mode
,
243 .udma_filter
= cs5530_udma_filter
,
246 static const struct ide_port_info cs5530_chipset __devinitdata
= {
248 .init_chipset
= init_chipset_cs5530
,
249 .init_hwif
= init_hwif_cs5530
,
250 .port_ops
= &cs5530_port_ops
,
251 .host_flags
= IDE_HFLAG_SERIALIZE
|
252 IDE_HFLAG_POST_SET_MODE
,
253 .pio_mask
= ATA_PIO4
,
254 .mwdma_mask
= ATA_MWDMA2
,
255 .udma_mask
= ATA_UDMA2
,
258 static int __devinit
cs5530_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
260 return ide_pci_init_one(dev
, &cs5530_chipset
, NULL
);
263 static const struct pci_device_id cs5530_pci_tbl
[] = {
264 { PCI_VDEVICE(CYRIX
, PCI_DEVICE_ID_CYRIX_5530_IDE
), 0 },
267 MODULE_DEVICE_TABLE(pci
, cs5530_pci_tbl
);
269 static struct pci_driver driver
= {
270 .name
= "CS5530 IDE",
271 .id_table
= cs5530_pci_tbl
,
272 .probe
= cs5530_init_one
,
273 .remove
= ide_pci_remove
,
276 static int __init
cs5530_ide_init(void)
278 return ide_pci_register_driver(&driver
);
281 static void __exit
cs5530_ide_exit(void)
283 pci_unregister_driver(&driver
);
286 module_init(cs5530_ide_init
);
287 module_exit(cs5530_ide_exit
);
289 MODULE_AUTHOR("Mark Lord");
290 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
291 MODULE_LICENSE("GPL");