2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/spinlock.h>
11 #include <linux/sched.h>
12 #include <linux/slab.h>
13 #include <linux/sched.h>
14 #include <linux/mutex.h>
16 #include <linux/uaccess.h>
17 #include <asm/synch.h>
22 static int afu_control(struct cxl_afu
*afu
, u64 command
,
23 u64 result
, u64 mask
, bool enabled
)
25 u64 AFU_Cntl
= cxl_p2n_read(afu
, CXL_AFU_Cntl_An
);
26 unsigned long timeout
= jiffies
+ (HZ
* CXL_TIMEOUT
);
28 spin_lock(&afu
->afu_cntl_lock
);
29 pr_devel("AFU command starting: %llx\n", command
);
31 cxl_p2n_write(afu
, CXL_AFU_Cntl_An
, AFU_Cntl
| command
);
33 AFU_Cntl
= cxl_p2n_read(afu
, CXL_AFU_Cntl_An
);
34 while ((AFU_Cntl
& mask
) != result
) {
35 if (time_after_eq(jiffies
, timeout
)) {
36 dev_warn(&afu
->dev
, "WARNING: AFU control timed out!\n");
37 spin_unlock(&afu
->afu_cntl_lock
);
40 pr_devel_ratelimited("AFU control... (0x%.16llx)\n",
43 AFU_Cntl
= cxl_p2n_read(afu
, CXL_AFU_Cntl_An
);
45 pr_devel("AFU command complete: %llx\n", command
);
46 afu
->enabled
= enabled
;
47 spin_unlock(&afu
->afu_cntl_lock
);
52 static int afu_enable(struct cxl_afu
*afu
)
54 pr_devel("AFU enable request\n");
56 return afu_control(afu
, CXL_AFU_Cntl_An_E
,
57 CXL_AFU_Cntl_An_ES_Enabled
,
58 CXL_AFU_Cntl_An_ES_MASK
, true);
61 int cxl_afu_disable(struct cxl_afu
*afu
)
63 pr_devel("AFU disable request\n");
65 return afu_control(afu
, 0, CXL_AFU_Cntl_An_ES_Disabled
,
66 CXL_AFU_Cntl_An_ES_MASK
, false);
69 /* This will disable as well as reset */
70 int cxl_afu_reset(struct cxl_afu
*afu
)
72 pr_devel("AFU reset request\n");
74 return afu_control(afu
, CXL_AFU_Cntl_An_RA
,
75 CXL_AFU_Cntl_An_RS_Complete
| CXL_AFU_Cntl_An_ES_Disabled
,
76 CXL_AFU_Cntl_An_RS_MASK
| CXL_AFU_Cntl_An_ES_MASK
,
80 static int afu_check_and_enable(struct cxl_afu
*afu
)
84 return afu_enable(afu
);
87 int cxl_psl_purge(struct cxl_afu
*afu
)
89 u64 PSL_CNTL
= cxl_p1n_read(afu
, CXL_PSL_SCNTL_An
);
90 u64 AFU_Cntl
= cxl_p2n_read(afu
, CXL_AFU_Cntl_An
);
93 unsigned long timeout
= jiffies
+ (HZ
* CXL_TIMEOUT
);
95 pr_devel("PSL purge request\n");
97 if ((AFU_Cntl
& CXL_AFU_Cntl_An_ES_MASK
) != CXL_AFU_Cntl_An_ES_Disabled
) {
98 WARN(1, "psl_purge request while AFU not disabled!\n");
102 cxl_p1n_write(afu
, CXL_PSL_SCNTL_An
,
103 PSL_CNTL
| CXL_PSL_SCNTL_An_Pc
);
104 start
= local_clock();
105 PSL_CNTL
= cxl_p1n_read(afu
, CXL_PSL_SCNTL_An
);
106 while ((PSL_CNTL
& CXL_PSL_SCNTL_An_Ps_MASK
)
107 == CXL_PSL_SCNTL_An_Ps_Pending
) {
108 if (time_after_eq(jiffies
, timeout
)) {
109 dev_warn(&afu
->dev
, "WARNING: PSL Purge timed out!\n");
112 dsisr
= cxl_p2n_read(afu
, CXL_PSL_DSISR_An
);
113 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%.16llx PSL_DSISR: 0x%.16llx\n", PSL_CNTL
, dsisr
);
114 if (dsisr
& CXL_PSL_DSISR_TRANS
) {
115 dar
= cxl_p2n_read(afu
, CXL_PSL_DAR_An
);
116 dev_notice(&afu
->dev
, "PSL purge terminating pending translation, DSISR: 0x%.16llx, DAR: 0x%.16llx\n", dsisr
, dar
);
117 cxl_p2n_write(afu
, CXL_PSL_TFC_An
, CXL_PSL_TFC_An_AE
);
119 dev_notice(&afu
->dev
, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%.16llx\n", dsisr
);
120 cxl_p2n_write(afu
, CXL_PSL_TFC_An
, CXL_PSL_TFC_An_A
);
124 PSL_CNTL
= cxl_p1n_read(afu
, CXL_PSL_SCNTL_An
);
127 pr_devel("PSL purged in %lld ns\n", end
- start
);
129 cxl_p1n_write(afu
, CXL_PSL_SCNTL_An
,
130 PSL_CNTL
& ~CXL_PSL_SCNTL_An_Pc
);
134 static int spa_max_procs(int spa_size
)
138 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
139 * Most of that junk is really just an overly-complicated way of saying
140 * the last 256 bytes are __aligned(128), so it's really:
141 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
143 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
145 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
146 * Ignore the alignment (which is safe in this case as long as we are
147 * careful with our rounding) and solve for n:
149 return ((spa_size
/ 8) - 96) / 17;
152 static int alloc_spa(struct cxl_afu
*afu
)
156 /* Work out how many pages to allocate */
160 afu
->spa_size
= (1 << afu
->spa_order
) * PAGE_SIZE
;
161 afu
->spa_max_procs
= spa_max_procs(afu
->spa_size
);
162 } while (afu
->spa_max_procs
< afu
->num_procs
);
164 WARN_ON(afu
->spa_size
> 0x100000); /* Max size supported by the hardware */
166 if (!(afu
->spa
= (struct cxl_process_element
*)
167 __get_free_pages(GFP_KERNEL
| __GFP_ZERO
, afu
->spa_order
))) {
168 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
171 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
172 1<<afu
->spa_order
, afu
->spa_max_procs
, afu
->num_procs
);
174 afu
->sw_command_status
= (__be64
*)((char *)afu
->spa
+
175 ((afu
->spa_max_procs
+ 3) * 128));
177 spap
= virt_to_phys(afu
->spa
) & CXL_PSL_SPAP_Addr
;
178 spap
|= ((afu
->spa_size
>> (12 - CXL_PSL_SPAP_Size_Shift
)) - 1) & CXL_PSL_SPAP_Size
;
179 spap
|= CXL_PSL_SPAP_V
;
180 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu
->spa
, afu
->spa_max_procs
, afu
->sw_command_status
, spap
);
181 cxl_p1n_write(afu
, CXL_PSL_SPAP_An
, spap
);
186 static void release_spa(struct cxl_afu
*afu
)
188 cxl_p1n_write(afu
, CXL_PSL_SPAP_An
, 0);
189 free_pages((unsigned long) afu
->spa
, afu
->spa_order
);
192 int cxl_tlb_slb_invalidate(struct cxl
*adapter
)
194 unsigned long timeout
= jiffies
+ (HZ
* CXL_TIMEOUT
);
196 pr_devel("CXL adapter wide TLBIA & SLBIA\n");
198 cxl_p1_write(adapter
, CXL_PSL_AFUSEL
, CXL_PSL_AFUSEL_A
);
200 cxl_p1_write(adapter
, CXL_PSL_TLBIA
, CXL_TLB_SLB_IQ_ALL
);
201 while (cxl_p1_read(adapter
, CXL_PSL_TLBIA
) & CXL_TLB_SLB_P
) {
202 if (time_after_eq(jiffies
, timeout
)) {
203 dev_warn(&adapter
->dev
, "WARNING: CXL adapter wide TLBIA timed out!\n");
209 cxl_p1_write(adapter
, CXL_PSL_SLBIA
, CXL_TLB_SLB_IQ_ALL
);
210 while (cxl_p1_read(adapter
, CXL_PSL_SLBIA
) & CXL_TLB_SLB_P
) {
211 if (time_after_eq(jiffies
, timeout
)) {
212 dev_warn(&adapter
->dev
, "WARNING: CXL adapter wide SLBIA timed out!\n");
220 int cxl_afu_slbia(struct cxl_afu
*afu
)
222 unsigned long timeout
= jiffies
+ (HZ
* CXL_TIMEOUT
);
224 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
225 cxl_p2n_write(afu
, CXL_SLBIA_An
, CXL_TLB_SLB_IQ_ALL
);
226 while (cxl_p2n_read(afu
, CXL_SLBIA_An
) & CXL_TLB_SLB_P
) {
227 if (time_after_eq(jiffies
, timeout
)) {
228 dev_warn(&afu
->dev
, "WARNING: CXL AFU SLBIA timed out!\n");
236 static int cxl_write_sstp(struct cxl_afu
*afu
, u64 sstp0
, u64 sstp1
)
240 /* 1. Disable SSTP by writing 0 to SSTP1[V] */
241 cxl_p2n_write(afu
, CXL_SSTP1_An
, 0);
243 /* 2. Invalidate all SLB entries */
244 if ((rc
= cxl_afu_slbia(afu
)))
247 /* 3. Set SSTP0_An */
248 cxl_p2n_write(afu
, CXL_SSTP0_An
, sstp0
);
250 /* 4. Set SSTP1_An */
251 cxl_p2n_write(afu
, CXL_SSTP1_An
, sstp1
);
256 /* Using per slice version may improve performance here. (ie. SLBIA_An) */
257 static void slb_invalid(struct cxl_context
*ctx
)
259 struct cxl
*adapter
= ctx
->afu
->adapter
;
262 WARN_ON(!mutex_is_locked(&ctx
->afu
->spa_mutex
));
264 cxl_p1_write(adapter
, CXL_PSL_LBISEL
,
265 ((u64
)be32_to_cpu(ctx
->elem
->common
.pid
) << 32) |
266 be32_to_cpu(ctx
->elem
->lpid
));
267 cxl_p1_write(adapter
, CXL_PSL_SLBIA
, CXL_TLB_SLB_IQ_LPIDPID
);
270 slbia
= cxl_p1_read(adapter
, CXL_PSL_SLBIA
);
271 if (!(slbia
& CXL_TLB_SLB_P
))
277 static int do_process_element_cmd(struct cxl_context
*ctx
,
278 u64 cmd
, u64 pe_state
)
281 unsigned long timeout
= jiffies
+ (HZ
* CXL_TIMEOUT
);
283 WARN_ON(!ctx
->afu
->enabled
);
285 ctx
->elem
->software_state
= cpu_to_be32(pe_state
);
287 *(ctx
->afu
->sw_command_status
) = cpu_to_be64(cmd
| 0 | ctx
->pe
);
289 cxl_p1n_write(ctx
->afu
, CXL_PSL_LLCMD_An
, cmd
| ctx
->pe
);
291 if (time_after_eq(jiffies
, timeout
)) {
292 dev_warn(&ctx
->afu
->dev
, "WARNING: Process Element Command timed out!\n");
295 state
= be64_to_cpup(ctx
->afu
->sw_command_status
);
296 if (state
== ~0ULL) {
297 pr_err("cxl: Error adding process element to AFU\n");
300 if ((state
& (CXL_SPA_SW_CMD_MASK
| CXL_SPA_SW_STATE_MASK
| CXL_SPA_SW_LINK_MASK
)) ==
301 (cmd
| (cmd
>> 16) | ctx
->pe
))
304 * The command won't finish in the PSL if there are
305 * outstanding DSIs. Hence we need to yield here in
306 * case there are outstanding DSIs that we need to
307 * service. Tuning possiblity: we could wait for a
316 static int add_process_element(struct cxl_context
*ctx
)
320 mutex_lock(&ctx
->afu
->spa_mutex
);
321 pr_devel("%s Adding pe: %i started\n", __func__
, ctx
->pe
);
322 if (!(rc
= do_process_element_cmd(ctx
, CXL_SPA_SW_CMD_ADD
, CXL_PE_SOFTWARE_STATE_V
)))
323 ctx
->pe_inserted
= true;
324 pr_devel("%s Adding pe: %i finished\n", __func__
, ctx
->pe
);
325 mutex_unlock(&ctx
->afu
->spa_mutex
);
329 static int terminate_process_element(struct cxl_context
*ctx
)
333 /* fast path terminate if it's already invalid */
334 if (!(ctx
->elem
->software_state
& cpu_to_be32(CXL_PE_SOFTWARE_STATE_V
)))
337 mutex_lock(&ctx
->afu
->spa_mutex
);
338 pr_devel("%s Terminate pe: %i started\n", __func__
, ctx
->pe
);
339 rc
= do_process_element_cmd(ctx
, CXL_SPA_SW_CMD_TERMINATE
,
340 CXL_PE_SOFTWARE_STATE_V
| CXL_PE_SOFTWARE_STATE_T
);
341 ctx
->elem
->software_state
= 0; /* Remove Valid bit */
342 pr_devel("%s Terminate pe: %i finished\n", __func__
, ctx
->pe
);
343 mutex_unlock(&ctx
->afu
->spa_mutex
);
347 static int remove_process_element(struct cxl_context
*ctx
)
351 mutex_lock(&ctx
->afu
->spa_mutex
);
352 pr_devel("%s Remove pe: %i started\n", __func__
, ctx
->pe
);
353 if (!(rc
= do_process_element_cmd(ctx
, CXL_SPA_SW_CMD_REMOVE
, 0)))
354 ctx
->pe_inserted
= false;
356 pr_devel("%s Remove pe: %i finished\n", __func__
, ctx
->pe
);
357 mutex_unlock(&ctx
->afu
->spa_mutex
);
363 static void assign_psn_space(struct cxl_context
*ctx
)
365 if (!ctx
->afu
->pp_size
|| ctx
->master
) {
366 ctx
->psn_phys
= ctx
->afu
->psn_phys
;
367 ctx
->psn_size
= ctx
->afu
->adapter
->ps_size
;
369 ctx
->psn_phys
= ctx
->afu
->psn_phys
+
370 (ctx
->afu
->pp_offset
+ ctx
->afu
->pp_size
* ctx
->pe
);
371 ctx
->psn_size
= ctx
->afu
->pp_size
;
375 static int activate_afu_directed(struct cxl_afu
*afu
)
379 dev_info(&afu
->dev
, "Activating AFU directed mode\n");
384 cxl_p1n_write(afu
, CXL_PSL_SCNTL_An
, CXL_PSL_SCNTL_An_PM_AFU
);
385 cxl_p1n_write(afu
, CXL_PSL_AMOR_An
, 0xFFFFFFFFFFFFFFFFULL
);
386 cxl_p1n_write(afu
, CXL_PSL_ID_An
, CXL_PSL_ID_An_F
| CXL_PSL_ID_An_L
);
388 afu
->current_mode
= CXL_MODE_DIRECTED
;
389 afu
->num_procs
= afu
->max_procs_virtualised
;
391 if ((rc
= cxl_chardev_m_afu_add(afu
)))
394 if ((rc
= cxl_sysfs_afu_m_add(afu
)))
397 if ((rc
= cxl_chardev_s_afu_add(afu
)))
402 cxl_sysfs_afu_m_remove(afu
);
404 cxl_chardev_afu_remove(afu
);
408 #ifdef CONFIG_CPU_LITTLE_ENDIAN
409 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
411 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
414 static int attach_afu_directed(struct cxl_context
*ctx
, u64 wed
, u64 amr
)
419 assign_psn_space(ctx
);
421 ctx
->elem
->ctxtime
= 0; /* disable */
422 ctx
->elem
->lpid
= cpu_to_be32(mfspr(SPRN_LPID
));
423 ctx
->elem
->haurp
= 0; /* disable */
424 ctx
->elem
->sdr
= cpu_to_be64(mfspr(SPRN_SDR1
));
428 sr
|= CXL_PSL_SR_An_MP
;
429 if (mfspr(SPRN_LPCR
) & LPCR_TC
)
430 sr
|= CXL_PSL_SR_An_TC
;
431 /* HV=0, PR=1, R=1 for userspace
432 * For kernel contexts: this would need to change
434 sr
|= CXL_PSL_SR_An_PR
| CXL_PSL_SR_An_R
;
436 sr
&= ~(CXL_PSL_SR_An_HV
);
437 if (!test_tsk_thread_flag(current
, TIF_32BIT
))
438 sr
|= CXL_PSL_SR_An_SF
;
439 ctx
->elem
->common
.pid
= cpu_to_be32(current
->pid
);
440 ctx
->elem
->common
.tid
= 0;
441 ctx
->elem
->sr
= cpu_to_be64(sr
);
443 ctx
->elem
->common
.csrp
= 0; /* disable */
444 ctx
->elem
->common
.aurp0
= 0; /* disable */
445 ctx
->elem
->common
.aurp1
= 0; /* disable */
447 cxl_prefault(ctx
, wed
);
449 ctx
->elem
->common
.sstp0
= cpu_to_be64(ctx
->sstp0
);
450 ctx
->elem
->common
.sstp1
= cpu_to_be64(ctx
->sstp1
);
452 for (r
= 0; r
< CXL_IRQ_RANGES
; r
++) {
453 ctx
->elem
->ivte_offsets
[r
] = cpu_to_be16(ctx
->irqs
.offset
[r
]);
454 ctx
->elem
->ivte_ranges
[r
] = cpu_to_be16(ctx
->irqs
.range
[r
]);
457 ctx
->elem
->common
.amr
= cpu_to_be64(amr
);
458 ctx
->elem
->common
.wed
= cpu_to_be64(wed
);
460 /* first guy needs to enable */
461 if ((result
= afu_check_and_enable(ctx
->afu
)))
464 add_process_element(ctx
);
469 static int deactivate_afu_directed(struct cxl_afu
*afu
)
471 dev_info(&afu
->dev
, "Deactivating AFU directed mode\n");
473 afu
->current_mode
= 0;
476 cxl_sysfs_afu_m_remove(afu
);
477 cxl_chardev_afu_remove(afu
);
480 cxl_afu_disable(afu
);
488 static int activate_dedicated_process(struct cxl_afu
*afu
)
490 dev_info(&afu
->dev
, "Activating dedicated process mode\n");
492 cxl_p1n_write(afu
, CXL_PSL_SCNTL_An
, CXL_PSL_SCNTL_An_PM_Process
);
494 cxl_p1n_write(afu
, CXL_PSL_CtxTime_An
, 0); /* disable */
495 cxl_p1n_write(afu
, CXL_PSL_SPAP_An
, 0); /* disable */
496 cxl_p1n_write(afu
, CXL_PSL_AMOR_An
, 0xFFFFFFFFFFFFFFFFULL
);
497 cxl_p1n_write(afu
, CXL_PSL_LPID_An
, mfspr(SPRN_LPID
));
498 cxl_p1n_write(afu
, CXL_HAURP_An
, 0); /* disable */
499 cxl_p1n_write(afu
, CXL_PSL_SDR_An
, mfspr(SPRN_SDR1
));
501 cxl_p2n_write(afu
, CXL_CSRP_An
, 0); /* disable */
502 cxl_p2n_write(afu
, CXL_AURP0_An
, 0); /* disable */
503 cxl_p2n_write(afu
, CXL_AURP1_An
, 0); /* disable */
505 afu
->current_mode
= CXL_MODE_DEDICATED
;
508 return cxl_chardev_d_afu_add(afu
);
511 static int attach_dedicated(struct cxl_context
*ctx
, u64 wed
, u64 amr
)
513 struct cxl_afu
*afu
= ctx
->afu
;
520 sr
|= CXL_PSL_SR_An_MP
;
521 if (mfspr(SPRN_LPCR
) & LPCR_TC
)
522 sr
|= CXL_PSL_SR_An_TC
;
523 sr
|= CXL_PSL_SR_An_PR
| CXL_PSL_SR_An_R
;
524 if (!test_tsk_thread_flag(current
, TIF_32BIT
))
525 sr
|= CXL_PSL_SR_An_SF
;
526 cxl_p2n_write(afu
, CXL_PSL_PID_TID_An
, (u64
)current
->pid
<< 32);
527 cxl_p1n_write(afu
, CXL_PSL_SR_An
, sr
);
529 if ((rc
= cxl_write_sstp(afu
, ctx
->sstp0
, ctx
->sstp1
)))
532 cxl_prefault(ctx
, wed
);
534 cxl_p1n_write(afu
, CXL_PSL_IVTE_Offset_An
,
535 (((u64
)ctx
->irqs
.offset
[0] & 0xffff) << 48) |
536 (((u64
)ctx
->irqs
.offset
[1] & 0xffff) << 32) |
537 (((u64
)ctx
->irqs
.offset
[2] & 0xffff) << 16) |
538 ((u64
)ctx
->irqs
.offset
[3] & 0xffff));
539 cxl_p1n_write(afu
, CXL_PSL_IVTE_Limit_An
, (u64
)
540 (((u64
)ctx
->irqs
.range
[0] & 0xffff) << 48) |
541 (((u64
)ctx
->irqs
.range
[1] & 0xffff) << 32) |
542 (((u64
)ctx
->irqs
.range
[2] & 0xffff) << 16) |
543 ((u64
)ctx
->irqs
.range
[3] & 0xffff));
545 cxl_p2n_write(afu
, CXL_PSL_AMR_An
, amr
);
547 /* master only context for dedicated */
548 assign_psn_space(ctx
);
550 if ((rc
= cxl_afu_reset(afu
)))
553 cxl_p2n_write(afu
, CXL_PSL_WED_An
, wed
);
555 return afu_enable(afu
);
558 static int deactivate_dedicated_process(struct cxl_afu
*afu
)
560 dev_info(&afu
->dev
, "Deactivating dedicated process mode\n");
562 afu
->current_mode
= 0;
565 cxl_chardev_afu_remove(afu
);
570 int _cxl_afu_deactivate_mode(struct cxl_afu
*afu
, int mode
)
572 if (mode
== CXL_MODE_DIRECTED
)
573 return deactivate_afu_directed(afu
);
574 if (mode
== CXL_MODE_DEDICATED
)
575 return deactivate_dedicated_process(afu
);
579 int cxl_afu_deactivate_mode(struct cxl_afu
*afu
)
581 return _cxl_afu_deactivate_mode(afu
, afu
->current_mode
);
584 int cxl_afu_activate_mode(struct cxl_afu
*afu
, int mode
)
588 if (!(mode
& afu
->modes_supported
))
591 if (mode
== CXL_MODE_DIRECTED
)
592 return activate_afu_directed(afu
);
593 if (mode
== CXL_MODE_DEDICATED
)
594 return activate_dedicated_process(afu
);
599 int cxl_attach_process(struct cxl_context
*ctx
, bool kernel
, u64 wed
, u64 amr
)
601 ctx
->kernel
= kernel
;
602 if (ctx
->afu
->current_mode
== CXL_MODE_DIRECTED
)
603 return attach_afu_directed(ctx
, wed
, amr
);
605 if (ctx
->afu
->current_mode
== CXL_MODE_DEDICATED
)
606 return attach_dedicated(ctx
, wed
, amr
);
611 static inline int detach_process_native_dedicated(struct cxl_context
*ctx
)
613 cxl_afu_reset(ctx
->afu
);
614 cxl_afu_disable(ctx
->afu
);
615 cxl_psl_purge(ctx
->afu
);
619 static inline int detach_process_native_afu_directed(struct cxl_context
*ctx
)
621 if (!ctx
->pe_inserted
)
623 if (terminate_process_element(ctx
))
625 if (remove_process_element(ctx
))
631 int cxl_detach_process(struct cxl_context
*ctx
)
633 if (ctx
->afu
->current_mode
== CXL_MODE_DEDICATED
)
634 return detach_process_native_dedicated(ctx
);
636 return detach_process_native_afu_directed(ctx
);
639 int cxl_get_irq(struct cxl_afu
*afu
, struct cxl_irq_info
*info
)
643 info
->dsisr
= cxl_p2n_read(afu
, CXL_PSL_DSISR_An
);
644 info
->dar
= cxl_p2n_read(afu
, CXL_PSL_DAR_An
);
645 info
->dsr
= cxl_p2n_read(afu
, CXL_PSL_DSR_An
);
646 pidtid
= cxl_p2n_read(afu
, CXL_PSL_PID_TID_An
);
647 info
->pid
= pidtid
>> 32;
648 info
->tid
= pidtid
& 0xffffffff;
649 info
->afu_err
= cxl_p2n_read(afu
, CXL_AFU_ERR_An
);
650 info
->errstat
= cxl_p2n_read(afu
, CXL_PSL_ErrStat_An
);
655 static void recover_psl_err(struct cxl_afu
*afu
, u64 errstat
)
659 pr_devel("RECOVERING FROM PSL ERROR... (0x%.16llx)\n", errstat
);
661 /* Clear PSL_DSISR[PE] */
662 dsisr
= cxl_p2n_read(afu
, CXL_PSL_DSISR_An
);
663 cxl_p2n_write(afu
, CXL_PSL_DSISR_An
, dsisr
& ~CXL_PSL_DSISR_An_PE
);
665 /* Write 1s to clear error status bits */
666 cxl_p2n_write(afu
, CXL_PSL_ErrStat_An
, errstat
);
669 int cxl_ack_irq(struct cxl_context
*ctx
, u64 tfc
, u64 psl_reset_mask
)
672 cxl_p2n_write(ctx
->afu
, CXL_PSL_TFC_An
, tfc
);
674 recover_psl_err(ctx
->afu
, psl_reset_mask
);
679 int cxl_check_error(struct cxl_afu
*afu
)
681 return (cxl_p1n_read(afu
, CXL_PSL_SCNTL_An
) == ~0ULL);