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ath9k: Store the correct max TX power level
[deliverable/linux.git] / drivers / net / bmac.c
1 /*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1998 Randy Gobbel.
6 *
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/proc_fs.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/crc32.h>
21 #include <linux/bitrev.h>
22 #include <linux/ethtool.h>
23 #include <asm/prom.h>
24 #include <asm/dbdma.h>
25 #include <asm/io.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/machdep.h>
29 #include <asm/pmac_feature.h>
30 #include <asm/macio.h>
31 #include <asm/irq.h>
32
33 #include "bmac.h"
34
35 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
36 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
37
38 /*
39 * CRC polynomial - used in working out multicast filter bits.
40 */
41 #define ENET_CRCPOLY 0x04c11db7
42
43 /* switch to use multicast code lifted from sunhme driver */
44 #define SUNHME_MULTICAST
45
46 #define N_RX_RING 64
47 #define N_TX_RING 32
48 #define MAX_TX_ACTIVE 1
49 #define ETHERCRC 4
50 #define ETHERMINPACKET 64
51 #define ETHERMTU 1500
52 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
53 #define TX_TIMEOUT HZ /* 1 second */
54
55 /* Bits in transmit DMA status */
56 #define TX_DMA_ERR 0x80
57
58 #define XXDEBUG(args)
59
60 struct bmac_data {
61 /* volatile struct bmac *bmac; */
62 struct sk_buff_head *queue;
63 volatile struct dbdma_regs __iomem *tx_dma;
64 int tx_dma_intr;
65 volatile struct dbdma_regs __iomem *rx_dma;
66 int rx_dma_intr;
67 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
68 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
69 struct macio_dev *mdev;
70 int is_bmac_plus;
71 struct sk_buff *rx_bufs[N_RX_RING];
72 int rx_fill;
73 int rx_empty;
74 struct sk_buff *tx_bufs[N_TX_RING];
75 int tx_fill;
76 int tx_empty;
77 unsigned char tx_fullup;
78 struct timer_list tx_timeout;
79 int timeout_active;
80 int sleeping;
81 int opened;
82 unsigned short hash_use_count[64];
83 unsigned short hash_table_mask[4];
84 spinlock_t lock;
85 };
86
87 #if 0 /* Move that to ethtool */
88
89 typedef struct bmac_reg_entry {
90 char *name;
91 unsigned short reg_offset;
92 } bmac_reg_entry_t;
93
94 #define N_REG_ENTRIES 31
95
96 static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
97 {"MEMADD", MEMADD},
98 {"MEMDATAHI", MEMDATAHI},
99 {"MEMDATALO", MEMDATALO},
100 {"TXPNTR", TXPNTR},
101 {"RXPNTR", RXPNTR},
102 {"IPG1", IPG1},
103 {"IPG2", IPG2},
104 {"ALIMIT", ALIMIT},
105 {"SLOT", SLOT},
106 {"PALEN", PALEN},
107 {"PAPAT", PAPAT},
108 {"TXSFD", TXSFD},
109 {"JAM", JAM},
110 {"TXCFG", TXCFG},
111 {"TXMAX", TXMAX},
112 {"TXMIN", TXMIN},
113 {"PAREG", PAREG},
114 {"DCNT", DCNT},
115 {"NCCNT", NCCNT},
116 {"NTCNT", NTCNT},
117 {"EXCNT", EXCNT},
118 {"LTCNT", LTCNT},
119 {"TXSM", TXSM},
120 {"RXCFG", RXCFG},
121 {"RXMAX", RXMAX},
122 {"RXMIN", RXMIN},
123 {"FRCNT", FRCNT},
124 {"AECNT", AECNT},
125 {"FECNT", FECNT},
126 {"RXSM", RXSM},
127 {"RXCV", RXCV}
128 };
129
130 #endif
131
132 static unsigned char *bmac_emergency_rxbuf;
133
134 /*
135 * Number of bytes of private data per BMAC: allow enough for
136 * the rx and tx dma commands plus a branch dma command each,
137 * and another 16 bytes to allow us to align the dma command
138 * buffers on a 16 byte boundary.
139 */
140 #define PRIV_BYTES (sizeof(struct bmac_data) \
141 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
142 + sizeof(struct sk_buff_head))
143
144 static int bmac_open(struct net_device *dev);
145 static int bmac_close(struct net_device *dev);
146 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
147 static void bmac_set_multicast(struct net_device *dev);
148 static void bmac_reset_and_enable(struct net_device *dev);
149 static void bmac_start_chip(struct net_device *dev);
150 static void bmac_init_chip(struct net_device *dev);
151 static void bmac_init_registers(struct net_device *dev);
152 static void bmac_enable_and_reset_chip(struct net_device *dev);
153 static int bmac_set_address(struct net_device *dev, void *addr);
154 static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
155 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
156 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
157 static void bmac_set_timeout(struct net_device *dev);
158 static void bmac_tx_timeout(unsigned long data);
159 static int bmac_output(struct sk_buff *skb, struct net_device *dev);
160 static void bmac_start(struct net_device *dev);
161
162 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
163 #define DBDMA_CLEAR(x) ( (x) << 16)
164
165 static inline void
166 dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
167 {
168 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
169 return;
170 }
171
172 static inline unsigned long
173 dbdma_ld32(volatile __u32 __iomem *a)
174 {
175 __u32 swap;
176 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
177 return swap;
178 }
179
180 static void
181 dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
182 {
183 dbdma_st32(&dmap->control,
184 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
185 eieio();
186 }
187
188 static void
189 dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
190 {
191 dbdma_st32(&dmap->control,
192 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
193 eieio();
194 while (dbdma_ld32(&dmap->status) & RUN)
195 eieio();
196 }
197
198 static void
199 dbdma_setcmd(volatile struct dbdma_cmd *cp,
200 unsigned short cmd, unsigned count, unsigned long addr,
201 unsigned long cmd_dep)
202 {
203 out_le16(&cp->command, cmd);
204 out_le16(&cp->req_count, count);
205 out_le32(&cp->phy_addr, addr);
206 out_le32(&cp->cmd_dep, cmd_dep);
207 out_le16(&cp->xfer_status, 0);
208 out_le16(&cp->res_count, 0);
209 }
210
211 static inline
212 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
213 {
214 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
215 }
216
217
218 static inline
219 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
220 {
221 return in_le16((void __iomem *)dev->base_addr + reg_offset);
222 }
223
224 static void
225 bmac_enable_and_reset_chip(struct net_device *dev)
226 {
227 struct bmac_data *bp = netdev_priv(dev);
228 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
229 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
230
231 if (rd)
232 dbdma_reset(rd);
233 if (td)
234 dbdma_reset(td);
235
236 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
237 }
238
239 #define MIFDELAY udelay(10)
240
241 static unsigned int
242 bmac_mif_readbits(struct net_device *dev, int nb)
243 {
244 unsigned int val = 0;
245
246 while (--nb >= 0) {
247 bmwrite(dev, MIFCSR, 0);
248 MIFDELAY;
249 if (bmread(dev, MIFCSR) & 8)
250 val |= 1 << nb;
251 bmwrite(dev, MIFCSR, 1);
252 MIFDELAY;
253 }
254 bmwrite(dev, MIFCSR, 0);
255 MIFDELAY;
256 bmwrite(dev, MIFCSR, 1);
257 MIFDELAY;
258 return val;
259 }
260
261 static void
262 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
263 {
264 int b;
265
266 while (--nb >= 0) {
267 b = (val & (1 << nb))? 6: 4;
268 bmwrite(dev, MIFCSR, b);
269 MIFDELAY;
270 bmwrite(dev, MIFCSR, b|1);
271 MIFDELAY;
272 }
273 }
274
275 static unsigned int
276 bmac_mif_read(struct net_device *dev, unsigned int addr)
277 {
278 unsigned int val;
279
280 bmwrite(dev, MIFCSR, 4);
281 MIFDELAY;
282 bmac_mif_writebits(dev, ~0U, 32);
283 bmac_mif_writebits(dev, 6, 4);
284 bmac_mif_writebits(dev, addr, 10);
285 bmwrite(dev, MIFCSR, 2);
286 MIFDELAY;
287 bmwrite(dev, MIFCSR, 1);
288 MIFDELAY;
289 val = bmac_mif_readbits(dev, 17);
290 bmwrite(dev, MIFCSR, 4);
291 MIFDELAY;
292 return val;
293 }
294
295 static void
296 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
297 {
298 bmwrite(dev, MIFCSR, 4);
299 MIFDELAY;
300 bmac_mif_writebits(dev, ~0U, 32);
301 bmac_mif_writebits(dev, 5, 4);
302 bmac_mif_writebits(dev, addr, 10);
303 bmac_mif_writebits(dev, 2, 2);
304 bmac_mif_writebits(dev, val, 16);
305 bmac_mif_writebits(dev, 3, 2);
306 }
307
308 static void
309 bmac_init_registers(struct net_device *dev)
310 {
311 struct bmac_data *bp = netdev_priv(dev);
312 volatile unsigned short regValue;
313 unsigned short *pWord16;
314 int i;
315
316 /* XXDEBUG(("bmac: enter init_registers\n")); */
317
318 bmwrite(dev, RXRST, RxResetValue);
319 bmwrite(dev, TXRST, TxResetBit);
320
321 i = 100;
322 do {
323 --i;
324 udelay(10000);
325 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
326 } while ((regValue & TxResetBit) && i > 0);
327
328 if (!bp->is_bmac_plus) {
329 regValue = bmread(dev, XCVRIF);
330 regValue |= ClkBit | SerialMode | COLActiveLow;
331 bmwrite(dev, XCVRIF, regValue);
332 udelay(10000);
333 }
334
335 bmwrite(dev, RSEED, (unsigned short)0x1968);
336
337 regValue = bmread(dev, XIFC);
338 regValue |= TxOutputEnable;
339 bmwrite(dev, XIFC, regValue);
340
341 bmread(dev, PAREG);
342
343 /* set collision counters to 0 */
344 bmwrite(dev, NCCNT, 0);
345 bmwrite(dev, NTCNT, 0);
346 bmwrite(dev, EXCNT, 0);
347 bmwrite(dev, LTCNT, 0);
348
349 /* set rx counters to 0 */
350 bmwrite(dev, FRCNT, 0);
351 bmwrite(dev, LECNT, 0);
352 bmwrite(dev, AECNT, 0);
353 bmwrite(dev, FECNT, 0);
354 bmwrite(dev, RXCV, 0);
355
356 /* set tx fifo information */
357 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
358
359 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
360 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
361
362 /* set rx fifo information */
363 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
364 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
365
366 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
367 bmread(dev, STATUS); /* read it just to clear it */
368
369 /* zero out the chip Hash Filter registers */
370 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
371 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
372 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
373 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
374 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
375
376 pWord16 = (unsigned short *)dev->dev_addr;
377 bmwrite(dev, MADD0, *pWord16++);
378 bmwrite(dev, MADD1, *pWord16++);
379 bmwrite(dev, MADD2, *pWord16);
380
381 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
382
383 bmwrite(dev, INTDISABLE, EnableNormal);
384
385 return;
386 }
387
388 #if 0
389 static void
390 bmac_disable_interrupts(struct net_device *dev)
391 {
392 bmwrite(dev, INTDISABLE, DisableAll);
393 }
394
395 static void
396 bmac_enable_interrupts(struct net_device *dev)
397 {
398 bmwrite(dev, INTDISABLE, EnableNormal);
399 }
400 #endif
401
402
403 static void
404 bmac_start_chip(struct net_device *dev)
405 {
406 struct bmac_data *bp = netdev_priv(dev);
407 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
408 unsigned short oldConfig;
409
410 /* enable rx dma channel */
411 dbdma_continue(rd);
412
413 oldConfig = bmread(dev, TXCFG);
414 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
415
416 /* turn on rx plus any other bits already on (promiscuous possibly) */
417 oldConfig = bmread(dev, RXCFG);
418 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
419 udelay(20000);
420 }
421
422 static void
423 bmac_init_phy(struct net_device *dev)
424 {
425 unsigned int addr;
426 struct bmac_data *bp = netdev_priv(dev);
427
428 printk(KERN_DEBUG "phy registers:");
429 for (addr = 0; addr < 32; ++addr) {
430 if ((addr & 7) == 0)
431 printk("\n" KERN_DEBUG);
432 printk(" %.4x", bmac_mif_read(dev, addr));
433 }
434 printk("\n");
435 if (bp->is_bmac_plus) {
436 unsigned int capable, ctrl;
437
438 ctrl = bmac_mif_read(dev, 0);
439 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
440 if (bmac_mif_read(dev, 4) != capable
441 || (ctrl & 0x1000) == 0) {
442 bmac_mif_write(dev, 4, capable);
443 bmac_mif_write(dev, 0, 0x1200);
444 } else
445 bmac_mif_write(dev, 0, 0x1000);
446 }
447 }
448
449 static void bmac_init_chip(struct net_device *dev)
450 {
451 bmac_init_phy(dev);
452 bmac_init_registers(dev);
453 }
454
455 #ifdef CONFIG_PM
456 static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
457 {
458 struct net_device* dev = macio_get_drvdata(mdev);
459 struct bmac_data *bp = netdev_priv(dev);
460 unsigned long flags;
461 unsigned short config;
462 int i;
463
464 netif_device_detach(dev);
465 /* prolly should wait for dma to finish & turn off the chip */
466 spin_lock_irqsave(&bp->lock, flags);
467 if (bp->timeout_active) {
468 del_timer(&bp->tx_timeout);
469 bp->timeout_active = 0;
470 }
471 disable_irq(dev->irq);
472 disable_irq(bp->tx_dma_intr);
473 disable_irq(bp->rx_dma_intr);
474 bp->sleeping = 1;
475 spin_unlock_irqrestore(&bp->lock, flags);
476 if (bp->opened) {
477 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
478 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
479
480 config = bmread(dev, RXCFG);
481 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
482 config = bmread(dev, TXCFG);
483 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
484 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
485 /* disable rx and tx dma */
486 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
487 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
488 /* free some skb's */
489 for (i=0; i<N_RX_RING; i++) {
490 if (bp->rx_bufs[i] != NULL) {
491 dev_kfree_skb(bp->rx_bufs[i]);
492 bp->rx_bufs[i] = NULL;
493 }
494 }
495 for (i = 0; i<N_TX_RING; i++) {
496 if (bp->tx_bufs[i] != NULL) {
497 dev_kfree_skb(bp->tx_bufs[i]);
498 bp->tx_bufs[i] = NULL;
499 }
500 }
501 }
502 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
503 return 0;
504 }
505
506 static int bmac_resume(struct macio_dev *mdev)
507 {
508 struct net_device* dev = macio_get_drvdata(mdev);
509 struct bmac_data *bp = netdev_priv(dev);
510
511 /* see if this is enough */
512 if (bp->opened)
513 bmac_reset_and_enable(dev);
514
515 enable_irq(dev->irq);
516 enable_irq(bp->tx_dma_intr);
517 enable_irq(bp->rx_dma_intr);
518 netif_device_attach(dev);
519
520 return 0;
521 }
522 #endif /* CONFIG_PM */
523
524 static int bmac_set_address(struct net_device *dev, void *addr)
525 {
526 struct bmac_data *bp = netdev_priv(dev);
527 unsigned char *p = addr;
528 unsigned short *pWord16;
529 unsigned long flags;
530 int i;
531
532 XXDEBUG(("bmac: enter set_address\n"));
533 spin_lock_irqsave(&bp->lock, flags);
534
535 for (i = 0; i < 6; ++i) {
536 dev->dev_addr[i] = p[i];
537 }
538 /* load up the hardware address */
539 pWord16 = (unsigned short *)dev->dev_addr;
540 bmwrite(dev, MADD0, *pWord16++);
541 bmwrite(dev, MADD1, *pWord16++);
542 bmwrite(dev, MADD2, *pWord16);
543
544 spin_unlock_irqrestore(&bp->lock, flags);
545 XXDEBUG(("bmac: exit set_address\n"));
546 return 0;
547 }
548
549 static inline void bmac_set_timeout(struct net_device *dev)
550 {
551 struct bmac_data *bp = netdev_priv(dev);
552 unsigned long flags;
553
554 spin_lock_irqsave(&bp->lock, flags);
555 if (bp->timeout_active)
556 del_timer(&bp->tx_timeout);
557 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
558 bp->tx_timeout.function = bmac_tx_timeout;
559 bp->tx_timeout.data = (unsigned long) dev;
560 add_timer(&bp->tx_timeout);
561 bp->timeout_active = 1;
562 spin_unlock_irqrestore(&bp->lock, flags);
563 }
564
565 static void
566 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
567 {
568 void *vaddr;
569 unsigned long baddr;
570 unsigned long len;
571
572 len = skb->len;
573 vaddr = skb->data;
574 baddr = virt_to_bus(vaddr);
575
576 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
577 }
578
579 static void
580 bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
581 {
582 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
583
584 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
585 virt_to_bus(addr), 0);
586 }
587
588 static void
589 bmac_init_tx_ring(struct bmac_data *bp)
590 {
591 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
592
593 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
594
595 bp->tx_empty = 0;
596 bp->tx_fill = 0;
597 bp->tx_fullup = 0;
598
599 /* put a branch at the end of the tx command list */
600 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
601 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
602
603 /* reset tx dma */
604 dbdma_reset(td);
605 out_le32(&td->wait_sel, 0x00200020);
606 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
607 }
608
609 static int
610 bmac_init_rx_ring(struct bmac_data *bp)
611 {
612 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
613 int i;
614 struct sk_buff *skb;
615
616 /* initialize list of sk_buffs for receiving and set up recv dma */
617 memset((char *)bp->rx_cmds, 0,
618 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
619 for (i = 0; i < N_RX_RING; i++) {
620 if ((skb = bp->rx_bufs[i]) == NULL) {
621 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
622 if (skb != NULL)
623 skb_reserve(skb, 2);
624 }
625 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
626 }
627
628 bp->rx_empty = 0;
629 bp->rx_fill = i;
630
631 /* Put a branch back to the beginning of the receive command list */
632 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
633 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
634
635 /* start rx dma */
636 dbdma_reset(rd);
637 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
638
639 return 1;
640 }
641
642
643 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
644 {
645 struct bmac_data *bp = netdev_priv(dev);
646 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
647 int i;
648
649 /* see if there's a free slot in the tx ring */
650 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
651 /* bp->tx_empty, bp->tx_fill)); */
652 i = bp->tx_fill + 1;
653 if (i >= N_TX_RING)
654 i = 0;
655 if (i == bp->tx_empty) {
656 netif_stop_queue(dev);
657 bp->tx_fullup = 1;
658 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
659 return -1; /* can't take it at the moment */
660 }
661
662 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
663
664 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
665
666 bp->tx_bufs[bp->tx_fill] = skb;
667 bp->tx_fill = i;
668
669 dev->stats.tx_bytes += skb->len;
670
671 dbdma_continue(td);
672
673 return 0;
674 }
675
676 static int rxintcount;
677
678 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
679 {
680 struct net_device *dev = (struct net_device *) dev_id;
681 struct bmac_data *bp = netdev_priv(dev);
682 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
683 volatile struct dbdma_cmd *cp;
684 int i, nb, stat;
685 struct sk_buff *skb;
686 unsigned int residual;
687 int last;
688 unsigned long flags;
689
690 spin_lock_irqsave(&bp->lock, flags);
691
692 if (++rxintcount < 10) {
693 XXDEBUG(("bmac_rxdma_intr\n"));
694 }
695
696 last = -1;
697 i = bp->rx_empty;
698
699 while (1) {
700 cp = &bp->rx_cmds[i];
701 stat = ld_le16(&cp->xfer_status);
702 residual = ld_le16(&cp->res_count);
703 if ((stat & ACTIVE) == 0)
704 break;
705 nb = RX_BUFLEN - residual - 2;
706 if (nb < (ETHERMINPACKET - ETHERCRC)) {
707 skb = NULL;
708 dev->stats.rx_length_errors++;
709 dev->stats.rx_errors++;
710 } else {
711 skb = bp->rx_bufs[i];
712 bp->rx_bufs[i] = NULL;
713 }
714 if (skb != NULL) {
715 nb -= ETHERCRC;
716 skb_put(skb, nb);
717 skb->protocol = eth_type_trans(skb, dev);
718 netif_rx(skb);
719 ++dev->stats.rx_packets;
720 dev->stats.rx_bytes += nb;
721 } else {
722 ++dev->stats.rx_dropped;
723 }
724 if ((skb = bp->rx_bufs[i]) == NULL) {
725 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
726 if (skb != NULL)
727 skb_reserve(bp->rx_bufs[i], 2);
728 }
729 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
730 st_le16(&cp->res_count, 0);
731 st_le16(&cp->xfer_status, 0);
732 last = i;
733 if (++i >= N_RX_RING) i = 0;
734 }
735
736 if (last != -1) {
737 bp->rx_fill = last;
738 bp->rx_empty = i;
739 }
740
741 dbdma_continue(rd);
742 spin_unlock_irqrestore(&bp->lock, flags);
743
744 if (rxintcount < 10) {
745 XXDEBUG(("bmac_rxdma_intr done\n"));
746 }
747 return IRQ_HANDLED;
748 }
749
750 static int txintcount;
751
752 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
753 {
754 struct net_device *dev = (struct net_device *) dev_id;
755 struct bmac_data *bp = netdev_priv(dev);
756 volatile struct dbdma_cmd *cp;
757 int stat;
758 unsigned long flags;
759
760 spin_lock_irqsave(&bp->lock, flags);
761
762 if (txintcount++ < 10) {
763 XXDEBUG(("bmac_txdma_intr\n"));
764 }
765
766 /* del_timer(&bp->tx_timeout); */
767 /* bp->timeout_active = 0; */
768
769 while (1) {
770 cp = &bp->tx_cmds[bp->tx_empty];
771 stat = ld_le16(&cp->xfer_status);
772 if (txintcount < 10) {
773 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
774 }
775 if (!(stat & ACTIVE)) {
776 /*
777 * status field might not have been filled by DBDMA
778 */
779 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
780 break;
781 }
782
783 if (bp->tx_bufs[bp->tx_empty]) {
784 ++dev->stats.tx_packets;
785 dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
786 }
787 bp->tx_bufs[bp->tx_empty] = NULL;
788 bp->tx_fullup = 0;
789 netif_wake_queue(dev);
790 if (++bp->tx_empty >= N_TX_RING)
791 bp->tx_empty = 0;
792 if (bp->tx_empty == bp->tx_fill)
793 break;
794 }
795
796 spin_unlock_irqrestore(&bp->lock, flags);
797
798 if (txintcount < 10) {
799 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
800 }
801
802 bmac_start(dev);
803 return IRQ_HANDLED;
804 }
805
806 #ifndef SUNHME_MULTICAST
807 /* Real fast bit-reversal algorithm, 6-bit values */
808 static int reverse6[64] = {
809 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
810 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
811 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
812 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
813 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
814 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
815 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
816 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
817 };
818
819 static unsigned int
820 crc416(unsigned int curval, unsigned short nxtval)
821 {
822 register unsigned int counter, cur = curval, next = nxtval;
823 register int high_crc_set, low_data_set;
824
825 /* Swap bytes */
826 next = ((next & 0x00FF) << 8) | (next >> 8);
827
828 /* Compute bit-by-bit */
829 for (counter = 0; counter < 16; ++counter) {
830 /* is high CRC bit set? */
831 if ((cur & 0x80000000) == 0) high_crc_set = 0;
832 else high_crc_set = 1;
833
834 cur = cur << 1;
835
836 if ((next & 0x0001) == 0) low_data_set = 0;
837 else low_data_set = 1;
838
839 next = next >> 1;
840
841 /* do the XOR */
842 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
843 }
844 return cur;
845 }
846
847 static unsigned int
848 bmac_crc(unsigned short *address)
849 {
850 unsigned int newcrc;
851
852 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
853 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
854 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
855 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
856
857 return(newcrc);
858 }
859
860 /*
861 * Add requested mcast addr to BMac's hash table filter.
862 *
863 */
864
865 static void
866 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
867 {
868 unsigned int crc;
869 unsigned short mask;
870
871 if (!(*addr)) return;
872 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
873 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
874 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
875 mask = crc % 16;
876 mask = (unsigned char)1 << mask;
877 bp->hash_use_count[crc/16] |= mask;
878 }
879
880 static void
881 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
882 {
883 unsigned int crc;
884 unsigned char mask;
885
886 /* Now, delete the address from the filter copy, as indicated */
887 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
888 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
889 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
890 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
891 mask = crc % 16;
892 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
893 bp->hash_table_mask[crc/16] &= mask;
894 }
895
896 /*
897 * Sync the adapter with the software copy of the multicast mask
898 * (logical address filter).
899 */
900
901 static void
902 bmac_rx_off(struct net_device *dev)
903 {
904 unsigned short rx_cfg;
905
906 rx_cfg = bmread(dev, RXCFG);
907 rx_cfg &= ~RxMACEnable;
908 bmwrite(dev, RXCFG, rx_cfg);
909 do {
910 rx_cfg = bmread(dev, RXCFG);
911 } while (rx_cfg & RxMACEnable);
912 }
913
914 unsigned short
915 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
916 {
917 unsigned short rx_cfg;
918
919 rx_cfg = bmread(dev, RXCFG);
920 rx_cfg |= RxMACEnable;
921 if (hash_enable) rx_cfg |= RxHashFilterEnable;
922 else rx_cfg &= ~RxHashFilterEnable;
923 if (promisc_enable) rx_cfg |= RxPromiscEnable;
924 else rx_cfg &= ~RxPromiscEnable;
925 bmwrite(dev, RXRST, RxResetValue);
926 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
927 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
928 bmwrite(dev, RXCFG, rx_cfg );
929 return rx_cfg;
930 }
931
932 static void
933 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
934 {
935 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
936 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
937 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
938 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
939 }
940
941 #if 0
942 static void
943 bmac_add_multi(struct net_device *dev,
944 struct bmac_data *bp, unsigned char *addr)
945 {
946 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
947 bmac_addhash(bp, addr);
948 bmac_rx_off(dev);
949 bmac_update_hash_table_mask(dev, bp);
950 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
951 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
952 }
953
954 static void
955 bmac_remove_multi(struct net_device *dev,
956 struct bmac_data *bp, unsigned char *addr)
957 {
958 bmac_removehash(bp, addr);
959 bmac_rx_off(dev);
960 bmac_update_hash_table_mask(dev, bp);
961 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
962 }
963 #endif
964
965 /* Set or clear the multicast filter for this adaptor.
966 num_addrs == -1 Promiscuous mode, receive all packets
967 num_addrs == 0 Normal mode, clear multicast list
968 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
969 best-effort filtering.
970 */
971 static void bmac_set_multicast(struct net_device *dev)
972 {
973 struct dev_mc_list *dmi;
974 struct bmac_data *bp = netdev_priv(dev);
975 int num_addrs = dev->mc_count;
976 unsigned short rx_cfg;
977 int i;
978
979 if (bp->sleeping)
980 return;
981
982 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
983
984 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
985 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
986 bmac_update_hash_table_mask(dev, bp);
987 rx_cfg = bmac_rx_on(dev, 1, 0);
988 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
989 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
990 rx_cfg = bmread(dev, RXCFG);
991 rx_cfg |= RxPromiscEnable;
992 bmwrite(dev, RXCFG, rx_cfg);
993 rx_cfg = bmac_rx_on(dev, 0, 1);
994 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
995 } else {
996 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
997 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
998 if (num_addrs == 0) {
999 rx_cfg = bmac_rx_on(dev, 0, 0);
1000 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
1001 } else {
1002 for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
1003 bmac_addhash(bp, dmi->dmi_addr);
1004 bmac_update_hash_table_mask(dev, bp);
1005 rx_cfg = bmac_rx_on(dev, 1, 0);
1006 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
1007 }
1008 }
1009 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1010 }
1011 #else /* ifdef SUNHME_MULTICAST */
1012
1013 /* The version of set_multicast below was lifted from sunhme.c */
1014
1015 static void bmac_set_multicast(struct net_device *dev)
1016 {
1017 struct dev_mc_list *dmi = dev->mc_list;
1018 char *addrs;
1019 int i;
1020 unsigned short rx_cfg;
1021 u32 crc;
1022
1023 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1024 bmwrite(dev, BHASH0, 0xffff);
1025 bmwrite(dev, BHASH1, 0xffff);
1026 bmwrite(dev, BHASH2, 0xffff);
1027 bmwrite(dev, BHASH3, 0xffff);
1028 } else if(dev->flags & IFF_PROMISC) {
1029 rx_cfg = bmread(dev, RXCFG);
1030 rx_cfg |= RxPromiscEnable;
1031 bmwrite(dev, RXCFG, rx_cfg);
1032 } else {
1033 u16 hash_table[4];
1034
1035 rx_cfg = bmread(dev, RXCFG);
1036 rx_cfg &= ~RxPromiscEnable;
1037 bmwrite(dev, RXCFG, rx_cfg);
1038
1039 for(i = 0; i < 4; i++) hash_table[i] = 0;
1040
1041 for(i = 0; i < dev->mc_count; i++) {
1042 addrs = dmi->dmi_addr;
1043 dmi = dmi->next;
1044
1045 if(!(*addrs & 1))
1046 continue;
1047
1048 crc = ether_crc_le(6, addrs);
1049 crc >>= 26;
1050 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1051 }
1052 bmwrite(dev, BHASH0, hash_table[0]);
1053 bmwrite(dev, BHASH1, hash_table[1]);
1054 bmwrite(dev, BHASH2, hash_table[2]);
1055 bmwrite(dev, BHASH3, hash_table[3]);
1056 }
1057 }
1058 #endif /* SUNHME_MULTICAST */
1059
1060 static int miscintcount;
1061
1062 static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
1063 {
1064 struct net_device *dev = (struct net_device *) dev_id;
1065 struct bmac_data *bp = netdev_priv(dev);
1066 unsigned int status = bmread(dev, STATUS);
1067 if (miscintcount++ < 10) {
1068 XXDEBUG(("bmac_misc_intr\n"));
1069 }
1070 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1071 /* bmac_txdma_intr_inner(irq, dev_id); */
1072 /* if (status & FrameReceived) dev->stats.rx_dropped++; */
1073 if (status & RxErrorMask) dev->stats.rx_errors++;
1074 if (status & RxCRCCntExp) dev->stats.rx_crc_errors++;
1075 if (status & RxLenCntExp) dev->stats.rx_length_errors++;
1076 if (status & RxOverFlow) dev->stats.rx_over_errors++;
1077 if (status & RxAlignCntExp) dev->stats.rx_frame_errors++;
1078
1079 /* if (status & FrameSent) dev->stats.tx_dropped++; */
1080 if (status & TxErrorMask) dev->stats.tx_errors++;
1081 if (status & TxUnderrun) dev->stats.tx_fifo_errors++;
1082 if (status & TxNormalCollExp) dev->stats.collisions++;
1083 return IRQ_HANDLED;
1084 }
1085
1086 /*
1087 * Procedure for reading EEPROM
1088 */
1089 #define SROMAddressLength 5
1090 #define DataInOn 0x0008
1091 #define DataInOff 0x0000
1092 #define Clk 0x0002
1093 #define ChipSelect 0x0001
1094 #define SDIShiftCount 3
1095 #define SD0ShiftCount 2
1096 #define DelayValue 1000 /* number of microseconds */
1097 #define SROMStartOffset 10 /* this is in words */
1098 #define SROMReadCount 3 /* number of words to read from SROM */
1099 #define SROMAddressBits 6
1100 #define EnetAddressOffset 20
1101
1102 static unsigned char
1103 bmac_clock_out_bit(struct net_device *dev)
1104 {
1105 unsigned short data;
1106 unsigned short val;
1107
1108 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1109 udelay(DelayValue);
1110
1111 data = bmread(dev, SROMCSR);
1112 udelay(DelayValue);
1113 val = (data >> SD0ShiftCount) & 1;
1114
1115 bmwrite(dev, SROMCSR, ChipSelect);
1116 udelay(DelayValue);
1117
1118 return val;
1119 }
1120
1121 static void
1122 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1123 {
1124 unsigned short data;
1125
1126 if (val != 0 && val != 1) return;
1127
1128 data = (val << SDIShiftCount);
1129 bmwrite(dev, SROMCSR, data | ChipSelect );
1130 udelay(DelayValue);
1131
1132 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1133 udelay(DelayValue);
1134
1135 bmwrite(dev, SROMCSR, data | ChipSelect);
1136 udelay(DelayValue);
1137 }
1138
1139 static void
1140 reset_and_select_srom(struct net_device *dev)
1141 {
1142 /* first reset */
1143 bmwrite(dev, SROMCSR, 0);
1144 udelay(DelayValue);
1145
1146 /* send it the read command (110) */
1147 bmac_clock_in_bit(dev, 1);
1148 bmac_clock_in_bit(dev, 1);
1149 bmac_clock_in_bit(dev, 0);
1150 }
1151
1152 static unsigned short
1153 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1154 {
1155 unsigned short data, val;
1156 int i;
1157
1158 /* send out the address we want to read from */
1159 for (i = 0; i < addr_len; i++) {
1160 val = addr >> (addr_len-i-1);
1161 bmac_clock_in_bit(dev, val & 1);
1162 }
1163
1164 /* Now read in the 16-bit data */
1165 data = 0;
1166 for (i = 0; i < 16; i++) {
1167 val = bmac_clock_out_bit(dev);
1168 data <<= 1;
1169 data |= val;
1170 }
1171 bmwrite(dev, SROMCSR, 0);
1172
1173 return data;
1174 }
1175
1176 /*
1177 * It looks like Cogent and SMC use different methods for calculating
1178 * checksums. What a pain..
1179 */
1180
1181 static int
1182 bmac_verify_checksum(struct net_device *dev)
1183 {
1184 unsigned short data, storedCS;
1185
1186 reset_and_select_srom(dev);
1187 data = read_srom(dev, 3, SROMAddressBits);
1188 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1189
1190 return 0;
1191 }
1192
1193
1194 static void
1195 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1196 {
1197 int i;
1198 unsigned short data;
1199
1200 for (i = 0; i < 6; i++)
1201 {
1202 reset_and_select_srom(dev);
1203 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1204 ea[2*i] = bitrev8(data & 0x0ff);
1205 ea[2*i+1] = bitrev8((data >> 8) & 0x0ff);
1206 }
1207 }
1208
1209 static void bmac_reset_and_enable(struct net_device *dev)
1210 {
1211 struct bmac_data *bp = netdev_priv(dev);
1212 unsigned long flags;
1213 struct sk_buff *skb;
1214 unsigned char *data;
1215
1216 spin_lock_irqsave(&bp->lock, flags);
1217 bmac_enable_and_reset_chip(dev);
1218 bmac_init_tx_ring(bp);
1219 bmac_init_rx_ring(bp);
1220 bmac_init_chip(dev);
1221 bmac_start_chip(dev);
1222 bmwrite(dev, INTDISABLE, EnableNormal);
1223 bp->sleeping = 0;
1224
1225 /*
1226 * It seems that the bmac can't receive until it's transmitted
1227 * a packet. So we give it a dummy packet to transmit.
1228 */
1229 skb = dev_alloc_skb(ETHERMINPACKET);
1230 if (skb != NULL) {
1231 data = skb_put(skb, ETHERMINPACKET);
1232 memset(data, 0, ETHERMINPACKET);
1233 memcpy(data, dev->dev_addr, 6);
1234 memcpy(data+6, dev->dev_addr, 6);
1235 bmac_transmit_packet(skb, dev);
1236 }
1237 spin_unlock_irqrestore(&bp->lock, flags);
1238 }
1239 static void bmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1240 {
1241 struct bmac_data *bp = netdev_priv(dev);
1242 strcpy(info->driver, "bmac");
1243 strcpy(info->bus_info, dev_name(&bp->mdev->ofdev.dev));
1244 }
1245
1246 static const struct ethtool_ops bmac_ethtool_ops = {
1247 .get_drvinfo = bmac_get_drvinfo,
1248 .get_link = ethtool_op_get_link,
1249 };
1250
1251 static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1252 {
1253 int j, rev, ret;
1254 struct bmac_data *bp;
1255 const unsigned char *prop_addr;
1256 unsigned char addr[6];
1257 struct net_device *dev;
1258 int is_bmac_plus = ((int)match->data) != 0;
1259
1260 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1261 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1262 return -ENODEV;
1263 }
1264 prop_addr = of_get_property(macio_get_of_node(mdev),
1265 "mac-address", NULL);
1266 if (prop_addr == NULL) {
1267 prop_addr = of_get_property(macio_get_of_node(mdev),
1268 "local-mac-address", NULL);
1269 if (prop_addr == NULL) {
1270 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1271 return -ENODEV;
1272 }
1273 }
1274 memcpy(addr, prop_addr, sizeof(addr));
1275
1276 dev = alloc_etherdev(PRIV_BYTES);
1277 if (!dev) {
1278 printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
1279 return -ENOMEM;
1280 }
1281
1282 bp = netdev_priv(dev);
1283 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1284 macio_set_drvdata(mdev, dev);
1285
1286 bp->mdev = mdev;
1287 spin_lock_init(&bp->lock);
1288
1289 if (macio_request_resources(mdev, "bmac")) {
1290 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1291 goto out_free;
1292 }
1293
1294 dev->base_addr = (unsigned long)
1295 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1296 if (dev->base_addr == 0)
1297 goto out_release;
1298
1299 dev->irq = macio_irq(mdev, 0);
1300
1301 bmac_enable_and_reset_chip(dev);
1302 bmwrite(dev, INTDISABLE, DisableAll);
1303
1304 rev = addr[0] == 0 && addr[1] == 0xA0;
1305 for (j = 0; j < 6; ++j)
1306 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
1307
1308 /* Enable chip without interrupts for now */
1309 bmac_enable_and_reset_chip(dev);
1310 bmwrite(dev, INTDISABLE, DisableAll);
1311
1312 dev->open = bmac_open;
1313 dev->stop = bmac_close;
1314 dev->ethtool_ops = &bmac_ethtool_ops;
1315 dev->hard_start_xmit = bmac_output;
1316 dev->set_multicast_list = bmac_set_multicast;
1317 dev->set_mac_address = bmac_set_address;
1318
1319 bmac_get_station_address(dev, addr);
1320 if (bmac_verify_checksum(dev) != 0)
1321 goto err_out_iounmap;
1322
1323 bp->is_bmac_plus = is_bmac_plus;
1324 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1325 if (!bp->tx_dma)
1326 goto err_out_iounmap;
1327 bp->tx_dma_intr = macio_irq(mdev, 1);
1328 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1329 if (!bp->rx_dma)
1330 goto err_out_iounmap_tx;
1331 bp->rx_dma_intr = macio_irq(mdev, 2);
1332
1333 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1334 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1335
1336 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1337 skb_queue_head_init(bp->queue);
1338
1339 init_timer(&bp->tx_timeout);
1340
1341 ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
1342 if (ret) {
1343 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1344 goto err_out_iounmap_rx;
1345 }
1346 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1347 if (ret) {
1348 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1349 goto err_out_irq0;
1350 }
1351 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1352 if (ret) {
1353 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1354 goto err_out_irq1;
1355 }
1356
1357 /* Mask chip interrupts and disable chip, will be
1358 * re-enabled on open()
1359 */
1360 disable_irq(dev->irq);
1361 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1362
1363 if (register_netdev(dev) != 0) {
1364 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1365 goto err_out_irq2;
1366 }
1367
1368 printk(KERN_INFO "%s: BMAC%s at %pM",
1369 dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr);
1370 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1371 printk("\n");
1372
1373 return 0;
1374
1375 err_out_irq2:
1376 free_irq(bp->rx_dma_intr, dev);
1377 err_out_irq1:
1378 free_irq(bp->tx_dma_intr, dev);
1379 err_out_irq0:
1380 free_irq(dev->irq, dev);
1381 err_out_iounmap_rx:
1382 iounmap(bp->rx_dma);
1383 err_out_iounmap_tx:
1384 iounmap(bp->tx_dma);
1385 err_out_iounmap:
1386 iounmap((void __iomem *)dev->base_addr);
1387 out_release:
1388 macio_release_resources(mdev);
1389 out_free:
1390 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1391 free_netdev(dev);
1392
1393 return -ENODEV;
1394 }
1395
1396 static int bmac_open(struct net_device *dev)
1397 {
1398 struct bmac_data *bp = netdev_priv(dev);
1399 /* XXDEBUG(("bmac: enter open\n")); */
1400 /* reset the chip */
1401 bp->opened = 1;
1402 bmac_reset_and_enable(dev);
1403 enable_irq(dev->irq);
1404 return 0;
1405 }
1406
1407 static int bmac_close(struct net_device *dev)
1408 {
1409 struct bmac_data *bp = netdev_priv(dev);
1410 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1411 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1412 unsigned short config;
1413 int i;
1414
1415 bp->sleeping = 1;
1416
1417 /* disable rx and tx */
1418 config = bmread(dev, RXCFG);
1419 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1420
1421 config = bmread(dev, TXCFG);
1422 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1423
1424 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1425
1426 /* disable rx and tx dma */
1427 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1428 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1429
1430 /* free some skb's */
1431 XXDEBUG(("bmac: free rx bufs\n"));
1432 for (i=0; i<N_RX_RING; i++) {
1433 if (bp->rx_bufs[i] != NULL) {
1434 dev_kfree_skb(bp->rx_bufs[i]);
1435 bp->rx_bufs[i] = NULL;
1436 }
1437 }
1438 XXDEBUG(("bmac: free tx bufs\n"));
1439 for (i = 0; i<N_TX_RING; i++) {
1440 if (bp->tx_bufs[i] != NULL) {
1441 dev_kfree_skb(bp->tx_bufs[i]);
1442 bp->tx_bufs[i] = NULL;
1443 }
1444 }
1445 XXDEBUG(("bmac: all bufs freed\n"));
1446
1447 bp->opened = 0;
1448 disable_irq(dev->irq);
1449 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1450
1451 return 0;
1452 }
1453
1454 static void
1455 bmac_start(struct net_device *dev)
1456 {
1457 struct bmac_data *bp = netdev_priv(dev);
1458 int i;
1459 struct sk_buff *skb;
1460 unsigned long flags;
1461
1462 if (bp->sleeping)
1463 return;
1464
1465 spin_lock_irqsave(&bp->lock, flags);
1466 while (1) {
1467 i = bp->tx_fill + 1;
1468 if (i >= N_TX_RING)
1469 i = 0;
1470 if (i == bp->tx_empty)
1471 break;
1472 skb = skb_dequeue(bp->queue);
1473 if (skb == NULL)
1474 break;
1475 bmac_transmit_packet(skb, dev);
1476 }
1477 spin_unlock_irqrestore(&bp->lock, flags);
1478 }
1479
1480 static int
1481 bmac_output(struct sk_buff *skb, struct net_device *dev)
1482 {
1483 struct bmac_data *bp = netdev_priv(dev);
1484 skb_queue_tail(bp->queue, skb);
1485 bmac_start(dev);
1486 return 0;
1487 }
1488
1489 static void bmac_tx_timeout(unsigned long data)
1490 {
1491 struct net_device *dev = (struct net_device *) data;
1492 struct bmac_data *bp = netdev_priv(dev);
1493 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1494 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1495 volatile struct dbdma_cmd *cp;
1496 unsigned long flags;
1497 unsigned short config, oldConfig;
1498 int i;
1499
1500 XXDEBUG(("bmac: tx_timeout called\n"));
1501 spin_lock_irqsave(&bp->lock, flags);
1502 bp->timeout_active = 0;
1503
1504 /* update various counters */
1505 /* bmac_handle_misc_intrs(bp, 0); */
1506
1507 cp = &bp->tx_cmds[bp->tx_empty];
1508 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1509 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1510 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1511
1512 /* turn off both tx and rx and reset the chip */
1513 config = bmread(dev, RXCFG);
1514 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1515 config = bmread(dev, TXCFG);
1516 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1517 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1518 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1519 bmac_enable_and_reset_chip(dev);
1520
1521 /* restart rx dma */
1522 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1523 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1524 out_le16(&cp->xfer_status, 0);
1525 out_le32(&rd->cmdptr, virt_to_bus(cp));
1526 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1527
1528 /* fix up the transmit side */
1529 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1530 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1531 i = bp->tx_empty;
1532 ++dev->stats.tx_errors;
1533 if (i != bp->tx_fill) {
1534 dev_kfree_skb(bp->tx_bufs[i]);
1535 bp->tx_bufs[i] = NULL;
1536 if (++i >= N_TX_RING) i = 0;
1537 bp->tx_empty = i;
1538 }
1539 bp->tx_fullup = 0;
1540 netif_wake_queue(dev);
1541 if (i != bp->tx_fill) {
1542 cp = &bp->tx_cmds[i];
1543 out_le16(&cp->xfer_status, 0);
1544 out_le16(&cp->command, OUTPUT_LAST);
1545 out_le32(&td->cmdptr, virt_to_bus(cp));
1546 out_le32(&td->control, DBDMA_SET(RUN));
1547 /* bmac_set_timeout(dev); */
1548 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1549 }
1550
1551 /* turn it back on */
1552 oldConfig = bmread(dev, RXCFG);
1553 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1554 oldConfig = bmread(dev, TXCFG);
1555 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1556
1557 spin_unlock_irqrestore(&bp->lock, flags);
1558 }
1559
1560 #if 0
1561 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1562 {
1563 int i,*ip;
1564
1565 for (i=0;i< count;i++) {
1566 ip = (int*)(cp+i);
1567
1568 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1569 ld_le32(ip+0),
1570 ld_le32(ip+1),
1571 ld_le32(ip+2),
1572 ld_le32(ip+3));
1573 }
1574
1575 }
1576 #endif
1577
1578 #if 0
1579 static int
1580 bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1581 {
1582 int len = 0;
1583 off_t pos = 0;
1584 off_t begin = 0;
1585 int i;
1586
1587 if (bmac_devs == NULL)
1588 return (-ENOSYS);
1589
1590 len += sprintf(buffer, "BMAC counters & registers\n");
1591
1592 for (i = 0; i<N_REG_ENTRIES; i++) {
1593 len += sprintf(buffer + len, "%s: %#08x\n",
1594 reg_entries[i].name,
1595 bmread(bmac_devs, reg_entries[i].reg_offset));
1596 pos = begin + len;
1597
1598 if (pos < offset) {
1599 len = 0;
1600 begin = pos;
1601 }
1602
1603 if (pos > offset+length) break;
1604 }
1605
1606 *start = buffer + (offset - begin);
1607 len -= (offset - begin);
1608
1609 if (len > length) len = length;
1610
1611 return len;
1612 }
1613 #endif
1614
1615 static int __devexit bmac_remove(struct macio_dev *mdev)
1616 {
1617 struct net_device *dev = macio_get_drvdata(mdev);
1618 struct bmac_data *bp = netdev_priv(dev);
1619
1620 unregister_netdev(dev);
1621
1622 free_irq(dev->irq, dev);
1623 free_irq(bp->tx_dma_intr, dev);
1624 free_irq(bp->rx_dma_intr, dev);
1625
1626 iounmap((void __iomem *)dev->base_addr);
1627 iounmap(bp->tx_dma);
1628 iounmap(bp->rx_dma);
1629
1630 macio_release_resources(mdev);
1631
1632 free_netdev(dev);
1633
1634 return 0;
1635 }
1636
1637 static struct of_device_id bmac_match[] =
1638 {
1639 {
1640 .name = "bmac",
1641 .data = (void *)0,
1642 },
1643 {
1644 .type = "network",
1645 .compatible = "bmac+",
1646 .data = (void *)1,
1647 },
1648 {},
1649 };
1650 MODULE_DEVICE_TABLE (of, bmac_match);
1651
1652 static struct macio_driver bmac_driver =
1653 {
1654 .name = "bmac",
1655 .match_table = bmac_match,
1656 .probe = bmac_probe,
1657 .remove = bmac_remove,
1658 #ifdef CONFIG_PM
1659 .suspend = bmac_suspend,
1660 .resume = bmac_resume,
1661 #endif
1662 };
1663
1664
1665 static int __init bmac_init(void)
1666 {
1667 if (bmac_emergency_rxbuf == NULL) {
1668 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1669 if (bmac_emergency_rxbuf == NULL) {
1670 printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
1671 return -ENOMEM;
1672 }
1673 }
1674
1675 return macio_register_driver(&bmac_driver);
1676 }
1677
1678 static void __exit bmac_exit(void)
1679 {
1680 macio_unregister_driver(&bmac_driver);
1681
1682 kfree(bmac_emergency_rxbuf);
1683 bmac_emergency_rxbuf = NULL;
1684 }
1685
1686 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1687 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1688 MODULE_LICENSE("GPL");
1689
1690 module_init(bmac_init);
1691 module_exit(bmac_exit);
Linux kernel - Deliverables
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