2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
22 static const struct bcma_device_id bgmac_bcma_tbl
[] = {
23 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_4706_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
24 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
27 MODULE_DEVICE_TABLE(bcma
, bgmac_bcma_tbl
);
29 static inline bool bgmac_is_bcm4707_family(struct bgmac
*bgmac
)
31 switch (bgmac
->core
->bus
->chipinfo
.id
) {
32 case BCMA_CHIP_ID_BCM4707
:
33 case BCMA_CHIP_ID_BCM47094
:
34 case BCMA_CHIP_ID_BCM53018
:
41 static bool bgmac_wait_value(struct bcma_device
*core
, u16 reg
, u32 mask
,
42 u32 value
, int timeout
)
47 for (i
= 0; i
< timeout
/ 10; i
++) {
48 val
= bcma_read32(core
, reg
);
49 if ((val
& mask
) == value
)
53 pr_err("Timeout waiting for reg 0x%X\n", reg
);
57 /**************************************************
59 **************************************************/
61 static void bgmac_dma_tx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
69 /* Suspend DMA TX ring first.
70 * bgmac_wait_value doesn't support waiting for any of few values, so
71 * implement whole loop here.
73 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
,
74 BGMAC_DMA_TX_SUSPEND
);
75 for (i
= 0; i
< 10000 / 10; i
++) {
76 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
77 val
&= BGMAC_DMA_TX_STAT
;
78 if (val
== BGMAC_DMA_TX_STAT_DISABLED
||
79 val
== BGMAC_DMA_TX_STAT_IDLEWAIT
||
80 val
== BGMAC_DMA_TX_STAT_STOPPED
) {
87 bgmac_err(bgmac
, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
88 ring
->mmio_base
, val
);
90 /* Remove SUSPEND bit */
91 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, 0);
92 if (!bgmac_wait_value(bgmac
->core
,
93 ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
,
94 BGMAC_DMA_TX_STAT
, BGMAC_DMA_TX_STAT_DISABLED
,
96 bgmac_warn(bgmac
, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
99 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
100 if ((val
& BGMAC_DMA_TX_STAT
) != BGMAC_DMA_TX_STAT_DISABLED
)
101 bgmac_err(bgmac
, "Reset of DMA TX ring 0x%X failed\n",
106 static void bgmac_dma_tx_enable(struct bgmac
*bgmac
,
107 struct bgmac_dma_ring
*ring
)
111 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
);
112 if (bgmac
->core
->id
.rev
>= 4) {
113 ctl
&= ~BGMAC_DMA_TX_BL_MASK
;
114 ctl
|= BGMAC_DMA_TX_BL_128
<< BGMAC_DMA_TX_BL_SHIFT
;
116 ctl
&= ~BGMAC_DMA_TX_MR_MASK
;
117 ctl
|= BGMAC_DMA_TX_MR_2
<< BGMAC_DMA_TX_MR_SHIFT
;
119 ctl
&= ~BGMAC_DMA_TX_PC_MASK
;
120 ctl
|= BGMAC_DMA_TX_PC_16
<< BGMAC_DMA_TX_PC_SHIFT
;
122 ctl
&= ~BGMAC_DMA_TX_PT_MASK
;
123 ctl
|= BGMAC_DMA_TX_PT_8
<< BGMAC_DMA_TX_PT_SHIFT
;
125 ctl
|= BGMAC_DMA_TX_ENABLE
;
126 ctl
|= BGMAC_DMA_TX_PARITY_DISABLE
;
127 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, ctl
);
131 bgmac_dma_tx_add_buf(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
132 int i
, int len
, u32 ctl0
)
134 struct bgmac_slot_info
*slot
;
135 struct bgmac_dma_desc
*dma_desc
;
138 if (i
== BGMAC_TX_RING_SLOTS
- 1)
139 ctl0
|= BGMAC_DESC_CTL0_EOT
;
141 ctl1
= len
& BGMAC_DESC_CTL1_LEN
;
143 slot
= &ring
->slots
[i
];
144 dma_desc
= &ring
->cpu_base
[i
];
145 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(slot
->dma_addr
));
146 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(slot
->dma_addr
));
147 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
148 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
151 static netdev_tx_t
bgmac_dma_tx_add(struct bgmac
*bgmac
,
152 struct bgmac_dma_ring
*ring
,
155 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
156 struct net_device
*net_dev
= bgmac
->net_dev
;
157 int index
= ring
->end
% BGMAC_TX_RING_SLOTS
;
158 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
163 if (skb
->len
> BGMAC_DESC_CTL1_LEN
) {
164 bgmac_err(bgmac
, "Too long skb (%d)\n", skb
->len
);
168 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
169 skb_checksum_help(skb
);
171 nr_frags
= skb_shinfo(skb
)->nr_frags
;
173 /* ring->end - ring->start will return the number of valid slots,
174 * even when ring->end overflows
176 if (ring
->end
- ring
->start
+ nr_frags
+ 1 >= BGMAC_TX_RING_SLOTS
) {
177 bgmac_err(bgmac
, "TX ring is full, queue should be stopped!\n");
178 netif_stop_queue(net_dev
);
179 return NETDEV_TX_BUSY
;
182 slot
->dma_addr
= dma_map_single(dma_dev
, skb
->data
, skb_headlen(skb
),
184 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
187 flags
= BGMAC_DESC_CTL0_SOF
;
189 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
191 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, skb_headlen(skb
), flags
);
194 for (i
= 0; i
< nr_frags
; i
++) {
195 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
196 int len
= skb_frag_size(frag
);
198 index
= (index
+ 1) % BGMAC_TX_RING_SLOTS
;
199 slot
= &ring
->slots
[index
];
200 slot
->dma_addr
= skb_frag_dma_map(dma_dev
, frag
, 0,
202 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
205 if (i
== nr_frags
- 1)
206 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
208 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, len
, flags
);
212 ring
->end
+= nr_frags
+ 1;
213 netdev_sent_queue(net_dev
, skb
->len
);
217 /* Increase ring->end to point empty slot. We tell hardware the first
218 * slot it should *not* read.
220 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_INDEX
,
222 (ring
->end
% BGMAC_TX_RING_SLOTS
) *
223 sizeof(struct bgmac_dma_desc
));
225 if (ring
->end
- ring
->start
>= BGMAC_TX_RING_SLOTS
- 8)
226 netif_stop_queue(net_dev
);
231 dma_unmap_single(dma_dev
, slot
->dma_addr
, skb_headlen(skb
),
235 int index
= (ring
->end
+ i
) % BGMAC_TX_RING_SLOTS
;
236 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
237 u32 ctl1
= le32_to_cpu(ring
->cpu_base
[index
].ctl1
);
238 int len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
240 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
, DMA_TO_DEVICE
);
244 bgmac_err(bgmac
, "Mapping error of skb on ring 0x%X\n",
252 /* Free transmitted packets */
253 static void bgmac_dma_tx_free(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
255 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
258 unsigned bytes_compl
= 0, pkts_compl
= 0;
260 /* The last slot that hardware didn't consume yet */
261 empty_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
262 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
263 empty_slot
-= ring
->index_base
;
264 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
265 empty_slot
/= sizeof(struct bgmac_dma_desc
);
267 while (ring
->start
!= ring
->end
) {
268 int slot_idx
= ring
->start
% BGMAC_TX_RING_SLOTS
;
269 struct bgmac_slot_info
*slot
= &ring
->slots
[slot_idx
];
273 if (slot_idx
== empty_slot
)
276 ctl0
= le32_to_cpu(ring
->cpu_base
[slot_idx
].ctl0
);
277 ctl1
= le32_to_cpu(ring
->cpu_base
[slot_idx
].ctl1
);
278 len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
279 if (ctl0
& BGMAC_DESC_CTL0_SOF
)
280 /* Unmap no longer used buffer */
281 dma_unmap_single(dma_dev
, slot
->dma_addr
, len
,
284 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
,
288 bytes_compl
+= slot
->skb
->len
;
291 /* Free memory! :) */
292 dev_kfree_skb(slot
->skb
);
304 netdev_completed_queue(bgmac
->net_dev
, pkts_compl
, bytes_compl
);
306 if (netif_queue_stopped(bgmac
->net_dev
))
307 netif_wake_queue(bgmac
->net_dev
);
310 static void bgmac_dma_rx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
312 if (!ring
->mmio_base
)
315 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, 0);
316 if (!bgmac_wait_value(bgmac
->core
,
317 ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
,
318 BGMAC_DMA_RX_STAT
, BGMAC_DMA_RX_STAT_DISABLED
,
320 bgmac_err(bgmac
, "Reset of ring 0x%X RX failed\n",
324 static void bgmac_dma_rx_enable(struct bgmac
*bgmac
,
325 struct bgmac_dma_ring
*ring
)
329 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
);
330 if (bgmac
->core
->id
.rev
>= 4) {
331 ctl
&= ~BGMAC_DMA_RX_BL_MASK
;
332 ctl
|= BGMAC_DMA_RX_BL_128
<< BGMAC_DMA_RX_BL_SHIFT
;
334 ctl
&= ~BGMAC_DMA_RX_PC_MASK
;
335 ctl
|= BGMAC_DMA_RX_PC_8
<< BGMAC_DMA_RX_PC_SHIFT
;
337 ctl
&= ~BGMAC_DMA_RX_PT_MASK
;
338 ctl
|= BGMAC_DMA_RX_PT_1
<< BGMAC_DMA_RX_PT_SHIFT
;
340 ctl
&= BGMAC_DMA_RX_ADDREXT_MASK
;
341 ctl
|= BGMAC_DMA_RX_ENABLE
;
342 ctl
|= BGMAC_DMA_RX_PARITY_DISABLE
;
343 ctl
|= BGMAC_DMA_RX_OVERFLOW_CONT
;
344 ctl
|= BGMAC_RX_FRAME_OFFSET
<< BGMAC_DMA_RX_FRAME_OFFSET_SHIFT
;
345 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, ctl
);
348 static int bgmac_dma_rx_skb_for_slot(struct bgmac
*bgmac
,
349 struct bgmac_slot_info
*slot
)
351 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
353 struct bgmac_rx_header
*rx
;
357 buf
= netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE
);
361 /* Poison - if everything goes fine, hardware will overwrite it */
362 rx
= buf
+ BGMAC_RX_BUF_OFFSET
;
363 rx
->len
= cpu_to_le16(0xdead);
364 rx
->flags
= cpu_to_le16(0xbeef);
366 /* Map skb for the DMA */
367 dma_addr
= dma_map_single(dma_dev
, buf
+ BGMAC_RX_BUF_OFFSET
,
368 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
369 if (dma_mapping_error(dma_dev
, dma_addr
)) {
370 bgmac_err(bgmac
, "DMA mapping error\n");
371 put_page(virt_to_head_page(buf
));
375 /* Update the slot */
377 slot
->dma_addr
= dma_addr
;
382 static void bgmac_dma_rx_update_index(struct bgmac
*bgmac
,
383 struct bgmac_dma_ring
*ring
)
387 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_INDEX
,
389 ring
->end
* sizeof(struct bgmac_dma_desc
));
392 static void bgmac_dma_rx_setup_desc(struct bgmac
*bgmac
,
393 struct bgmac_dma_ring
*ring
, int desc_idx
)
395 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
+ desc_idx
;
396 u32 ctl0
= 0, ctl1
= 0;
398 if (desc_idx
== BGMAC_RX_RING_SLOTS
- 1)
399 ctl0
|= BGMAC_DESC_CTL0_EOT
;
400 ctl1
|= BGMAC_RX_BUF_SIZE
& BGMAC_DESC_CTL1_LEN
;
401 /* Is there any BGMAC device that requires extension? */
402 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
403 * B43_DMA64_DCTL1_ADDREXT_MASK;
406 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(ring
->slots
[desc_idx
].dma_addr
));
407 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(ring
->slots
[desc_idx
].dma_addr
));
408 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
409 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
411 ring
->end
= desc_idx
;
414 static void bgmac_dma_rx_poison_buf(struct device
*dma_dev
,
415 struct bgmac_slot_info
*slot
)
417 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
419 dma_sync_single_for_cpu(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
421 rx
->len
= cpu_to_le16(0xdead);
422 rx
->flags
= cpu_to_le16(0xbeef);
423 dma_sync_single_for_device(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
427 static int bgmac_dma_rx_read(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
433 end_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
);
434 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
435 end_slot
-= ring
->index_base
;
436 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
437 end_slot
/= sizeof(struct bgmac_dma_desc
);
439 while (ring
->start
!= end_slot
) {
440 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
441 struct bgmac_slot_info
*slot
= &ring
->slots
[ring
->start
];
442 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
444 void *buf
= slot
->buf
;
445 dma_addr_t dma_addr
= slot
->dma_addr
;
449 /* Prepare new skb as replacement */
450 if (bgmac_dma_rx_skb_for_slot(bgmac
, slot
)) {
451 bgmac_dma_rx_poison_buf(dma_dev
, slot
);
455 /* Unmap buffer to make it accessible to the CPU */
456 dma_unmap_single(dma_dev
, dma_addr
,
457 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
459 /* Get info from the header */
460 len
= le16_to_cpu(rx
->len
);
461 flags
= le16_to_cpu(rx
->flags
);
463 /* Check for poison and drop or pass the packet */
464 if (len
== 0xdead && flags
== 0xbeef) {
465 bgmac_err(bgmac
, "Found poisoned packet at slot %d, DMA issue!\n",
467 put_page(virt_to_head_page(buf
));
471 if (len
> BGMAC_RX_ALLOC_SIZE
) {
472 bgmac_err(bgmac
, "Found oversized packet at slot %d, DMA issue!\n",
474 put_page(virt_to_head_page(buf
));
481 skb
= build_skb(buf
, BGMAC_RX_ALLOC_SIZE
);
482 if (unlikely(!skb
)) {
483 bgmac_err(bgmac
, "build_skb failed\n");
484 put_page(virt_to_head_page(buf
));
487 skb_put(skb
, BGMAC_RX_FRAME_OFFSET
+
488 BGMAC_RX_BUF_OFFSET
+ len
);
489 skb_pull(skb
, BGMAC_RX_FRAME_OFFSET
+
490 BGMAC_RX_BUF_OFFSET
);
492 skb_checksum_none_assert(skb
);
493 skb
->protocol
= eth_type_trans(skb
, bgmac
->net_dev
);
494 napi_gro_receive(&bgmac
->napi
, skb
);
498 bgmac_dma_rx_setup_desc(bgmac
, ring
, ring
->start
);
500 if (++ring
->start
>= BGMAC_RX_RING_SLOTS
)
503 if (handled
>= weight
) /* Should never be greater */
507 bgmac_dma_rx_update_index(bgmac
, ring
);
512 /* Does ring support unaligned addressing? */
513 static bool bgmac_dma_unaligned(struct bgmac
*bgmac
,
514 struct bgmac_dma_ring
*ring
,
515 enum bgmac_dma_ring_type ring_type
)
518 case BGMAC_DMA_RING_TX
:
519 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
521 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
))
524 case BGMAC_DMA_RING_RX
:
525 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
527 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
))
534 static void bgmac_dma_tx_ring_free(struct bgmac
*bgmac
,
535 struct bgmac_dma_ring
*ring
)
537 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
538 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
;
539 struct bgmac_slot_info
*slot
;
542 for (i
= 0; i
< BGMAC_TX_RING_SLOTS
; i
++) {
543 int len
= dma_desc
[i
].ctl1
& BGMAC_DESC_CTL1_LEN
;
545 slot
= &ring
->slots
[i
];
546 dev_kfree_skb(slot
->skb
);
552 dma_unmap_single(dma_dev
, slot
->dma_addr
,
555 dma_unmap_page(dma_dev
, slot
->dma_addr
,
560 static void bgmac_dma_rx_ring_free(struct bgmac
*bgmac
,
561 struct bgmac_dma_ring
*ring
)
563 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
564 struct bgmac_slot_info
*slot
;
567 for (i
= 0; i
< BGMAC_RX_RING_SLOTS
; i
++) {
568 slot
= &ring
->slots
[i
];
572 dma_unmap_single(dma_dev
, slot
->dma_addr
,
575 put_page(virt_to_head_page(slot
->buf
));
580 static void bgmac_dma_ring_desc_free(struct bgmac
*bgmac
,
581 struct bgmac_dma_ring
*ring
,
584 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
590 /* Free ring of descriptors */
591 size
= num_slots
* sizeof(struct bgmac_dma_desc
);
592 dma_free_coherent(dma_dev
, size
, ring
->cpu_base
,
596 static void bgmac_dma_cleanup(struct bgmac
*bgmac
)
600 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
601 bgmac_dma_tx_ring_free(bgmac
, &bgmac
->tx_ring
[i
]);
603 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
604 bgmac_dma_rx_ring_free(bgmac
, &bgmac
->rx_ring
[i
]);
607 static void bgmac_dma_free(struct bgmac
*bgmac
)
611 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
612 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->tx_ring
[i
],
613 BGMAC_TX_RING_SLOTS
);
615 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
616 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->rx_ring
[i
],
617 BGMAC_RX_RING_SLOTS
);
620 static int bgmac_dma_alloc(struct bgmac
*bgmac
)
622 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
623 struct bgmac_dma_ring
*ring
;
624 static const u16 ring_base
[] = { BGMAC_DMA_BASE0
, BGMAC_DMA_BASE1
,
625 BGMAC_DMA_BASE2
, BGMAC_DMA_BASE3
, };
626 int size
; /* ring size: different for Tx and Rx */
630 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS
> ARRAY_SIZE(ring_base
));
631 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS
> ARRAY_SIZE(ring_base
));
633 if (!(bcma_aread32(bgmac
->core
, BCMA_IOST
) & BCMA_IOST_DMA64
)) {
634 bgmac_err(bgmac
, "Core does not report 64-bit DMA\n");
638 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
639 ring
= &bgmac
->tx_ring
[i
];
640 ring
->mmio_base
= ring_base
[i
];
642 /* Alloc ring of descriptors */
643 size
= BGMAC_TX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
644 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
647 if (!ring
->cpu_base
) {
648 bgmac_err(bgmac
, "Allocation of TX ring 0x%X failed\n",
653 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
656 ring
->index_base
= lower_32_bits(ring
->dma_base
);
658 ring
->index_base
= 0;
660 /* No need to alloc TX slots yet */
663 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
664 ring
= &bgmac
->rx_ring
[i
];
665 ring
->mmio_base
= ring_base
[i
];
667 /* Alloc ring of descriptors */
668 size
= BGMAC_RX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
669 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
672 if (!ring
->cpu_base
) {
673 bgmac_err(bgmac
, "Allocation of RX ring 0x%X failed\n",
679 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
682 ring
->index_base
= lower_32_bits(ring
->dma_base
);
684 ring
->index_base
= 0;
690 bgmac_dma_free(bgmac
);
694 static int bgmac_dma_init(struct bgmac
*bgmac
)
696 struct bgmac_dma_ring
*ring
;
699 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
700 ring
= &bgmac
->tx_ring
[i
];
702 if (!ring
->unaligned
)
703 bgmac_dma_tx_enable(bgmac
, ring
);
704 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
705 lower_32_bits(ring
->dma_base
));
706 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGHI
,
707 upper_32_bits(ring
->dma_base
));
709 bgmac_dma_tx_enable(bgmac
, ring
);
712 ring
->end
= 0; /* Points the slot that should *not* be read */
715 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
718 ring
= &bgmac
->rx_ring
[i
];
720 if (!ring
->unaligned
)
721 bgmac_dma_rx_enable(bgmac
, ring
);
722 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
723 lower_32_bits(ring
->dma_base
));
724 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGHI
,
725 upper_32_bits(ring
->dma_base
));
727 bgmac_dma_rx_enable(bgmac
, ring
);
731 for (j
= 0; j
< BGMAC_RX_RING_SLOTS
; j
++) {
732 err
= bgmac_dma_rx_skb_for_slot(bgmac
, &ring
->slots
[j
]);
736 bgmac_dma_rx_setup_desc(bgmac
, ring
, j
);
739 bgmac_dma_rx_update_index(bgmac
, ring
);
745 bgmac_dma_cleanup(bgmac
);
749 /**************************************************
751 **************************************************/
753 static u16
bgmac_phy_read(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
)
755 struct bcma_device
*core
;
760 BUILD_BUG_ON(BGMAC_PA_DATA_MASK
!= BCMA_GMAC_CMN_PA_DATA_MASK
);
761 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK
!= BCMA_GMAC_CMN_PA_ADDR_MASK
);
762 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT
!= BCMA_GMAC_CMN_PA_ADDR_SHIFT
);
763 BUILD_BUG_ON(BGMAC_PA_REG_MASK
!= BCMA_GMAC_CMN_PA_REG_MASK
);
764 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT
!= BCMA_GMAC_CMN_PA_REG_SHIFT
);
765 BUILD_BUG_ON(BGMAC_PA_WRITE
!= BCMA_GMAC_CMN_PA_WRITE
);
766 BUILD_BUG_ON(BGMAC_PA_START
!= BCMA_GMAC_CMN_PA_START
);
767 BUILD_BUG_ON(BGMAC_PC_EPA_MASK
!= BCMA_GMAC_CMN_PC_EPA_MASK
);
768 BUILD_BUG_ON(BGMAC_PC_MCT_MASK
!= BCMA_GMAC_CMN_PC_MCT_MASK
);
769 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT
!= BCMA_GMAC_CMN_PC_MCT_SHIFT
);
770 BUILD_BUG_ON(BGMAC_PC_MTE
!= BCMA_GMAC_CMN_PC_MTE
);
772 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
773 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
774 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
775 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
778 phy_access_addr
= BGMAC_PHY_ACCESS
;
779 phy_ctl_addr
= BGMAC_PHY_CNTL
;
782 tmp
= bcma_read32(core
, phy_ctl_addr
);
783 tmp
&= ~BGMAC_PC_EPA_MASK
;
785 bcma_write32(core
, phy_ctl_addr
, tmp
);
787 tmp
= BGMAC_PA_START
;
788 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
789 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
790 bcma_write32(core
, phy_access_addr
, tmp
);
792 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
793 bgmac_err(bgmac
, "Reading PHY %d register 0x%X failed\n",
798 return bcma_read32(core
, phy_access_addr
) & BGMAC_PA_DATA_MASK
;
801 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
802 static int bgmac_phy_write(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
, u16 value
)
804 struct bcma_device
*core
;
809 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
810 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
811 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
812 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
815 phy_access_addr
= BGMAC_PHY_ACCESS
;
816 phy_ctl_addr
= BGMAC_PHY_CNTL
;
819 tmp
= bcma_read32(core
, phy_ctl_addr
);
820 tmp
&= ~BGMAC_PC_EPA_MASK
;
822 bcma_write32(core
, phy_ctl_addr
, tmp
);
824 bgmac_write(bgmac
, BGMAC_INT_STATUS
, BGMAC_IS_MDIO
);
825 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & BGMAC_IS_MDIO
)
826 bgmac_warn(bgmac
, "Error setting MDIO int\n");
828 tmp
= BGMAC_PA_START
;
829 tmp
|= BGMAC_PA_WRITE
;
830 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
831 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
833 bcma_write32(core
, phy_access_addr
, tmp
);
835 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
836 bgmac_err(bgmac
, "Writing to PHY %d register 0x%X failed\n",
844 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
845 static void bgmac_phy_init(struct bgmac
*bgmac
)
847 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
848 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
851 if (ci
->id
== BCMA_CHIP_ID_BCM5356
) {
852 for (i
= 0; i
< 5; i
++) {
853 bgmac_phy_write(bgmac
, i
, 0x1f, 0x008b);
854 bgmac_phy_write(bgmac
, i
, 0x15, 0x0100);
855 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
856 bgmac_phy_write(bgmac
, i
, 0x12, 0x2aaa);
857 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
860 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
!= 10) ||
861 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
!= 10) ||
862 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
!= 9)) {
863 bcma_chipco_chipctl_maskset(cc
, 2, ~0xc0000000, 0);
864 bcma_chipco_chipctl_maskset(cc
, 4, ~0x80000000, 0);
865 for (i
= 0; i
< 5; i
++) {
866 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
867 bgmac_phy_write(bgmac
, i
, 0x16, 0x5284);
868 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
869 bgmac_phy_write(bgmac
, i
, 0x17, 0x0010);
870 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
871 bgmac_phy_write(bgmac
, i
, 0x16, 0x5296);
872 bgmac_phy_write(bgmac
, i
, 0x17, 0x1073);
873 bgmac_phy_write(bgmac
, i
, 0x17, 0x9073);
874 bgmac_phy_write(bgmac
, i
, 0x16, 0x52b6);
875 bgmac_phy_write(bgmac
, i
, 0x17, 0x9273);
876 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
881 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
882 static void bgmac_phy_reset(struct bgmac
*bgmac
)
884 if (bgmac
->phyaddr
== BGMAC_PHY_NOREGS
)
887 bgmac_phy_write(bgmac
, bgmac
->phyaddr
, MII_BMCR
, BMCR_RESET
);
889 if (bgmac_phy_read(bgmac
, bgmac
->phyaddr
, MII_BMCR
) & BMCR_RESET
)
890 bgmac_err(bgmac
, "PHY reset failed\n");
891 bgmac_phy_init(bgmac
);
894 /**************************************************
896 **************************************************/
898 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
899 * nothing to change? Try if after stabilizng driver.
901 static void bgmac_cmdcfg_maskset(struct bgmac
*bgmac
, u32 mask
, u32 set
,
904 u32 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
905 u32 new_val
= (cmdcfg
& mask
) | set
;
907 bgmac_set(bgmac
, BGMAC_CMDCFG
, BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
910 if (new_val
!= cmdcfg
|| force
)
911 bgmac_write(bgmac
, BGMAC_CMDCFG
, new_val
);
913 bgmac_mask(bgmac
, BGMAC_CMDCFG
, ~BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
917 static void bgmac_write_mac_address(struct bgmac
*bgmac
, u8
*addr
)
921 tmp
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
922 bgmac_write(bgmac
, BGMAC_MACADDR_HIGH
, tmp
);
923 tmp
= (addr
[4] << 8) | addr
[5];
924 bgmac_write(bgmac
, BGMAC_MACADDR_LOW
, tmp
);
927 static void bgmac_set_rx_mode(struct net_device
*net_dev
)
929 struct bgmac
*bgmac
= netdev_priv(net_dev
);
931 if (net_dev
->flags
& IFF_PROMISC
)
932 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_PROM
, true);
934 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_PROM
, 0, true);
937 #if 0 /* We don't use that regs yet */
938 static void bgmac_chip_stats_update(struct bgmac
*bgmac
)
942 if (bgmac
->core
->id
.id
!= BCMA_CORE_4706_MAC_GBIT
) {
943 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
944 bgmac
->mib_tx_regs
[i
] =
946 BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
947 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
948 bgmac
->mib_rx_regs
[i
] =
950 BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
953 /* TODO: what else? how to handle BCM4706? Specs are needed */
957 static void bgmac_clear_mib(struct bgmac
*bgmac
)
961 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
964 bgmac_set(bgmac
, BGMAC_DEV_CTL
, BGMAC_DC_MROR
);
965 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
966 bgmac_read(bgmac
, BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
967 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
968 bgmac_read(bgmac
, BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
971 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
972 static void bgmac_mac_speed(struct bgmac
*bgmac
)
974 u32 mask
= ~(BGMAC_CMDCFG_ES_MASK
| BGMAC_CMDCFG_HD
);
977 switch (bgmac
->mac_speed
) {
979 set
|= BGMAC_CMDCFG_ES_10
;
982 set
|= BGMAC_CMDCFG_ES_100
;
985 set
|= BGMAC_CMDCFG_ES_1000
;
988 set
|= BGMAC_CMDCFG_ES_2500
;
991 bgmac_err(bgmac
, "Unsupported speed: %d\n", bgmac
->mac_speed
);
994 if (bgmac
->mac_duplex
== DUPLEX_HALF
)
995 set
|= BGMAC_CMDCFG_HD
;
997 bgmac_cmdcfg_maskset(bgmac
, mask
, set
, true);
1000 static void bgmac_miiconfig(struct bgmac
*bgmac
)
1002 struct bcma_device
*core
= bgmac
->core
;
1005 if (bgmac_is_bcm4707_family(bgmac
)) {
1006 bcma_awrite32(core
, BCMA_IOCTL
,
1007 bcma_aread32(core
, BCMA_IOCTL
) | 0x40 |
1008 BGMAC_BCMA_IOCTL_SW_CLKEN
);
1009 bgmac
->mac_speed
= SPEED_2500
;
1010 bgmac
->mac_duplex
= DUPLEX_FULL
;
1011 bgmac_mac_speed(bgmac
);
1013 imode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) &
1014 BGMAC_DS_MM_MASK
) >> BGMAC_DS_MM_SHIFT
;
1015 if (imode
== 0 || imode
== 1) {
1016 bgmac
->mac_speed
= SPEED_100
;
1017 bgmac
->mac_duplex
= DUPLEX_FULL
;
1018 bgmac_mac_speed(bgmac
);
1023 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1024 static void bgmac_chip_reset(struct bgmac
*bgmac
)
1026 struct bcma_device
*core
= bgmac
->core
;
1027 struct bcma_bus
*bus
= core
->bus
;
1028 struct bcma_chipinfo
*ci
= &bus
->chipinfo
;
1033 if (bcma_core_is_enabled(core
)) {
1034 if (!bgmac
->stats_grabbed
) {
1035 /* bgmac_chip_stats_update(bgmac); */
1036 bgmac
->stats_grabbed
= true;
1039 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
1040 bgmac_dma_tx_reset(bgmac
, &bgmac
->tx_ring
[i
]);
1042 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1045 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
1046 bgmac_dma_rx_reset(bgmac
, &bgmac
->rx_ring
[i
]);
1048 /* TODO: Clear software multicast filter list */
1051 iost
= bcma_aread32(core
, BCMA_IOST
);
1052 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1053 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1054 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
))
1055 iost
&= ~BGMAC_BCMA_IOST_ATTACHED
;
1057 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
1058 if (ci
->id
!= BCMA_CHIP_ID_BCM4707
&&
1059 ci
->id
!= BCMA_CHIP_ID_BCM47094
) {
1061 if (iost
& BGMAC_BCMA_IOST_ATTACHED
) {
1062 flags
= BGMAC_BCMA_IOCTL_SW_CLKEN
;
1063 if (!bgmac
->has_robosw
)
1064 flags
|= BGMAC_BCMA_IOCTL_SW_RESET
;
1066 bcma_core_enable(core
, flags
);
1069 /* Request Misc PLL for corerev > 2 */
1070 if (core
->id
.rev
> 2 && !bgmac_is_bcm4707_family(bgmac
)) {
1071 bgmac_set(bgmac
, BCMA_CLKCTLST
,
1072 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ
);
1073 bgmac_wait_value(bgmac
->core
, BCMA_CLKCTLST
,
1074 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1075 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1079 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1080 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1081 ci
->id
== BCMA_CHIP_ID_BCM53572
) {
1082 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
1084 u8 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHY
|
1085 BGMAC_CHIPCTL_1_IF_TYPE_MII
;
1088 if (bcm47xx_nvram_getenv("et_swtype", buf
, sizeof(buf
)) > 0) {
1089 if (kstrtou8(buf
, 0, &et_swtype
))
1090 bgmac_err(bgmac
, "Failed to parse et_swtype (%s)\n",
1094 sw_type
= et_swtype
;
1095 } else if (ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM5358
) {
1096 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII
;
1097 } else if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1098 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1099 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
)) {
1100 sw_type
= BGMAC_CHIPCTL_1_IF_TYPE_RGMII
|
1101 BGMAC_CHIPCTL_1_SW_TYPE_RGMII
;
1103 bcma_chipco_chipctl_maskset(cc
, 1,
1104 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK
|
1105 BGMAC_CHIPCTL_1_SW_TYPE_MASK
),
1109 if (iost
& BGMAC_BCMA_IOST_ATTACHED
&& !bgmac
->has_robosw
)
1110 bcma_awrite32(core
, BCMA_IOCTL
,
1111 bcma_aread32(core
, BCMA_IOCTL
) &
1112 ~BGMAC_BCMA_IOCTL_SW_RESET
);
1114 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1115 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1116 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1117 * be keps until taking MAC out of the reset.
1119 bgmac_cmdcfg_maskset(bgmac
,
1131 BGMAC_CMDCFG_PAD_EN
|
1136 BGMAC_CMDCFG_SR(core
->id
.rev
),
1138 bgmac
->mac_speed
= SPEED_UNKNOWN
;
1139 bgmac
->mac_duplex
= DUPLEX_UNKNOWN
;
1141 bgmac_clear_mib(bgmac
);
1142 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
1143 bcma_maskset32(bgmac
->cmn
, BCMA_GMAC_CMN_PHY_CTL
, ~0,
1144 BCMA_GMAC_CMN_PC_MTE
);
1146 bgmac_set(bgmac
, BGMAC_PHY_CNTL
, BGMAC_PC_MTE
);
1147 bgmac_miiconfig(bgmac
);
1148 bgmac_phy_init(bgmac
);
1150 netdev_reset_queue(bgmac
->net_dev
);
1153 static void bgmac_chip_intrs_on(struct bgmac
*bgmac
)
1155 bgmac_write(bgmac
, BGMAC_INT_MASK
, bgmac
->int_mask
);
1158 static void bgmac_chip_intrs_off(struct bgmac
*bgmac
)
1160 bgmac_write(bgmac
, BGMAC_INT_MASK
, 0);
1161 bgmac_read(bgmac
, BGMAC_INT_MASK
);
1164 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1165 static void bgmac_enable(struct bgmac
*bgmac
)
1167 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
1175 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
1176 bgmac_cmdcfg_maskset(bgmac
, ~(BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
),
1177 BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
), true);
1179 cmdcfg
|= BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
;
1180 bgmac_write(bgmac
, BGMAC_CMDCFG
, cmdcfg
);
1182 mode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) & BGMAC_DS_MM_MASK
) >>
1184 if (ci
->id
!= BCMA_CHIP_ID_BCM47162
|| mode
!= 0)
1185 bgmac_set(bgmac
, BCMA_CLKCTLST
, BCMA_CLKCTLST_FORCEHT
);
1186 if (ci
->id
== BCMA_CHIP_ID_BCM47162
&& mode
== 2)
1187 bcma_chipco_chipctl_maskset(&bgmac
->core
->bus
->drv_cc
, 1, ~0,
1188 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS
);
1191 case BCMA_CHIP_ID_BCM5357
:
1192 case BCMA_CHIP_ID_BCM4749
:
1193 case BCMA_CHIP_ID_BCM53572
:
1194 case BCMA_CHIP_ID_BCM4716
:
1195 case BCMA_CHIP_ID_BCM47162
:
1196 fl_ctl
= 0x03cb04cb;
1197 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1198 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1199 ci
->id
== BCMA_CHIP_ID_BCM53572
)
1201 bgmac_write(bgmac
, BGMAC_FLOW_CTL_THRESH
, fl_ctl
);
1202 bgmac_write(bgmac
, BGMAC_PAUSE_CTL
, 0x27fff);
1206 if (!bgmac_is_bcm4707_family(bgmac
)) {
1207 rxq_ctl
= bgmac_read(bgmac
, BGMAC_RXQ_CTL
);
1208 rxq_ctl
&= ~BGMAC_RXQ_CTL_MDP_MASK
;
1209 bp_clk
= bcma_pmu_get_bus_clock(&bgmac
->core
->bus
->drv_cc
) /
1211 mdp
= (bp_clk
* 128 / 1000) - 3;
1212 rxq_ctl
|= (mdp
<< BGMAC_RXQ_CTL_MDP_SHIFT
);
1213 bgmac_write(bgmac
, BGMAC_RXQ_CTL
, rxq_ctl
);
1217 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1218 static void bgmac_chip_init(struct bgmac
*bgmac
)
1220 /* 1 interrupt per received frame */
1221 bgmac_write(bgmac
, BGMAC_INT_RECV_LAZY
, 1 << BGMAC_IRL_FC_SHIFT
);
1223 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1224 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_RPI
, 0, true);
1226 bgmac_set_rx_mode(bgmac
->net_dev
);
1228 bgmac_write_mac_address(bgmac
, bgmac
->net_dev
->dev_addr
);
1230 if (bgmac
->loopback
)
1231 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1233 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_ML
, 0, false);
1235 bgmac_write(bgmac
, BGMAC_RXMAX_LENGTH
, 32 + ETHER_MAX_LEN
);
1237 bgmac_chip_intrs_on(bgmac
);
1239 bgmac_enable(bgmac
);
1242 static irqreturn_t
bgmac_interrupt(int irq
, void *dev_id
)
1244 struct bgmac
*bgmac
= netdev_priv(dev_id
);
1246 u32 int_status
= bgmac_read(bgmac
, BGMAC_INT_STATUS
);
1247 int_status
&= bgmac
->int_mask
;
1252 int_status
&= ~(BGMAC_IS_TX0
| BGMAC_IS_RX
);
1254 bgmac_err(bgmac
, "Unknown IRQs: 0x%08X\n", int_status
);
1256 /* Disable new interrupts until handling existing ones */
1257 bgmac_chip_intrs_off(bgmac
);
1259 napi_schedule(&bgmac
->napi
);
1264 static int bgmac_poll(struct napi_struct
*napi
, int weight
)
1266 struct bgmac
*bgmac
= container_of(napi
, struct bgmac
, napi
);
1270 bgmac_write(bgmac
, BGMAC_INT_STATUS
, ~0);
1272 bgmac_dma_tx_free(bgmac
, &bgmac
->tx_ring
[0]);
1273 handled
+= bgmac_dma_rx_read(bgmac
, &bgmac
->rx_ring
[0], weight
);
1275 /* Poll again if more events arrived in the meantime */
1276 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & (BGMAC_IS_TX0
| BGMAC_IS_RX
))
1279 if (handled
< weight
) {
1280 napi_complete(napi
);
1281 bgmac_chip_intrs_on(bgmac
);
1287 /**************************************************
1289 **************************************************/
1291 static int bgmac_open(struct net_device
*net_dev
)
1293 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1296 bgmac_chip_reset(bgmac
);
1298 err
= bgmac_dma_init(bgmac
);
1302 /* Specs say about reclaiming rings here, but we do that in DMA init */
1303 bgmac_chip_init(bgmac
);
1305 err
= request_irq(bgmac
->core
->irq
, bgmac_interrupt
, IRQF_SHARED
,
1306 KBUILD_MODNAME
, net_dev
);
1308 bgmac_err(bgmac
, "IRQ request error: %d!\n", err
);
1309 bgmac_dma_cleanup(bgmac
);
1312 napi_enable(&bgmac
->napi
);
1314 phy_start(bgmac
->phy_dev
);
1316 netif_start_queue(net_dev
);
1321 static int bgmac_stop(struct net_device
*net_dev
)
1323 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1325 netif_carrier_off(net_dev
);
1327 phy_stop(bgmac
->phy_dev
);
1329 napi_disable(&bgmac
->napi
);
1330 bgmac_chip_intrs_off(bgmac
);
1331 free_irq(bgmac
->core
->irq
, net_dev
);
1333 bgmac_chip_reset(bgmac
);
1334 bgmac_dma_cleanup(bgmac
);
1339 static netdev_tx_t
bgmac_start_xmit(struct sk_buff
*skb
,
1340 struct net_device
*net_dev
)
1342 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1343 struct bgmac_dma_ring
*ring
;
1345 /* No QOS support yet */
1346 ring
= &bgmac
->tx_ring
[0];
1347 return bgmac_dma_tx_add(bgmac
, ring
, skb
);
1350 static int bgmac_set_mac_address(struct net_device
*net_dev
, void *addr
)
1352 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1355 ret
= eth_prepare_mac_addr_change(net_dev
, addr
);
1358 bgmac_write_mac_address(bgmac
, (u8
*)addr
);
1359 eth_commit_mac_addr_change(net_dev
, addr
);
1363 static int bgmac_ioctl(struct net_device
*net_dev
, struct ifreq
*ifr
, int cmd
)
1365 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1367 if (!netif_running(net_dev
))
1370 return phy_mii_ioctl(bgmac
->phy_dev
, ifr
, cmd
);
1373 static const struct net_device_ops bgmac_netdev_ops
= {
1374 .ndo_open
= bgmac_open
,
1375 .ndo_stop
= bgmac_stop
,
1376 .ndo_start_xmit
= bgmac_start_xmit
,
1377 .ndo_set_rx_mode
= bgmac_set_rx_mode
,
1378 .ndo_set_mac_address
= bgmac_set_mac_address
,
1379 .ndo_validate_addr
= eth_validate_addr
,
1380 .ndo_do_ioctl
= bgmac_ioctl
,
1383 /**************************************************
1385 **************************************************/
1387 static int bgmac_get_settings(struct net_device
*net_dev
,
1388 struct ethtool_cmd
*cmd
)
1390 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1392 return phy_ethtool_gset(bgmac
->phy_dev
, cmd
);
1395 static int bgmac_set_settings(struct net_device
*net_dev
,
1396 struct ethtool_cmd
*cmd
)
1398 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1400 return phy_ethtool_sset(bgmac
->phy_dev
, cmd
);
1403 static void bgmac_get_drvinfo(struct net_device
*net_dev
,
1404 struct ethtool_drvinfo
*info
)
1406 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1407 strlcpy(info
->bus_info
, "BCMA", sizeof(info
->bus_info
));
1410 static const struct ethtool_ops bgmac_ethtool_ops
= {
1411 .get_settings
= bgmac_get_settings
,
1412 .set_settings
= bgmac_set_settings
,
1413 .get_drvinfo
= bgmac_get_drvinfo
,
1416 /**************************************************
1418 **************************************************/
1420 static int bgmac_mii_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1422 return bgmac_phy_read(bus
->priv
, mii_id
, regnum
);
1425 static int bgmac_mii_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
1428 return bgmac_phy_write(bus
->priv
, mii_id
, regnum
, value
);
1431 static void bgmac_adjust_link(struct net_device
*net_dev
)
1433 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1434 struct phy_device
*phy_dev
= bgmac
->phy_dev
;
1435 bool update
= false;
1437 if (phy_dev
->link
) {
1438 if (phy_dev
->speed
!= bgmac
->mac_speed
) {
1439 bgmac
->mac_speed
= phy_dev
->speed
;
1443 if (phy_dev
->duplex
!= bgmac
->mac_duplex
) {
1444 bgmac
->mac_duplex
= phy_dev
->duplex
;
1450 bgmac_mac_speed(bgmac
);
1451 phy_print_status(phy_dev
);
1455 static int bgmac_fixed_phy_register(struct bgmac
*bgmac
)
1457 struct fixed_phy_status fphy_status
= {
1459 .speed
= SPEED_1000
,
1460 .duplex
= DUPLEX_FULL
,
1462 struct phy_device
*phy_dev
;
1465 phy_dev
= fixed_phy_register(PHY_POLL
, &fphy_status
, -1, NULL
);
1466 if (!phy_dev
|| IS_ERR(phy_dev
)) {
1467 bgmac_err(bgmac
, "Failed to register fixed PHY device\n");
1471 err
= phy_connect_direct(bgmac
->net_dev
, phy_dev
, bgmac_adjust_link
,
1472 PHY_INTERFACE_MODE_MII
);
1474 bgmac_err(bgmac
, "Connecting PHY failed\n");
1478 bgmac
->phy_dev
= phy_dev
;
1483 static int bgmac_mii_register(struct bgmac
*bgmac
)
1485 struct mii_bus
*mii_bus
;
1486 struct phy_device
*phy_dev
;
1487 char bus_id
[MII_BUS_ID_SIZE
+ 3];
1490 if (bgmac_is_bcm4707_family(bgmac
))
1491 return bgmac_fixed_phy_register(bgmac
);
1493 mii_bus
= mdiobus_alloc();
1497 mii_bus
->name
= "bgmac mii bus";
1498 sprintf(mii_bus
->id
, "%s-%d-%d", "bgmac", bgmac
->core
->bus
->num
,
1499 bgmac
->core
->core_unit
);
1500 mii_bus
->priv
= bgmac
;
1501 mii_bus
->read
= bgmac_mii_read
;
1502 mii_bus
->write
= bgmac_mii_write
;
1503 mii_bus
->parent
= &bgmac
->core
->dev
;
1504 mii_bus
->phy_mask
= ~(1 << bgmac
->phyaddr
);
1506 err
= mdiobus_register(mii_bus
);
1508 bgmac_err(bgmac
, "Registration of mii bus failed\n");
1512 bgmac
->mii_bus
= mii_bus
;
1514 /* Connect to the PHY */
1515 snprintf(bus_id
, sizeof(bus_id
), PHY_ID_FMT
, mii_bus
->id
,
1517 phy_dev
= phy_connect(bgmac
->net_dev
, bus_id
, &bgmac_adjust_link
,
1518 PHY_INTERFACE_MODE_MII
);
1519 if (IS_ERR(phy_dev
)) {
1520 bgmac_err(bgmac
, "PHY connection failed\n");
1521 err
= PTR_ERR(phy_dev
);
1522 goto err_unregister_bus
;
1524 bgmac
->phy_dev
= phy_dev
;
1529 mdiobus_unregister(mii_bus
);
1531 mdiobus_free(mii_bus
);
1535 static void bgmac_mii_unregister(struct bgmac
*bgmac
)
1537 struct mii_bus
*mii_bus
= bgmac
->mii_bus
;
1539 mdiobus_unregister(mii_bus
);
1540 mdiobus_free(mii_bus
);
1543 /**************************************************
1545 **************************************************/
1547 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1548 static int bgmac_probe(struct bcma_device
*core
)
1550 struct net_device
*net_dev
;
1551 struct bgmac
*bgmac
;
1552 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
1556 switch (core
->core_unit
) {
1558 mac
= sprom
->et0mac
;
1561 mac
= sprom
->et1mac
;
1564 mac
= sprom
->et2mac
;
1567 pr_err("Unsupported core_unit %d\n", core
->core_unit
);
1571 if (!is_valid_ether_addr(mac
)) {
1572 dev_err(&core
->dev
, "Invalid MAC addr: %pM\n", mac
);
1573 eth_random_addr(mac
);
1574 dev_warn(&core
->dev
, "Using random MAC: %pM\n", mac
);
1577 /* This (reset &) enable is not preset in specs or reference driver but
1578 * Broadcom does it in arch PCI code when enabling fake PCI device.
1580 bcma_core_enable(core
, 0);
1582 /* Allocation and references */
1583 net_dev
= alloc_etherdev(sizeof(*bgmac
));
1586 net_dev
->netdev_ops
= &bgmac_netdev_ops
;
1587 net_dev
->irq
= core
->irq
;
1588 net_dev
->ethtool_ops
= &bgmac_ethtool_ops
;
1589 bgmac
= netdev_priv(net_dev
);
1590 bgmac
->net_dev
= net_dev
;
1592 bcma_set_drvdata(core
, bgmac
);
1595 memcpy(bgmac
->net_dev
->dev_addr
, mac
, ETH_ALEN
);
1597 /* On BCM4706 we need common core to access PHY */
1598 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
&&
1599 !core
->bus
->drv_gmac_cmn
.core
) {
1600 bgmac_err(bgmac
, "GMAC CMN core not found (required for BCM4706)\n");
1602 goto err_netdev_free
;
1604 bgmac
->cmn
= core
->bus
->drv_gmac_cmn
.core
;
1606 switch (core
->core_unit
) {
1608 bgmac
->phyaddr
= sprom
->et0phyaddr
;
1611 bgmac
->phyaddr
= sprom
->et1phyaddr
;
1614 bgmac
->phyaddr
= sprom
->et2phyaddr
;
1617 bgmac
->phyaddr
&= BGMAC_PHY_MASK
;
1618 if (bgmac
->phyaddr
== BGMAC_PHY_MASK
) {
1619 bgmac_err(bgmac
, "No PHY found\n");
1621 goto err_netdev_free
;
1623 bgmac_info(bgmac
, "Found PHY addr: %d%s\n", bgmac
->phyaddr
,
1624 bgmac
->phyaddr
== BGMAC_PHY_NOREGS
? " (NOREGS)" : "");
1626 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
1627 bgmac_err(bgmac
, "PCI setup not implemented\n");
1629 goto err_netdev_free
;
1632 bgmac_chip_reset(bgmac
);
1634 /* For Northstar, we have to take all GMAC core out of reset */
1635 if (bgmac_is_bcm4707_family(bgmac
)) {
1636 struct bcma_device
*ns_core
;
1639 /* Northstar has 4 GMAC cores */
1640 for (ns_gmac
= 0; ns_gmac
< 4; ns_gmac
++) {
1641 /* As Northstar requirement, we have to reset all GMACs
1642 * before accessing one. bgmac_chip_reset() call
1643 * bcma_core_enable() for this core. Then the other
1644 * three GMACs didn't reset. We do it here.
1646 ns_core
= bcma_find_core_unit(core
->bus
,
1649 if (ns_core
&& !bcma_core_is_enabled(ns_core
))
1650 bcma_core_enable(ns_core
, 0);
1654 err
= bgmac_dma_alloc(bgmac
);
1656 bgmac_err(bgmac
, "Unable to alloc memory for DMA\n");
1657 goto err_netdev_free
;
1660 bgmac
->int_mask
= BGMAC_IS_ERRMASK
| BGMAC_IS_RX
| BGMAC_IS_TX_MASK
;
1661 if (bcm47xx_nvram_getenv("et0_no_txint", NULL
, 0) == 0)
1662 bgmac
->int_mask
&= ~BGMAC_IS_TX_MASK
;
1664 /* TODO: reset the external phy. Specs are needed */
1665 bgmac_phy_reset(bgmac
);
1667 bgmac
->has_robosw
= !!(core
->bus
->sprom
.boardflags_lo
&
1668 BGMAC_BFL_ENETROBO
);
1669 if (bgmac
->has_robosw
)
1670 bgmac_warn(bgmac
, "Support for Roboswitch not implemented\n");
1672 if (core
->bus
->sprom
.boardflags_lo
& BGMAC_BFL_ENETADM
)
1673 bgmac_warn(bgmac
, "Support for ADMtek ethernet switch not implemented\n");
1675 netif_napi_add(net_dev
, &bgmac
->napi
, bgmac_poll
, BGMAC_WEIGHT
);
1677 err
= bgmac_mii_register(bgmac
);
1679 bgmac_err(bgmac
, "Cannot register MDIO\n");
1683 net_dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
1684 net_dev
->hw_features
= net_dev
->features
;
1685 net_dev
->vlan_features
= net_dev
->features
;
1687 err
= register_netdev(bgmac
->net_dev
);
1689 bgmac_err(bgmac
, "Cannot register net device\n");
1690 goto err_mii_unregister
;
1693 netif_carrier_off(net_dev
);
1698 bgmac_mii_unregister(bgmac
);
1700 bgmac_dma_free(bgmac
);
1703 bcma_set_drvdata(core
, NULL
);
1704 free_netdev(net_dev
);
1709 static void bgmac_remove(struct bcma_device
*core
)
1711 struct bgmac
*bgmac
= bcma_get_drvdata(core
);
1713 unregister_netdev(bgmac
->net_dev
);
1714 bgmac_mii_unregister(bgmac
);
1715 netif_napi_del(&bgmac
->napi
);
1716 bgmac_dma_free(bgmac
);
1717 bcma_set_drvdata(core
, NULL
);
1718 free_netdev(bgmac
->net_dev
);
1721 static struct bcma_driver bgmac_bcma_driver
= {
1722 .name
= KBUILD_MODNAME
,
1723 .id_table
= bgmac_bcma_tbl
,
1724 .probe
= bgmac_probe
,
1725 .remove
= bgmac_remove
,
1728 static int __init
bgmac_init(void)
1732 err
= bcma_driver_register(&bgmac_bcma_driver
);
1735 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1740 static void __exit
bgmac_exit(void)
1742 bcma_driver_unregister(&bgmac_bcma_driver
);
1745 module_init(bgmac_init
)
1746 module_exit(bgmac_exit
)
1748 MODULE_AUTHOR("Rafał Miłecki");
1749 MODULE_LICENSE("GPL");