2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40 #define RX_RING_SIZE 512 /* must be power of 2 */
41 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
43 #define TX_RING_SIZE 128 /* must be power of 2 */
44 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
46 /* level of occupied TX descriptors under which we wake up TX process */
47 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
49 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
51 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
54 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
59 #define GEM_MTU_MIN_SIZE 68
61 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
62 #define MACB_WOL_ENABLED (0x1 << 1)
65 * Graceful stop timeouts in us. We should allow up to
66 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
68 #define MACB_HALT_TIMEOUT 1230
70 /* Ring buffer accessors */
71 static unsigned int macb_tx_ring_wrap(unsigned int index
)
73 return index
& (TX_RING_SIZE
- 1);
76 static struct macb_dma_desc
*macb_tx_desc(struct macb_queue
*queue
,
79 return &queue
->tx_ring
[macb_tx_ring_wrap(index
)];
82 static struct macb_tx_skb
*macb_tx_skb(struct macb_queue
*queue
,
85 return &queue
->tx_skb
[macb_tx_ring_wrap(index
)];
88 static dma_addr_t
macb_tx_dma(struct macb_queue
*queue
, unsigned int index
)
92 offset
= macb_tx_ring_wrap(index
) * sizeof(struct macb_dma_desc
);
94 return queue
->tx_ring_dma
+ offset
;
97 static unsigned int macb_rx_ring_wrap(unsigned int index
)
99 return index
& (RX_RING_SIZE
- 1);
102 static struct macb_dma_desc
*macb_rx_desc(struct macb
*bp
, unsigned int index
)
104 return &bp
->rx_ring
[macb_rx_ring_wrap(index
)];
107 static void *macb_rx_buffer(struct macb
*bp
, unsigned int index
)
109 return bp
->rx_buffers
+ bp
->rx_buffer_size
* macb_rx_ring_wrap(index
);
113 static u32
hw_readl_native(struct macb
*bp
, int offset
)
115 return __raw_readl(bp
->regs
+ offset
);
118 static void hw_writel_native(struct macb
*bp
, int offset
, u32 value
)
120 __raw_writel(value
, bp
->regs
+ offset
);
123 static u32
hw_readl(struct macb
*bp
, int offset
)
125 return readl_relaxed(bp
->regs
+ offset
);
128 static void hw_writel(struct macb
*bp
, int offset
, u32 value
)
130 writel_relaxed(value
, bp
->regs
+ offset
);
134 * Find the CPU endianness by using the loopback bit of NCR register. When the
135 * CPU is in big endian we need to program swaped mode for management
138 static bool hw_is_native_io(void __iomem
*addr
)
140 u32 value
= MACB_BIT(LLB
);
142 __raw_writel(value
, addr
+ MACB_NCR
);
143 value
= __raw_readl(addr
+ MACB_NCR
);
145 /* Write 0 back to disable everything */
146 __raw_writel(0, addr
+ MACB_NCR
);
148 return value
== MACB_BIT(LLB
);
151 static bool hw_is_gem(void __iomem
*addr
, bool native_io
)
156 id
= __raw_readl(addr
+ MACB_MID
);
158 id
= readl_relaxed(addr
+ MACB_MID
);
160 return MACB_BFEXT(IDNUM
, id
) >= 0x2;
163 static void macb_set_hwaddr(struct macb
*bp
)
168 bottom
= cpu_to_le32(*((u32
*)bp
->dev
->dev_addr
));
169 macb_or_gem_writel(bp
, SA1B
, bottom
);
170 top
= cpu_to_le16(*((u16
*)(bp
->dev
->dev_addr
+ 4)));
171 macb_or_gem_writel(bp
, SA1T
, top
);
173 /* Clear unused address register sets */
174 macb_or_gem_writel(bp
, SA2B
, 0);
175 macb_or_gem_writel(bp
, SA2T
, 0);
176 macb_or_gem_writel(bp
, SA3B
, 0);
177 macb_or_gem_writel(bp
, SA3T
, 0);
178 macb_or_gem_writel(bp
, SA4B
, 0);
179 macb_or_gem_writel(bp
, SA4T
, 0);
182 static void macb_get_hwaddr(struct macb
*bp
)
184 struct macb_platform_data
*pdata
;
190 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
192 /* Check all 4 address register for vaild address */
193 for (i
= 0; i
< 4; i
++) {
194 bottom
= macb_or_gem_readl(bp
, SA1B
+ i
* 8);
195 top
= macb_or_gem_readl(bp
, SA1T
+ i
* 8);
197 if (pdata
&& pdata
->rev_eth_addr
) {
198 addr
[5] = bottom
& 0xff;
199 addr
[4] = (bottom
>> 8) & 0xff;
200 addr
[3] = (bottom
>> 16) & 0xff;
201 addr
[2] = (bottom
>> 24) & 0xff;
202 addr
[1] = top
& 0xff;
203 addr
[0] = (top
& 0xff00) >> 8;
205 addr
[0] = bottom
& 0xff;
206 addr
[1] = (bottom
>> 8) & 0xff;
207 addr
[2] = (bottom
>> 16) & 0xff;
208 addr
[3] = (bottom
>> 24) & 0xff;
209 addr
[4] = top
& 0xff;
210 addr
[5] = (top
>> 8) & 0xff;
213 if (is_valid_ether_addr(addr
)) {
214 memcpy(bp
->dev
->dev_addr
, addr
, sizeof(addr
));
219 dev_info(&bp
->pdev
->dev
, "invalid hw address, using random\n");
220 eth_hw_addr_random(bp
->dev
);
223 static int macb_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
225 struct macb
*bp
= bus
->priv
;
228 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
229 | MACB_BF(RW
, MACB_MAN_READ
)
230 | MACB_BF(PHYA
, mii_id
)
231 | MACB_BF(REGA
, regnum
)
232 | MACB_BF(CODE
, MACB_MAN_CODE
)));
234 /* wait for end of transfer */
235 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
238 value
= MACB_BFEXT(DATA
, macb_readl(bp
, MAN
));
243 static int macb_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
246 struct macb
*bp
= bus
->priv
;
248 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
249 | MACB_BF(RW
, MACB_MAN_WRITE
)
250 | MACB_BF(PHYA
, mii_id
)
251 | MACB_BF(REGA
, regnum
)
252 | MACB_BF(CODE
, MACB_MAN_CODE
)
253 | MACB_BF(DATA
, value
)));
255 /* wait for end of transfer */
256 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
263 * macb_set_tx_clk() - Set a clock to a new frequency
264 * @clk Pointer to the clock to change
265 * @rate New frequency in Hz
266 * @dev Pointer to the struct net_device
268 static void macb_set_tx_clk(struct clk
*clk
, int speed
, struct net_device
*dev
)
270 long ferr
, rate
, rate_rounded
;
289 rate_rounded
= clk_round_rate(clk
, rate
);
290 if (rate_rounded
< 0)
293 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
296 ferr
= abs(rate_rounded
- rate
);
297 ferr
= DIV_ROUND_UP(ferr
, rate
/ 100000);
299 netdev_warn(dev
, "unable to generate target frequency: %ld Hz\n",
302 if (clk_set_rate(clk
, rate_rounded
))
303 netdev_err(dev
, "adjusting tx_clk failed.\n");
306 static void macb_handle_link_change(struct net_device
*dev
)
308 struct macb
*bp
= netdev_priv(dev
);
309 struct phy_device
*phydev
= bp
->phy_dev
;
311 int status_change
= 0;
313 spin_lock_irqsave(&bp
->lock
, flags
);
316 if ((bp
->speed
!= phydev
->speed
) ||
317 (bp
->duplex
!= phydev
->duplex
)) {
320 reg
= macb_readl(bp
, NCFGR
);
321 reg
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
));
323 reg
&= ~GEM_BIT(GBE
);
327 if (phydev
->speed
== SPEED_100
)
328 reg
|= MACB_BIT(SPD
);
329 if (phydev
->speed
== SPEED_1000
&&
330 bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
333 macb_or_gem_writel(bp
, NCFGR
, reg
);
335 bp
->speed
= phydev
->speed
;
336 bp
->duplex
= phydev
->duplex
;
341 if (phydev
->link
!= bp
->link
) {
346 bp
->link
= phydev
->link
;
351 spin_unlock_irqrestore(&bp
->lock
, flags
);
355 /* Update the TX clock rate if and only if the link is
356 * up and there has been a link change.
358 macb_set_tx_clk(bp
->tx_clk
, phydev
->speed
, dev
);
360 netif_carrier_on(dev
);
361 netdev_info(dev
, "link up (%d/%s)\n",
363 phydev
->duplex
== DUPLEX_FULL
?
366 netif_carrier_off(dev
);
367 netdev_info(dev
, "link down\n");
372 /* based on au1000_eth. c*/
373 static int macb_mii_probe(struct net_device
*dev
)
375 struct macb
*bp
= netdev_priv(dev
);
376 struct macb_platform_data
*pdata
;
377 struct phy_device
*phydev
;
381 phydev
= phy_find_first(bp
->mii_bus
);
383 netdev_err(dev
, "no PHY found\n");
387 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
388 if (pdata
&& gpio_is_valid(pdata
->phy_irq_pin
)) {
389 ret
= devm_gpio_request(&bp
->pdev
->dev
, pdata
->phy_irq_pin
, "phy int");
391 phy_irq
= gpio_to_irq(pdata
->phy_irq_pin
);
392 phydev
->irq
= (phy_irq
< 0) ? PHY_POLL
: phy_irq
;
396 /* attach the mac to the phy */
397 ret
= phy_connect_direct(dev
, phydev
, &macb_handle_link_change
,
400 netdev_err(dev
, "Could not attach to PHY\n");
404 /* mask with MAC supported features */
405 if (macb_is_gem(bp
) && bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
406 phydev
->supported
&= PHY_GBIT_FEATURES
;
408 phydev
->supported
&= PHY_BASIC_FEATURES
;
410 if (bp
->caps
& MACB_CAPS_NO_GIGABIT_HALF
)
411 phydev
->supported
&= ~SUPPORTED_1000baseT_Half
;
413 phydev
->advertising
= phydev
->supported
;
418 bp
->phy_dev
= phydev
;
423 static int macb_mii_init(struct macb
*bp
)
425 struct macb_platform_data
*pdata
;
426 struct device_node
*np
;
429 /* Enable management port */
430 macb_writel(bp
, NCR
, MACB_BIT(MPE
));
432 bp
->mii_bus
= mdiobus_alloc();
433 if (bp
->mii_bus
== NULL
) {
438 bp
->mii_bus
->name
= "MACB_mii_bus";
439 bp
->mii_bus
->read
= &macb_mdio_read
;
440 bp
->mii_bus
->write
= &macb_mdio_write
;
441 snprintf(bp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
442 bp
->pdev
->name
, bp
->pdev
->id
);
443 bp
->mii_bus
->priv
= bp
;
444 bp
->mii_bus
->parent
= &bp
->dev
->dev
;
445 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
447 dev_set_drvdata(&bp
->dev
->dev
, bp
->mii_bus
);
449 np
= bp
->pdev
->dev
.of_node
;
451 /* try dt phy registration */
452 err
= of_mdiobus_register(bp
->mii_bus
, np
);
454 /* fallback to standard phy registration if no phy were
455 found during dt phy registration */
456 if (!err
&& !phy_find_first(bp
->mii_bus
)) {
457 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
458 struct phy_device
*phydev
;
460 phydev
= mdiobus_scan(bp
->mii_bus
, i
);
461 if (IS_ERR(phydev
)) {
462 err
= PTR_ERR(phydev
);
468 goto err_out_unregister_bus
;
472 bp
->mii_bus
->phy_mask
= pdata
->phy_mask
;
474 err
= mdiobus_register(bp
->mii_bus
);
478 goto err_out_free_mdiobus
;
480 err
= macb_mii_probe(bp
->dev
);
482 goto err_out_unregister_bus
;
486 err_out_unregister_bus
:
487 mdiobus_unregister(bp
->mii_bus
);
488 err_out_free_mdiobus
:
489 mdiobus_free(bp
->mii_bus
);
494 static void macb_update_stats(struct macb
*bp
)
496 u32
*p
= &bp
->hw_stats
.macb
.rx_pause_frames
;
497 u32
*end
= &bp
->hw_stats
.macb
.tx_pause_frames
+ 1;
498 int offset
= MACB_PFR
;
500 WARN_ON((unsigned long)(end
- p
- 1) != (MACB_TPF
- MACB_PFR
) / 4);
502 for(; p
< end
; p
++, offset
+= 4)
503 *p
+= bp
->macb_reg_readl(bp
, offset
);
506 static int macb_halt_tx(struct macb
*bp
)
508 unsigned long halt_time
, timeout
;
511 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(THALT
));
513 timeout
= jiffies
+ usecs_to_jiffies(MACB_HALT_TIMEOUT
);
516 status
= macb_readl(bp
, TSR
);
517 if (!(status
& MACB_BIT(TGO
)))
520 usleep_range(10, 250);
521 } while (time_before(halt_time
, timeout
));
526 static void macb_tx_unmap(struct macb
*bp
, struct macb_tx_skb
*tx_skb
)
528 if (tx_skb
->mapping
) {
529 if (tx_skb
->mapped_as_page
)
530 dma_unmap_page(&bp
->pdev
->dev
, tx_skb
->mapping
,
531 tx_skb
->size
, DMA_TO_DEVICE
);
533 dma_unmap_single(&bp
->pdev
->dev
, tx_skb
->mapping
,
534 tx_skb
->size
, DMA_TO_DEVICE
);
539 dev_kfree_skb_any(tx_skb
->skb
);
544 static void macb_tx_error_task(struct work_struct
*work
)
546 struct macb_queue
*queue
= container_of(work
, struct macb_queue
,
548 struct macb
*bp
= queue
->bp
;
549 struct macb_tx_skb
*tx_skb
;
550 struct macb_dma_desc
*desc
;
555 netdev_vdbg(bp
->dev
, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
556 (unsigned int)(queue
- bp
->queues
),
557 queue
->tx_tail
, queue
->tx_head
);
559 /* Prevent the queue IRQ handlers from running: each of them may call
560 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
561 * As explained below, we have to halt the transmission before updating
562 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
563 * network engine about the macb/gem being halted.
565 spin_lock_irqsave(&bp
->lock
, flags
);
567 /* Make sure nobody is trying to queue up new packets */
568 netif_tx_stop_all_queues(bp
->dev
);
571 * Stop transmission now
572 * (in case we have just queued new packets)
573 * macb/gem must be halted to write TBQP register
575 if (macb_halt_tx(bp
))
576 /* Just complain for now, reinitializing TX path can be good */
577 netdev_err(bp
->dev
, "BUG: halt tx timed out\n");
580 * Treat frames in TX queue including the ones that caused the error.
581 * Free transmit buffers in upper layer.
583 for (tail
= queue
->tx_tail
; tail
!= queue
->tx_head
; tail
++) {
586 desc
= macb_tx_desc(queue
, tail
);
588 tx_skb
= macb_tx_skb(queue
, tail
);
591 if (ctrl
& MACB_BIT(TX_USED
)) {
592 /* skb is set for the last buffer of the frame */
594 macb_tx_unmap(bp
, tx_skb
);
596 tx_skb
= macb_tx_skb(queue
, tail
);
600 /* ctrl still refers to the first buffer descriptor
601 * since it's the only one written back by the hardware
603 if (!(ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))) {
604 netdev_vdbg(bp
->dev
, "txerr skb %u (data %p) TX complete\n",
605 macb_tx_ring_wrap(tail
), skb
->data
);
606 bp
->stats
.tx_packets
++;
607 bp
->stats
.tx_bytes
+= skb
->len
;
611 * "Buffers exhausted mid-frame" errors may only happen
612 * if the driver is buggy, so complain loudly about those.
613 * Statistics are updated by hardware.
615 if (ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))
617 "BUG: TX buffers exhausted mid-frame\n");
619 desc
->ctrl
= ctrl
| MACB_BIT(TX_USED
);
622 macb_tx_unmap(bp
, tx_skb
);
625 /* Set end of TX queue */
626 desc
= macb_tx_desc(queue
, 0);
628 desc
->ctrl
= MACB_BIT(TX_USED
);
630 /* Make descriptor updates visible to hardware */
633 /* Reinitialize the TX desc queue */
634 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
635 /* Make TX ring reflect state of hardware */
639 /* Housework before enabling TX IRQ */
640 macb_writel(bp
, TSR
, macb_readl(bp
, TSR
));
641 queue_writel(queue
, IER
, MACB_TX_INT_FLAGS
);
643 /* Now we are ready to start transmission again */
644 netif_tx_start_all_queues(bp
->dev
);
645 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
647 spin_unlock_irqrestore(&bp
->lock
, flags
);
650 static void macb_tx_interrupt(struct macb_queue
*queue
)
655 struct macb
*bp
= queue
->bp
;
656 u16 queue_index
= queue
- bp
->queues
;
658 status
= macb_readl(bp
, TSR
);
659 macb_writel(bp
, TSR
, status
);
661 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
662 queue_writel(queue
, ISR
, MACB_BIT(TCOMP
));
664 netdev_vdbg(bp
->dev
, "macb_tx_interrupt status = 0x%03lx\n",
665 (unsigned long)status
);
667 head
= queue
->tx_head
;
668 for (tail
= queue
->tx_tail
; tail
!= head
; tail
++) {
669 struct macb_tx_skb
*tx_skb
;
671 struct macb_dma_desc
*desc
;
674 desc
= macb_tx_desc(queue
, tail
);
676 /* Make hw descriptor updates visible to CPU */
681 /* TX_USED bit is only set by hardware on the very first buffer
682 * descriptor of the transmitted frame.
684 if (!(ctrl
& MACB_BIT(TX_USED
)))
687 /* Process all buffers of the current transmitted frame */
689 tx_skb
= macb_tx_skb(queue
, tail
);
692 /* First, update TX stats if needed */
694 netdev_vdbg(bp
->dev
, "skb %u (data %p) TX complete\n",
695 macb_tx_ring_wrap(tail
), skb
->data
);
696 bp
->stats
.tx_packets
++;
697 bp
->stats
.tx_bytes
+= skb
->len
;
700 /* Now we can safely release resources */
701 macb_tx_unmap(bp
, tx_skb
);
703 /* skb is set only for the last buffer of the frame.
704 * WARNING: at this point skb has been freed by
712 queue
->tx_tail
= tail
;
713 if (__netif_subqueue_stopped(bp
->dev
, queue_index
) &&
714 CIRC_CNT(queue
->tx_head
, queue
->tx_tail
,
715 TX_RING_SIZE
) <= MACB_TX_WAKEUP_THRESH
)
716 netif_wake_subqueue(bp
->dev
, queue_index
);
719 static void gem_rx_refill(struct macb
*bp
)
725 while (CIRC_SPACE(bp
->rx_prepared_head
, bp
->rx_tail
, RX_RING_SIZE
) > 0) {
726 entry
= macb_rx_ring_wrap(bp
->rx_prepared_head
);
728 /* Make hw descriptor updates visible to CPU */
731 bp
->rx_prepared_head
++;
733 if (bp
->rx_skbuff
[entry
] == NULL
) {
734 /* allocate sk_buff for this free entry in ring */
735 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buffer_size
);
736 if (unlikely(skb
== NULL
)) {
738 "Unable to allocate sk_buff\n");
742 /* now fill corresponding descriptor entry */
743 paddr
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
744 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
745 if (dma_mapping_error(&bp
->pdev
->dev
, paddr
)) {
750 bp
->rx_skbuff
[entry
] = skb
;
752 if (entry
== RX_RING_SIZE
- 1)
753 paddr
|= MACB_BIT(RX_WRAP
);
754 bp
->rx_ring
[entry
].addr
= paddr
;
755 bp
->rx_ring
[entry
].ctrl
= 0;
757 /* properly align Ethernet header */
758 skb_reserve(skb
, NET_IP_ALIGN
);
760 bp
->rx_ring
[entry
].addr
&= ~MACB_BIT(RX_USED
);
761 bp
->rx_ring
[entry
].ctrl
= 0;
765 /* Make descriptor updates visible to hardware */
768 netdev_vdbg(bp
->dev
, "rx ring: prepared head %d, tail %d\n",
769 bp
->rx_prepared_head
, bp
->rx_tail
);
772 /* Mark DMA descriptors from begin up to and not including end as unused */
773 static void discard_partial_frame(struct macb
*bp
, unsigned int begin
,
778 for (frag
= begin
; frag
!= end
; frag
++) {
779 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, frag
);
780 desc
->addr
&= ~MACB_BIT(RX_USED
);
783 /* Make descriptor updates visible to hardware */
787 * When this happens, the hardware stats registers for
788 * whatever caused this is updated, so we don't have to record
793 static int gem_rx(struct macb
*bp
, int budget
)
798 struct macb_dma_desc
*desc
;
801 while (count
< budget
) {
804 entry
= macb_rx_ring_wrap(bp
->rx_tail
);
805 desc
= &bp
->rx_ring
[entry
];
807 /* Make hw descriptor updates visible to CPU */
813 if (!(addr
& MACB_BIT(RX_USED
)))
819 if (!(ctrl
& MACB_BIT(RX_SOF
) && ctrl
& MACB_BIT(RX_EOF
))) {
821 "not whole frame pointed by descriptor\n");
822 bp
->stats
.rx_dropped
++;
825 skb
= bp
->rx_skbuff
[entry
];
826 if (unlikely(!skb
)) {
828 "inconsistent Rx descriptor chain\n");
829 bp
->stats
.rx_dropped
++;
832 /* now everything is ready for receiving packet */
833 bp
->rx_skbuff
[entry
] = NULL
;
834 len
= ctrl
& bp
->rx_frm_len_mask
;
836 netdev_vdbg(bp
->dev
, "gem_rx %u (len %u)\n", entry
, len
);
839 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, addr
));
840 dma_unmap_single(&bp
->pdev
->dev
, addr
,
841 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
843 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
844 skb_checksum_none_assert(skb
);
845 if (bp
->dev
->features
& NETIF_F_RXCSUM
&&
846 !(bp
->dev
->flags
& IFF_PROMISC
) &&
847 GEM_BFEXT(RX_CSUM
, ctrl
) & GEM_RX_CSUM_CHECKED_MASK
)
848 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
850 bp
->stats
.rx_packets
++;
851 bp
->stats
.rx_bytes
+= skb
->len
;
853 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
854 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
855 skb
->len
, skb
->csum
);
856 print_hex_dump(KERN_DEBUG
, " mac: ", DUMP_PREFIX_ADDRESS
, 16, 1,
857 skb_mac_header(skb
), 16, true);
858 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_ADDRESS
, 16, 1,
859 skb
->data
, 32, true);
862 netif_receive_skb(skb
);
870 static int macb_rx_frame(struct macb
*bp
, unsigned int first_frag
,
871 unsigned int last_frag
)
877 struct macb_dma_desc
*desc
;
879 desc
= macb_rx_desc(bp
, last_frag
);
880 len
= desc
->ctrl
& bp
->rx_frm_len_mask
;
882 netdev_vdbg(bp
->dev
, "macb_rx_frame frags %u - %u (len %u)\n",
883 macb_rx_ring_wrap(first_frag
),
884 macb_rx_ring_wrap(last_frag
), len
);
887 * The ethernet header starts NET_IP_ALIGN bytes into the
888 * first buffer. Since the header is 14 bytes, this makes the
889 * payload word-aligned.
891 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
892 * the two padding bytes into the skb so that we avoid hitting
893 * the slowpath in memcpy(), and pull them off afterwards.
895 skb
= netdev_alloc_skb(bp
->dev
, len
+ NET_IP_ALIGN
);
897 bp
->stats
.rx_dropped
++;
898 for (frag
= first_frag
; ; frag
++) {
899 desc
= macb_rx_desc(bp
, frag
);
900 desc
->addr
&= ~MACB_BIT(RX_USED
);
901 if (frag
== last_frag
)
905 /* Make descriptor updates visible to hardware */
913 skb_checksum_none_assert(skb
);
916 for (frag
= first_frag
; ; frag
++) {
917 unsigned int frag_len
= bp
->rx_buffer_size
;
919 if (offset
+ frag_len
> len
) {
920 if (unlikely(frag
!= last_frag
)) {
921 dev_kfree_skb_any(skb
);
924 frag_len
= len
- offset
;
926 skb_copy_to_linear_data_offset(skb
, offset
,
927 macb_rx_buffer(bp
, frag
), frag_len
);
928 offset
+= bp
->rx_buffer_size
;
929 desc
= macb_rx_desc(bp
, frag
);
930 desc
->addr
&= ~MACB_BIT(RX_USED
);
932 if (frag
== last_frag
)
936 /* Make descriptor updates visible to hardware */
939 __skb_pull(skb
, NET_IP_ALIGN
);
940 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
942 bp
->stats
.rx_packets
++;
943 bp
->stats
.rx_bytes
+= skb
->len
;
944 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
945 skb
->len
, skb
->csum
);
946 netif_receive_skb(skb
);
951 static inline void macb_init_rx_ring(struct macb
*bp
)
956 addr
= bp
->rx_buffers_dma
;
957 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
958 bp
->rx_ring
[i
].addr
= addr
;
959 bp
->rx_ring
[i
].ctrl
= 0;
960 addr
+= bp
->rx_buffer_size
;
962 bp
->rx_ring
[RX_RING_SIZE
- 1].addr
|= MACB_BIT(RX_WRAP
);
965 static int macb_rx(struct macb
*bp
, int budget
)
967 bool reset_rx_queue
= false;
972 for (tail
= bp
->rx_tail
; budget
> 0; tail
++) {
973 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, tail
);
976 /* Make hw descriptor updates visible to CPU */
982 if (!(addr
& MACB_BIT(RX_USED
)))
985 if (ctrl
& MACB_BIT(RX_SOF
)) {
986 if (first_frag
!= -1)
987 discard_partial_frame(bp
, first_frag
, tail
);
991 if (ctrl
& MACB_BIT(RX_EOF
)) {
994 if (unlikely(first_frag
== -1)) {
995 reset_rx_queue
= true;
999 dropped
= macb_rx_frame(bp
, first_frag
, tail
);
1001 if (unlikely(dropped
< 0)) {
1002 reset_rx_queue
= true;
1012 if (unlikely(reset_rx_queue
)) {
1013 unsigned long flags
;
1016 netdev_err(bp
->dev
, "RX queue corruption: reset it\n");
1018 spin_lock_irqsave(&bp
->lock
, flags
);
1020 ctrl
= macb_readl(bp
, NCR
);
1021 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1023 macb_init_rx_ring(bp
);
1024 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1026 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1028 spin_unlock_irqrestore(&bp
->lock
, flags
);
1032 if (first_frag
!= -1)
1033 bp
->rx_tail
= first_frag
;
1040 static int macb_poll(struct napi_struct
*napi
, int budget
)
1042 struct macb
*bp
= container_of(napi
, struct macb
, napi
);
1046 status
= macb_readl(bp
, RSR
);
1047 macb_writel(bp
, RSR
, status
);
1051 netdev_vdbg(bp
->dev
, "poll: status = %08lx, budget = %d\n",
1052 (unsigned long)status
, budget
);
1054 work_done
= bp
->macbgem_ops
.mog_rx(bp
, budget
);
1055 if (work_done
< budget
) {
1056 napi_complete(napi
);
1058 /* Packets received while interrupts were disabled */
1059 status
= macb_readl(bp
, RSR
);
1061 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1062 macb_writel(bp
, ISR
, MACB_BIT(RCOMP
));
1063 napi_reschedule(napi
);
1065 macb_writel(bp
, IER
, MACB_RX_INT_FLAGS
);
1069 /* TODO: Handle errors */
1074 static irqreturn_t
macb_interrupt(int irq
, void *dev_id
)
1076 struct macb_queue
*queue
= dev_id
;
1077 struct macb
*bp
= queue
->bp
;
1078 struct net_device
*dev
= bp
->dev
;
1081 status
= queue_readl(queue
, ISR
);
1083 if (unlikely(!status
))
1086 spin_lock(&bp
->lock
);
1089 /* close possible race with dev_close */
1090 if (unlikely(!netif_running(dev
))) {
1091 queue_writel(queue
, IDR
, -1);
1092 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1093 queue_writel(queue
, ISR
, -1);
1097 netdev_vdbg(bp
->dev
, "queue = %u, isr = 0x%08lx\n",
1098 (unsigned int)(queue
- bp
->queues
),
1099 (unsigned long)status
);
1101 if (status
& MACB_RX_INT_FLAGS
) {
1103 * There's no point taking any more interrupts
1104 * until we have processed the buffers. The
1105 * scheduling call may fail if the poll routine
1106 * is already scheduled, so disable interrupts
1109 queue_writel(queue
, IDR
, MACB_RX_INT_FLAGS
);
1110 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1111 queue_writel(queue
, ISR
, MACB_BIT(RCOMP
));
1113 if (napi_schedule_prep(&bp
->napi
)) {
1114 netdev_vdbg(bp
->dev
, "scheduling RX softirq\n");
1115 __napi_schedule(&bp
->napi
);
1119 if (unlikely(status
& (MACB_TX_ERR_FLAGS
))) {
1120 queue_writel(queue
, IDR
, MACB_TX_INT_FLAGS
);
1121 schedule_work(&queue
->tx_error_task
);
1123 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1124 queue_writel(queue
, ISR
, MACB_TX_ERR_FLAGS
);
1129 if (status
& MACB_BIT(TCOMP
))
1130 macb_tx_interrupt(queue
);
1133 * Link change detection isn't possible with RMII, so we'll
1134 * add that if/when we get our hands on a full-blown MII PHY.
1137 /* There is a hardware issue under heavy load where DMA can
1138 * stop, this causes endless "used buffer descriptor read"
1139 * interrupts but it can be cleared by re-enabling RX. See
1140 * the at91 manual, section 41.3.1 or the Zynq manual
1141 * section 16.7.4 for details.
1143 if (status
& MACB_BIT(RXUBR
)) {
1144 ctrl
= macb_readl(bp
, NCR
);
1145 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1146 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1148 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1149 queue_writel(queue
, ISR
, MACB_BIT(RXUBR
));
1152 if (status
& MACB_BIT(ISR_ROVR
)) {
1153 /* We missed at least one packet */
1154 if (macb_is_gem(bp
))
1155 bp
->hw_stats
.gem
.rx_overruns
++;
1157 bp
->hw_stats
.macb
.rx_overruns
++;
1159 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1160 queue_writel(queue
, ISR
, MACB_BIT(ISR_ROVR
));
1163 if (status
& MACB_BIT(HRESP
)) {
1165 * TODO: Reset the hardware, and maybe move the
1166 * netdev_err to a lower-priority context as well
1169 netdev_err(dev
, "DMA bus error: HRESP not OK\n");
1171 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1172 queue_writel(queue
, ISR
, MACB_BIT(HRESP
));
1175 status
= queue_readl(queue
, ISR
);
1178 spin_unlock(&bp
->lock
);
1183 #ifdef CONFIG_NET_POLL_CONTROLLER
1185 * Polling receive - used by netconsole and other diagnostic tools
1186 * to allow network i/o with interrupts disabled.
1188 static void macb_poll_controller(struct net_device
*dev
)
1190 struct macb
*bp
= netdev_priv(dev
);
1191 struct macb_queue
*queue
;
1192 unsigned long flags
;
1195 local_irq_save(flags
);
1196 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
)
1197 macb_interrupt(dev
->irq
, queue
);
1198 local_irq_restore(flags
);
1202 static unsigned int macb_tx_map(struct macb
*bp
,
1203 struct macb_queue
*queue
,
1204 struct sk_buff
*skb
)
1207 unsigned int len
, entry
, i
, tx_head
= queue
->tx_head
;
1208 struct macb_tx_skb
*tx_skb
= NULL
;
1209 struct macb_dma_desc
*desc
;
1210 unsigned int offset
, size
, count
= 0;
1211 unsigned int f
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1212 unsigned int eof
= 1;
1215 /* First, map non-paged data */
1216 len
= skb_headlen(skb
);
1219 size
= min(len
, bp
->max_tx_length
);
1220 entry
= macb_tx_ring_wrap(tx_head
);
1221 tx_skb
= &queue
->tx_skb
[entry
];
1223 mapping
= dma_map_single(&bp
->pdev
->dev
,
1225 size
, DMA_TO_DEVICE
);
1226 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1229 /* Save info to properly release resources */
1231 tx_skb
->mapping
= mapping
;
1232 tx_skb
->size
= size
;
1233 tx_skb
->mapped_as_page
= false;
1241 /* Then, map paged data from fragments */
1242 for (f
= 0; f
< nr_frags
; f
++) {
1243 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[f
];
1245 len
= skb_frag_size(frag
);
1248 size
= min(len
, bp
->max_tx_length
);
1249 entry
= macb_tx_ring_wrap(tx_head
);
1250 tx_skb
= &queue
->tx_skb
[entry
];
1252 mapping
= skb_frag_dma_map(&bp
->pdev
->dev
, frag
,
1253 offset
, size
, DMA_TO_DEVICE
);
1254 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1257 /* Save info to properly release resources */
1259 tx_skb
->mapping
= mapping
;
1260 tx_skb
->size
= size
;
1261 tx_skb
->mapped_as_page
= true;
1270 /* Should never happen */
1271 if (unlikely(tx_skb
== NULL
)) {
1272 netdev_err(bp
->dev
, "BUG! empty skb!\n");
1276 /* This is the last buffer of the frame: save socket buffer */
1279 /* Update TX ring: update buffer descriptors in reverse order
1280 * to avoid race condition
1283 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1284 * to set the end of TX queue
1287 entry
= macb_tx_ring_wrap(i
);
1288 ctrl
= MACB_BIT(TX_USED
);
1289 desc
= &queue
->tx_ring
[entry
];
1294 entry
= macb_tx_ring_wrap(i
);
1295 tx_skb
= &queue
->tx_skb
[entry
];
1296 desc
= &queue
->tx_ring
[entry
];
1298 ctrl
= (u32
)tx_skb
->size
;
1300 ctrl
|= MACB_BIT(TX_LAST
);
1303 if (unlikely(entry
== (TX_RING_SIZE
- 1)))
1304 ctrl
|= MACB_BIT(TX_WRAP
);
1306 /* Set TX buffer descriptor */
1307 desc
->addr
= tx_skb
->mapping
;
1308 /* desc->addr must be visible to hardware before clearing
1309 * 'TX_USED' bit in desc->ctrl.
1313 } while (i
!= queue
->tx_head
);
1315 queue
->tx_head
= tx_head
;
1320 netdev_err(bp
->dev
, "TX DMA map failed\n");
1322 for (i
= queue
->tx_head
; i
!= tx_head
; i
++) {
1323 tx_skb
= macb_tx_skb(queue
, i
);
1325 macb_tx_unmap(bp
, tx_skb
);
1331 static int macb_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1333 u16 queue_index
= skb_get_queue_mapping(skb
);
1334 struct macb
*bp
= netdev_priv(dev
);
1335 struct macb_queue
*queue
= &bp
->queues
[queue_index
];
1336 unsigned long flags
;
1337 unsigned int count
, nr_frags
, frag_size
, f
;
1339 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1340 netdev_vdbg(bp
->dev
,
1341 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1342 queue_index
, skb
->len
, skb
->head
, skb
->data
,
1343 skb_tail_pointer(skb
), skb_end_pointer(skb
));
1344 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_OFFSET
, 16, 1,
1345 skb
->data
, 16, true);
1348 /* Count how many TX buffer descriptors are needed to send this
1349 * socket buffer: skb fragments of jumbo frames may need to be
1350 * splitted into many buffer descriptors.
1352 count
= DIV_ROUND_UP(skb_headlen(skb
), bp
->max_tx_length
);
1353 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1354 for (f
= 0; f
< nr_frags
; f
++) {
1355 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[f
]);
1356 count
+= DIV_ROUND_UP(frag_size
, bp
->max_tx_length
);
1359 spin_lock_irqsave(&bp
->lock
, flags
);
1361 /* This is a hard error, log it. */
1362 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < count
) {
1363 netif_stop_subqueue(dev
, queue_index
);
1364 spin_unlock_irqrestore(&bp
->lock
, flags
);
1365 netdev_dbg(bp
->dev
, "tx_head = %u, tx_tail = %u\n",
1366 queue
->tx_head
, queue
->tx_tail
);
1367 return NETDEV_TX_BUSY
;
1370 /* Map socket buffer for DMA transfer */
1371 if (!macb_tx_map(bp
, queue
, skb
)) {
1372 dev_kfree_skb_any(skb
);
1376 /* Make newly initialized descriptor visible to hardware */
1379 skb_tx_timestamp(skb
);
1381 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
1383 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < 1)
1384 netif_stop_subqueue(dev
, queue_index
);
1387 spin_unlock_irqrestore(&bp
->lock
, flags
);
1389 return NETDEV_TX_OK
;
1392 static void macb_init_rx_buffer_size(struct macb
*bp
, size_t size
)
1394 if (!macb_is_gem(bp
)) {
1395 bp
->rx_buffer_size
= MACB_RX_BUFFER_SIZE
;
1397 bp
->rx_buffer_size
= size
;
1399 if (bp
->rx_buffer_size
% RX_BUFFER_MULTIPLE
) {
1401 "RX buffer must be multiple of %d bytes, expanding\n",
1402 RX_BUFFER_MULTIPLE
);
1403 bp
->rx_buffer_size
=
1404 roundup(bp
->rx_buffer_size
, RX_BUFFER_MULTIPLE
);
1408 netdev_dbg(bp
->dev
, "mtu [%u] rx_buffer_size [%Zu]\n",
1409 bp
->dev
->mtu
, bp
->rx_buffer_size
);
1412 static void gem_free_rx_buffers(struct macb
*bp
)
1414 struct sk_buff
*skb
;
1415 struct macb_dma_desc
*desc
;
1422 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1423 skb
= bp
->rx_skbuff
[i
];
1428 desc
= &bp
->rx_ring
[i
];
1429 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, desc
->addr
));
1430 dma_unmap_single(&bp
->pdev
->dev
, addr
, bp
->rx_buffer_size
,
1432 dev_kfree_skb_any(skb
);
1436 kfree(bp
->rx_skbuff
);
1437 bp
->rx_skbuff
= NULL
;
1440 static void macb_free_rx_buffers(struct macb
*bp
)
1442 if (bp
->rx_buffers
) {
1443 dma_free_coherent(&bp
->pdev
->dev
,
1444 RX_RING_SIZE
* bp
->rx_buffer_size
,
1445 bp
->rx_buffers
, bp
->rx_buffers_dma
);
1446 bp
->rx_buffers
= NULL
;
1450 static void macb_free_consistent(struct macb
*bp
)
1452 struct macb_queue
*queue
;
1455 bp
->macbgem_ops
.mog_free_rx_buffers(bp
);
1457 dma_free_coherent(&bp
->pdev
->dev
, RX_RING_BYTES
,
1458 bp
->rx_ring
, bp
->rx_ring_dma
);
1462 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1463 kfree(queue
->tx_skb
);
1464 queue
->tx_skb
= NULL
;
1465 if (queue
->tx_ring
) {
1466 dma_free_coherent(&bp
->pdev
->dev
, TX_RING_BYTES
,
1467 queue
->tx_ring
, queue
->tx_ring_dma
);
1468 queue
->tx_ring
= NULL
;
1473 static int gem_alloc_rx_buffers(struct macb
*bp
)
1477 size
= RX_RING_SIZE
* sizeof(struct sk_buff
*);
1478 bp
->rx_skbuff
= kzalloc(size
, GFP_KERNEL
);
1483 "Allocated %d RX struct sk_buff entries at %p\n",
1484 RX_RING_SIZE
, bp
->rx_skbuff
);
1488 static int macb_alloc_rx_buffers(struct macb
*bp
)
1492 size
= RX_RING_SIZE
* bp
->rx_buffer_size
;
1493 bp
->rx_buffers
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1494 &bp
->rx_buffers_dma
, GFP_KERNEL
);
1495 if (!bp
->rx_buffers
)
1499 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1500 size
, (unsigned long)bp
->rx_buffers_dma
, bp
->rx_buffers
);
1504 static int macb_alloc_consistent(struct macb
*bp
)
1506 struct macb_queue
*queue
;
1510 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1511 size
= TX_RING_BYTES
;
1512 queue
->tx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1513 &queue
->tx_ring_dma
,
1515 if (!queue
->tx_ring
)
1518 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1519 q
, size
, (unsigned long)queue
->tx_ring_dma
,
1522 size
= TX_RING_SIZE
* sizeof(struct macb_tx_skb
);
1523 queue
->tx_skb
= kmalloc(size
, GFP_KERNEL
);
1528 size
= RX_RING_BYTES
;
1529 bp
->rx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1530 &bp
->rx_ring_dma
, GFP_KERNEL
);
1534 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1535 size
, (unsigned long)bp
->rx_ring_dma
, bp
->rx_ring
);
1537 if (bp
->macbgem_ops
.mog_alloc_rx_buffers(bp
))
1543 macb_free_consistent(bp
);
1547 static void gem_init_rings(struct macb
*bp
)
1549 struct macb_queue
*queue
;
1553 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1554 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1555 queue
->tx_ring
[i
].addr
= 0;
1556 queue
->tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1558 queue
->tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1564 bp
->rx_prepared_head
= 0;
1569 static void macb_init_rings(struct macb
*bp
)
1573 macb_init_rx_ring(bp
);
1575 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1576 bp
->queues
[0].tx_ring
[i
].addr
= 0;
1577 bp
->queues
[0].tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1579 bp
->queues
[0].tx_head
= 0;
1580 bp
->queues
[0].tx_tail
= 0;
1581 bp
->queues
[0].tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1586 static void macb_reset_hw(struct macb
*bp
)
1588 struct macb_queue
*queue
;
1592 * Disable RX and TX (XXX: Should we halt the transmission
1595 macb_writel(bp
, NCR
, 0);
1597 /* Clear the stats registers (XXX: Update stats first?) */
1598 macb_writel(bp
, NCR
, MACB_BIT(CLRSTAT
));
1600 /* Clear all status flags */
1601 macb_writel(bp
, TSR
, -1);
1602 macb_writel(bp
, RSR
, -1);
1604 /* Disable all interrupts */
1605 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1606 queue_writel(queue
, IDR
, -1);
1607 queue_readl(queue
, ISR
);
1608 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1609 queue_writel(queue
, ISR
, -1);
1613 static u32
gem_mdc_clk_div(struct macb
*bp
)
1616 unsigned long pclk_hz
= clk_get_rate(bp
->pclk
);
1618 if (pclk_hz
<= 20000000)
1619 config
= GEM_BF(CLK
, GEM_CLK_DIV8
);
1620 else if (pclk_hz
<= 40000000)
1621 config
= GEM_BF(CLK
, GEM_CLK_DIV16
);
1622 else if (pclk_hz
<= 80000000)
1623 config
= GEM_BF(CLK
, GEM_CLK_DIV32
);
1624 else if (pclk_hz
<= 120000000)
1625 config
= GEM_BF(CLK
, GEM_CLK_DIV48
);
1626 else if (pclk_hz
<= 160000000)
1627 config
= GEM_BF(CLK
, GEM_CLK_DIV64
);
1629 config
= GEM_BF(CLK
, GEM_CLK_DIV96
);
1634 static u32
macb_mdc_clk_div(struct macb
*bp
)
1637 unsigned long pclk_hz
;
1639 if (macb_is_gem(bp
))
1640 return gem_mdc_clk_div(bp
);
1642 pclk_hz
= clk_get_rate(bp
->pclk
);
1643 if (pclk_hz
<= 20000000)
1644 config
= MACB_BF(CLK
, MACB_CLK_DIV8
);
1645 else if (pclk_hz
<= 40000000)
1646 config
= MACB_BF(CLK
, MACB_CLK_DIV16
);
1647 else if (pclk_hz
<= 80000000)
1648 config
= MACB_BF(CLK
, MACB_CLK_DIV32
);
1650 config
= MACB_BF(CLK
, MACB_CLK_DIV64
);
1656 * Get the DMA bus width field of the network configuration register that we
1657 * should program. We find the width from decoding the design configuration
1658 * register to find the maximum supported data bus width.
1660 static u32
macb_dbw(struct macb
*bp
)
1662 if (!macb_is_gem(bp
))
1665 switch (GEM_BFEXT(DBWDEF
, gem_readl(bp
, DCFG1
))) {
1667 return GEM_BF(DBW
, GEM_DBW128
);
1669 return GEM_BF(DBW
, GEM_DBW64
);
1672 return GEM_BF(DBW
, GEM_DBW32
);
1677 * Configure the receive DMA engine
1678 * - use the correct receive buffer size
1679 * - set best burst length for DMA operations
1680 * (if not supported by FIFO, it will fallback to default)
1681 * - set both rx/tx packet buffers to full memory size
1682 * These are configurable parameters for GEM.
1684 static void macb_configure_dma(struct macb
*bp
)
1688 if (macb_is_gem(bp
)) {
1689 dmacfg
= gem_readl(bp
, DMACFG
) & ~GEM_BF(RXBS
, -1L);
1690 dmacfg
|= GEM_BF(RXBS
, bp
->rx_buffer_size
/ RX_BUFFER_MULTIPLE
);
1691 if (bp
->dma_burst_length
)
1692 dmacfg
= GEM_BFINS(FBLDO
, bp
->dma_burst_length
, dmacfg
);
1693 dmacfg
|= GEM_BIT(TXPBMS
) | GEM_BF(RXBMS
, -1L);
1694 dmacfg
&= ~GEM_BIT(ENDIA_PKT
);
1697 dmacfg
&= ~GEM_BIT(ENDIA_DESC
);
1699 dmacfg
|= GEM_BIT(ENDIA_DESC
); /* CPU in big endian */
1701 if (bp
->dev
->features
& NETIF_F_HW_CSUM
)
1702 dmacfg
|= GEM_BIT(TXCOEN
);
1704 dmacfg
&= ~GEM_BIT(TXCOEN
);
1705 netdev_dbg(bp
->dev
, "Cadence configure DMA with 0x%08x\n",
1707 gem_writel(bp
, DMACFG
, dmacfg
);
1711 static void macb_init_hw(struct macb
*bp
)
1713 struct macb_queue
*queue
;
1719 macb_set_hwaddr(bp
);
1721 config
= macb_mdc_clk_div(bp
);
1722 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
1723 config
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
1724 config
|= MACB_BF(RBOF
, NET_IP_ALIGN
); /* Make eth data aligned */
1725 config
|= MACB_BIT(PAE
); /* PAuse Enable */
1726 config
|= MACB_BIT(DRFCS
); /* Discard Rx FCS */
1727 if (bp
->caps
& MACB_CAPS_JUMBO
)
1728 config
|= MACB_BIT(JFRAME
); /* Enable jumbo frames */
1730 config
|= MACB_BIT(BIG
); /* Receive oversized frames */
1731 if (bp
->dev
->flags
& IFF_PROMISC
)
1732 config
|= MACB_BIT(CAF
); /* Copy All Frames */
1733 else if (macb_is_gem(bp
) && bp
->dev
->features
& NETIF_F_RXCSUM
)
1734 config
|= GEM_BIT(RXCOEN
);
1735 if (!(bp
->dev
->flags
& IFF_BROADCAST
))
1736 config
|= MACB_BIT(NBC
); /* No BroadCast */
1737 config
|= macb_dbw(bp
);
1738 macb_writel(bp
, NCFGR
, config
);
1739 if ((bp
->caps
& MACB_CAPS_JUMBO
) && bp
->jumbo_max_len
)
1740 gem_writel(bp
, JML
, bp
->jumbo_max_len
);
1741 bp
->speed
= SPEED_10
;
1742 bp
->duplex
= DUPLEX_HALF
;
1743 bp
->rx_frm_len_mask
= MACB_RX_FRMLEN_MASK
;
1744 if (bp
->caps
& MACB_CAPS_JUMBO
)
1745 bp
->rx_frm_len_mask
= MACB_RX_JFRMLEN_MASK
;
1747 macb_configure_dma(bp
);
1749 /* Initialize TX and RX buffers */
1750 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1751 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1752 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
1754 /* Enable interrupts */
1755 queue_writel(queue
, IER
,
1761 /* Enable TX and RX */
1762 macb_writel(bp
, NCR
, MACB_BIT(RE
) | MACB_BIT(TE
) | MACB_BIT(MPE
));
1766 * The hash address register is 64 bits long and takes up two
1767 * locations in the memory map. The least significant bits are stored
1768 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1770 * The unicast hash enable and the multicast hash enable bits in the
1771 * network configuration register enable the reception of hash matched
1772 * frames. The destination address is reduced to a 6 bit index into
1773 * the 64 bit hash register using the following hash function. The
1774 * hash function is an exclusive or of every sixth bit of the
1775 * destination address.
1777 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1778 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1779 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1780 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1781 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1782 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1784 * da[0] represents the least significant bit of the first byte
1785 * received, that is, the multicast/unicast indicator, and da[47]
1786 * represents the most significant bit of the last byte received. If
1787 * the hash index, hi[n], points to a bit that is set in the hash
1788 * register then the frame will be matched according to whether the
1789 * frame is multicast or unicast. A multicast match will be signalled
1790 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1791 * index points to a bit set in the hash register. A unicast match
1792 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1793 * and the hash index points to a bit set in the hash register. To
1794 * receive all multicast frames, the hash register should be set with
1795 * all ones and the multicast hash enable bit should be set in the
1796 * network configuration register.
1799 static inline int hash_bit_value(int bitnr
, __u8
*addr
)
1801 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
1807 * Return the hash index value for the specified address.
1809 static int hash_get_index(__u8
*addr
)
1814 for (j
= 0; j
< 6; j
++) {
1815 for (i
= 0, bitval
= 0; i
< 8; i
++)
1816 bitval
^= hash_bit_value(i
* 6 + j
, addr
);
1818 hash_index
|= (bitval
<< j
);
1825 * Add multicast addresses to the internal multicast-hash table.
1827 static void macb_sethashtable(struct net_device
*dev
)
1829 struct netdev_hw_addr
*ha
;
1830 unsigned long mc_filter
[2];
1832 struct macb
*bp
= netdev_priv(dev
);
1834 mc_filter
[0] = mc_filter
[1] = 0;
1836 netdev_for_each_mc_addr(ha
, dev
) {
1837 bitnr
= hash_get_index(ha
->addr
);
1838 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
1841 macb_or_gem_writel(bp
, HRB
, mc_filter
[0]);
1842 macb_or_gem_writel(bp
, HRT
, mc_filter
[1]);
1846 * Enable/Disable promiscuous and multicast modes.
1848 static void macb_set_rx_mode(struct net_device
*dev
)
1851 struct macb
*bp
= netdev_priv(dev
);
1853 cfg
= macb_readl(bp
, NCFGR
);
1855 if (dev
->flags
& IFF_PROMISC
) {
1856 /* Enable promiscuous mode */
1857 cfg
|= MACB_BIT(CAF
);
1859 /* Disable RX checksum offload */
1860 if (macb_is_gem(bp
))
1861 cfg
&= ~GEM_BIT(RXCOEN
);
1863 /* Disable promiscuous mode */
1864 cfg
&= ~MACB_BIT(CAF
);
1866 /* Enable RX checksum offload only if requested */
1867 if (macb_is_gem(bp
) && dev
->features
& NETIF_F_RXCSUM
)
1868 cfg
|= GEM_BIT(RXCOEN
);
1871 if (dev
->flags
& IFF_ALLMULTI
) {
1872 /* Enable all multicast mode */
1873 macb_or_gem_writel(bp
, HRB
, -1);
1874 macb_or_gem_writel(bp
, HRT
, -1);
1875 cfg
|= MACB_BIT(NCFGR_MTI
);
1876 } else if (!netdev_mc_empty(dev
)) {
1877 /* Enable specific multicasts */
1878 macb_sethashtable(dev
);
1879 cfg
|= MACB_BIT(NCFGR_MTI
);
1880 } else if (dev
->flags
& (~IFF_ALLMULTI
)) {
1881 /* Disable all multicast mode */
1882 macb_or_gem_writel(bp
, HRB
, 0);
1883 macb_or_gem_writel(bp
, HRT
, 0);
1884 cfg
&= ~MACB_BIT(NCFGR_MTI
);
1887 macb_writel(bp
, NCFGR
, cfg
);
1890 static int macb_open(struct net_device
*dev
)
1892 struct macb
*bp
= netdev_priv(dev
);
1893 size_t bufsz
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ NET_IP_ALIGN
;
1896 netdev_dbg(bp
->dev
, "open\n");
1898 /* carrier starts down */
1899 netif_carrier_off(dev
);
1901 /* if the phy is not yet register, retry later*/
1905 /* RX buffers initialization */
1906 macb_init_rx_buffer_size(bp
, bufsz
);
1908 err
= macb_alloc_consistent(bp
);
1910 netdev_err(dev
, "Unable to allocate DMA memory (error %d)\n",
1915 napi_enable(&bp
->napi
);
1917 bp
->macbgem_ops
.mog_init_rings(bp
);
1920 /* schedule a link state check */
1921 phy_start(bp
->phy_dev
);
1923 netif_tx_start_all_queues(dev
);
1928 static int macb_close(struct net_device
*dev
)
1930 struct macb
*bp
= netdev_priv(dev
);
1931 unsigned long flags
;
1933 netif_tx_stop_all_queues(dev
);
1934 napi_disable(&bp
->napi
);
1937 phy_stop(bp
->phy_dev
);
1939 spin_lock_irqsave(&bp
->lock
, flags
);
1941 netif_carrier_off(dev
);
1942 spin_unlock_irqrestore(&bp
->lock
, flags
);
1944 macb_free_consistent(bp
);
1949 static int macb_change_mtu(struct net_device
*dev
, int new_mtu
)
1951 struct macb
*bp
= netdev_priv(dev
);
1954 if (netif_running(dev
))
1957 max_mtu
= ETH_DATA_LEN
;
1958 if (bp
->caps
& MACB_CAPS_JUMBO
)
1959 max_mtu
= gem_readl(bp
, JML
) - ETH_HLEN
- ETH_FCS_LEN
;
1961 if ((new_mtu
> max_mtu
) || (new_mtu
< GEM_MTU_MIN_SIZE
))
1969 static void gem_update_stats(struct macb
*bp
)
1972 u32
*p
= &bp
->hw_stats
.gem
.tx_octets_31_0
;
1974 for (i
= 0; i
< GEM_STATS_LEN
; ++i
, ++p
) {
1975 u32 offset
= gem_statistics
[i
].offset
;
1976 u64 val
= bp
->macb_reg_readl(bp
, offset
);
1978 bp
->ethtool_stats
[i
] += val
;
1981 if (offset
== GEM_OCTTXL
|| offset
== GEM_OCTRXL
) {
1982 /* Add GEM_OCTTXH, GEM_OCTRXH */
1983 val
= bp
->macb_reg_readl(bp
, offset
+ 4);
1984 bp
->ethtool_stats
[i
] += ((u64
)val
) << 32;
1990 static struct net_device_stats
*gem_get_stats(struct macb
*bp
)
1992 struct gem_stats
*hwstat
= &bp
->hw_stats
.gem
;
1993 struct net_device_stats
*nstat
= &bp
->stats
;
1995 gem_update_stats(bp
);
1997 nstat
->rx_errors
= (hwstat
->rx_frame_check_sequence_errors
+
1998 hwstat
->rx_alignment_errors
+
1999 hwstat
->rx_resource_errors
+
2000 hwstat
->rx_overruns
+
2001 hwstat
->rx_oversize_frames
+
2002 hwstat
->rx_jabbers
+
2003 hwstat
->rx_undersized_frames
+
2004 hwstat
->rx_length_field_frame_errors
);
2005 nstat
->tx_errors
= (hwstat
->tx_late_collisions
+
2006 hwstat
->tx_excessive_collisions
+
2007 hwstat
->tx_underrun
+
2008 hwstat
->tx_carrier_sense_errors
);
2009 nstat
->multicast
= hwstat
->rx_multicast_frames
;
2010 nstat
->collisions
= (hwstat
->tx_single_collision_frames
+
2011 hwstat
->tx_multiple_collision_frames
+
2012 hwstat
->tx_excessive_collisions
);
2013 nstat
->rx_length_errors
= (hwstat
->rx_oversize_frames
+
2014 hwstat
->rx_jabbers
+
2015 hwstat
->rx_undersized_frames
+
2016 hwstat
->rx_length_field_frame_errors
);
2017 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
;
2018 nstat
->rx_crc_errors
= hwstat
->rx_frame_check_sequence_errors
;
2019 nstat
->rx_frame_errors
= hwstat
->rx_alignment_errors
;
2020 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2021 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_collisions
;
2022 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_sense_errors
;
2023 nstat
->tx_fifo_errors
= hwstat
->tx_underrun
;
2028 static void gem_get_ethtool_stats(struct net_device
*dev
,
2029 struct ethtool_stats
*stats
, u64
*data
)
2033 bp
= netdev_priv(dev
);
2034 gem_update_stats(bp
);
2035 memcpy(data
, &bp
->ethtool_stats
, sizeof(u64
) * GEM_STATS_LEN
);
2038 static int gem_get_sset_count(struct net_device
*dev
, int sset
)
2042 return GEM_STATS_LEN
;
2048 static void gem_get_ethtool_strings(struct net_device
*dev
, u32 sset
, u8
*p
)
2054 for (i
= 0; i
< GEM_STATS_LEN
; i
++, p
+= ETH_GSTRING_LEN
)
2055 memcpy(p
, gem_statistics
[i
].stat_string
,
2061 static struct net_device_stats
*macb_get_stats(struct net_device
*dev
)
2063 struct macb
*bp
= netdev_priv(dev
);
2064 struct net_device_stats
*nstat
= &bp
->stats
;
2065 struct macb_stats
*hwstat
= &bp
->hw_stats
.macb
;
2067 if (macb_is_gem(bp
))
2068 return gem_get_stats(bp
);
2070 /* read stats from hardware */
2071 macb_update_stats(bp
);
2073 /* Convert HW stats into netdevice stats */
2074 nstat
->rx_errors
= (hwstat
->rx_fcs_errors
+
2075 hwstat
->rx_align_errors
+
2076 hwstat
->rx_resource_errors
+
2077 hwstat
->rx_overruns
+
2078 hwstat
->rx_oversize_pkts
+
2079 hwstat
->rx_jabbers
+
2080 hwstat
->rx_undersize_pkts
+
2081 hwstat
->rx_length_mismatch
);
2082 nstat
->tx_errors
= (hwstat
->tx_late_cols
+
2083 hwstat
->tx_excessive_cols
+
2084 hwstat
->tx_underruns
+
2085 hwstat
->tx_carrier_errors
+
2086 hwstat
->sqe_test_errors
);
2087 nstat
->collisions
= (hwstat
->tx_single_cols
+
2088 hwstat
->tx_multiple_cols
+
2089 hwstat
->tx_excessive_cols
);
2090 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
2091 hwstat
->rx_jabbers
+
2092 hwstat
->rx_undersize_pkts
+
2093 hwstat
->rx_length_mismatch
);
2094 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
+
2095 hwstat
->rx_overruns
;
2096 nstat
->rx_crc_errors
= hwstat
->rx_fcs_errors
;
2097 nstat
->rx_frame_errors
= hwstat
->rx_align_errors
;
2098 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2099 /* XXX: What does "missed" mean? */
2100 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_cols
;
2101 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_errors
;
2102 nstat
->tx_fifo_errors
= hwstat
->tx_underruns
;
2103 /* Don't know about heartbeat or window errors... */
2108 static int macb_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2110 struct macb
*bp
= netdev_priv(dev
);
2111 struct phy_device
*phydev
= bp
->phy_dev
;
2116 return phy_ethtool_gset(phydev
, cmd
);
2119 static int macb_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2121 struct macb
*bp
= netdev_priv(dev
);
2122 struct phy_device
*phydev
= bp
->phy_dev
;
2127 return phy_ethtool_sset(phydev
, cmd
);
2130 static int macb_get_regs_len(struct net_device
*netdev
)
2132 return MACB_GREGS_NBR
* sizeof(u32
);
2135 static void macb_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2138 struct macb
*bp
= netdev_priv(dev
);
2139 unsigned int tail
, head
;
2142 regs
->version
= (macb_readl(bp
, MID
) & ((1 << MACB_REV_SIZE
) - 1))
2143 | MACB_GREGS_VERSION
;
2145 tail
= macb_tx_ring_wrap(bp
->queues
[0].tx_tail
);
2146 head
= macb_tx_ring_wrap(bp
->queues
[0].tx_head
);
2148 regs_buff
[0] = macb_readl(bp
, NCR
);
2149 regs_buff
[1] = macb_or_gem_readl(bp
, NCFGR
);
2150 regs_buff
[2] = macb_readl(bp
, NSR
);
2151 regs_buff
[3] = macb_readl(bp
, TSR
);
2152 regs_buff
[4] = macb_readl(bp
, RBQP
);
2153 regs_buff
[5] = macb_readl(bp
, TBQP
);
2154 regs_buff
[6] = macb_readl(bp
, RSR
);
2155 regs_buff
[7] = macb_readl(bp
, IMR
);
2157 regs_buff
[8] = tail
;
2158 regs_buff
[9] = head
;
2159 regs_buff
[10] = macb_tx_dma(&bp
->queues
[0], tail
);
2160 regs_buff
[11] = macb_tx_dma(&bp
->queues
[0], head
);
2162 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
))
2163 regs_buff
[12] = macb_or_gem_readl(bp
, USRIO
);
2164 if (macb_is_gem(bp
)) {
2165 regs_buff
[13] = gem_readl(bp
, DMACFG
);
2169 static void macb_get_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2171 struct macb
*bp
= netdev_priv(netdev
);
2176 if (bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) {
2177 wol
->supported
= WAKE_MAGIC
;
2179 if (bp
->wol
& MACB_WOL_ENABLED
)
2180 wol
->wolopts
|= WAKE_MAGIC
;
2184 static int macb_set_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2186 struct macb
*bp
= netdev_priv(netdev
);
2188 if (!(bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) ||
2189 (wol
->wolopts
& ~WAKE_MAGIC
))
2192 if (wol
->wolopts
& WAKE_MAGIC
)
2193 bp
->wol
|= MACB_WOL_ENABLED
;
2195 bp
->wol
&= ~MACB_WOL_ENABLED
;
2197 device_set_wakeup_enable(&bp
->pdev
->dev
, bp
->wol
& MACB_WOL_ENABLED
);
2202 static const struct ethtool_ops macb_ethtool_ops
= {
2203 .get_settings
= macb_get_settings
,
2204 .set_settings
= macb_set_settings
,
2205 .get_regs_len
= macb_get_regs_len
,
2206 .get_regs
= macb_get_regs
,
2207 .get_link
= ethtool_op_get_link
,
2208 .get_ts_info
= ethtool_op_get_ts_info
,
2209 .get_wol
= macb_get_wol
,
2210 .set_wol
= macb_set_wol
,
2213 static const struct ethtool_ops gem_ethtool_ops
= {
2214 .get_settings
= macb_get_settings
,
2215 .set_settings
= macb_set_settings
,
2216 .get_regs_len
= macb_get_regs_len
,
2217 .get_regs
= macb_get_regs
,
2218 .get_link
= ethtool_op_get_link
,
2219 .get_ts_info
= ethtool_op_get_ts_info
,
2220 .get_ethtool_stats
= gem_get_ethtool_stats
,
2221 .get_strings
= gem_get_ethtool_strings
,
2222 .get_sset_count
= gem_get_sset_count
,
2225 static int macb_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2227 struct macb
*bp
= netdev_priv(dev
);
2228 struct phy_device
*phydev
= bp
->phy_dev
;
2230 if (!netif_running(dev
))
2236 return phy_mii_ioctl(phydev
, rq
, cmd
);
2239 static int macb_set_features(struct net_device
*netdev
,
2240 netdev_features_t features
)
2242 struct macb
*bp
= netdev_priv(netdev
);
2243 netdev_features_t changed
= features
^ netdev
->features
;
2245 /* TX checksum offload */
2246 if ((changed
& NETIF_F_HW_CSUM
) && macb_is_gem(bp
)) {
2249 dmacfg
= gem_readl(bp
, DMACFG
);
2250 if (features
& NETIF_F_HW_CSUM
)
2251 dmacfg
|= GEM_BIT(TXCOEN
);
2253 dmacfg
&= ~GEM_BIT(TXCOEN
);
2254 gem_writel(bp
, DMACFG
, dmacfg
);
2257 /* RX checksum offload */
2258 if ((changed
& NETIF_F_RXCSUM
) && macb_is_gem(bp
)) {
2261 netcfg
= gem_readl(bp
, NCFGR
);
2262 if (features
& NETIF_F_RXCSUM
&&
2263 !(netdev
->flags
& IFF_PROMISC
))
2264 netcfg
|= GEM_BIT(RXCOEN
);
2266 netcfg
&= ~GEM_BIT(RXCOEN
);
2267 gem_writel(bp
, NCFGR
, netcfg
);
2273 static const struct net_device_ops macb_netdev_ops
= {
2274 .ndo_open
= macb_open
,
2275 .ndo_stop
= macb_close
,
2276 .ndo_start_xmit
= macb_start_xmit
,
2277 .ndo_set_rx_mode
= macb_set_rx_mode
,
2278 .ndo_get_stats
= macb_get_stats
,
2279 .ndo_do_ioctl
= macb_ioctl
,
2280 .ndo_validate_addr
= eth_validate_addr
,
2281 .ndo_change_mtu
= macb_change_mtu
,
2282 .ndo_set_mac_address
= eth_mac_addr
,
2283 #ifdef CONFIG_NET_POLL_CONTROLLER
2284 .ndo_poll_controller
= macb_poll_controller
,
2286 .ndo_set_features
= macb_set_features
,
2290 * Configure peripheral capabilities according to device tree
2291 * and integration options used
2293 static void macb_configure_caps(struct macb
*bp
, const struct macb_config
*dt_conf
)
2298 bp
->caps
= dt_conf
->caps
;
2300 if (hw_is_gem(bp
->regs
, bp
->native_io
)) {
2301 bp
->caps
|= MACB_CAPS_MACB_IS_GEM
;
2303 dcfg
= gem_readl(bp
, DCFG1
);
2304 if (GEM_BFEXT(IRQCOR
, dcfg
) == 0)
2305 bp
->caps
|= MACB_CAPS_ISR_CLEAR_ON_WRITE
;
2306 dcfg
= gem_readl(bp
, DCFG2
);
2307 if ((dcfg
& (GEM_BIT(RX_PKT_BUFF
) | GEM_BIT(TX_PKT_BUFF
))) == 0)
2308 bp
->caps
|= MACB_CAPS_FIFO_MODE
;
2311 dev_dbg(&bp
->pdev
->dev
, "Cadence caps 0x%08x\n", bp
->caps
);
2314 static void macb_probe_queues(void __iomem
*mem
,
2316 unsigned int *queue_mask
,
2317 unsigned int *num_queues
)
2324 /* is it macb or gem ?
2326 * We need to read directly from the hardware here because
2327 * we are early in the probe process and don't have the
2328 * MACB_CAPS_MACB_IS_GEM flag positioned
2330 if (!hw_is_gem(mem
, native_io
))
2333 /* bit 0 is never set but queue 0 always exists */
2334 *queue_mask
= readl_relaxed(mem
+ GEM_DCFG6
) & 0xff;
2338 for (hw_q
= 1; hw_q
< MACB_MAX_QUEUES
; ++hw_q
)
2339 if (*queue_mask
& (1 << hw_q
))
2343 static int macb_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2344 struct clk
**hclk
, struct clk
**tx_clk
)
2348 *pclk
= devm_clk_get(&pdev
->dev
, "pclk");
2349 if (IS_ERR(*pclk
)) {
2350 err
= PTR_ERR(*pclk
);
2351 dev_err(&pdev
->dev
, "failed to get macb_clk (%u)\n", err
);
2355 *hclk
= devm_clk_get(&pdev
->dev
, "hclk");
2356 if (IS_ERR(*hclk
)) {
2357 err
= PTR_ERR(*hclk
);
2358 dev_err(&pdev
->dev
, "failed to get hclk (%u)\n", err
);
2362 *tx_clk
= devm_clk_get(&pdev
->dev
, "tx_clk");
2363 if (IS_ERR(*tx_clk
))
2366 err
= clk_prepare_enable(*pclk
);
2368 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2372 err
= clk_prepare_enable(*hclk
);
2374 dev_err(&pdev
->dev
, "failed to enable hclk (%u)\n", err
);
2375 goto err_disable_pclk
;
2378 err
= clk_prepare_enable(*tx_clk
);
2380 dev_err(&pdev
->dev
, "failed to enable tx_clk (%u)\n", err
);
2381 goto err_disable_hclk
;
2387 clk_disable_unprepare(*hclk
);
2390 clk_disable_unprepare(*pclk
);
2395 static int macb_init(struct platform_device
*pdev
)
2397 struct net_device
*dev
= platform_get_drvdata(pdev
);
2398 unsigned int hw_q
, q
;
2399 struct macb
*bp
= netdev_priv(dev
);
2400 struct macb_queue
*queue
;
2404 /* set the queue register mapping once for all: queue0 has a special
2405 * register mapping but we don't want to test the queue index then
2406 * compute the corresponding register offset at run time.
2408 for (hw_q
= 0, q
= 0; hw_q
< MACB_MAX_QUEUES
; ++hw_q
) {
2409 if (!(bp
->queue_mask
& (1 << hw_q
)))
2412 queue
= &bp
->queues
[q
];
2415 queue
->ISR
= GEM_ISR(hw_q
- 1);
2416 queue
->IER
= GEM_IER(hw_q
- 1);
2417 queue
->IDR
= GEM_IDR(hw_q
- 1);
2418 queue
->IMR
= GEM_IMR(hw_q
- 1);
2419 queue
->TBQP
= GEM_TBQP(hw_q
- 1);
2421 /* queue0 uses legacy registers */
2422 queue
->ISR
= MACB_ISR
;
2423 queue
->IER
= MACB_IER
;
2424 queue
->IDR
= MACB_IDR
;
2425 queue
->IMR
= MACB_IMR
;
2426 queue
->TBQP
= MACB_TBQP
;
2429 /* get irq: here we use the linux queue index, not the hardware
2430 * queue index. the queue irq definitions in the device tree
2431 * must remove the optional gaps that could exist in the
2432 * hardware queue mask.
2434 queue
->irq
= platform_get_irq(pdev
, q
);
2435 err
= devm_request_irq(&pdev
->dev
, queue
->irq
, macb_interrupt
,
2436 IRQF_SHARED
, dev
->name
, queue
);
2439 "Unable to request IRQ %d (error %d)\n",
2444 INIT_WORK(&queue
->tx_error_task
, macb_tx_error_task
);
2448 dev
->netdev_ops
= &macb_netdev_ops
;
2449 netif_napi_add(dev
, &bp
->napi
, macb_poll
, 64);
2451 /* setup appropriated routines according to adapter type */
2452 if (macb_is_gem(bp
)) {
2453 bp
->max_tx_length
= GEM_MAX_TX_LEN
;
2454 bp
->macbgem_ops
.mog_alloc_rx_buffers
= gem_alloc_rx_buffers
;
2455 bp
->macbgem_ops
.mog_free_rx_buffers
= gem_free_rx_buffers
;
2456 bp
->macbgem_ops
.mog_init_rings
= gem_init_rings
;
2457 bp
->macbgem_ops
.mog_rx
= gem_rx
;
2458 dev
->ethtool_ops
= &gem_ethtool_ops
;
2460 bp
->max_tx_length
= MACB_MAX_TX_LEN
;
2461 bp
->macbgem_ops
.mog_alloc_rx_buffers
= macb_alloc_rx_buffers
;
2462 bp
->macbgem_ops
.mog_free_rx_buffers
= macb_free_rx_buffers
;
2463 bp
->macbgem_ops
.mog_init_rings
= macb_init_rings
;
2464 bp
->macbgem_ops
.mog_rx
= macb_rx
;
2465 dev
->ethtool_ops
= &macb_ethtool_ops
;
2469 dev
->hw_features
= NETIF_F_SG
;
2470 /* Checksum offload is only available on gem with packet buffer */
2471 if (macb_is_gem(bp
) && !(bp
->caps
& MACB_CAPS_FIFO_MODE
))
2472 dev
->hw_features
|= NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
;
2473 if (bp
->caps
& MACB_CAPS_SG_DISABLED
)
2474 dev
->hw_features
&= ~NETIF_F_SG
;
2475 dev
->features
= dev
->hw_features
;
2477 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
)) {
2479 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
2480 val
= GEM_BIT(RGMII
);
2481 else if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
&&
2482 (bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2483 val
= MACB_BIT(RMII
);
2484 else if (!(bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2485 val
= MACB_BIT(MII
);
2487 if (bp
->caps
& MACB_CAPS_USRIO_HAS_CLKEN
)
2488 val
|= MACB_BIT(CLKEN
);
2490 macb_or_gem_writel(bp
, USRIO
, val
);
2493 /* Set MII management clock divider */
2494 val
= macb_mdc_clk_div(bp
);
2495 val
|= macb_dbw(bp
);
2496 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2497 val
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
2498 macb_writel(bp
, NCFGR
, val
);
2503 #if defined(CONFIG_OF)
2504 /* 1518 rounded up */
2505 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2506 /* max number of receive buffers */
2507 #define AT91ETHER_MAX_RX_DESCR 9
2509 /* Initialize and start the Receiver and Transmit subsystems */
2510 static int at91ether_start(struct net_device
*dev
)
2512 struct macb
*lp
= netdev_priv(dev
);
2517 lp
->rx_ring
= dma_alloc_coherent(&lp
->pdev
->dev
,
2518 (AT91ETHER_MAX_RX_DESCR
*
2519 sizeof(struct macb_dma_desc
)),
2520 &lp
->rx_ring_dma
, GFP_KERNEL
);
2524 lp
->rx_buffers
= dma_alloc_coherent(&lp
->pdev
->dev
,
2525 AT91ETHER_MAX_RX_DESCR
*
2526 AT91ETHER_MAX_RBUFF_SZ
,
2527 &lp
->rx_buffers_dma
, GFP_KERNEL
);
2528 if (!lp
->rx_buffers
) {
2529 dma_free_coherent(&lp
->pdev
->dev
,
2530 AT91ETHER_MAX_RX_DESCR
*
2531 sizeof(struct macb_dma_desc
),
2532 lp
->rx_ring
, lp
->rx_ring_dma
);
2537 addr
= lp
->rx_buffers_dma
;
2538 for (i
= 0; i
< AT91ETHER_MAX_RX_DESCR
; i
++) {
2539 lp
->rx_ring
[i
].addr
= addr
;
2540 lp
->rx_ring
[i
].ctrl
= 0;
2541 addr
+= AT91ETHER_MAX_RBUFF_SZ
;
2544 /* Set the Wrap bit on the last descriptor */
2545 lp
->rx_ring
[AT91ETHER_MAX_RX_DESCR
- 1].addr
|= MACB_BIT(RX_WRAP
);
2547 /* Reset buffer index */
2550 /* Program address of descriptor list in Rx Buffer Queue register */
2551 macb_writel(lp
, RBQP
, lp
->rx_ring_dma
);
2553 /* Enable Receive and Transmit */
2554 ctl
= macb_readl(lp
, NCR
);
2555 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
) | MACB_BIT(TE
));
2560 /* Open the ethernet interface */
2561 static int at91ether_open(struct net_device
*dev
)
2563 struct macb
*lp
= netdev_priv(dev
);
2567 /* Clear internal statistics */
2568 ctl
= macb_readl(lp
, NCR
);
2569 macb_writel(lp
, NCR
, ctl
| MACB_BIT(CLRSTAT
));
2571 macb_set_hwaddr(lp
);
2573 ret
= at91ether_start(dev
);
2577 /* Enable MAC interrupts */
2578 macb_writel(lp
, IER
, MACB_BIT(RCOMP
) |
2580 MACB_BIT(ISR_TUND
) |
2583 MACB_BIT(ISR_ROVR
) |
2586 /* schedule a link state check */
2587 phy_start(lp
->phy_dev
);
2589 netif_start_queue(dev
);
2594 /* Close the interface */
2595 static int at91ether_close(struct net_device
*dev
)
2597 struct macb
*lp
= netdev_priv(dev
);
2600 /* Disable Receiver and Transmitter */
2601 ctl
= macb_readl(lp
, NCR
);
2602 macb_writel(lp
, NCR
, ctl
& ~(MACB_BIT(TE
) | MACB_BIT(RE
)));
2604 /* Disable MAC interrupts */
2605 macb_writel(lp
, IDR
, MACB_BIT(RCOMP
) |
2607 MACB_BIT(ISR_TUND
) |
2610 MACB_BIT(ISR_ROVR
) |
2613 netif_stop_queue(dev
);
2615 dma_free_coherent(&lp
->pdev
->dev
,
2616 AT91ETHER_MAX_RX_DESCR
*
2617 sizeof(struct macb_dma_desc
),
2618 lp
->rx_ring
, lp
->rx_ring_dma
);
2621 dma_free_coherent(&lp
->pdev
->dev
,
2622 AT91ETHER_MAX_RX_DESCR
* AT91ETHER_MAX_RBUFF_SZ
,
2623 lp
->rx_buffers
, lp
->rx_buffers_dma
);
2624 lp
->rx_buffers
= NULL
;
2629 /* Transmit packet */
2630 static int at91ether_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2632 struct macb
*lp
= netdev_priv(dev
);
2634 if (macb_readl(lp
, TSR
) & MACB_BIT(RM9200_BNQ
)) {
2635 netif_stop_queue(dev
);
2637 /* Store packet information (to free when Tx completed) */
2639 lp
->skb_length
= skb
->len
;
2640 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
2643 /* Set address of the data in the Transmit Address register */
2644 macb_writel(lp
, TAR
, lp
->skb_physaddr
);
2645 /* Set length of the packet in the Transmit Control register */
2646 macb_writel(lp
, TCR
, skb
->len
);
2649 netdev_err(dev
, "%s called, but device is busy!\n", __func__
);
2650 return NETDEV_TX_BUSY
;
2653 return NETDEV_TX_OK
;
2656 /* Extract received frame from buffer descriptors and sent to upper layers.
2657 * (Called from interrupt context)
2659 static void at91ether_rx(struct net_device
*dev
)
2661 struct macb
*lp
= netdev_priv(dev
);
2662 unsigned char *p_recv
;
2663 struct sk_buff
*skb
;
2664 unsigned int pktlen
;
2666 while (lp
->rx_ring
[lp
->rx_tail
].addr
& MACB_BIT(RX_USED
)) {
2667 p_recv
= lp
->rx_buffers
+ lp
->rx_tail
* AT91ETHER_MAX_RBUFF_SZ
;
2668 pktlen
= MACB_BF(RX_FRMLEN
, lp
->rx_ring
[lp
->rx_tail
].ctrl
);
2669 skb
= netdev_alloc_skb(dev
, pktlen
+ 2);
2671 skb_reserve(skb
, 2);
2672 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
2674 skb
->protocol
= eth_type_trans(skb
, dev
);
2675 lp
->stats
.rx_packets
++;
2676 lp
->stats
.rx_bytes
+= pktlen
;
2679 lp
->stats
.rx_dropped
++;
2682 if (lp
->rx_ring
[lp
->rx_tail
].ctrl
& MACB_BIT(RX_MHASH_MATCH
))
2683 lp
->stats
.multicast
++;
2685 /* reset ownership bit */
2686 lp
->rx_ring
[lp
->rx_tail
].addr
&= ~MACB_BIT(RX_USED
);
2688 /* wrap after last buffer */
2689 if (lp
->rx_tail
== AT91ETHER_MAX_RX_DESCR
- 1)
2696 /* MAC interrupt handler */
2697 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
)
2699 struct net_device
*dev
= dev_id
;
2700 struct macb
*lp
= netdev_priv(dev
);
2703 /* MAC Interrupt Status register indicates what interrupts are pending.
2704 * It is automatically cleared once read.
2706 intstatus
= macb_readl(lp
, ISR
);
2708 /* Receive complete */
2709 if (intstatus
& MACB_BIT(RCOMP
))
2712 /* Transmit complete */
2713 if (intstatus
& MACB_BIT(TCOMP
)) {
2714 /* The TCOM bit is set even if the transmission failed */
2715 if (intstatus
& (MACB_BIT(ISR_TUND
) | MACB_BIT(ISR_RLE
)))
2716 lp
->stats
.tx_errors
++;
2719 dev_kfree_skb_irq(lp
->skb
);
2721 dma_unmap_single(NULL
, lp
->skb_physaddr
,
2722 lp
->skb_length
, DMA_TO_DEVICE
);
2723 lp
->stats
.tx_packets
++;
2724 lp
->stats
.tx_bytes
+= lp
->skb_length
;
2726 netif_wake_queue(dev
);
2729 /* Work-around for EMAC Errata section 41.3.1 */
2730 if (intstatus
& MACB_BIT(RXUBR
)) {
2731 ctl
= macb_readl(lp
, NCR
);
2732 macb_writel(lp
, NCR
, ctl
& ~MACB_BIT(RE
));
2733 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
));
2736 if (intstatus
& MACB_BIT(ISR_ROVR
))
2737 netdev_err(dev
, "ROVR error\n");
2742 #ifdef CONFIG_NET_POLL_CONTROLLER
2743 static void at91ether_poll_controller(struct net_device
*dev
)
2745 unsigned long flags
;
2747 local_irq_save(flags
);
2748 at91ether_interrupt(dev
->irq
, dev
);
2749 local_irq_restore(flags
);
2753 static const struct net_device_ops at91ether_netdev_ops
= {
2754 .ndo_open
= at91ether_open
,
2755 .ndo_stop
= at91ether_close
,
2756 .ndo_start_xmit
= at91ether_start_xmit
,
2757 .ndo_get_stats
= macb_get_stats
,
2758 .ndo_set_rx_mode
= macb_set_rx_mode
,
2759 .ndo_set_mac_address
= eth_mac_addr
,
2760 .ndo_do_ioctl
= macb_ioctl
,
2761 .ndo_validate_addr
= eth_validate_addr
,
2762 .ndo_change_mtu
= eth_change_mtu
,
2763 #ifdef CONFIG_NET_POLL_CONTROLLER
2764 .ndo_poll_controller
= at91ether_poll_controller
,
2768 static int at91ether_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2769 struct clk
**hclk
, struct clk
**tx_clk
)
2776 *pclk
= devm_clk_get(&pdev
->dev
, "ether_clk");
2778 return PTR_ERR(*pclk
);
2780 err
= clk_prepare_enable(*pclk
);
2782 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2789 static int at91ether_init(struct platform_device
*pdev
)
2791 struct net_device
*dev
= platform_get_drvdata(pdev
);
2792 struct macb
*bp
= netdev_priv(dev
);
2796 dev
->netdev_ops
= &at91ether_netdev_ops
;
2797 dev
->ethtool_ops
= &macb_ethtool_ops
;
2799 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, at91ether_interrupt
,
2804 macb_writel(bp
, NCR
, 0);
2806 reg
= MACB_BF(CLK
, MACB_CLK_DIV32
) | MACB_BIT(BIG
);
2807 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
2808 reg
|= MACB_BIT(RM9200_RMII
);
2810 macb_writel(bp
, NCFGR
, reg
);
2815 static const struct macb_config at91sam9260_config
= {
2816 .caps
= MACB_CAPS_USRIO_HAS_CLKEN
| MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2817 .clk_init
= macb_clk_init
,
2821 static const struct macb_config pc302gem_config
= {
2822 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
,
2823 .dma_burst_length
= 16,
2824 .clk_init
= macb_clk_init
,
2828 static const struct macb_config sama5d2_config
= {
2829 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2830 .dma_burst_length
= 16,
2831 .clk_init
= macb_clk_init
,
2835 static const struct macb_config sama5d3_config
= {
2836 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
2837 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2838 .dma_burst_length
= 16,
2839 .clk_init
= macb_clk_init
,
2843 static const struct macb_config sama5d4_config
= {
2844 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2845 .dma_burst_length
= 4,
2846 .clk_init
= macb_clk_init
,
2850 static const struct macb_config emac_config
= {
2851 .clk_init
= at91ether_clk_init
,
2852 .init
= at91ether_init
,
2855 static const struct macb_config np4_config
= {
2856 .caps
= MACB_CAPS_USRIO_DISABLED
,
2857 .clk_init
= macb_clk_init
,
2861 static const struct macb_config zynqmp_config
= {
2862 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_JUMBO
,
2863 .dma_burst_length
= 16,
2864 .clk_init
= macb_clk_init
,
2866 .jumbo_max_len
= 10240,
2869 static const struct macb_config zynq_config
= {
2870 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_NO_GIGABIT_HALF
,
2871 .dma_burst_length
= 16,
2872 .clk_init
= macb_clk_init
,
2876 static const struct of_device_id macb_dt_ids
[] = {
2877 { .compatible
= "cdns,at32ap7000-macb" },
2878 { .compatible
= "cdns,at91sam9260-macb", .data
= &at91sam9260_config
},
2879 { .compatible
= "cdns,macb" },
2880 { .compatible
= "cdns,np4-macb", .data
= &np4_config
},
2881 { .compatible
= "cdns,pc302-gem", .data
= &pc302gem_config
},
2882 { .compatible
= "cdns,gem", .data
= &pc302gem_config
},
2883 { .compatible
= "atmel,sama5d2-gem", .data
= &sama5d2_config
},
2884 { .compatible
= "atmel,sama5d3-gem", .data
= &sama5d3_config
},
2885 { .compatible
= "atmel,sama5d4-gem", .data
= &sama5d4_config
},
2886 { .compatible
= "cdns,at91rm9200-emac", .data
= &emac_config
},
2887 { .compatible
= "cdns,emac", .data
= &emac_config
},
2888 { .compatible
= "cdns,zynqmp-gem", .data
= &zynqmp_config
},
2889 { .compatible
= "cdns,zynq-gem", .data
= &zynq_config
},
2892 MODULE_DEVICE_TABLE(of
, macb_dt_ids
);
2893 #endif /* CONFIG_OF */
2895 static int macb_probe(struct platform_device
*pdev
)
2897 int (*clk_init
)(struct platform_device
*, struct clk
**,
2898 struct clk
**, struct clk
**)
2900 int (*init
)(struct platform_device
*) = macb_init
;
2901 struct device_node
*np
= pdev
->dev
.of_node
;
2902 struct device_node
*phy_node
;
2903 const struct macb_config
*macb_config
= NULL
;
2904 struct clk
*pclk
, *hclk
= NULL
, *tx_clk
= NULL
;
2905 unsigned int queue_mask
, num_queues
;
2906 struct macb_platform_data
*pdata
;
2908 struct phy_device
*phydev
;
2909 struct net_device
*dev
;
2910 struct resource
*regs
;
2916 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2917 mem
= devm_ioremap_resource(&pdev
->dev
, regs
);
2919 return PTR_ERR(mem
);
2922 const struct of_device_id
*match
;
2924 match
= of_match_node(macb_dt_ids
, np
);
2925 if (match
&& match
->data
) {
2926 macb_config
= match
->data
;
2927 clk_init
= macb_config
->clk_init
;
2928 init
= macb_config
->init
;
2932 err
= clk_init(pdev
, &pclk
, &hclk
, &tx_clk
);
2936 native_io
= hw_is_native_io(mem
);
2938 macb_probe_queues(mem
, native_io
, &queue_mask
, &num_queues
);
2939 dev
= alloc_etherdev_mq(sizeof(*bp
), num_queues
);
2942 goto err_disable_clocks
;
2945 dev
->base_addr
= regs
->start
;
2947 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2949 bp
= netdev_priv(dev
);
2953 bp
->native_io
= native_io
;
2955 bp
->macb_reg_readl
= hw_readl_native
;
2956 bp
->macb_reg_writel
= hw_writel_native
;
2958 bp
->macb_reg_readl
= hw_readl
;
2959 bp
->macb_reg_writel
= hw_writel
;
2961 bp
->num_queues
= num_queues
;
2962 bp
->queue_mask
= queue_mask
;
2964 bp
->dma_burst_length
= macb_config
->dma_burst_length
;
2967 bp
->tx_clk
= tx_clk
;
2969 bp
->jumbo_max_len
= macb_config
->jumbo_max_len
;
2972 if (of_get_property(np
, "magic-packet", NULL
))
2973 bp
->wol
|= MACB_WOL_HAS_MAGIC_PACKET
;
2974 device_init_wakeup(&pdev
->dev
, bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
);
2976 spin_lock_init(&bp
->lock
);
2978 /* setup capabilities */
2979 macb_configure_caps(bp
, macb_config
);
2981 platform_set_drvdata(pdev
, dev
);
2983 dev
->irq
= platform_get_irq(pdev
, 0);
2986 goto err_disable_clocks
;
2989 mac
= of_get_mac_address(np
);
2991 memcpy(bp
->dev
->dev_addr
, mac
, ETH_ALEN
);
2993 macb_get_hwaddr(bp
);
2995 /* Power up the PHY if there is a GPIO reset */
2996 phy_node
= of_get_next_available_child(np
, NULL
);
2998 int gpio
= of_get_named_gpio(phy_node
, "reset-gpios", 0);
2999 if (gpio_is_valid(gpio
)) {
3000 bp
->reset_gpio
= gpio_to_desc(gpio
);
3001 gpiod_direction_output(bp
->reset_gpio
, 1);
3004 of_node_put(phy_node
);
3006 err
= of_get_phy_mode(np
);
3008 pdata
= dev_get_platdata(&pdev
->dev
);
3009 if (pdata
&& pdata
->is_rmii
)
3010 bp
->phy_interface
= PHY_INTERFACE_MODE_RMII
;
3012 bp
->phy_interface
= PHY_INTERFACE_MODE_MII
;
3014 bp
->phy_interface
= err
;
3017 /* IP specific init */
3020 goto err_out_free_netdev
;
3022 err
= register_netdev(dev
);
3024 dev_err(&pdev
->dev
, "Cannot register net device, aborting.\n");
3025 goto err_out_unregister_netdev
;
3028 err
= macb_mii_init(bp
);
3030 goto err_out_unregister_netdev
;
3032 netif_carrier_off(dev
);
3034 netdev_info(dev
, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3035 macb_is_gem(bp
) ? "GEM" : "MACB", macb_readl(bp
, MID
),
3036 dev
->base_addr
, dev
->irq
, dev
->dev_addr
);
3038 phydev
= bp
->phy_dev
;
3039 phy_attached_info(phydev
);
3043 err_out_unregister_netdev
:
3044 unregister_netdev(dev
);
3046 err_out_free_netdev
:
3050 clk_disable_unprepare(tx_clk
);
3051 clk_disable_unprepare(hclk
);
3052 clk_disable_unprepare(pclk
);
3057 static int macb_remove(struct platform_device
*pdev
)
3059 struct net_device
*dev
;
3062 dev
= platform_get_drvdata(pdev
);
3065 bp
= netdev_priv(dev
);
3067 phy_disconnect(bp
->phy_dev
);
3068 mdiobus_unregister(bp
->mii_bus
);
3069 mdiobus_free(bp
->mii_bus
);
3071 /* Shutdown the PHY if there is a GPIO reset */
3073 gpiod_set_value(bp
->reset_gpio
, 0);
3075 unregister_netdev(dev
);
3076 clk_disable_unprepare(bp
->tx_clk
);
3077 clk_disable_unprepare(bp
->hclk
);
3078 clk_disable_unprepare(bp
->pclk
);
3085 static int __maybe_unused
macb_suspend(struct device
*dev
)
3087 struct platform_device
*pdev
= to_platform_device(dev
);
3088 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3089 struct macb
*bp
= netdev_priv(netdev
);
3091 netif_carrier_off(netdev
);
3092 netif_device_detach(netdev
);
3094 if (bp
->wol
& MACB_WOL_ENABLED
) {
3095 macb_writel(bp
, IER
, MACB_BIT(WOL
));
3096 macb_writel(bp
, WOL
, MACB_BIT(MAG
));
3097 enable_irq_wake(bp
->queues
[0].irq
);
3099 clk_disable_unprepare(bp
->tx_clk
);
3100 clk_disable_unprepare(bp
->hclk
);
3101 clk_disable_unprepare(bp
->pclk
);
3107 static int __maybe_unused
macb_resume(struct device
*dev
)
3109 struct platform_device
*pdev
= to_platform_device(dev
);
3110 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3111 struct macb
*bp
= netdev_priv(netdev
);
3113 if (bp
->wol
& MACB_WOL_ENABLED
) {
3114 macb_writel(bp
, IDR
, MACB_BIT(WOL
));
3115 macb_writel(bp
, WOL
, 0);
3116 disable_irq_wake(bp
->queues
[0].irq
);
3118 clk_prepare_enable(bp
->pclk
);
3119 clk_prepare_enable(bp
->hclk
);
3120 clk_prepare_enable(bp
->tx_clk
);
3123 netif_device_attach(netdev
);
3128 static SIMPLE_DEV_PM_OPS(macb_pm_ops
, macb_suspend
, macb_resume
);
3130 static struct platform_driver macb_driver
= {
3131 .probe
= macb_probe
,
3132 .remove
= macb_remove
,
3135 .of_match_table
= of_match_ptr(macb_dt_ids
),
3140 module_platform_driver(macb_driver
);
3142 MODULE_LICENSE("GPL");
3143 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3144 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3145 MODULE_ALIAS("platform:macb");