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Merge branch 'pci/msi-affinity' into next
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/interrupt.h>
33 #include <linux/tcp.h>
34 #include <linux/ipv6.h>
35 #include <linux/slab.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/cpu.h>
41 #include <linux/smp.h>
42 #include <linux/pm_qos.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/aer.h>
45 #include <linux/prefetch.h>
46
47 #include "e1000.h"
48
49 #define DRV_EXTRAVERSION "-k"
50
51 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
52 char e1000e_driver_name[] = "e1000e";
53 const char e1000e_driver_version[] = DRV_VERSION;
54
55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56 static int debug = -1;
57 module_param(debug, int, 0);
58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60 static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
64 [board_82574] = &e1000_82574_info,
65 [board_82583] = &e1000_82583_info,
66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
69 [board_ich10lan] = &e1000_ich10_info,
70 [board_pchlan] = &e1000_pch_info,
71 [board_pch2lan] = &e1000_pch2_info,
72 [board_pch_lpt] = &e1000_pch_lpt_info,
73 [board_pch_spt] = &e1000_pch_spt_info,
74 };
75
76 struct e1000_reg_info {
77 u32 ofs;
78 char *name;
79 };
80
81 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
82 /* General Registers */
83 {E1000_CTRL, "CTRL"},
84 {E1000_STATUS, "STATUS"},
85 {E1000_CTRL_EXT, "CTRL_EXT"},
86
87 /* Interrupt Registers */
88 {E1000_ICR, "ICR"},
89
90 /* Rx Registers */
91 {E1000_RCTL, "RCTL"},
92 {E1000_RDLEN(0), "RDLEN"},
93 {E1000_RDH(0), "RDH"},
94 {E1000_RDT(0), "RDT"},
95 {E1000_RDTR, "RDTR"},
96 {E1000_RXDCTL(0), "RXDCTL"},
97 {E1000_ERT, "ERT"},
98 {E1000_RDBAL(0), "RDBAL"},
99 {E1000_RDBAH(0), "RDBAH"},
100 {E1000_RDFH, "RDFH"},
101 {E1000_RDFT, "RDFT"},
102 {E1000_RDFHS, "RDFHS"},
103 {E1000_RDFTS, "RDFTS"},
104 {E1000_RDFPC, "RDFPC"},
105
106 /* Tx Registers */
107 {E1000_TCTL, "TCTL"},
108 {E1000_TDBAL(0), "TDBAL"},
109 {E1000_TDBAH(0), "TDBAH"},
110 {E1000_TDLEN(0), "TDLEN"},
111 {E1000_TDH(0), "TDH"},
112 {E1000_TDT(0), "TDT"},
113 {E1000_TIDV, "TIDV"},
114 {E1000_TXDCTL(0), "TXDCTL"},
115 {E1000_TADV, "TADV"},
116 {E1000_TARC(0), "TARC"},
117 {E1000_TDFH, "TDFH"},
118 {E1000_TDFT, "TDFT"},
119 {E1000_TDFHS, "TDFHS"},
120 {E1000_TDFTS, "TDFTS"},
121 {E1000_TDFPC, "TDFPC"},
122
123 /* List Terminator */
124 {0, NULL}
125 };
126
127 /**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
139 s32 __ew32_prepare(struct e1000_hw *hw)
140 {
141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
142
143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
144 udelay(50);
145
146 return i;
147 }
148
149 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
150 {
151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
152 __ew32_prepare(hw);
153
154 writel(val, hw->hw_addr + reg);
155 }
156
157 static bool e1000e_vlan_used(struct e1000_adapter *adapter)
158 {
159 u16 vid;
160
161 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
162 return true;
163
164 return false;
165 }
166
167 /**
168 * e1000_regdump - register printout routine
169 * @hw: pointer to the HW structure
170 * @reginfo: pointer to the register info table
171 **/
172 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
173 {
174 int n = 0;
175 char rname[16];
176 u32 regs[8];
177
178 switch (reginfo->ofs) {
179 case E1000_RXDCTL(0):
180 for (n = 0; n < 2; n++)
181 regs[n] = __er32(hw, E1000_RXDCTL(n));
182 break;
183 case E1000_TXDCTL(0):
184 for (n = 0; n < 2; n++)
185 regs[n] = __er32(hw, E1000_TXDCTL(n));
186 break;
187 case E1000_TARC(0):
188 for (n = 0; n < 2; n++)
189 regs[n] = __er32(hw, E1000_TARC(n));
190 break;
191 default:
192 pr_info("%-15s %08x\n",
193 reginfo->name, __er32(hw, reginfo->ofs));
194 return;
195 }
196
197 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
198 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
199 }
200
201 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
202 struct e1000_buffer *bi)
203 {
204 int i;
205 struct e1000_ps_page *ps_page;
206
207 for (i = 0; i < adapter->rx_ps_pages; i++) {
208 ps_page = &bi->ps_pages[i];
209
210 if (ps_page->page) {
211 pr_info("packet dump for ps_page %d:\n", i);
212 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
213 16, 1, page_address(ps_page->page),
214 PAGE_SIZE, true);
215 }
216 }
217 }
218
219 /**
220 * e1000e_dump - Print registers, Tx-ring and Rx-ring
221 * @adapter: board private structure
222 **/
223 static void e1000e_dump(struct e1000_adapter *adapter)
224 {
225 struct net_device *netdev = adapter->netdev;
226 struct e1000_hw *hw = &adapter->hw;
227 struct e1000_reg_info *reginfo;
228 struct e1000_ring *tx_ring = adapter->tx_ring;
229 struct e1000_tx_desc *tx_desc;
230 struct my_u0 {
231 __le64 a;
232 __le64 b;
233 } *u0;
234 struct e1000_buffer *buffer_info;
235 struct e1000_ring *rx_ring = adapter->rx_ring;
236 union e1000_rx_desc_packet_split *rx_desc_ps;
237 union e1000_rx_desc_extended *rx_desc;
238 struct my_u1 {
239 __le64 a;
240 __le64 b;
241 __le64 c;
242 __le64 d;
243 } *u1;
244 u32 staterr;
245 int i = 0;
246
247 if (!netif_msg_hw(adapter))
248 return;
249
250 /* Print netdevice Info */
251 if (netdev) {
252 dev_info(&adapter->pdev->dev, "Net device Info\n");
253 pr_info("Device Name state trans_start last_rx\n");
254 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
255 netdev->state, dev_trans_start(netdev), netdev->last_rx);
256 }
257
258 /* Print Registers */
259 dev_info(&adapter->pdev->dev, "Register Dump\n");
260 pr_info(" Register Name Value\n");
261 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
262 reginfo->name; reginfo++) {
263 e1000_regdump(hw, reginfo);
264 }
265
266 /* Print Tx Ring Summary */
267 if (!netdev || !netif_running(netdev))
268 return;
269
270 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
271 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
272 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
273 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
274 0, tx_ring->next_to_use, tx_ring->next_to_clean,
275 (unsigned long long)buffer_info->dma,
276 buffer_info->length,
277 buffer_info->next_to_watch,
278 (unsigned long long)buffer_info->time_stamp);
279
280 /* Print Tx Ring */
281 if (!netif_msg_tx_done(adapter))
282 goto rx_ring_summary;
283
284 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
285
286 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
287 *
288 * Legacy Transmit Descriptor
289 * +--------------------------------------------------------------+
290 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
291 * +--------------------------------------------------------------+
292 * 8 | Special | CSS | Status | CMD | CSO | Length |
293 * +--------------------------------------------------------------+
294 * 63 48 47 36 35 32 31 24 23 16 15 0
295 *
296 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
297 * 63 48 47 40 39 32 31 16 15 8 7 0
298 * +----------------------------------------------------------------+
299 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
300 * +----------------------------------------------------------------+
301 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
302 * +----------------------------------------------------------------+
303 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
304 *
305 * Extended Data Descriptor (DTYP=0x1)
306 * +----------------------------------------------------------------+
307 * 0 | Buffer Address [63:0] |
308 * +----------------------------------------------------------------+
309 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
310 * +----------------------------------------------------------------+
311 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
312 */
313 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
314 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
315 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
316 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
317 const char *next_desc;
318 tx_desc = E1000_TX_DESC(*tx_ring, i);
319 buffer_info = &tx_ring->buffer_info[i];
320 u0 = (struct my_u0 *)tx_desc;
321 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
322 next_desc = " NTC/U";
323 else if (i == tx_ring->next_to_use)
324 next_desc = " NTU";
325 else if (i == tx_ring->next_to_clean)
326 next_desc = " NTC";
327 else
328 next_desc = "";
329 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
330 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
331 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
332 i,
333 (unsigned long long)le64_to_cpu(u0->a),
334 (unsigned long long)le64_to_cpu(u0->b),
335 (unsigned long long)buffer_info->dma,
336 buffer_info->length, buffer_info->next_to_watch,
337 (unsigned long long)buffer_info->time_stamp,
338 buffer_info->skb, next_desc);
339
340 if (netif_msg_pktdata(adapter) && buffer_info->skb)
341 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
342 16, 1, buffer_info->skb->data,
343 buffer_info->skb->len, true);
344 }
345
346 /* Print Rx Ring Summary */
347 rx_ring_summary:
348 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
349 pr_info("Queue [NTU] [NTC]\n");
350 pr_info(" %5d %5X %5X\n",
351 0, rx_ring->next_to_use, rx_ring->next_to_clean);
352
353 /* Print Rx Ring */
354 if (!netif_msg_rx_status(adapter))
355 return;
356
357 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
358 switch (adapter->rx_ps_pages) {
359 case 1:
360 case 2:
361 case 3:
362 /* [Extended] Packet Split Receive Descriptor Format
363 *
364 * +-----------------------------------------------------+
365 * 0 | Buffer Address 0 [63:0] |
366 * +-----------------------------------------------------+
367 * 8 | Buffer Address 1 [63:0] |
368 * +-----------------------------------------------------+
369 * 16 | Buffer Address 2 [63:0] |
370 * +-----------------------------------------------------+
371 * 24 | Buffer Address 3 [63:0] |
372 * +-----------------------------------------------------+
373 */
374 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
375 /* [Extended] Receive Descriptor (Write-Back) Format
376 *
377 * 63 48 47 32 31 13 12 8 7 4 3 0
378 * +------------------------------------------------------+
379 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
380 * | Checksum | Ident | | Queue | | Type |
381 * +------------------------------------------------------+
382 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
383 * +------------------------------------------------------+
384 * 63 48 47 32 31 20 19 0
385 */
386 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
387 for (i = 0; i < rx_ring->count; i++) {
388 const char *next_desc;
389 buffer_info = &rx_ring->buffer_info[i];
390 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
391 u1 = (struct my_u1 *)rx_desc_ps;
392 staterr =
393 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
394
395 if (i == rx_ring->next_to_use)
396 next_desc = " NTU";
397 else if (i == rx_ring->next_to_clean)
398 next_desc = " NTC";
399 else
400 next_desc = "";
401
402 if (staterr & E1000_RXD_STAT_DD) {
403 /* Descriptor Done */
404 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
405 "RWB", i,
406 (unsigned long long)le64_to_cpu(u1->a),
407 (unsigned long long)le64_to_cpu(u1->b),
408 (unsigned long long)le64_to_cpu(u1->c),
409 (unsigned long long)le64_to_cpu(u1->d),
410 buffer_info->skb, next_desc);
411 } else {
412 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
413 "R ", i,
414 (unsigned long long)le64_to_cpu(u1->a),
415 (unsigned long long)le64_to_cpu(u1->b),
416 (unsigned long long)le64_to_cpu(u1->c),
417 (unsigned long long)le64_to_cpu(u1->d),
418 (unsigned long long)buffer_info->dma,
419 buffer_info->skb, next_desc);
420
421 if (netif_msg_pktdata(adapter))
422 e1000e_dump_ps_pages(adapter,
423 buffer_info);
424 }
425 }
426 break;
427 default:
428 case 0:
429 /* Extended Receive Descriptor (Read) Format
430 *
431 * +-----------------------------------------------------+
432 * 0 | Buffer Address [63:0] |
433 * +-----------------------------------------------------+
434 * 8 | Reserved |
435 * +-----------------------------------------------------+
436 */
437 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
438 /* Extended Receive Descriptor (Write-Back) Format
439 *
440 * 63 48 47 32 31 24 23 4 3 0
441 * +------------------------------------------------------+
442 * | RSS Hash | | | |
443 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
444 * | Packet | IP | | | Type |
445 * | Checksum | Ident | | | |
446 * +------------------------------------------------------+
447 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
448 * +------------------------------------------------------+
449 * 63 48 47 32 31 20 19 0
450 */
451 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
452
453 for (i = 0; i < rx_ring->count; i++) {
454 const char *next_desc;
455
456 buffer_info = &rx_ring->buffer_info[i];
457 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
458 u1 = (struct my_u1 *)rx_desc;
459 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
460
461 if (i == rx_ring->next_to_use)
462 next_desc = " NTU";
463 else if (i == rx_ring->next_to_clean)
464 next_desc = " NTC";
465 else
466 next_desc = "";
467
468 if (staterr & E1000_RXD_STAT_DD) {
469 /* Descriptor Done */
470 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
471 "RWB", i,
472 (unsigned long long)le64_to_cpu(u1->a),
473 (unsigned long long)le64_to_cpu(u1->b),
474 buffer_info->skb, next_desc);
475 } else {
476 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
477 "R ", i,
478 (unsigned long long)le64_to_cpu(u1->a),
479 (unsigned long long)le64_to_cpu(u1->b),
480 (unsigned long long)buffer_info->dma,
481 buffer_info->skb, next_desc);
482
483 if (netif_msg_pktdata(adapter) &&
484 buffer_info->skb)
485 print_hex_dump(KERN_INFO, "",
486 DUMP_PREFIX_ADDRESS, 16,
487 1,
488 buffer_info->skb->data,
489 adapter->rx_buffer_len,
490 true);
491 }
492 }
493 }
494 }
495
496 /**
497 * e1000_desc_unused - calculate if we have unused descriptors
498 **/
499 static int e1000_desc_unused(struct e1000_ring *ring)
500 {
501 if (ring->next_to_clean > ring->next_to_use)
502 return ring->next_to_clean - ring->next_to_use - 1;
503
504 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
505 }
506
507 /**
508 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
509 * @adapter: board private structure
510 * @hwtstamps: time stamp structure to update
511 * @systim: unsigned 64bit system time value.
512 *
513 * Convert the system time value stored in the RX/TXSTMP registers into a
514 * hwtstamp which can be used by the upper level time stamping functions.
515 *
516 * The 'systim_lock' spinlock is used to protect the consistency of the
517 * system time value. This is needed because reading the 64 bit time
518 * value involves reading two 32 bit registers. The first read latches the
519 * value.
520 **/
521 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
522 struct skb_shared_hwtstamps *hwtstamps,
523 u64 systim)
524 {
525 u64 ns;
526 unsigned long flags;
527
528 spin_lock_irqsave(&adapter->systim_lock, flags);
529 ns = timecounter_cyc2time(&adapter->tc, systim);
530 spin_unlock_irqrestore(&adapter->systim_lock, flags);
531
532 memset(hwtstamps, 0, sizeof(*hwtstamps));
533 hwtstamps->hwtstamp = ns_to_ktime(ns);
534 }
535
536 /**
537 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
538 * @adapter: board private structure
539 * @status: descriptor extended error and status field
540 * @skb: particular skb to include time stamp
541 *
542 * If the time stamp is valid, convert it into the timecounter ns value
543 * and store that result into the shhwtstamps structure which is passed
544 * up the network stack.
545 **/
546 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
547 struct sk_buff *skb)
548 {
549 struct e1000_hw *hw = &adapter->hw;
550 u64 rxstmp;
551
552 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
553 !(status & E1000_RXDEXT_STATERR_TST) ||
554 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
555 return;
556
557 /* The Rx time stamp registers contain the time stamp. No other
558 * received packet will be time stamped until the Rx time stamp
559 * registers are read. Because only one packet can be time stamped
560 * at a time, the register values must belong to this packet and
561 * therefore none of the other additional attributes need to be
562 * compared.
563 */
564 rxstmp = (u64)er32(RXSTMPL);
565 rxstmp |= (u64)er32(RXSTMPH) << 32;
566 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
567
568 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
569 }
570
571 /**
572 * e1000_receive_skb - helper function to handle Rx indications
573 * @adapter: board private structure
574 * @staterr: descriptor extended error and status field as written by hardware
575 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
576 * @skb: pointer to sk_buff to be indicated to stack
577 **/
578 static void e1000_receive_skb(struct e1000_adapter *adapter,
579 struct net_device *netdev, struct sk_buff *skb,
580 u32 staterr, __le16 vlan)
581 {
582 u16 tag = le16_to_cpu(vlan);
583
584 e1000e_rx_hwtstamp(adapter, staterr, skb);
585
586 skb->protocol = eth_type_trans(skb, netdev);
587
588 if (staterr & E1000_RXD_STAT_VP)
589 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
590
591 napi_gro_receive(&adapter->napi, skb);
592 }
593
594 /**
595 * e1000_rx_checksum - Receive Checksum Offload
596 * @adapter: board private structure
597 * @status_err: receive descriptor status and error fields
598 * @csum: receive descriptor csum field
599 * @sk_buff: socket buffer with received data
600 **/
601 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
602 struct sk_buff *skb)
603 {
604 u16 status = (u16)status_err;
605 u8 errors = (u8)(status_err >> 24);
606
607 skb_checksum_none_assert(skb);
608
609 /* Rx checksum disabled */
610 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
611 return;
612
613 /* Ignore Checksum bit is set */
614 if (status & E1000_RXD_STAT_IXSM)
615 return;
616
617 /* TCP/UDP checksum error bit or IP checksum error bit is set */
618 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
619 /* let the stack verify checksum errors */
620 adapter->hw_csum_err++;
621 return;
622 }
623
624 /* TCP/UDP Checksum has not been calculated */
625 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
626 return;
627
628 /* It must be a TCP or UDP packet with a valid checksum */
629 skb->ip_summed = CHECKSUM_UNNECESSARY;
630 adapter->hw_csum_good++;
631 }
632
633 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
634 {
635 struct e1000_adapter *adapter = rx_ring->adapter;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 ret_val = __ew32_prepare(hw);
638
639 writel(i, rx_ring->tail);
640
641 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
642 u32 rctl = er32(RCTL);
643
644 ew32(RCTL, rctl & ~E1000_RCTL_EN);
645 e_err("ME firmware caused invalid RDT - resetting\n");
646 schedule_work(&adapter->reset_task);
647 }
648 }
649
650 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
651 {
652 struct e1000_adapter *adapter = tx_ring->adapter;
653 struct e1000_hw *hw = &adapter->hw;
654 s32 ret_val = __ew32_prepare(hw);
655
656 writel(i, tx_ring->tail);
657
658 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
659 u32 tctl = er32(TCTL);
660
661 ew32(TCTL, tctl & ~E1000_TCTL_EN);
662 e_err("ME firmware caused invalid TDT - resetting\n");
663 schedule_work(&adapter->reset_task);
664 }
665 }
666
667 /**
668 * e1000_alloc_rx_buffers - Replace used receive buffers
669 * @rx_ring: Rx descriptor ring
670 **/
671 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
672 int cleaned_count, gfp_t gfp)
673 {
674 struct e1000_adapter *adapter = rx_ring->adapter;
675 struct net_device *netdev = adapter->netdev;
676 struct pci_dev *pdev = adapter->pdev;
677 union e1000_rx_desc_extended *rx_desc;
678 struct e1000_buffer *buffer_info;
679 struct sk_buff *skb;
680 unsigned int i;
681 unsigned int bufsz = adapter->rx_buffer_len;
682
683 i = rx_ring->next_to_use;
684 buffer_info = &rx_ring->buffer_info[i];
685
686 while (cleaned_count--) {
687 skb = buffer_info->skb;
688 if (skb) {
689 skb_trim(skb, 0);
690 goto map_skb;
691 }
692
693 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
694 if (!skb) {
695 /* Better luck next round */
696 adapter->alloc_rx_buff_failed++;
697 break;
698 }
699
700 buffer_info->skb = skb;
701 map_skb:
702 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
703 adapter->rx_buffer_len,
704 DMA_FROM_DEVICE);
705 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
706 dev_err(&pdev->dev, "Rx DMA map failed\n");
707 adapter->rx_dma_failed++;
708 break;
709 }
710
711 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
712 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
713
714 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
715 /* Force memory writes to complete before letting h/w
716 * know there are new descriptors to fetch. (Only
717 * applicable for weak-ordered memory model archs,
718 * such as IA-64).
719 */
720 wmb();
721 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
722 e1000e_update_rdt_wa(rx_ring, i);
723 else
724 writel(i, rx_ring->tail);
725 }
726 i++;
727 if (i == rx_ring->count)
728 i = 0;
729 buffer_info = &rx_ring->buffer_info[i];
730 }
731
732 rx_ring->next_to_use = i;
733 }
734
735 /**
736 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
737 * @rx_ring: Rx descriptor ring
738 **/
739 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
740 int cleaned_count, gfp_t gfp)
741 {
742 struct e1000_adapter *adapter = rx_ring->adapter;
743 struct net_device *netdev = adapter->netdev;
744 struct pci_dev *pdev = adapter->pdev;
745 union e1000_rx_desc_packet_split *rx_desc;
746 struct e1000_buffer *buffer_info;
747 struct e1000_ps_page *ps_page;
748 struct sk_buff *skb;
749 unsigned int i, j;
750
751 i = rx_ring->next_to_use;
752 buffer_info = &rx_ring->buffer_info[i];
753
754 while (cleaned_count--) {
755 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
756
757 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
758 ps_page = &buffer_info->ps_pages[j];
759 if (j >= adapter->rx_ps_pages) {
760 /* all unused desc entries get hw null ptr */
761 rx_desc->read.buffer_addr[j + 1] =
762 ~cpu_to_le64(0);
763 continue;
764 }
765 if (!ps_page->page) {
766 ps_page->page = alloc_page(gfp);
767 if (!ps_page->page) {
768 adapter->alloc_rx_buff_failed++;
769 goto no_buffers;
770 }
771 ps_page->dma = dma_map_page(&pdev->dev,
772 ps_page->page,
773 0, PAGE_SIZE,
774 DMA_FROM_DEVICE);
775 if (dma_mapping_error(&pdev->dev,
776 ps_page->dma)) {
777 dev_err(&adapter->pdev->dev,
778 "Rx DMA page map failed\n");
779 adapter->rx_dma_failed++;
780 goto no_buffers;
781 }
782 }
783 /* Refresh the desc even if buffer_addrs
784 * didn't change because each write-back
785 * erases this info.
786 */
787 rx_desc->read.buffer_addr[j + 1] =
788 cpu_to_le64(ps_page->dma);
789 }
790
791 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
792 gfp);
793
794 if (!skb) {
795 adapter->alloc_rx_buff_failed++;
796 break;
797 }
798
799 buffer_info->skb = skb;
800 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
801 adapter->rx_ps_bsize0,
802 DMA_FROM_DEVICE);
803 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
804 dev_err(&pdev->dev, "Rx DMA map failed\n");
805 adapter->rx_dma_failed++;
806 /* cleanup skb */
807 dev_kfree_skb_any(skb);
808 buffer_info->skb = NULL;
809 break;
810 }
811
812 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
813
814 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
815 /* Force memory writes to complete before letting h/w
816 * know there are new descriptors to fetch. (Only
817 * applicable for weak-ordered memory model archs,
818 * such as IA-64).
819 */
820 wmb();
821 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
822 e1000e_update_rdt_wa(rx_ring, i << 1);
823 else
824 writel(i << 1, rx_ring->tail);
825 }
826
827 i++;
828 if (i == rx_ring->count)
829 i = 0;
830 buffer_info = &rx_ring->buffer_info[i];
831 }
832
833 no_buffers:
834 rx_ring->next_to_use = i;
835 }
836
837 /**
838 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
839 * @rx_ring: Rx descriptor ring
840 * @cleaned_count: number of buffers to allocate this pass
841 **/
842
843 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
844 int cleaned_count, gfp_t gfp)
845 {
846 struct e1000_adapter *adapter = rx_ring->adapter;
847 struct net_device *netdev = adapter->netdev;
848 struct pci_dev *pdev = adapter->pdev;
849 union e1000_rx_desc_extended *rx_desc;
850 struct e1000_buffer *buffer_info;
851 struct sk_buff *skb;
852 unsigned int i;
853 unsigned int bufsz = 256 - 16; /* for skb_reserve */
854
855 i = rx_ring->next_to_use;
856 buffer_info = &rx_ring->buffer_info[i];
857
858 while (cleaned_count--) {
859 skb = buffer_info->skb;
860 if (skb) {
861 skb_trim(skb, 0);
862 goto check_page;
863 }
864
865 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
866 if (unlikely(!skb)) {
867 /* Better luck next round */
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871
872 buffer_info->skb = skb;
873 check_page:
874 /* allocate a new page if necessary */
875 if (!buffer_info->page) {
876 buffer_info->page = alloc_page(gfp);
877 if (unlikely(!buffer_info->page)) {
878 adapter->alloc_rx_buff_failed++;
879 break;
880 }
881 }
882
883 if (!buffer_info->dma) {
884 buffer_info->dma = dma_map_page(&pdev->dev,
885 buffer_info->page, 0,
886 PAGE_SIZE,
887 DMA_FROM_DEVICE);
888 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
889 adapter->alloc_rx_buff_failed++;
890 break;
891 }
892 }
893
894 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
895 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
896
897 if (unlikely(++i == rx_ring->count))
898 i = 0;
899 buffer_info = &rx_ring->buffer_info[i];
900 }
901
902 if (likely(rx_ring->next_to_use != i)) {
903 rx_ring->next_to_use = i;
904 if (unlikely(i-- == 0))
905 i = (rx_ring->count - 1);
906
907 /* Force memory writes to complete before letting h/w
908 * know there are new descriptors to fetch. (Only
909 * applicable for weak-ordered memory model archs,
910 * such as IA-64).
911 */
912 wmb();
913 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
914 e1000e_update_rdt_wa(rx_ring, i);
915 else
916 writel(i, rx_ring->tail);
917 }
918 }
919
920 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
921 struct sk_buff *skb)
922 {
923 if (netdev->features & NETIF_F_RXHASH)
924 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
925 }
926
927 /**
928 * e1000_clean_rx_irq - Send received data up the network stack
929 * @rx_ring: Rx descriptor ring
930 *
931 * the return value indicates whether actual cleaning was done, there
932 * is no guarantee that everything was cleaned
933 **/
934 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
935 int work_to_do)
936 {
937 struct e1000_adapter *adapter = rx_ring->adapter;
938 struct net_device *netdev = adapter->netdev;
939 struct pci_dev *pdev = adapter->pdev;
940 struct e1000_hw *hw = &adapter->hw;
941 union e1000_rx_desc_extended *rx_desc, *next_rxd;
942 struct e1000_buffer *buffer_info, *next_buffer;
943 u32 length, staterr;
944 unsigned int i;
945 int cleaned_count = 0;
946 bool cleaned = false;
947 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
948
949 i = rx_ring->next_to_clean;
950 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
951 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
952 buffer_info = &rx_ring->buffer_info[i];
953
954 while (staterr & E1000_RXD_STAT_DD) {
955 struct sk_buff *skb;
956
957 if (*work_done >= work_to_do)
958 break;
959 (*work_done)++;
960 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
961
962 skb = buffer_info->skb;
963 buffer_info->skb = NULL;
964
965 prefetch(skb->data - NET_IP_ALIGN);
966
967 i++;
968 if (i == rx_ring->count)
969 i = 0;
970 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
971 prefetch(next_rxd);
972
973 next_buffer = &rx_ring->buffer_info[i];
974
975 cleaned = true;
976 cleaned_count++;
977 dma_unmap_single(&pdev->dev, buffer_info->dma,
978 adapter->rx_buffer_len, DMA_FROM_DEVICE);
979 buffer_info->dma = 0;
980
981 length = le16_to_cpu(rx_desc->wb.upper.length);
982
983 /* !EOP means multiple descriptors were used to store a single
984 * packet, if that's the case we need to toss it. In fact, we
985 * need to toss every packet with the EOP bit clear and the
986 * next frame that _does_ have the EOP bit set, as it is by
987 * definition only a frame fragment
988 */
989 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
990 adapter->flags2 |= FLAG2_IS_DISCARDING;
991
992 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
993 /* All receives must fit into a single buffer */
994 e_dbg("Receive packet consumed multiple buffers\n");
995 /* recycle */
996 buffer_info->skb = skb;
997 if (staterr & E1000_RXD_STAT_EOP)
998 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
999 goto next_desc;
1000 }
1001
1002 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1003 !(netdev->features & NETIF_F_RXALL))) {
1004 /* recycle */
1005 buffer_info->skb = skb;
1006 goto next_desc;
1007 }
1008
1009 /* adjust length to remove Ethernet CRC */
1010 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1011 /* If configured to store CRC, don't subtract FCS,
1012 * but keep the FCS bytes out of the total_rx_bytes
1013 * counter
1014 */
1015 if (netdev->features & NETIF_F_RXFCS)
1016 total_rx_bytes -= 4;
1017 else
1018 length -= 4;
1019 }
1020
1021 total_rx_bytes += length;
1022 total_rx_packets++;
1023
1024 /* code added for copybreak, this should improve
1025 * performance for small packets with large amounts
1026 * of reassembly being done in the stack
1027 */
1028 if (length < copybreak) {
1029 struct sk_buff *new_skb =
1030 napi_alloc_skb(&adapter->napi, length);
1031 if (new_skb) {
1032 skb_copy_to_linear_data_offset(new_skb,
1033 -NET_IP_ALIGN,
1034 (skb->data -
1035 NET_IP_ALIGN),
1036 (length +
1037 NET_IP_ALIGN));
1038 /* save the skb in buffer_info as good */
1039 buffer_info->skb = skb;
1040 skb = new_skb;
1041 }
1042 /* else just continue with the old one */
1043 }
1044 /* end copybreak code */
1045 skb_put(skb, length);
1046
1047 /* Receive Checksum Offload */
1048 e1000_rx_checksum(adapter, staterr, skb);
1049
1050 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1051
1052 e1000_receive_skb(adapter, netdev, skb, staterr,
1053 rx_desc->wb.upper.vlan);
1054
1055 next_desc:
1056 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1057
1058 /* return some buffers to hardware, one at a time is too slow */
1059 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1060 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1061 GFP_ATOMIC);
1062 cleaned_count = 0;
1063 }
1064
1065 /* use prefetched values */
1066 rx_desc = next_rxd;
1067 buffer_info = next_buffer;
1068
1069 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1070 }
1071 rx_ring->next_to_clean = i;
1072
1073 cleaned_count = e1000_desc_unused(rx_ring);
1074 if (cleaned_count)
1075 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1076
1077 adapter->total_rx_bytes += total_rx_bytes;
1078 adapter->total_rx_packets += total_rx_packets;
1079 return cleaned;
1080 }
1081
1082 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1083 struct e1000_buffer *buffer_info)
1084 {
1085 struct e1000_adapter *adapter = tx_ring->adapter;
1086
1087 if (buffer_info->dma) {
1088 if (buffer_info->mapped_as_page)
1089 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1090 buffer_info->length, DMA_TO_DEVICE);
1091 else
1092 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1093 buffer_info->length, DMA_TO_DEVICE);
1094 buffer_info->dma = 0;
1095 }
1096 if (buffer_info->skb) {
1097 dev_kfree_skb_any(buffer_info->skb);
1098 buffer_info->skb = NULL;
1099 }
1100 buffer_info->time_stamp = 0;
1101 }
1102
1103 static void e1000_print_hw_hang(struct work_struct *work)
1104 {
1105 struct e1000_adapter *adapter = container_of(work,
1106 struct e1000_adapter,
1107 print_hang_task);
1108 struct net_device *netdev = adapter->netdev;
1109 struct e1000_ring *tx_ring = adapter->tx_ring;
1110 unsigned int i = tx_ring->next_to_clean;
1111 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1112 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1113 struct e1000_hw *hw = &adapter->hw;
1114 u16 phy_status, phy_1000t_status, phy_ext_status;
1115 u16 pci_status;
1116
1117 if (test_bit(__E1000_DOWN, &adapter->state))
1118 return;
1119
1120 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1121 /* May be block on write-back, flush and detect again
1122 * flush pending descriptor writebacks to memory
1123 */
1124 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1125 /* execute the writes immediately */
1126 e1e_flush();
1127 /* Due to rare timing issues, write to TIDV again to ensure
1128 * the write is successful
1129 */
1130 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1131 /* execute the writes immediately */
1132 e1e_flush();
1133 adapter->tx_hang_recheck = true;
1134 return;
1135 }
1136 adapter->tx_hang_recheck = false;
1137
1138 if (er32(TDH(0)) == er32(TDT(0))) {
1139 e_dbg("false hang detected, ignoring\n");
1140 return;
1141 }
1142
1143 /* Real hang detected */
1144 netif_stop_queue(netdev);
1145
1146 e1e_rphy(hw, MII_BMSR, &phy_status);
1147 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1148 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1149
1150 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1151
1152 /* detected Hardware unit hang */
1153 e_err("Detected Hardware Unit Hang:\n"
1154 " TDH <%x>\n"
1155 " TDT <%x>\n"
1156 " next_to_use <%x>\n"
1157 " next_to_clean <%x>\n"
1158 "buffer_info[next_to_clean]:\n"
1159 " time_stamp <%lx>\n"
1160 " next_to_watch <%x>\n"
1161 " jiffies <%lx>\n"
1162 " next_to_watch.status <%x>\n"
1163 "MAC Status <%x>\n"
1164 "PHY Status <%x>\n"
1165 "PHY 1000BASE-T Status <%x>\n"
1166 "PHY Extended Status <%x>\n"
1167 "PCI Status <%x>\n",
1168 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1169 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1170 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1171 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1172
1173 e1000e_dump(adapter);
1174
1175 /* Suggest workaround for known h/w issue */
1176 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1177 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1178 }
1179
1180 /**
1181 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1182 * @work: pointer to work struct
1183 *
1184 * This work function polls the TSYNCTXCTL valid bit to determine when a
1185 * timestamp has been taken for the current stored skb. The timestamp must
1186 * be for this skb because only one such packet is allowed in the queue.
1187 */
1188 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1189 {
1190 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1191 tx_hwtstamp_work);
1192 struct e1000_hw *hw = &adapter->hw;
1193
1194 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1195 struct skb_shared_hwtstamps shhwtstamps;
1196 u64 txstmp;
1197
1198 txstmp = er32(TXSTMPL);
1199 txstmp |= (u64)er32(TXSTMPH) << 32;
1200
1201 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1202
1203 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1204 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1205 adapter->tx_hwtstamp_skb = NULL;
1206 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1207 + adapter->tx_timeout_factor * HZ)) {
1208 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1209 adapter->tx_hwtstamp_skb = NULL;
1210 adapter->tx_hwtstamp_timeouts++;
1211 e_warn("clearing Tx timestamp hang\n");
1212 } else {
1213 /* reschedule to check later */
1214 schedule_work(&adapter->tx_hwtstamp_work);
1215 }
1216 }
1217
1218 /**
1219 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1220 * @tx_ring: Tx descriptor ring
1221 *
1222 * the return value indicates whether actual cleaning was done, there
1223 * is no guarantee that everything was cleaned
1224 **/
1225 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1226 {
1227 struct e1000_adapter *adapter = tx_ring->adapter;
1228 struct net_device *netdev = adapter->netdev;
1229 struct e1000_hw *hw = &adapter->hw;
1230 struct e1000_tx_desc *tx_desc, *eop_desc;
1231 struct e1000_buffer *buffer_info;
1232 unsigned int i, eop;
1233 unsigned int count = 0;
1234 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1235 unsigned int bytes_compl = 0, pkts_compl = 0;
1236
1237 i = tx_ring->next_to_clean;
1238 eop = tx_ring->buffer_info[i].next_to_watch;
1239 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1240
1241 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1242 (count < tx_ring->count)) {
1243 bool cleaned = false;
1244
1245 dma_rmb(); /* read buffer_info after eop_desc */
1246 for (; !cleaned; count++) {
1247 tx_desc = E1000_TX_DESC(*tx_ring, i);
1248 buffer_info = &tx_ring->buffer_info[i];
1249 cleaned = (i == eop);
1250
1251 if (cleaned) {
1252 total_tx_packets += buffer_info->segs;
1253 total_tx_bytes += buffer_info->bytecount;
1254 if (buffer_info->skb) {
1255 bytes_compl += buffer_info->skb->len;
1256 pkts_compl++;
1257 }
1258 }
1259
1260 e1000_put_txbuf(tx_ring, buffer_info);
1261 tx_desc->upper.data = 0;
1262
1263 i++;
1264 if (i == tx_ring->count)
1265 i = 0;
1266 }
1267
1268 if (i == tx_ring->next_to_use)
1269 break;
1270 eop = tx_ring->buffer_info[i].next_to_watch;
1271 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1272 }
1273
1274 tx_ring->next_to_clean = i;
1275
1276 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1277
1278 #define TX_WAKE_THRESHOLD 32
1279 if (count && netif_carrier_ok(netdev) &&
1280 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1281 /* Make sure that anybody stopping the queue after this
1282 * sees the new next_to_clean.
1283 */
1284 smp_mb();
1285
1286 if (netif_queue_stopped(netdev) &&
1287 !(test_bit(__E1000_DOWN, &adapter->state))) {
1288 netif_wake_queue(netdev);
1289 ++adapter->restart_queue;
1290 }
1291 }
1292
1293 if (adapter->detect_tx_hung) {
1294 /* Detect a transmit hang in hardware, this serializes the
1295 * check with the clearing of time_stamp and movement of i
1296 */
1297 adapter->detect_tx_hung = false;
1298 if (tx_ring->buffer_info[i].time_stamp &&
1299 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1300 + (adapter->tx_timeout_factor * HZ)) &&
1301 !(er32(STATUS) & E1000_STATUS_TXOFF))
1302 schedule_work(&adapter->print_hang_task);
1303 else
1304 adapter->tx_hang_recheck = false;
1305 }
1306 adapter->total_tx_bytes += total_tx_bytes;
1307 adapter->total_tx_packets += total_tx_packets;
1308 return count < tx_ring->count;
1309 }
1310
1311 /**
1312 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1313 * @rx_ring: Rx descriptor ring
1314 *
1315 * the return value indicates whether actual cleaning was done, there
1316 * is no guarantee that everything was cleaned
1317 **/
1318 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1319 int work_to_do)
1320 {
1321 struct e1000_adapter *adapter = rx_ring->adapter;
1322 struct e1000_hw *hw = &adapter->hw;
1323 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1324 struct net_device *netdev = adapter->netdev;
1325 struct pci_dev *pdev = adapter->pdev;
1326 struct e1000_buffer *buffer_info, *next_buffer;
1327 struct e1000_ps_page *ps_page;
1328 struct sk_buff *skb;
1329 unsigned int i, j;
1330 u32 length, staterr;
1331 int cleaned_count = 0;
1332 bool cleaned = false;
1333 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1334
1335 i = rx_ring->next_to_clean;
1336 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1337 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1338 buffer_info = &rx_ring->buffer_info[i];
1339
1340 while (staterr & E1000_RXD_STAT_DD) {
1341 if (*work_done >= work_to_do)
1342 break;
1343 (*work_done)++;
1344 skb = buffer_info->skb;
1345 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1346
1347 /* in the packet split case this is header only */
1348 prefetch(skb->data - NET_IP_ALIGN);
1349
1350 i++;
1351 if (i == rx_ring->count)
1352 i = 0;
1353 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1354 prefetch(next_rxd);
1355
1356 next_buffer = &rx_ring->buffer_info[i];
1357
1358 cleaned = true;
1359 cleaned_count++;
1360 dma_unmap_single(&pdev->dev, buffer_info->dma,
1361 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1362 buffer_info->dma = 0;
1363
1364 /* see !EOP comment in other Rx routine */
1365 if (!(staterr & E1000_RXD_STAT_EOP))
1366 adapter->flags2 |= FLAG2_IS_DISCARDING;
1367
1368 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1369 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1370 dev_kfree_skb_irq(skb);
1371 if (staterr & E1000_RXD_STAT_EOP)
1372 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1373 goto next_desc;
1374 }
1375
1376 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1377 !(netdev->features & NETIF_F_RXALL))) {
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 length = le16_to_cpu(rx_desc->wb.middle.length0);
1383
1384 if (!length) {
1385 e_dbg("Last part of the packet spanning multiple descriptors\n");
1386 dev_kfree_skb_irq(skb);
1387 goto next_desc;
1388 }
1389
1390 /* Good Receive */
1391 skb_put(skb, length);
1392
1393 {
1394 /* this looks ugly, but it seems compiler issues make
1395 * it more efficient than reusing j
1396 */
1397 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1398
1399 /* page alloc/put takes too long and effects small
1400 * packet throughput, so unsplit small packets and
1401 * save the alloc/put only valid in softirq (napi)
1402 * context to call kmap_*
1403 */
1404 if (l1 && (l1 <= copybreak) &&
1405 ((length + l1) <= adapter->rx_ps_bsize0)) {
1406 u8 *vaddr;
1407
1408 ps_page = &buffer_info->ps_pages[0];
1409
1410 /* there is no documentation about how to call
1411 * kmap_atomic, so we can't hold the mapping
1412 * very long
1413 */
1414 dma_sync_single_for_cpu(&pdev->dev,
1415 ps_page->dma,
1416 PAGE_SIZE,
1417 DMA_FROM_DEVICE);
1418 vaddr = kmap_atomic(ps_page->page);
1419 memcpy(skb_tail_pointer(skb), vaddr, l1);
1420 kunmap_atomic(vaddr);
1421 dma_sync_single_for_device(&pdev->dev,
1422 ps_page->dma,
1423 PAGE_SIZE,
1424 DMA_FROM_DEVICE);
1425
1426 /* remove the CRC */
1427 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1428 if (!(netdev->features & NETIF_F_RXFCS))
1429 l1 -= 4;
1430 }
1431
1432 skb_put(skb, l1);
1433 goto copydone;
1434 } /* if */
1435 }
1436
1437 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1438 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1439 if (!length)
1440 break;
1441
1442 ps_page = &buffer_info->ps_pages[j];
1443 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1444 DMA_FROM_DEVICE);
1445 ps_page->dma = 0;
1446 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1447 ps_page->page = NULL;
1448 skb->len += length;
1449 skb->data_len += length;
1450 skb->truesize += PAGE_SIZE;
1451 }
1452
1453 /* strip the ethernet crc, problem is we're using pages now so
1454 * this whole operation can get a little cpu intensive
1455 */
1456 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1457 if (!(netdev->features & NETIF_F_RXFCS))
1458 pskb_trim(skb, skb->len - 4);
1459 }
1460
1461 copydone:
1462 total_rx_bytes += skb->len;
1463 total_rx_packets++;
1464
1465 e1000_rx_checksum(adapter, staterr, skb);
1466
1467 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1468
1469 if (rx_desc->wb.upper.header_status &
1470 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1471 adapter->rx_hdr_split++;
1472
1473 e1000_receive_skb(adapter, netdev, skb, staterr,
1474 rx_desc->wb.middle.vlan);
1475
1476 next_desc:
1477 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1478 buffer_info->skb = NULL;
1479
1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1482 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1483 GFP_ATOMIC);
1484 cleaned_count = 0;
1485 }
1486
1487 /* use prefetched values */
1488 rx_desc = next_rxd;
1489 buffer_info = next_buffer;
1490
1491 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1492 }
1493 rx_ring->next_to_clean = i;
1494
1495 cleaned_count = e1000_desc_unused(rx_ring);
1496 if (cleaned_count)
1497 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1498
1499 adapter->total_rx_bytes += total_rx_bytes;
1500 adapter->total_rx_packets += total_rx_packets;
1501 return cleaned;
1502 }
1503
1504 /**
1505 * e1000_consume_page - helper function
1506 **/
1507 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1508 u16 length)
1509 {
1510 bi->page = NULL;
1511 skb->len += length;
1512 skb->data_len += length;
1513 skb->truesize += PAGE_SIZE;
1514 }
1515
1516 /**
1517 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1518 * @adapter: board private structure
1519 *
1520 * the return value indicates whether actual cleaning was done, there
1521 * is no guarantee that everything was cleaned
1522 **/
1523 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1524 int work_to_do)
1525 {
1526 struct e1000_adapter *adapter = rx_ring->adapter;
1527 struct net_device *netdev = adapter->netdev;
1528 struct pci_dev *pdev = adapter->pdev;
1529 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1530 struct e1000_buffer *buffer_info, *next_buffer;
1531 u32 length, staterr;
1532 unsigned int i;
1533 int cleaned_count = 0;
1534 bool cleaned = false;
1535 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1536 struct skb_shared_info *shinfo;
1537
1538 i = rx_ring->next_to_clean;
1539 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1540 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1541 buffer_info = &rx_ring->buffer_info[i];
1542
1543 while (staterr & E1000_RXD_STAT_DD) {
1544 struct sk_buff *skb;
1545
1546 if (*work_done >= work_to_do)
1547 break;
1548 (*work_done)++;
1549 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1550
1551 skb = buffer_info->skb;
1552 buffer_info->skb = NULL;
1553
1554 ++i;
1555 if (i == rx_ring->count)
1556 i = 0;
1557 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1558 prefetch(next_rxd);
1559
1560 next_buffer = &rx_ring->buffer_info[i];
1561
1562 cleaned = true;
1563 cleaned_count++;
1564 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1565 DMA_FROM_DEVICE);
1566 buffer_info->dma = 0;
1567
1568 length = le16_to_cpu(rx_desc->wb.upper.length);
1569
1570 /* errors is only valid for DD + EOP descriptors */
1571 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1572 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1573 !(netdev->features & NETIF_F_RXALL)))) {
1574 /* recycle both page and skb */
1575 buffer_info->skb = skb;
1576 /* an error means any chain goes out the window too */
1577 if (rx_ring->rx_skb_top)
1578 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1579 rx_ring->rx_skb_top = NULL;
1580 goto next_desc;
1581 }
1582 #define rxtop (rx_ring->rx_skb_top)
1583 if (!(staterr & E1000_RXD_STAT_EOP)) {
1584 /* this descriptor is only the beginning (or middle) */
1585 if (!rxtop) {
1586 /* this is the beginning of a chain */
1587 rxtop = skb;
1588 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1589 0, length);
1590 } else {
1591 /* this is the middle of a chain */
1592 shinfo = skb_shinfo(rxtop);
1593 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1594 buffer_info->page, 0,
1595 length);
1596 /* re-use the skb, only consumed the page */
1597 buffer_info->skb = skb;
1598 }
1599 e1000_consume_page(buffer_info, rxtop, length);
1600 goto next_desc;
1601 } else {
1602 if (rxtop) {
1603 /* end of the chain */
1604 shinfo = skb_shinfo(rxtop);
1605 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1606 buffer_info->page, 0,
1607 length);
1608 /* re-use the current skb, we only consumed the
1609 * page
1610 */
1611 buffer_info->skb = skb;
1612 skb = rxtop;
1613 rxtop = NULL;
1614 e1000_consume_page(buffer_info, skb, length);
1615 } else {
1616 /* no chain, got EOP, this buf is the packet
1617 * copybreak to save the put_page/alloc_page
1618 */
1619 if (length <= copybreak &&
1620 skb_tailroom(skb) >= length) {
1621 u8 *vaddr;
1622 vaddr = kmap_atomic(buffer_info->page);
1623 memcpy(skb_tail_pointer(skb), vaddr,
1624 length);
1625 kunmap_atomic(vaddr);
1626 /* re-use the page, so don't erase
1627 * buffer_info->page
1628 */
1629 skb_put(skb, length);
1630 } else {
1631 skb_fill_page_desc(skb, 0,
1632 buffer_info->page, 0,
1633 length);
1634 e1000_consume_page(buffer_info, skb,
1635 length);
1636 }
1637 }
1638 }
1639
1640 /* Receive Checksum Offload */
1641 e1000_rx_checksum(adapter, staterr, skb);
1642
1643 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1644
1645 /* probably a little skewed due to removing CRC */
1646 total_rx_bytes += skb->len;
1647 total_rx_packets++;
1648
1649 /* eth type trans needs skb->data to point to something */
1650 if (!pskb_may_pull(skb, ETH_HLEN)) {
1651 e_err("pskb_may_pull failed.\n");
1652 dev_kfree_skb_irq(skb);
1653 goto next_desc;
1654 }
1655
1656 e1000_receive_skb(adapter, netdev, skb, staterr,
1657 rx_desc->wb.upper.vlan);
1658
1659 next_desc:
1660 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1661
1662 /* return some buffers to hardware, one at a time is too slow */
1663 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1664 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1665 GFP_ATOMIC);
1666 cleaned_count = 0;
1667 }
1668
1669 /* use prefetched values */
1670 rx_desc = next_rxd;
1671 buffer_info = next_buffer;
1672
1673 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1674 }
1675 rx_ring->next_to_clean = i;
1676
1677 cleaned_count = e1000_desc_unused(rx_ring);
1678 if (cleaned_count)
1679 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1680
1681 adapter->total_rx_bytes += total_rx_bytes;
1682 adapter->total_rx_packets += total_rx_packets;
1683 return cleaned;
1684 }
1685
1686 /**
1687 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1688 * @rx_ring: Rx descriptor ring
1689 **/
1690 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1691 {
1692 struct e1000_adapter *adapter = rx_ring->adapter;
1693 struct e1000_buffer *buffer_info;
1694 struct e1000_ps_page *ps_page;
1695 struct pci_dev *pdev = adapter->pdev;
1696 unsigned int i, j;
1697
1698 /* Free all the Rx ring sk_buffs */
1699 for (i = 0; i < rx_ring->count; i++) {
1700 buffer_info = &rx_ring->buffer_info[i];
1701 if (buffer_info->dma) {
1702 if (adapter->clean_rx == e1000_clean_rx_irq)
1703 dma_unmap_single(&pdev->dev, buffer_info->dma,
1704 adapter->rx_buffer_len,
1705 DMA_FROM_DEVICE);
1706 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1707 dma_unmap_page(&pdev->dev, buffer_info->dma,
1708 PAGE_SIZE, DMA_FROM_DEVICE);
1709 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1710 dma_unmap_single(&pdev->dev, buffer_info->dma,
1711 adapter->rx_ps_bsize0,
1712 DMA_FROM_DEVICE);
1713 buffer_info->dma = 0;
1714 }
1715
1716 if (buffer_info->page) {
1717 put_page(buffer_info->page);
1718 buffer_info->page = NULL;
1719 }
1720
1721 if (buffer_info->skb) {
1722 dev_kfree_skb(buffer_info->skb);
1723 buffer_info->skb = NULL;
1724 }
1725
1726 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1727 ps_page = &buffer_info->ps_pages[j];
1728 if (!ps_page->page)
1729 break;
1730 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1731 DMA_FROM_DEVICE);
1732 ps_page->dma = 0;
1733 put_page(ps_page->page);
1734 ps_page->page = NULL;
1735 }
1736 }
1737
1738 /* there also may be some cached data from a chained receive */
1739 if (rx_ring->rx_skb_top) {
1740 dev_kfree_skb(rx_ring->rx_skb_top);
1741 rx_ring->rx_skb_top = NULL;
1742 }
1743
1744 /* Zero out the descriptor ring */
1745 memset(rx_ring->desc, 0, rx_ring->size);
1746
1747 rx_ring->next_to_clean = 0;
1748 rx_ring->next_to_use = 0;
1749 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1750 }
1751
1752 static void e1000e_downshift_workaround(struct work_struct *work)
1753 {
1754 struct e1000_adapter *adapter = container_of(work,
1755 struct e1000_adapter,
1756 downshift_task);
1757
1758 if (test_bit(__E1000_DOWN, &adapter->state))
1759 return;
1760
1761 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1762 }
1763
1764 /**
1765 * e1000_intr_msi - Interrupt Handler
1766 * @irq: interrupt number
1767 * @data: pointer to a network interface device structure
1768 **/
1769 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1770 {
1771 struct net_device *netdev = data;
1772 struct e1000_adapter *adapter = netdev_priv(netdev);
1773 struct e1000_hw *hw = &adapter->hw;
1774 u32 icr = er32(ICR);
1775
1776 /* read ICR disables interrupts using IAM */
1777 if (icr & E1000_ICR_LSC) {
1778 hw->mac.get_link_status = true;
1779 /* ICH8 workaround-- Call gig speed drop workaround on cable
1780 * disconnect (LSC) before accessing any PHY registers
1781 */
1782 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1783 (!(er32(STATUS) & E1000_STATUS_LU)))
1784 schedule_work(&adapter->downshift_task);
1785
1786 /* 80003ES2LAN workaround-- For packet buffer work-around on
1787 * link down event; disable receives here in the ISR and reset
1788 * adapter in watchdog
1789 */
1790 if (netif_carrier_ok(netdev) &&
1791 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1792 /* disable receives */
1793 u32 rctl = er32(RCTL);
1794
1795 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1796 adapter->flags |= FLAG_RESTART_NOW;
1797 }
1798 /* guard against interrupt when we're going down */
1799 if (!test_bit(__E1000_DOWN, &adapter->state))
1800 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1801 }
1802
1803 /* Reset on uncorrectable ECC error */
1804 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1805 (hw->mac.type == e1000_pch_spt))) {
1806 u32 pbeccsts = er32(PBECCSTS);
1807
1808 adapter->corr_errors +=
1809 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1810 adapter->uncorr_errors +=
1811 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1812 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1813
1814 /* Do the reset outside of interrupt context */
1815 schedule_work(&adapter->reset_task);
1816
1817 /* return immediately since reset is imminent */
1818 return IRQ_HANDLED;
1819 }
1820
1821 if (napi_schedule_prep(&adapter->napi)) {
1822 adapter->total_tx_bytes = 0;
1823 adapter->total_tx_packets = 0;
1824 adapter->total_rx_bytes = 0;
1825 adapter->total_rx_packets = 0;
1826 __napi_schedule(&adapter->napi);
1827 }
1828
1829 return IRQ_HANDLED;
1830 }
1831
1832 /**
1833 * e1000_intr - Interrupt Handler
1834 * @irq: interrupt number
1835 * @data: pointer to a network interface device structure
1836 **/
1837 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1838 {
1839 struct net_device *netdev = data;
1840 struct e1000_adapter *adapter = netdev_priv(netdev);
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 rctl, icr = er32(ICR);
1843
1844 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1845 return IRQ_NONE; /* Not our interrupt */
1846
1847 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1848 * not set, then the adapter didn't send an interrupt
1849 */
1850 if (!(icr & E1000_ICR_INT_ASSERTED))
1851 return IRQ_NONE;
1852
1853 /* Interrupt Auto-Mask...upon reading ICR,
1854 * interrupts are masked. No need for the
1855 * IMC write
1856 */
1857
1858 if (icr & E1000_ICR_LSC) {
1859 hw->mac.get_link_status = true;
1860 /* ICH8 workaround-- Call gig speed drop workaround on cable
1861 * disconnect (LSC) before accessing any PHY registers
1862 */
1863 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1864 (!(er32(STATUS) & E1000_STATUS_LU)))
1865 schedule_work(&adapter->downshift_task);
1866
1867 /* 80003ES2LAN workaround--
1868 * For packet buffer work-around on link down event;
1869 * disable receives here in the ISR and
1870 * reset adapter in watchdog
1871 */
1872 if (netif_carrier_ok(netdev) &&
1873 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1874 /* disable receives */
1875 rctl = er32(RCTL);
1876 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1877 adapter->flags |= FLAG_RESTART_NOW;
1878 }
1879 /* guard against interrupt when we're going down */
1880 if (!test_bit(__E1000_DOWN, &adapter->state))
1881 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1882 }
1883
1884 /* Reset on uncorrectable ECC error */
1885 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1886 (hw->mac.type == e1000_pch_spt))) {
1887 u32 pbeccsts = er32(PBECCSTS);
1888
1889 adapter->corr_errors +=
1890 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1891 adapter->uncorr_errors +=
1892 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1893 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1894
1895 /* Do the reset outside of interrupt context */
1896 schedule_work(&adapter->reset_task);
1897
1898 /* return immediately since reset is imminent */
1899 return IRQ_HANDLED;
1900 }
1901
1902 if (napi_schedule_prep(&adapter->napi)) {
1903 adapter->total_tx_bytes = 0;
1904 adapter->total_tx_packets = 0;
1905 adapter->total_rx_bytes = 0;
1906 adapter->total_rx_packets = 0;
1907 __napi_schedule(&adapter->napi);
1908 }
1909
1910 return IRQ_HANDLED;
1911 }
1912
1913 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1914 {
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918
1919 hw->mac.get_link_status = true;
1920
1921 /* guard against interrupt when we're going down */
1922 if (!test_bit(__E1000_DOWN, &adapter->state)) {
1923 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1924 ew32(IMS, E1000_IMS_OTHER);
1925 }
1926
1927 return IRQ_HANDLED;
1928 }
1929
1930 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1931 {
1932 struct net_device *netdev = data;
1933 struct e1000_adapter *adapter = netdev_priv(netdev);
1934 struct e1000_hw *hw = &adapter->hw;
1935 struct e1000_ring *tx_ring = adapter->tx_ring;
1936
1937 adapter->total_tx_bytes = 0;
1938 adapter->total_tx_packets = 0;
1939
1940 if (!e1000_clean_tx_irq(tx_ring))
1941 /* Ring was not completely cleaned, so fire another interrupt */
1942 ew32(ICS, tx_ring->ims_val);
1943
1944 if (!test_bit(__E1000_DOWN, &adapter->state))
1945 ew32(IMS, adapter->tx_ring->ims_val);
1946
1947 return IRQ_HANDLED;
1948 }
1949
1950 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1951 {
1952 struct net_device *netdev = data;
1953 struct e1000_adapter *adapter = netdev_priv(netdev);
1954 struct e1000_ring *rx_ring = adapter->rx_ring;
1955
1956 /* Write the ITR value calculated at the end of the
1957 * previous interrupt.
1958 */
1959 if (rx_ring->set_itr) {
1960 u32 itr = rx_ring->itr_val ?
1961 1000000000 / (rx_ring->itr_val * 256) : 0;
1962
1963 writel(itr, rx_ring->itr_register);
1964 rx_ring->set_itr = 0;
1965 }
1966
1967 if (napi_schedule_prep(&adapter->napi)) {
1968 adapter->total_rx_bytes = 0;
1969 adapter->total_rx_packets = 0;
1970 __napi_schedule(&adapter->napi);
1971 }
1972 return IRQ_HANDLED;
1973 }
1974
1975 /**
1976 * e1000_configure_msix - Configure MSI-X hardware
1977 *
1978 * e1000_configure_msix sets up the hardware to properly
1979 * generate MSI-X interrupts.
1980 **/
1981 static void e1000_configure_msix(struct e1000_adapter *adapter)
1982 {
1983 struct e1000_hw *hw = &adapter->hw;
1984 struct e1000_ring *rx_ring = adapter->rx_ring;
1985 struct e1000_ring *tx_ring = adapter->tx_ring;
1986 int vector = 0;
1987 u32 ctrl_ext, ivar = 0;
1988
1989 adapter->eiac_mask = 0;
1990
1991 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1992 if (hw->mac.type == e1000_82574) {
1993 u32 rfctl = er32(RFCTL);
1994
1995 rfctl |= E1000_RFCTL_ACK_DIS;
1996 ew32(RFCTL, rfctl);
1997 }
1998
1999 /* Configure Rx vector */
2000 rx_ring->ims_val = E1000_IMS_RXQ0;
2001 adapter->eiac_mask |= rx_ring->ims_val;
2002 if (rx_ring->itr_val)
2003 writel(1000000000 / (rx_ring->itr_val * 256),
2004 rx_ring->itr_register);
2005 else
2006 writel(1, rx_ring->itr_register);
2007 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2008
2009 /* Configure Tx vector */
2010 tx_ring->ims_val = E1000_IMS_TXQ0;
2011 vector++;
2012 if (tx_ring->itr_val)
2013 writel(1000000000 / (tx_ring->itr_val * 256),
2014 tx_ring->itr_register);
2015 else
2016 writel(1, tx_ring->itr_register);
2017 adapter->eiac_mask |= tx_ring->ims_val;
2018 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2019
2020 /* set vector for Other Causes, e.g. link changes */
2021 vector++;
2022 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2023 if (rx_ring->itr_val)
2024 writel(1000000000 / (rx_ring->itr_val * 256),
2025 hw->hw_addr + E1000_EITR_82574(vector));
2026 else
2027 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2028 adapter->eiac_mask |= E1000_IMS_OTHER;
2029
2030 /* Cause Tx interrupts on every write back */
2031 ivar |= BIT(31);
2032
2033 ew32(IVAR, ivar);
2034
2035 /* enable MSI-X PBA support */
2036 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2037 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2038 ew32(CTRL_EXT, ctrl_ext);
2039 e1e_flush();
2040 }
2041
2042 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2043 {
2044 if (adapter->msix_entries) {
2045 pci_disable_msix(adapter->pdev);
2046 kfree(adapter->msix_entries);
2047 adapter->msix_entries = NULL;
2048 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2049 pci_disable_msi(adapter->pdev);
2050 adapter->flags &= ~FLAG_MSI_ENABLED;
2051 }
2052 }
2053
2054 /**
2055 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2056 *
2057 * Attempt to configure interrupts using the best available
2058 * capabilities of the hardware and kernel.
2059 **/
2060 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2061 {
2062 int err;
2063 int i;
2064
2065 switch (adapter->int_mode) {
2066 case E1000E_INT_MODE_MSIX:
2067 if (adapter->flags & FLAG_HAS_MSIX) {
2068 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2069 adapter->msix_entries = kcalloc(adapter->num_vectors,
2070 sizeof(struct
2071 msix_entry),
2072 GFP_KERNEL);
2073 if (adapter->msix_entries) {
2074 struct e1000_adapter *a = adapter;
2075
2076 for (i = 0; i < adapter->num_vectors; i++)
2077 adapter->msix_entries[i].entry = i;
2078
2079 err = pci_enable_msix_range(a->pdev,
2080 a->msix_entries,
2081 a->num_vectors,
2082 a->num_vectors);
2083 if (err > 0)
2084 return;
2085 }
2086 /* MSI-X failed, so fall through and try MSI */
2087 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2088 e1000e_reset_interrupt_capability(adapter);
2089 }
2090 adapter->int_mode = E1000E_INT_MODE_MSI;
2091 /* Fall through */
2092 case E1000E_INT_MODE_MSI:
2093 if (!pci_enable_msi(adapter->pdev)) {
2094 adapter->flags |= FLAG_MSI_ENABLED;
2095 } else {
2096 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2097 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2098 }
2099 /* Fall through */
2100 case E1000E_INT_MODE_LEGACY:
2101 /* Don't do anything; this is the system default */
2102 break;
2103 }
2104
2105 /* store the number of vectors being used */
2106 adapter->num_vectors = 1;
2107 }
2108
2109 /**
2110 * e1000_request_msix - Initialize MSI-X interrupts
2111 *
2112 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2113 * kernel.
2114 **/
2115 static int e1000_request_msix(struct e1000_adapter *adapter)
2116 {
2117 struct net_device *netdev = adapter->netdev;
2118 int err = 0, vector = 0;
2119
2120 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2121 snprintf(adapter->rx_ring->name,
2122 sizeof(adapter->rx_ring->name) - 1,
2123 "%s-rx-0", netdev->name);
2124 else
2125 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2126 err = request_irq(adapter->msix_entries[vector].vector,
2127 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2128 netdev);
2129 if (err)
2130 return err;
2131 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2132 E1000_EITR_82574(vector);
2133 adapter->rx_ring->itr_val = adapter->itr;
2134 vector++;
2135
2136 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2137 snprintf(adapter->tx_ring->name,
2138 sizeof(adapter->tx_ring->name) - 1,
2139 "%s-tx-0", netdev->name);
2140 else
2141 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2142 err = request_irq(adapter->msix_entries[vector].vector,
2143 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2144 netdev);
2145 if (err)
2146 return err;
2147 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2148 E1000_EITR_82574(vector);
2149 adapter->tx_ring->itr_val = adapter->itr;
2150 vector++;
2151
2152 err = request_irq(adapter->msix_entries[vector].vector,
2153 e1000_msix_other, 0, netdev->name, netdev);
2154 if (err)
2155 return err;
2156
2157 e1000_configure_msix(adapter);
2158
2159 return 0;
2160 }
2161
2162 /**
2163 * e1000_request_irq - initialize interrupts
2164 *
2165 * Attempts to configure interrupts using the best available
2166 * capabilities of the hardware and kernel.
2167 **/
2168 static int e1000_request_irq(struct e1000_adapter *adapter)
2169 {
2170 struct net_device *netdev = adapter->netdev;
2171 int err;
2172
2173 if (adapter->msix_entries) {
2174 err = e1000_request_msix(adapter);
2175 if (!err)
2176 return err;
2177 /* fall back to MSI */
2178 e1000e_reset_interrupt_capability(adapter);
2179 adapter->int_mode = E1000E_INT_MODE_MSI;
2180 e1000e_set_interrupt_capability(adapter);
2181 }
2182 if (adapter->flags & FLAG_MSI_ENABLED) {
2183 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2184 netdev->name, netdev);
2185 if (!err)
2186 return err;
2187
2188 /* fall back to legacy interrupt */
2189 e1000e_reset_interrupt_capability(adapter);
2190 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2191 }
2192
2193 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2194 netdev->name, netdev);
2195 if (err)
2196 e_err("Unable to allocate interrupt, Error: %d\n", err);
2197
2198 return err;
2199 }
2200
2201 static void e1000_free_irq(struct e1000_adapter *adapter)
2202 {
2203 struct net_device *netdev = adapter->netdev;
2204
2205 if (adapter->msix_entries) {
2206 int vector = 0;
2207
2208 free_irq(adapter->msix_entries[vector].vector, netdev);
2209 vector++;
2210
2211 free_irq(adapter->msix_entries[vector].vector, netdev);
2212 vector++;
2213
2214 /* Other Causes interrupt vector */
2215 free_irq(adapter->msix_entries[vector].vector, netdev);
2216 return;
2217 }
2218
2219 free_irq(adapter->pdev->irq, netdev);
2220 }
2221
2222 /**
2223 * e1000_irq_disable - Mask off interrupt generation on the NIC
2224 **/
2225 static void e1000_irq_disable(struct e1000_adapter *adapter)
2226 {
2227 struct e1000_hw *hw = &adapter->hw;
2228
2229 ew32(IMC, ~0);
2230 if (adapter->msix_entries)
2231 ew32(EIAC_82574, 0);
2232 e1e_flush();
2233
2234 if (adapter->msix_entries) {
2235 int i;
2236
2237 for (i = 0; i < adapter->num_vectors; i++)
2238 synchronize_irq(adapter->msix_entries[i].vector);
2239 } else {
2240 synchronize_irq(adapter->pdev->irq);
2241 }
2242 }
2243
2244 /**
2245 * e1000_irq_enable - Enable default interrupt generation settings
2246 **/
2247 static void e1000_irq_enable(struct e1000_adapter *adapter)
2248 {
2249 struct e1000_hw *hw = &adapter->hw;
2250
2251 if (adapter->msix_entries) {
2252 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2253 ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);
2254 } else if ((hw->mac.type == e1000_pch_lpt) ||
2255 (hw->mac.type == e1000_pch_spt)) {
2256 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2257 } else {
2258 ew32(IMS, IMS_ENABLE_MASK);
2259 }
2260 e1e_flush();
2261 }
2262
2263 /**
2264 * e1000e_get_hw_control - get control of the h/w from f/w
2265 * @adapter: address of board private structure
2266 *
2267 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2268 * For ASF and Pass Through versions of f/w this means that
2269 * the driver is loaded. For AMT version (only with 82573)
2270 * of the f/w this means that the network i/f is open.
2271 **/
2272 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2273 {
2274 struct e1000_hw *hw = &adapter->hw;
2275 u32 ctrl_ext;
2276 u32 swsm;
2277
2278 /* Let firmware know the driver has taken over */
2279 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2280 swsm = er32(SWSM);
2281 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2282 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2283 ctrl_ext = er32(CTRL_EXT);
2284 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2285 }
2286 }
2287
2288 /**
2289 * e1000e_release_hw_control - release control of the h/w to f/w
2290 * @adapter: address of board private structure
2291 *
2292 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2293 * For ASF and Pass Through versions of f/w this means that the
2294 * driver is no longer loaded. For AMT version (only with 82573) i
2295 * of the f/w this means that the network i/f is closed.
2296 *
2297 **/
2298 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2299 {
2300 struct e1000_hw *hw = &adapter->hw;
2301 u32 ctrl_ext;
2302 u32 swsm;
2303
2304 /* Let firmware taken over control of h/w */
2305 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2306 swsm = er32(SWSM);
2307 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2308 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2309 ctrl_ext = er32(CTRL_EXT);
2310 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2311 }
2312 }
2313
2314 /**
2315 * e1000_alloc_ring_dma - allocate memory for a ring structure
2316 **/
2317 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2318 struct e1000_ring *ring)
2319 {
2320 struct pci_dev *pdev = adapter->pdev;
2321
2322 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2323 GFP_KERNEL);
2324 if (!ring->desc)
2325 return -ENOMEM;
2326
2327 return 0;
2328 }
2329
2330 /**
2331 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2332 * @tx_ring: Tx descriptor ring
2333 *
2334 * Return 0 on success, negative on failure
2335 **/
2336 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2337 {
2338 struct e1000_adapter *adapter = tx_ring->adapter;
2339 int err = -ENOMEM, size;
2340
2341 size = sizeof(struct e1000_buffer) * tx_ring->count;
2342 tx_ring->buffer_info = vzalloc(size);
2343 if (!tx_ring->buffer_info)
2344 goto err;
2345
2346 /* round up to nearest 4K */
2347 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2348 tx_ring->size = ALIGN(tx_ring->size, 4096);
2349
2350 err = e1000_alloc_ring_dma(adapter, tx_ring);
2351 if (err)
2352 goto err;
2353
2354 tx_ring->next_to_use = 0;
2355 tx_ring->next_to_clean = 0;
2356
2357 return 0;
2358 err:
2359 vfree(tx_ring->buffer_info);
2360 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2361 return err;
2362 }
2363
2364 /**
2365 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2366 * @rx_ring: Rx descriptor ring
2367 *
2368 * Returns 0 on success, negative on failure
2369 **/
2370 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2371 {
2372 struct e1000_adapter *adapter = rx_ring->adapter;
2373 struct e1000_buffer *buffer_info;
2374 int i, size, desc_len, err = -ENOMEM;
2375
2376 size = sizeof(struct e1000_buffer) * rx_ring->count;
2377 rx_ring->buffer_info = vzalloc(size);
2378 if (!rx_ring->buffer_info)
2379 goto err;
2380
2381 for (i = 0; i < rx_ring->count; i++) {
2382 buffer_info = &rx_ring->buffer_info[i];
2383 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2384 sizeof(struct e1000_ps_page),
2385 GFP_KERNEL);
2386 if (!buffer_info->ps_pages)
2387 goto err_pages;
2388 }
2389
2390 desc_len = sizeof(union e1000_rx_desc_packet_split);
2391
2392 /* Round up to nearest 4K */
2393 rx_ring->size = rx_ring->count * desc_len;
2394 rx_ring->size = ALIGN(rx_ring->size, 4096);
2395
2396 err = e1000_alloc_ring_dma(adapter, rx_ring);
2397 if (err)
2398 goto err_pages;
2399
2400 rx_ring->next_to_clean = 0;
2401 rx_ring->next_to_use = 0;
2402 rx_ring->rx_skb_top = NULL;
2403
2404 return 0;
2405
2406 err_pages:
2407 for (i = 0; i < rx_ring->count; i++) {
2408 buffer_info = &rx_ring->buffer_info[i];
2409 kfree(buffer_info->ps_pages);
2410 }
2411 err:
2412 vfree(rx_ring->buffer_info);
2413 e_err("Unable to allocate memory for the receive descriptor ring\n");
2414 return err;
2415 }
2416
2417 /**
2418 * e1000_clean_tx_ring - Free Tx Buffers
2419 * @tx_ring: Tx descriptor ring
2420 **/
2421 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2422 {
2423 struct e1000_adapter *adapter = tx_ring->adapter;
2424 struct e1000_buffer *buffer_info;
2425 unsigned long size;
2426 unsigned int i;
2427
2428 for (i = 0; i < tx_ring->count; i++) {
2429 buffer_info = &tx_ring->buffer_info[i];
2430 e1000_put_txbuf(tx_ring, buffer_info);
2431 }
2432
2433 netdev_reset_queue(adapter->netdev);
2434 size = sizeof(struct e1000_buffer) * tx_ring->count;
2435 memset(tx_ring->buffer_info, 0, size);
2436
2437 memset(tx_ring->desc, 0, tx_ring->size);
2438
2439 tx_ring->next_to_use = 0;
2440 tx_ring->next_to_clean = 0;
2441 }
2442
2443 /**
2444 * e1000e_free_tx_resources - Free Tx Resources per Queue
2445 * @tx_ring: Tx descriptor ring
2446 *
2447 * Free all transmit software resources
2448 **/
2449 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2450 {
2451 struct e1000_adapter *adapter = tx_ring->adapter;
2452 struct pci_dev *pdev = adapter->pdev;
2453
2454 e1000_clean_tx_ring(tx_ring);
2455
2456 vfree(tx_ring->buffer_info);
2457 tx_ring->buffer_info = NULL;
2458
2459 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2460 tx_ring->dma);
2461 tx_ring->desc = NULL;
2462 }
2463
2464 /**
2465 * e1000e_free_rx_resources - Free Rx Resources
2466 * @rx_ring: Rx descriptor ring
2467 *
2468 * Free all receive software resources
2469 **/
2470 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2471 {
2472 struct e1000_adapter *adapter = rx_ring->adapter;
2473 struct pci_dev *pdev = adapter->pdev;
2474 int i;
2475
2476 e1000_clean_rx_ring(rx_ring);
2477
2478 for (i = 0; i < rx_ring->count; i++)
2479 kfree(rx_ring->buffer_info[i].ps_pages);
2480
2481 vfree(rx_ring->buffer_info);
2482 rx_ring->buffer_info = NULL;
2483
2484 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2485 rx_ring->dma);
2486 rx_ring->desc = NULL;
2487 }
2488
2489 /**
2490 * e1000_update_itr - update the dynamic ITR value based on statistics
2491 * @adapter: pointer to adapter
2492 * @itr_setting: current adapter->itr
2493 * @packets: the number of packets during this measurement interval
2494 * @bytes: the number of bytes during this measurement interval
2495 *
2496 * Stores a new ITR value based on packets and byte
2497 * counts during the last interrupt. The advantage of per interrupt
2498 * computation is faster updates and more accurate ITR for the current
2499 * traffic pattern. Constants in this function were computed
2500 * based on theoretical maximum wire speed and thresholds were set based
2501 * on testing data as well as attempting to minimize response time
2502 * while increasing bulk throughput. This functionality is controlled
2503 * by the InterruptThrottleRate module parameter.
2504 **/
2505 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2506 {
2507 unsigned int retval = itr_setting;
2508
2509 if (packets == 0)
2510 return itr_setting;
2511
2512 switch (itr_setting) {
2513 case lowest_latency:
2514 /* handle TSO and jumbo frames */
2515 if (bytes / packets > 8000)
2516 retval = bulk_latency;
2517 else if ((packets < 5) && (bytes > 512))
2518 retval = low_latency;
2519 break;
2520 case low_latency: /* 50 usec aka 20000 ints/s */
2521 if (bytes > 10000) {
2522 /* this if handles the TSO accounting */
2523 if (bytes / packets > 8000)
2524 retval = bulk_latency;
2525 else if ((packets < 10) || ((bytes / packets) > 1200))
2526 retval = bulk_latency;
2527 else if ((packets > 35))
2528 retval = lowest_latency;
2529 } else if (bytes / packets > 2000) {
2530 retval = bulk_latency;
2531 } else if (packets <= 2 && bytes < 512) {
2532 retval = lowest_latency;
2533 }
2534 break;
2535 case bulk_latency: /* 250 usec aka 4000 ints/s */
2536 if (bytes > 25000) {
2537 if (packets > 35)
2538 retval = low_latency;
2539 } else if (bytes < 6000) {
2540 retval = low_latency;
2541 }
2542 break;
2543 }
2544
2545 return retval;
2546 }
2547
2548 static void e1000_set_itr(struct e1000_adapter *adapter)
2549 {
2550 u16 current_itr;
2551 u32 new_itr = adapter->itr;
2552
2553 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2554 if (adapter->link_speed != SPEED_1000) {
2555 current_itr = 0;
2556 new_itr = 4000;
2557 goto set_itr_now;
2558 }
2559
2560 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2561 new_itr = 0;
2562 goto set_itr_now;
2563 }
2564
2565 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2566 adapter->total_tx_packets,
2567 adapter->total_tx_bytes);
2568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2569 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2570 adapter->tx_itr = low_latency;
2571
2572 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2573 adapter->total_rx_packets,
2574 adapter->total_rx_bytes);
2575 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2576 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2577 adapter->rx_itr = low_latency;
2578
2579 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2580
2581 /* counts and packets in update_itr are dependent on these numbers */
2582 switch (current_itr) {
2583 case lowest_latency:
2584 new_itr = 70000;
2585 break;
2586 case low_latency:
2587 new_itr = 20000; /* aka hwitr = ~200 */
2588 break;
2589 case bulk_latency:
2590 new_itr = 4000;
2591 break;
2592 default:
2593 break;
2594 }
2595
2596 set_itr_now:
2597 if (new_itr != adapter->itr) {
2598 /* this attempts to bias the interrupt rate towards Bulk
2599 * by adding intermediate steps when interrupt rate is
2600 * increasing
2601 */
2602 new_itr = new_itr > adapter->itr ?
2603 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2604 adapter->itr = new_itr;
2605 adapter->rx_ring->itr_val = new_itr;
2606 if (adapter->msix_entries)
2607 adapter->rx_ring->set_itr = 1;
2608 else
2609 e1000e_write_itr(adapter, new_itr);
2610 }
2611 }
2612
2613 /**
2614 * e1000e_write_itr - write the ITR value to the appropriate registers
2615 * @adapter: address of board private structure
2616 * @itr: new ITR value to program
2617 *
2618 * e1000e_write_itr determines if the adapter is in MSI-X mode
2619 * and, if so, writes the EITR registers with the ITR value.
2620 * Otherwise, it writes the ITR value into the ITR register.
2621 **/
2622 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2623 {
2624 struct e1000_hw *hw = &adapter->hw;
2625 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2626
2627 if (adapter->msix_entries) {
2628 int vector;
2629
2630 for (vector = 0; vector < adapter->num_vectors; vector++)
2631 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2632 } else {
2633 ew32(ITR, new_itr);
2634 }
2635 }
2636
2637 /**
2638 * e1000_alloc_queues - Allocate memory for all rings
2639 * @adapter: board private structure to initialize
2640 **/
2641 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2642 {
2643 int size = sizeof(struct e1000_ring);
2644
2645 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2646 if (!adapter->tx_ring)
2647 goto err;
2648 adapter->tx_ring->count = adapter->tx_ring_count;
2649 adapter->tx_ring->adapter = adapter;
2650
2651 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2652 if (!adapter->rx_ring)
2653 goto err;
2654 adapter->rx_ring->count = adapter->rx_ring_count;
2655 adapter->rx_ring->adapter = adapter;
2656
2657 return 0;
2658 err:
2659 e_err("Unable to allocate memory for queues\n");
2660 kfree(adapter->rx_ring);
2661 kfree(adapter->tx_ring);
2662 return -ENOMEM;
2663 }
2664
2665 /**
2666 * e1000e_poll - NAPI Rx polling callback
2667 * @napi: struct associated with this polling callback
2668 * @weight: number of packets driver is allowed to process this poll
2669 **/
2670 static int e1000e_poll(struct napi_struct *napi, int weight)
2671 {
2672 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2673 napi);
2674 struct e1000_hw *hw = &adapter->hw;
2675 struct net_device *poll_dev = adapter->netdev;
2676 int tx_cleaned = 1, work_done = 0;
2677
2678 adapter = netdev_priv(poll_dev);
2679
2680 if (!adapter->msix_entries ||
2681 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2682 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2683
2684 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
2685
2686 if (!tx_cleaned)
2687 work_done = weight;
2688
2689 /* If weight not fully consumed, exit the polling mode */
2690 if (work_done < weight) {
2691 if (adapter->itr_setting & 3)
2692 e1000_set_itr(adapter);
2693 napi_complete_done(napi, work_done);
2694 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2695 if (adapter->msix_entries)
2696 ew32(IMS, adapter->rx_ring->ims_val);
2697 else
2698 e1000_irq_enable(adapter);
2699 }
2700 }
2701
2702 return work_done;
2703 }
2704
2705 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2706 __always_unused __be16 proto, u16 vid)
2707 {
2708 struct e1000_adapter *adapter = netdev_priv(netdev);
2709 struct e1000_hw *hw = &adapter->hw;
2710 u32 vfta, index;
2711
2712 /* don't update vlan cookie if already programmed */
2713 if ((adapter->hw.mng_cookie.status &
2714 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2715 (vid == adapter->mng_vlan_id))
2716 return 0;
2717
2718 /* add VID to filter table */
2719 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2720 index = (vid >> 5) & 0x7F;
2721 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2722 vfta |= BIT((vid & 0x1F));
2723 hw->mac.ops.write_vfta(hw, index, vfta);
2724 }
2725
2726 set_bit(vid, adapter->active_vlans);
2727
2728 return 0;
2729 }
2730
2731 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2732 __always_unused __be16 proto, u16 vid)
2733 {
2734 struct e1000_adapter *adapter = netdev_priv(netdev);
2735 struct e1000_hw *hw = &adapter->hw;
2736 u32 vfta, index;
2737
2738 if ((adapter->hw.mng_cookie.status &
2739 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2740 (vid == adapter->mng_vlan_id)) {
2741 /* release control to f/w */
2742 e1000e_release_hw_control(adapter);
2743 return 0;
2744 }
2745
2746 /* remove VID from filter table */
2747 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2748 index = (vid >> 5) & 0x7F;
2749 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2750 vfta &= ~BIT((vid & 0x1F));
2751 hw->mac.ops.write_vfta(hw, index, vfta);
2752 }
2753
2754 clear_bit(vid, adapter->active_vlans);
2755
2756 return 0;
2757 }
2758
2759 /**
2760 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2761 * @adapter: board private structure to initialize
2762 **/
2763 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2764 {
2765 struct net_device *netdev = adapter->netdev;
2766 struct e1000_hw *hw = &adapter->hw;
2767 u32 rctl;
2768
2769 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2770 /* disable VLAN receive filtering */
2771 rctl = er32(RCTL);
2772 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2773 ew32(RCTL, rctl);
2774
2775 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2776 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2777 adapter->mng_vlan_id);
2778 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2779 }
2780 }
2781 }
2782
2783 /**
2784 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2785 * @adapter: board private structure to initialize
2786 **/
2787 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2788 {
2789 struct e1000_hw *hw = &adapter->hw;
2790 u32 rctl;
2791
2792 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2793 /* enable VLAN receive filtering */
2794 rctl = er32(RCTL);
2795 rctl |= E1000_RCTL_VFE;
2796 rctl &= ~E1000_RCTL_CFIEN;
2797 ew32(RCTL, rctl);
2798 }
2799 }
2800
2801 /**
2802 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2803 * @adapter: board private structure to initialize
2804 **/
2805 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2806 {
2807 struct e1000_hw *hw = &adapter->hw;
2808 u32 ctrl;
2809
2810 /* disable VLAN tag insert/strip */
2811 ctrl = er32(CTRL);
2812 ctrl &= ~E1000_CTRL_VME;
2813 ew32(CTRL, ctrl);
2814 }
2815
2816 /**
2817 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2818 * @adapter: board private structure to initialize
2819 **/
2820 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2821 {
2822 struct e1000_hw *hw = &adapter->hw;
2823 u32 ctrl;
2824
2825 /* enable VLAN tag insert/strip */
2826 ctrl = er32(CTRL);
2827 ctrl |= E1000_CTRL_VME;
2828 ew32(CTRL, ctrl);
2829 }
2830
2831 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2832 {
2833 struct net_device *netdev = adapter->netdev;
2834 u16 vid = adapter->hw.mng_cookie.vlan_id;
2835 u16 old_vid = adapter->mng_vlan_id;
2836
2837 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2838 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2839 adapter->mng_vlan_id = vid;
2840 }
2841
2842 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2843 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2844 }
2845
2846 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2847 {
2848 u16 vid;
2849
2850 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2851
2852 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2853 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2854 }
2855
2856 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2857 {
2858 struct e1000_hw *hw = &adapter->hw;
2859 u32 manc, manc2h, mdef, i, j;
2860
2861 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2862 return;
2863
2864 manc = er32(MANC);
2865
2866 /* enable receiving management packets to the host. this will probably
2867 * generate destination unreachable messages from the host OS, but
2868 * the packets will be handled on SMBUS
2869 */
2870 manc |= E1000_MANC_EN_MNG2HOST;
2871 manc2h = er32(MANC2H);
2872
2873 switch (hw->mac.type) {
2874 default:
2875 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2876 break;
2877 case e1000_82574:
2878 case e1000_82583:
2879 /* Check if IPMI pass-through decision filter already exists;
2880 * if so, enable it.
2881 */
2882 for (i = 0, j = 0; i < 8; i++) {
2883 mdef = er32(MDEF(i));
2884
2885 /* Ignore filters with anything other than IPMI ports */
2886 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2887 continue;
2888
2889 /* Enable this decision filter in MANC2H */
2890 if (mdef)
2891 manc2h |= BIT(i);
2892
2893 j |= mdef;
2894 }
2895
2896 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2897 break;
2898
2899 /* Create new decision filter in an empty filter */
2900 for (i = 0, j = 0; i < 8; i++)
2901 if (er32(MDEF(i)) == 0) {
2902 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2903 E1000_MDEF_PORT_664));
2904 manc2h |= BIT(1);
2905 j++;
2906 break;
2907 }
2908
2909 if (!j)
2910 e_warn("Unable to create IPMI pass-through filter\n");
2911 break;
2912 }
2913
2914 ew32(MANC2H, manc2h);
2915 ew32(MANC, manc);
2916 }
2917
2918 /**
2919 * e1000_configure_tx - Configure Transmit Unit after Reset
2920 * @adapter: board private structure
2921 *
2922 * Configure the Tx unit of the MAC after a reset.
2923 **/
2924 static void e1000_configure_tx(struct e1000_adapter *adapter)
2925 {
2926 struct e1000_hw *hw = &adapter->hw;
2927 struct e1000_ring *tx_ring = adapter->tx_ring;
2928 u64 tdba;
2929 u32 tdlen, tctl, tarc;
2930
2931 /* Setup the HW Tx Head and Tail descriptor pointers */
2932 tdba = tx_ring->dma;
2933 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2934 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2935 ew32(TDBAH(0), (tdba >> 32));
2936 ew32(TDLEN(0), tdlen);
2937 ew32(TDH(0), 0);
2938 ew32(TDT(0), 0);
2939 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2940 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2941
2942 writel(0, tx_ring->head);
2943 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2944 e1000e_update_tdt_wa(tx_ring, 0);
2945 else
2946 writel(0, tx_ring->tail);
2947
2948 /* Set the Tx Interrupt Delay register */
2949 ew32(TIDV, adapter->tx_int_delay);
2950 /* Tx irq moderation */
2951 ew32(TADV, adapter->tx_abs_int_delay);
2952
2953 if (adapter->flags2 & FLAG2_DMA_BURST) {
2954 u32 txdctl = er32(TXDCTL(0));
2955
2956 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2957 E1000_TXDCTL_WTHRESH);
2958 /* set up some performance related parameters to encourage the
2959 * hardware to use the bus more efficiently in bursts, depends
2960 * on the tx_int_delay to be enabled,
2961 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2962 * hthresh = 1 ==> prefetch when one or more available
2963 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2964 * BEWARE: this seems to work but should be considered first if
2965 * there are Tx hangs or other Tx related bugs
2966 */
2967 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2968 ew32(TXDCTL(0), txdctl);
2969 }
2970 /* erratum work around: set txdctl the same for both queues */
2971 ew32(TXDCTL(1), er32(TXDCTL(0)));
2972
2973 /* Program the Transmit Control Register */
2974 tctl = er32(TCTL);
2975 tctl &= ~E1000_TCTL_CT;
2976 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2977 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2978
2979 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2980 tarc = er32(TARC(0));
2981 /* set the speed mode bit, we'll clear it if we're not at
2982 * gigabit link later
2983 */
2984 #define SPEED_MODE_BIT BIT(21)
2985 tarc |= SPEED_MODE_BIT;
2986 ew32(TARC(0), tarc);
2987 }
2988
2989 /* errata: program both queues to unweighted RR */
2990 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2991 tarc = er32(TARC(0));
2992 tarc |= 1;
2993 ew32(TARC(0), tarc);
2994 tarc = er32(TARC(1));
2995 tarc |= 1;
2996 ew32(TARC(1), tarc);
2997 }
2998
2999 /* Setup Transmit Descriptor Settings for eop descriptor */
3000 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3001
3002 /* only set IDE if we are delaying interrupts using the timers */
3003 if (adapter->tx_int_delay)
3004 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3005
3006 /* enable Report Status bit */
3007 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3008
3009 ew32(TCTL, tctl);
3010
3011 hw->mac.ops.config_collision_dist(hw);
3012
3013 /* SPT Si errata workaround to avoid data corruption */
3014 if (hw->mac.type == e1000_pch_spt) {
3015 u32 reg_val;
3016
3017 reg_val = er32(IOSFPC);
3018 reg_val |= E1000_RCTL_RDMTS_HEX;
3019 ew32(IOSFPC, reg_val);
3020
3021 reg_val = er32(TARC(0));
3022 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3023 ew32(TARC(0), reg_val);
3024 }
3025 }
3026
3027 /**
3028 * e1000_setup_rctl - configure the receive control registers
3029 * @adapter: Board private structure
3030 **/
3031 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3032 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3033 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3034 {
3035 struct e1000_hw *hw = &adapter->hw;
3036 u32 rctl, rfctl;
3037 u32 pages = 0;
3038
3039 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3040 * If jumbo frames not set, program related MAC/PHY registers
3041 * to h/w defaults
3042 */
3043 if (hw->mac.type >= e1000_pch2lan) {
3044 s32 ret_val;
3045
3046 if (adapter->netdev->mtu > ETH_DATA_LEN)
3047 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3048 else
3049 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3050
3051 if (ret_val)
3052 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3053 }
3054
3055 /* Program MC offset vector base */
3056 rctl = er32(RCTL);
3057 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3058 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3059 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3060 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3061
3062 /* Do not Store bad packets */
3063 rctl &= ~E1000_RCTL_SBP;
3064
3065 /* Enable Long Packet receive */
3066 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3067 rctl &= ~E1000_RCTL_LPE;
3068 else
3069 rctl |= E1000_RCTL_LPE;
3070
3071 /* Some systems expect that the CRC is included in SMBUS traffic. The
3072 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3073 * host memory when this is enabled
3074 */
3075 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3076 rctl |= E1000_RCTL_SECRC;
3077
3078 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3079 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3080 u16 phy_data;
3081
3082 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3083 phy_data &= 0xfff8;
3084 phy_data |= BIT(2);
3085 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3086
3087 e1e_rphy(hw, 22, &phy_data);
3088 phy_data &= 0x0fff;
3089 phy_data |= BIT(14);
3090 e1e_wphy(hw, 0x10, 0x2823);
3091 e1e_wphy(hw, 0x11, 0x0003);
3092 e1e_wphy(hw, 22, phy_data);
3093 }
3094
3095 /* Setup buffer sizes */
3096 rctl &= ~E1000_RCTL_SZ_4096;
3097 rctl |= E1000_RCTL_BSEX;
3098 switch (adapter->rx_buffer_len) {
3099 case 2048:
3100 default:
3101 rctl |= E1000_RCTL_SZ_2048;
3102 rctl &= ~E1000_RCTL_BSEX;
3103 break;
3104 case 4096:
3105 rctl |= E1000_RCTL_SZ_4096;
3106 break;
3107 case 8192:
3108 rctl |= E1000_RCTL_SZ_8192;
3109 break;
3110 case 16384:
3111 rctl |= E1000_RCTL_SZ_16384;
3112 break;
3113 }
3114
3115 /* Enable Extended Status in all Receive Descriptors */
3116 rfctl = er32(RFCTL);
3117 rfctl |= E1000_RFCTL_EXTEN;
3118 ew32(RFCTL, rfctl);
3119
3120 /* 82571 and greater support packet-split where the protocol
3121 * header is placed in skb->data and the packet data is
3122 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3123 * In the case of a non-split, skb->data is linearly filled,
3124 * followed by the page buffers. Therefore, skb->data is
3125 * sized to hold the largest protocol header.
3126 *
3127 * allocations using alloc_page take too long for regular MTU
3128 * so only enable packet split for jumbo frames
3129 *
3130 * Using pages when the page size is greater than 16k wastes
3131 * a lot of memory, since we allocate 3 pages at all times
3132 * per packet.
3133 */
3134 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3135 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3136 adapter->rx_ps_pages = pages;
3137 else
3138 adapter->rx_ps_pages = 0;
3139
3140 if (adapter->rx_ps_pages) {
3141 u32 psrctl = 0;
3142
3143 /* Enable Packet split descriptors */
3144 rctl |= E1000_RCTL_DTYP_PS;
3145
3146 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3147
3148 switch (adapter->rx_ps_pages) {
3149 case 3:
3150 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3151 /* fall-through */
3152 case 2:
3153 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3154 /* fall-through */
3155 case 1:
3156 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3157 break;
3158 }
3159
3160 ew32(PSRCTL, psrctl);
3161 }
3162
3163 /* This is useful for sniffing bad packets. */
3164 if (adapter->netdev->features & NETIF_F_RXALL) {
3165 /* UPE and MPE will be handled by normal PROMISC logic
3166 * in e1000e_set_rx_mode
3167 */
3168 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3169 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3170 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3171
3172 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3173 E1000_RCTL_DPF | /* Allow filtered pause */
3174 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3175 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3176 * and that breaks VLANs.
3177 */
3178 }
3179
3180 ew32(RCTL, rctl);
3181 /* just started the receive unit, no need to restart */
3182 adapter->flags &= ~FLAG_RESTART_NOW;
3183 }
3184
3185 /**
3186 * e1000_configure_rx - Configure Receive Unit after Reset
3187 * @adapter: board private structure
3188 *
3189 * Configure the Rx unit of the MAC after a reset.
3190 **/
3191 static void e1000_configure_rx(struct e1000_adapter *adapter)
3192 {
3193 struct e1000_hw *hw = &adapter->hw;
3194 struct e1000_ring *rx_ring = adapter->rx_ring;
3195 u64 rdba;
3196 u32 rdlen, rctl, rxcsum, ctrl_ext;
3197
3198 if (adapter->rx_ps_pages) {
3199 /* this is a 32 byte descriptor */
3200 rdlen = rx_ring->count *
3201 sizeof(union e1000_rx_desc_packet_split);
3202 adapter->clean_rx = e1000_clean_rx_irq_ps;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3204 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3205 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3206 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3207 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3208 } else {
3209 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3210 adapter->clean_rx = e1000_clean_rx_irq;
3211 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3212 }
3213
3214 /* disable receives while setting up the descriptors */
3215 rctl = er32(RCTL);
3216 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3217 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3218 e1e_flush();
3219 usleep_range(10000, 20000);
3220
3221 if (adapter->flags2 & FLAG2_DMA_BURST) {
3222 /* set the writeback threshold (only takes effect if the RDTR
3223 * is set). set GRAN=1 and write back up to 0x4 worth, and
3224 * enable prefetching of 0x20 Rx descriptors
3225 * granularity = 01
3226 * wthresh = 04,
3227 * hthresh = 04,
3228 * pthresh = 0x20
3229 */
3230 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3231 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3232
3233 /* override the delay timers for enabling bursting, only if
3234 * the value was not set by the user via module options
3235 */
3236 if (adapter->rx_int_delay == DEFAULT_RDTR)
3237 adapter->rx_int_delay = BURST_RDTR;
3238 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3239 adapter->rx_abs_int_delay = BURST_RADV;
3240 }
3241
3242 /* set the Receive Delay Timer Register */
3243 ew32(RDTR, adapter->rx_int_delay);
3244
3245 /* irq moderation */
3246 ew32(RADV, adapter->rx_abs_int_delay);
3247 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3248 e1000e_write_itr(adapter, adapter->itr);
3249
3250 ctrl_ext = er32(CTRL_EXT);
3251 /* Auto-Mask interrupts upon ICR access */
3252 ctrl_ext |= E1000_CTRL_EXT_IAME;
3253 ew32(IAM, 0xffffffff);
3254 ew32(CTRL_EXT, ctrl_ext);
3255 e1e_flush();
3256
3257 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3258 * the Base and Length of the Rx Descriptor Ring
3259 */
3260 rdba = rx_ring->dma;
3261 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3262 ew32(RDBAH(0), (rdba >> 32));
3263 ew32(RDLEN(0), rdlen);
3264 ew32(RDH(0), 0);
3265 ew32(RDT(0), 0);
3266 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3267 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3268
3269 writel(0, rx_ring->head);
3270 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3271 e1000e_update_rdt_wa(rx_ring, 0);
3272 else
3273 writel(0, rx_ring->tail);
3274
3275 /* Enable Receive Checksum Offload for TCP and UDP */
3276 rxcsum = er32(RXCSUM);
3277 if (adapter->netdev->features & NETIF_F_RXCSUM)
3278 rxcsum |= E1000_RXCSUM_TUOFL;
3279 else
3280 rxcsum &= ~E1000_RXCSUM_TUOFL;
3281 ew32(RXCSUM, rxcsum);
3282
3283 /* With jumbo frames, excessive C-state transition latencies result
3284 * in dropped transactions.
3285 */
3286 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3287 u32 lat =
3288 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3289 adapter->max_frame_size) * 8 / 1000;
3290
3291 if (adapter->flags & FLAG_IS_ICH) {
3292 u32 rxdctl = er32(RXDCTL(0));
3293
3294 ew32(RXDCTL(0), rxdctl | 0x3);
3295 }
3296
3297 pm_qos_update_request(&adapter->pm_qos_req, lat);
3298 } else {
3299 pm_qos_update_request(&adapter->pm_qos_req,
3300 PM_QOS_DEFAULT_VALUE);
3301 }
3302
3303 /* Enable Receives */
3304 ew32(RCTL, rctl);
3305 }
3306
3307 /**
3308 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3309 * @netdev: network interface device structure
3310 *
3311 * Writes multicast address list to the MTA hash table.
3312 * Returns: -ENOMEM on failure
3313 * 0 on no addresses written
3314 * X on writing X addresses to MTA
3315 */
3316 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3317 {
3318 struct e1000_adapter *adapter = netdev_priv(netdev);
3319 struct e1000_hw *hw = &adapter->hw;
3320 struct netdev_hw_addr *ha;
3321 u8 *mta_list;
3322 int i;
3323
3324 if (netdev_mc_empty(netdev)) {
3325 /* nothing to program, so clear mc list */
3326 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3327 return 0;
3328 }
3329
3330 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3331 if (!mta_list)
3332 return -ENOMEM;
3333
3334 /* update_mc_addr_list expects a packed array of only addresses. */
3335 i = 0;
3336 netdev_for_each_mc_addr(ha, netdev)
3337 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3338
3339 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3340 kfree(mta_list);
3341
3342 return netdev_mc_count(netdev);
3343 }
3344
3345 /**
3346 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3347 * @netdev: network interface device structure
3348 *
3349 * Writes unicast address list to the RAR table.
3350 * Returns: -ENOMEM on failure/insufficient address space
3351 * 0 on no addresses written
3352 * X on writing X addresses to the RAR table
3353 **/
3354 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3355 {
3356 struct e1000_adapter *adapter = netdev_priv(netdev);
3357 struct e1000_hw *hw = &adapter->hw;
3358 unsigned int rar_entries;
3359 int count = 0;
3360
3361 rar_entries = hw->mac.ops.rar_get_count(hw);
3362
3363 /* save a rar entry for our hardware address */
3364 rar_entries--;
3365
3366 /* save a rar entry for the LAA workaround */
3367 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3368 rar_entries--;
3369
3370 /* return ENOMEM indicating insufficient memory for addresses */
3371 if (netdev_uc_count(netdev) > rar_entries)
3372 return -ENOMEM;
3373
3374 if (!netdev_uc_empty(netdev) && rar_entries) {
3375 struct netdev_hw_addr *ha;
3376
3377 /* write the addresses in reverse order to avoid write
3378 * combining
3379 */
3380 netdev_for_each_uc_addr(ha, netdev) {
3381 int ret_val;
3382
3383 if (!rar_entries)
3384 break;
3385 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3386 if (ret_val < 0)
3387 return -ENOMEM;
3388 count++;
3389 }
3390 }
3391
3392 /* zero out the remaining RAR entries not used above */
3393 for (; rar_entries > 0; rar_entries--) {
3394 ew32(RAH(rar_entries), 0);
3395 ew32(RAL(rar_entries), 0);
3396 }
3397 e1e_flush();
3398
3399 return count;
3400 }
3401
3402 /**
3403 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3404 * @netdev: network interface device structure
3405 *
3406 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3407 * address list or the network interface flags are updated. This routine is
3408 * responsible for configuring the hardware for proper unicast, multicast,
3409 * promiscuous mode, and all-multi behavior.
3410 **/
3411 static void e1000e_set_rx_mode(struct net_device *netdev)
3412 {
3413 struct e1000_adapter *adapter = netdev_priv(netdev);
3414 struct e1000_hw *hw = &adapter->hw;
3415 u32 rctl;
3416
3417 if (pm_runtime_suspended(netdev->dev.parent))
3418 return;
3419
3420 /* Check for Promiscuous and All Multicast modes */
3421 rctl = er32(RCTL);
3422
3423 /* clear the affected bits */
3424 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3425
3426 if (netdev->flags & IFF_PROMISC) {
3427 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3428 /* Do not hardware filter VLANs in promisc mode */
3429 e1000e_vlan_filter_disable(adapter);
3430 } else {
3431 int count;
3432
3433 if (netdev->flags & IFF_ALLMULTI) {
3434 rctl |= E1000_RCTL_MPE;
3435 } else {
3436 /* Write addresses to the MTA, if the attempt fails
3437 * then we should just turn on promiscuous mode so
3438 * that we can at least receive multicast traffic
3439 */
3440 count = e1000e_write_mc_addr_list(netdev);
3441 if (count < 0)
3442 rctl |= E1000_RCTL_MPE;
3443 }
3444 e1000e_vlan_filter_enable(adapter);
3445 /* Write addresses to available RAR registers, if there is not
3446 * sufficient space to store all the addresses then enable
3447 * unicast promiscuous mode
3448 */
3449 count = e1000e_write_uc_addr_list(netdev);
3450 if (count < 0)
3451 rctl |= E1000_RCTL_UPE;
3452 }
3453
3454 ew32(RCTL, rctl);
3455
3456 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX ||
3457 e1000e_vlan_used(adapter))
3458 e1000e_vlan_strip_enable(adapter);
3459 else
3460 e1000e_vlan_strip_disable(adapter);
3461 }
3462
3463 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3464 {
3465 struct e1000_hw *hw = &adapter->hw;
3466 u32 mrqc, rxcsum;
3467 u32 rss_key[10];
3468 int i;
3469
3470 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3471 for (i = 0; i < 10; i++)
3472 ew32(RSSRK(i), rss_key[i]);
3473
3474 /* Direct all traffic to queue 0 */
3475 for (i = 0; i < 32; i++)
3476 ew32(RETA(i), 0);
3477
3478 /* Disable raw packet checksumming so that RSS hash is placed in
3479 * descriptor on writeback.
3480 */
3481 rxcsum = er32(RXCSUM);
3482 rxcsum |= E1000_RXCSUM_PCSD;
3483
3484 ew32(RXCSUM, rxcsum);
3485
3486 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3487 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3488 E1000_MRQC_RSS_FIELD_IPV6 |
3489 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3490 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3491
3492 ew32(MRQC, mrqc);
3493 }
3494
3495 /**
3496 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3497 * @adapter: board private structure
3498 * @timinca: pointer to returned time increment attributes
3499 *
3500 * Get attributes for incrementing the System Time Register SYSTIML/H at
3501 * the default base frequency, and set the cyclecounter shift value.
3502 **/
3503 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3504 {
3505 struct e1000_hw *hw = &adapter->hw;
3506 u32 incvalue, incperiod, shift;
3507
3508 /* Make sure clock is enabled on I217/I218/I219 before checking
3509 * the frequency
3510 */
3511 if (((hw->mac.type == e1000_pch_lpt) ||
3512 (hw->mac.type == e1000_pch_spt)) &&
3513 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3514 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3515 u32 fextnvm7 = er32(FEXTNVM7);
3516
3517 if (!(fextnvm7 & BIT(0))) {
3518 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3519 e1e_flush();
3520 }
3521 }
3522
3523 switch (hw->mac.type) {
3524 case e1000_pch2lan:
3525 case e1000_pch_lpt:
3526 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3527 /* Stable 96MHz frequency */
3528 incperiod = INCPERIOD_96MHz;
3529 incvalue = INCVALUE_96MHz;
3530 shift = INCVALUE_SHIFT_96MHz;
3531 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3532 } else {
3533 /* Stable 25MHz frequency */
3534 incperiod = INCPERIOD_25MHz;
3535 incvalue = INCVALUE_25MHz;
3536 shift = INCVALUE_SHIFT_25MHz;
3537 adapter->cc.shift = shift;
3538 }
3539 break;
3540 case e1000_pch_spt:
3541 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3542 /* Stable 24MHz frequency */
3543 incperiod = INCPERIOD_24MHz;
3544 incvalue = INCVALUE_24MHz;
3545 shift = INCVALUE_SHIFT_24MHz;
3546 adapter->cc.shift = shift;
3547 break;
3548 }
3549 return -EINVAL;
3550 case e1000_82574:
3551 case e1000_82583:
3552 /* Stable 25MHz frequency */
3553 incperiod = INCPERIOD_25MHz;
3554 incvalue = INCVALUE_25MHz;
3555 shift = INCVALUE_SHIFT_25MHz;
3556 adapter->cc.shift = shift;
3557 break;
3558 default:
3559 return -EINVAL;
3560 }
3561
3562 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3563 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3564
3565 return 0;
3566 }
3567
3568 /**
3569 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3570 * @adapter: board private structure
3571 *
3572 * Outgoing time stamping can be enabled and disabled. Play nice and
3573 * disable it when requested, although it shouldn't cause any overhead
3574 * when no packet needs it. At most one packet in the queue may be
3575 * marked for time stamping, otherwise it would be impossible to tell
3576 * for sure to which packet the hardware time stamp belongs.
3577 *
3578 * Incoming time stamping has to be configured via the hardware filters.
3579 * Not all combinations are supported, in particular event type has to be
3580 * specified. Matching the kind of event packet is not supported, with the
3581 * exception of "all V2 events regardless of level 2 or 4".
3582 **/
3583 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3584 struct hwtstamp_config *config)
3585 {
3586 struct e1000_hw *hw = &adapter->hw;
3587 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3588 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3589 u32 rxmtrl = 0;
3590 u16 rxudp = 0;
3591 bool is_l4 = false;
3592 bool is_l2 = false;
3593 u32 regval;
3594
3595 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3596 return -EINVAL;
3597
3598 /* flags reserved for future extensions - must be zero */
3599 if (config->flags)
3600 return -EINVAL;
3601
3602 switch (config->tx_type) {
3603 case HWTSTAMP_TX_OFF:
3604 tsync_tx_ctl = 0;
3605 break;
3606 case HWTSTAMP_TX_ON:
3607 break;
3608 default:
3609 return -ERANGE;
3610 }
3611
3612 switch (config->rx_filter) {
3613 case HWTSTAMP_FILTER_NONE:
3614 tsync_rx_ctl = 0;
3615 break;
3616 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3617 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3618 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3619 is_l4 = true;
3620 break;
3621 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3622 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3623 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3624 is_l4 = true;
3625 break;
3626 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3627 /* Also time stamps V2 L2 Path Delay Request/Response */
3628 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3629 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3630 is_l2 = true;
3631 break;
3632 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3633 /* Also time stamps V2 L2 Path Delay Request/Response. */
3634 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3635 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3636 is_l2 = true;
3637 break;
3638 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3639 /* Hardware cannot filter just V2 L4 Sync messages;
3640 * fall-through to V2 (both L2 and L4) Sync.
3641 */
3642 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3643 /* Also time stamps V2 Path Delay Request/Response. */
3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3645 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3646 is_l2 = true;
3647 is_l4 = true;
3648 break;
3649 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3650 /* Hardware cannot filter just V2 L4 Delay Request messages;
3651 * fall-through to V2 (both L2 and L4) Delay Request.
3652 */
3653 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3654 /* Also time stamps V2 Path Delay Request/Response. */
3655 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3656 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3657 is_l2 = true;
3658 is_l4 = true;
3659 break;
3660 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3661 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3662 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3663 * fall-through to all V2 (both L2 and L4) Events.
3664 */
3665 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3666 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3667 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3668 is_l2 = true;
3669 is_l4 = true;
3670 break;
3671 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3672 /* For V1, the hardware can only filter Sync messages or
3673 * Delay Request messages but not both so fall-through to
3674 * time stamp all packets.
3675 */
3676 case HWTSTAMP_FILTER_ALL:
3677 is_l2 = true;
3678 is_l4 = true;
3679 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3680 config->rx_filter = HWTSTAMP_FILTER_ALL;
3681 break;
3682 default:
3683 return -ERANGE;
3684 }
3685
3686 adapter->hwtstamp_config = *config;
3687
3688 /* enable/disable Tx h/w time stamping */
3689 regval = er32(TSYNCTXCTL);
3690 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3691 regval |= tsync_tx_ctl;
3692 ew32(TSYNCTXCTL, regval);
3693 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3694 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3695 e_err("Timesync Tx Control register not set as expected\n");
3696 return -EAGAIN;
3697 }
3698
3699 /* enable/disable Rx h/w time stamping */
3700 regval = er32(TSYNCRXCTL);
3701 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3702 regval |= tsync_rx_ctl;
3703 ew32(TSYNCRXCTL, regval);
3704 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3705 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3706 (regval & (E1000_TSYNCRXCTL_ENABLED |
3707 E1000_TSYNCRXCTL_TYPE_MASK))) {
3708 e_err("Timesync Rx Control register not set as expected\n");
3709 return -EAGAIN;
3710 }
3711
3712 /* L2: define ethertype filter for time stamped packets */
3713 if (is_l2)
3714 rxmtrl |= ETH_P_1588;
3715
3716 /* define which PTP packets get time stamped */
3717 ew32(RXMTRL, rxmtrl);
3718
3719 /* Filter by destination port */
3720 if (is_l4) {
3721 rxudp = PTP_EV_PORT;
3722 cpu_to_be16s(&rxudp);
3723 }
3724 ew32(RXUDP, rxudp);
3725
3726 e1e_flush();
3727
3728 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3729 er32(RXSTMPH);
3730 er32(TXSTMPH);
3731
3732 return 0;
3733 }
3734
3735 /**
3736 * e1000_configure - configure the hardware for Rx and Tx
3737 * @adapter: private board structure
3738 **/
3739 static void e1000_configure(struct e1000_adapter *adapter)
3740 {
3741 struct e1000_ring *rx_ring = adapter->rx_ring;
3742
3743 e1000e_set_rx_mode(adapter->netdev);
3744
3745 e1000_restore_vlan(adapter);
3746 e1000_init_manageability_pt(adapter);
3747
3748 e1000_configure_tx(adapter);
3749
3750 if (adapter->netdev->features & NETIF_F_RXHASH)
3751 e1000e_setup_rss_hash(adapter);
3752 e1000_setup_rctl(adapter);
3753 e1000_configure_rx(adapter);
3754 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3755 }
3756
3757 /**
3758 * e1000e_power_up_phy - restore link in case the phy was powered down
3759 * @adapter: address of board private structure
3760 *
3761 * The phy may be powered down to save power and turn off link when the
3762 * driver is unloaded and wake on lan is not enabled (among others)
3763 * *** this routine MUST be followed by a call to e1000e_reset ***
3764 **/
3765 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3766 {
3767 if (adapter->hw.phy.ops.power_up)
3768 adapter->hw.phy.ops.power_up(&adapter->hw);
3769
3770 adapter->hw.mac.ops.setup_link(&adapter->hw);
3771 }
3772
3773 /**
3774 * e1000_power_down_phy - Power down the PHY
3775 *
3776 * Power down the PHY so no link is implied when interface is down.
3777 * The PHY cannot be powered down if management or WoL is active.
3778 */
3779 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3780 {
3781 if (adapter->hw.phy.ops.power_down)
3782 adapter->hw.phy.ops.power_down(&adapter->hw);
3783 }
3784
3785 /**
3786 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3787 *
3788 * We want to clear all pending descriptors from the TX ring.
3789 * zeroing happens when the HW reads the regs. We assign the ring itself as
3790 * the data of the next descriptor. We don't care about the data we are about
3791 * to reset the HW.
3792 */
3793 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3794 {
3795 struct e1000_hw *hw = &adapter->hw;
3796 struct e1000_ring *tx_ring = adapter->tx_ring;
3797 struct e1000_tx_desc *tx_desc = NULL;
3798 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3799 u16 size = 512;
3800
3801 tctl = er32(TCTL);
3802 ew32(TCTL, tctl | E1000_TCTL_EN);
3803 tdt = er32(TDT(0));
3804 BUG_ON(tdt != tx_ring->next_to_use);
3805 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3806 tx_desc->buffer_addr = tx_ring->dma;
3807
3808 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3809 tx_desc->upper.data = 0;
3810 /* flush descriptors to memory before notifying the HW */
3811 wmb();
3812 tx_ring->next_to_use++;
3813 if (tx_ring->next_to_use == tx_ring->count)
3814 tx_ring->next_to_use = 0;
3815 ew32(TDT(0), tx_ring->next_to_use);
3816 mmiowb();
3817 usleep_range(200, 250);
3818 }
3819
3820 /**
3821 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3822 *
3823 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3824 */
3825 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3826 {
3827 u32 rctl, rxdctl;
3828 struct e1000_hw *hw = &adapter->hw;
3829
3830 rctl = er32(RCTL);
3831 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3832 e1e_flush();
3833 usleep_range(100, 150);
3834
3835 rxdctl = er32(RXDCTL(0));
3836 /* zero the lower 14 bits (prefetch and host thresholds) */
3837 rxdctl &= 0xffffc000;
3838
3839 /* update thresholds: prefetch threshold to 31, host threshold to 1
3840 * and make sure the granularity is "descriptors" and not "cache lines"
3841 */
3842 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3843
3844 ew32(RXDCTL(0), rxdctl);
3845 /* momentarily enable the RX ring for the changes to take effect */
3846 ew32(RCTL, rctl | E1000_RCTL_EN);
3847 e1e_flush();
3848 usleep_range(100, 150);
3849 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3850 }
3851
3852 /**
3853 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3854 *
3855 * In i219, the descriptor rings must be emptied before resetting the HW
3856 * or before changing the device state to D3 during runtime (runtime PM).
3857 *
3858 * Failure to do this will cause the HW to enter a unit hang state which can
3859 * only be released by PCI reset on the device
3860 *
3861 */
3862
3863 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3864 {
3865 u16 hang_state;
3866 u32 fext_nvm11, tdlen;
3867 struct e1000_hw *hw = &adapter->hw;
3868
3869 /* First, disable MULR fix in FEXTNVM11 */
3870 fext_nvm11 = er32(FEXTNVM11);
3871 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3872 ew32(FEXTNVM11, fext_nvm11);
3873 /* do nothing if we're not in faulty state, or if the queue is empty */
3874 tdlen = er32(TDLEN(0));
3875 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3876 &hang_state);
3877 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3878 return;
3879 e1000_flush_tx_ring(adapter);
3880 /* recheck, maybe the fault is caused by the rx ring */
3881 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3882 &hang_state);
3883 if (hang_state & FLUSH_DESC_REQUIRED)
3884 e1000_flush_rx_ring(adapter);
3885 }
3886
3887 /**
3888 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3889 * @adapter: board private structure
3890 *
3891 * When the MAC is reset, all hardware bits for timesync will be reset to the
3892 * default values. This function will restore the settings last in place.
3893 * Since the clock SYSTIME registers are reset, we will simply restore the
3894 * cyclecounter to the kernel real clock time.
3895 **/
3896 static void e1000e_systim_reset(struct e1000_adapter *adapter)
3897 {
3898 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3899 struct e1000_hw *hw = &adapter->hw;
3900 unsigned long flags;
3901 u32 timinca;
3902 s32 ret_val;
3903
3904 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3905 return;
3906
3907 if (info->adjfreq) {
3908 /* restore the previous ptp frequency delta */
3909 ret_val = info->adjfreq(info, adapter->ptp_delta);
3910 } else {
3911 /* set the default base frequency if no adjustment possible */
3912 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3913 if (!ret_val)
3914 ew32(TIMINCA, timinca);
3915 }
3916
3917 if (ret_val) {
3918 dev_warn(&adapter->pdev->dev,
3919 "Failed to restore TIMINCA clock rate delta: %d\n",
3920 ret_val);
3921 return;
3922 }
3923
3924 /* reset the systim ns time counter */
3925 spin_lock_irqsave(&adapter->systim_lock, flags);
3926 timecounter_init(&adapter->tc, &adapter->cc,
3927 ktime_to_ns(ktime_get_real()));
3928 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3929
3930 /* restore the previous hwtstamp configuration settings */
3931 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3932 }
3933
3934 /**
3935 * e1000e_reset - bring the hardware into a known good state
3936 *
3937 * This function boots the hardware and enables some settings that
3938 * require a configuration cycle of the hardware - those cannot be
3939 * set/changed during runtime. After reset the device needs to be
3940 * properly configured for Rx, Tx etc.
3941 */
3942 void e1000e_reset(struct e1000_adapter *adapter)
3943 {
3944 struct e1000_mac_info *mac = &adapter->hw.mac;
3945 struct e1000_fc_info *fc = &adapter->hw.fc;
3946 struct e1000_hw *hw = &adapter->hw;
3947 u32 tx_space, min_tx_space, min_rx_space;
3948 u32 pba = adapter->pba;
3949 u16 hwm;
3950
3951 /* reset Packet Buffer Allocation to default */
3952 ew32(PBA, pba);
3953
3954 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3955 /* To maintain wire speed transmits, the Tx FIFO should be
3956 * large enough to accommodate two full transmit packets,
3957 * rounded up to the next 1KB and expressed in KB. Likewise,
3958 * the Rx FIFO should be large enough to accommodate at least
3959 * one full receive packet and is similarly rounded up and
3960 * expressed in KB.
3961 */
3962 pba = er32(PBA);
3963 /* upper 16 bits has Tx packet buffer allocation size in KB */
3964 tx_space = pba >> 16;
3965 /* lower 16 bits has Rx packet buffer allocation size in KB */
3966 pba &= 0xffff;
3967 /* the Tx fifo also stores 16 bytes of information about the Tx
3968 * but don't include ethernet FCS because hardware appends it
3969 */
3970 min_tx_space = (adapter->max_frame_size +
3971 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3972 min_tx_space = ALIGN(min_tx_space, 1024);
3973 min_tx_space >>= 10;
3974 /* software strips receive CRC, so leave room for it */
3975 min_rx_space = adapter->max_frame_size;
3976 min_rx_space = ALIGN(min_rx_space, 1024);
3977 min_rx_space >>= 10;
3978
3979 /* If current Tx allocation is less than the min Tx FIFO size,
3980 * and the min Tx FIFO size is less than the current Rx FIFO
3981 * allocation, take space away from current Rx allocation
3982 */
3983 if ((tx_space < min_tx_space) &&
3984 ((min_tx_space - tx_space) < pba)) {
3985 pba -= min_tx_space - tx_space;
3986
3987 /* if short on Rx space, Rx wins and must trump Tx
3988 * adjustment
3989 */
3990 if (pba < min_rx_space)
3991 pba = min_rx_space;
3992 }
3993
3994 ew32(PBA, pba);
3995 }
3996
3997 /* flow control settings
3998 *
3999 * The high water mark must be low enough to fit one full frame
4000 * (or the size used for early receive) above it in the Rx FIFO.
4001 * Set it to the lower of:
4002 * - 90% of the Rx FIFO size, and
4003 * - the full Rx FIFO size minus one full frame
4004 */
4005 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4006 fc->pause_time = 0xFFFF;
4007 else
4008 fc->pause_time = E1000_FC_PAUSE_TIME;
4009 fc->send_xon = true;
4010 fc->current_mode = fc->requested_mode;
4011
4012 switch (hw->mac.type) {
4013 case e1000_ich9lan:
4014 case e1000_ich10lan:
4015 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4016 pba = 14;
4017 ew32(PBA, pba);
4018 fc->high_water = 0x2800;
4019 fc->low_water = fc->high_water - 8;
4020 break;
4021 }
4022 /* fall-through */
4023 default:
4024 hwm = min(((pba << 10) * 9 / 10),
4025 ((pba << 10) - adapter->max_frame_size));
4026
4027 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4028 fc->low_water = fc->high_water - 8;
4029 break;
4030 case e1000_pchlan:
4031 /* Workaround PCH LOM adapter hangs with certain network
4032 * loads. If hangs persist, try disabling Tx flow control.
4033 */
4034 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4035 fc->high_water = 0x3500;
4036 fc->low_water = 0x1500;
4037 } else {
4038 fc->high_water = 0x5000;
4039 fc->low_water = 0x3000;
4040 }
4041 fc->refresh_time = 0x1000;
4042 break;
4043 case e1000_pch2lan:
4044 case e1000_pch_lpt:
4045 case e1000_pch_spt:
4046 fc->refresh_time = 0x0400;
4047
4048 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4049 fc->high_water = 0x05C20;
4050 fc->low_water = 0x05048;
4051 fc->pause_time = 0x0650;
4052 break;
4053 }
4054
4055 pba = 14;
4056 ew32(PBA, pba);
4057 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4058 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4059 break;
4060 }
4061
4062 /* Alignment of Tx data is on an arbitrary byte boundary with the
4063 * maximum size per Tx descriptor limited only to the transmit
4064 * allocation of the packet buffer minus 96 bytes with an upper
4065 * limit of 24KB due to receive synchronization limitations.
4066 */
4067 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4068 24 << 10);
4069
4070 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4071 * fit in receive buffer.
4072 */
4073 if (adapter->itr_setting & 0x3) {
4074 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4075 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4076 dev_info(&adapter->pdev->dev,
4077 "Interrupt Throttle Rate off\n");
4078 adapter->flags2 |= FLAG2_DISABLE_AIM;
4079 e1000e_write_itr(adapter, 0);
4080 }
4081 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4082 dev_info(&adapter->pdev->dev,
4083 "Interrupt Throttle Rate on\n");
4084 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4085 adapter->itr = 20000;
4086 e1000e_write_itr(adapter, adapter->itr);
4087 }
4088 }
4089
4090 if (hw->mac.type == e1000_pch_spt)
4091 e1000_flush_desc_rings(adapter);
4092 /* Allow time for pending master requests to run */
4093 mac->ops.reset_hw(hw);
4094
4095 /* For parts with AMT enabled, let the firmware know
4096 * that the network interface is in control
4097 */
4098 if (adapter->flags & FLAG_HAS_AMT)
4099 e1000e_get_hw_control(adapter);
4100
4101 ew32(WUC, 0);
4102
4103 if (mac->ops.init_hw(hw))
4104 e_err("Hardware Error\n");
4105
4106 e1000_update_mng_vlan(adapter);
4107
4108 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4109 ew32(VET, ETH_P_8021Q);
4110
4111 e1000e_reset_adaptive(hw);
4112
4113 /* restore systim and hwtstamp settings */
4114 e1000e_systim_reset(adapter);
4115
4116 /* Set EEE advertisement as appropriate */
4117 if (adapter->flags2 & FLAG2_HAS_EEE) {
4118 s32 ret_val;
4119 u16 adv_addr;
4120
4121 switch (hw->phy.type) {
4122 case e1000_phy_82579:
4123 adv_addr = I82579_EEE_ADVERTISEMENT;
4124 break;
4125 case e1000_phy_i217:
4126 adv_addr = I217_EEE_ADVERTISEMENT;
4127 break;
4128 default:
4129 dev_err(&adapter->pdev->dev,
4130 "Invalid PHY type setting EEE advertisement\n");
4131 return;
4132 }
4133
4134 ret_val = hw->phy.ops.acquire(hw);
4135 if (ret_val) {
4136 dev_err(&adapter->pdev->dev,
4137 "EEE advertisement - unable to acquire PHY\n");
4138 return;
4139 }
4140
4141 e1000_write_emi_reg_locked(hw, adv_addr,
4142 hw->dev_spec.ich8lan.eee_disable ?
4143 0 : adapter->eee_advert);
4144
4145 hw->phy.ops.release(hw);
4146 }
4147
4148 if (!netif_running(adapter->netdev) &&
4149 !test_bit(__E1000_TESTING, &adapter->state))
4150 e1000_power_down_phy(adapter);
4151
4152 e1000_get_phy_info(hw);
4153
4154 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4155 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4156 u16 phy_data = 0;
4157 /* speed up time to link by disabling smart power down, ignore
4158 * the return value of this function because there is nothing
4159 * different we would do if it failed
4160 */
4161 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4162 phy_data &= ~IGP02E1000_PM_SPD;
4163 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4164 }
4165 if (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {
4166 u32 reg;
4167
4168 /* Fextnvm7 @ 0xe4[2] = 1 */
4169 reg = er32(FEXTNVM7);
4170 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4171 ew32(FEXTNVM7, reg);
4172 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4173 reg = er32(FEXTNVM9);
4174 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4175 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4176 ew32(FEXTNVM9, reg);
4177 }
4178
4179 }
4180
4181 /**
4182 * e1000e_trigger_lsc - trigger an LSC interrupt
4183 * @adapter:
4184 *
4185 * Fire a link status change interrupt to start the watchdog.
4186 **/
4187 static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4188 {
4189 struct e1000_hw *hw = &adapter->hw;
4190
4191 if (adapter->msix_entries)
4192 ew32(ICS, E1000_ICS_OTHER);
4193 else
4194 ew32(ICS, E1000_ICS_LSC);
4195 }
4196
4197 void e1000e_up(struct e1000_adapter *adapter)
4198 {
4199 /* hardware has been reset, we need to reload some things */
4200 e1000_configure(adapter);
4201
4202 clear_bit(__E1000_DOWN, &adapter->state);
4203
4204 if (adapter->msix_entries)
4205 e1000_configure_msix(adapter);
4206 e1000_irq_enable(adapter);
4207
4208 netif_start_queue(adapter->netdev);
4209
4210 e1000e_trigger_lsc(adapter);
4211 }
4212
4213 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4214 {
4215 struct e1000_hw *hw = &adapter->hw;
4216
4217 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4218 return;
4219
4220 /* flush pending descriptor writebacks to memory */
4221 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4222 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4223
4224 /* execute the writes immediately */
4225 e1e_flush();
4226
4227 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4228 * write is successful
4229 */
4230 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4231 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4232
4233 /* execute the writes immediately */
4234 e1e_flush();
4235 }
4236
4237 static void e1000e_update_stats(struct e1000_adapter *adapter);
4238
4239 /**
4240 * e1000e_down - quiesce the device and optionally reset the hardware
4241 * @adapter: board private structure
4242 * @reset: boolean flag to reset the hardware or not
4243 */
4244 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4245 {
4246 struct net_device *netdev = adapter->netdev;
4247 struct e1000_hw *hw = &adapter->hw;
4248 u32 tctl, rctl;
4249
4250 /* signal that we're down so the interrupt handler does not
4251 * reschedule our watchdog timer
4252 */
4253 set_bit(__E1000_DOWN, &adapter->state);
4254
4255 netif_carrier_off(netdev);
4256
4257 /* disable receives in the hardware */
4258 rctl = er32(RCTL);
4259 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4260 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4261 /* flush and sleep below */
4262
4263 netif_stop_queue(netdev);
4264
4265 /* disable transmits in the hardware */
4266 tctl = er32(TCTL);
4267 tctl &= ~E1000_TCTL_EN;
4268 ew32(TCTL, tctl);
4269
4270 /* flush both disables and wait for them to finish */
4271 e1e_flush();
4272 usleep_range(10000, 20000);
4273
4274 e1000_irq_disable(adapter);
4275
4276 napi_synchronize(&adapter->napi);
4277
4278 del_timer_sync(&adapter->watchdog_timer);
4279 del_timer_sync(&adapter->phy_info_timer);
4280
4281 spin_lock(&adapter->stats64_lock);
4282 e1000e_update_stats(adapter);
4283 spin_unlock(&adapter->stats64_lock);
4284
4285 e1000e_flush_descriptors(adapter);
4286
4287 adapter->link_speed = 0;
4288 adapter->link_duplex = 0;
4289
4290 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4291 if ((hw->mac.type >= e1000_pch2lan) &&
4292 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4293 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4294 e_dbg("failed to disable jumbo frame workaround mode\n");
4295
4296 if (!pci_channel_offline(adapter->pdev)) {
4297 if (reset)
4298 e1000e_reset(adapter);
4299 else if (hw->mac.type == e1000_pch_spt)
4300 e1000_flush_desc_rings(adapter);
4301 }
4302 e1000_clean_tx_ring(adapter->tx_ring);
4303 e1000_clean_rx_ring(adapter->rx_ring);
4304 }
4305
4306 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4307 {
4308 might_sleep();
4309 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4310 usleep_range(1000, 2000);
4311 e1000e_down(adapter, true);
4312 e1000e_up(adapter);
4313 clear_bit(__E1000_RESETTING, &adapter->state);
4314 }
4315
4316 /**
4317 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4318 * @cc: cyclecounter structure
4319 **/
4320 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4321 {
4322 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4323 cc);
4324 struct e1000_hw *hw = &adapter->hw;
4325 u32 systimel, systimeh;
4326 cycle_t systim, systim_next;
4327 /* SYSTIMH latching upon SYSTIML read does not work well.
4328 * This means that if SYSTIML overflows after we read it but before
4329 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4330 * will experience a huge non linear increment in the systime value
4331 * to fix that we test for overflow and if true, we re-read systime.
4332 */
4333 systimel = er32(SYSTIML);
4334 systimeh = er32(SYSTIMH);
4335 /* Is systimel is so large that overflow is possible? */
4336 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4337 u32 systimel_2 = er32(SYSTIML);
4338 if (systimel > systimel_2) {
4339 /* There was an overflow, read again SYSTIMH, and use
4340 * systimel_2
4341 */
4342 systimeh = er32(SYSTIMH);
4343 systimel = systimel_2;
4344 }
4345 }
4346 systim = (cycle_t)systimel;
4347 systim |= (cycle_t)systimeh << 32;
4348
4349 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4350 u64 time_delta, rem, temp;
4351 u32 incvalue;
4352 int i;
4353
4354 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4355 * check to see that the time is incrementing at a reasonable
4356 * rate and is a multiple of incvalue
4357 */
4358 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4359 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4360 /* latch SYSTIMH on read of SYSTIML */
4361 systim_next = (cycle_t)er32(SYSTIML);
4362 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4363
4364 time_delta = systim_next - systim;
4365 temp = time_delta;
4366 rem = do_div(temp, incvalue);
4367
4368 systim = systim_next;
4369
4370 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4371 (rem == 0))
4372 break;
4373 }
4374 }
4375 return systim;
4376 }
4377
4378 /**
4379 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4380 * @adapter: board private structure to initialize
4381 *
4382 * e1000_sw_init initializes the Adapter private data structure.
4383 * Fields are initialized based on PCI device information and
4384 * OS network device settings (MTU size).
4385 **/
4386 static int e1000_sw_init(struct e1000_adapter *adapter)
4387 {
4388 struct net_device *netdev = adapter->netdev;
4389
4390 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4391 adapter->rx_ps_bsize0 = 128;
4392 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4393 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4394 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4395 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4396
4397 spin_lock_init(&adapter->stats64_lock);
4398
4399 e1000e_set_interrupt_capability(adapter);
4400
4401 if (e1000_alloc_queues(adapter))
4402 return -ENOMEM;
4403
4404 /* Setup hardware time stamping cyclecounter */
4405 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4406 adapter->cc.read = e1000e_cyclecounter_read;
4407 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4408 adapter->cc.mult = 1;
4409 /* cc.shift set in e1000e_get_base_tininca() */
4410
4411 spin_lock_init(&adapter->systim_lock);
4412 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4413 }
4414
4415 /* Explicitly disable IRQ since the NIC can be in any state. */
4416 e1000_irq_disable(adapter);
4417
4418 set_bit(__E1000_DOWN, &adapter->state);
4419 return 0;
4420 }
4421
4422 /**
4423 * e1000_intr_msi_test - Interrupt Handler
4424 * @irq: interrupt number
4425 * @data: pointer to a network interface device structure
4426 **/
4427 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4428 {
4429 struct net_device *netdev = data;
4430 struct e1000_adapter *adapter = netdev_priv(netdev);
4431 struct e1000_hw *hw = &adapter->hw;
4432 u32 icr = er32(ICR);
4433
4434 e_dbg("icr is %08X\n", icr);
4435 if (icr & E1000_ICR_RXSEQ) {
4436 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4437 /* Force memory writes to complete before acknowledging the
4438 * interrupt is handled.
4439 */
4440 wmb();
4441 }
4442
4443 return IRQ_HANDLED;
4444 }
4445
4446 /**
4447 * e1000_test_msi_interrupt - Returns 0 for successful test
4448 * @adapter: board private struct
4449 *
4450 * code flow taken from tg3.c
4451 **/
4452 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4453 {
4454 struct net_device *netdev = adapter->netdev;
4455 struct e1000_hw *hw = &adapter->hw;
4456 int err;
4457
4458 /* poll_enable hasn't been called yet, so don't need disable */
4459 /* clear any pending events */
4460 er32(ICR);
4461
4462 /* free the real vector and request a test handler */
4463 e1000_free_irq(adapter);
4464 e1000e_reset_interrupt_capability(adapter);
4465
4466 /* Assume that the test fails, if it succeeds then the test
4467 * MSI irq handler will unset this flag
4468 */
4469 adapter->flags |= FLAG_MSI_TEST_FAILED;
4470
4471 err = pci_enable_msi(adapter->pdev);
4472 if (err)
4473 goto msi_test_failed;
4474
4475 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4476 netdev->name, netdev);
4477 if (err) {
4478 pci_disable_msi(adapter->pdev);
4479 goto msi_test_failed;
4480 }
4481
4482 /* Force memory writes to complete before enabling and firing an
4483 * interrupt.
4484 */
4485 wmb();
4486
4487 e1000_irq_enable(adapter);
4488
4489 /* fire an unusual interrupt on the test handler */
4490 ew32(ICS, E1000_ICS_RXSEQ);
4491 e1e_flush();
4492 msleep(100);
4493
4494 e1000_irq_disable(adapter);
4495
4496 rmb(); /* read flags after interrupt has been fired */
4497
4498 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4499 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4500 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4501 } else {
4502 e_dbg("MSI interrupt test succeeded!\n");
4503 }
4504
4505 free_irq(adapter->pdev->irq, netdev);
4506 pci_disable_msi(adapter->pdev);
4507
4508 msi_test_failed:
4509 e1000e_set_interrupt_capability(adapter);
4510 return e1000_request_irq(adapter);
4511 }
4512
4513 /**
4514 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4515 * @adapter: board private struct
4516 *
4517 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4518 **/
4519 static int e1000_test_msi(struct e1000_adapter *adapter)
4520 {
4521 int err;
4522 u16 pci_cmd;
4523
4524 if (!(adapter->flags & FLAG_MSI_ENABLED))
4525 return 0;
4526
4527 /* disable SERR in case the MSI write causes a master abort */
4528 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4529 if (pci_cmd & PCI_COMMAND_SERR)
4530 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4531 pci_cmd & ~PCI_COMMAND_SERR);
4532
4533 err = e1000_test_msi_interrupt(adapter);
4534
4535 /* re-enable SERR */
4536 if (pci_cmd & PCI_COMMAND_SERR) {
4537 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4538 pci_cmd |= PCI_COMMAND_SERR;
4539 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4540 }
4541
4542 return err;
4543 }
4544
4545 /**
4546 * e1000e_open - Called when a network interface is made active
4547 * @netdev: network interface device structure
4548 *
4549 * Returns 0 on success, negative value on failure
4550 *
4551 * The open entry point is called when a network interface is made
4552 * active by the system (IFF_UP). At this point all resources needed
4553 * for transmit and receive operations are allocated, the interrupt
4554 * handler is registered with the OS, the watchdog timer is started,
4555 * and the stack is notified that the interface is ready.
4556 **/
4557 int e1000e_open(struct net_device *netdev)
4558 {
4559 struct e1000_adapter *adapter = netdev_priv(netdev);
4560 struct e1000_hw *hw = &adapter->hw;
4561 struct pci_dev *pdev = adapter->pdev;
4562 int err;
4563
4564 /* disallow open during test */
4565 if (test_bit(__E1000_TESTING, &adapter->state))
4566 return -EBUSY;
4567
4568 pm_runtime_get_sync(&pdev->dev);
4569
4570 netif_carrier_off(netdev);
4571
4572 /* allocate transmit descriptors */
4573 err = e1000e_setup_tx_resources(adapter->tx_ring);
4574 if (err)
4575 goto err_setup_tx;
4576
4577 /* allocate receive descriptors */
4578 err = e1000e_setup_rx_resources(adapter->rx_ring);
4579 if (err)
4580 goto err_setup_rx;
4581
4582 /* If AMT is enabled, let the firmware know that the network
4583 * interface is now open and reset the part to a known state.
4584 */
4585 if (adapter->flags & FLAG_HAS_AMT) {
4586 e1000e_get_hw_control(adapter);
4587 e1000e_reset(adapter);
4588 }
4589
4590 e1000e_power_up_phy(adapter);
4591
4592 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4593 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4594 e1000_update_mng_vlan(adapter);
4595
4596 /* DMA latency requirement to workaround jumbo issue */
4597 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4598 PM_QOS_DEFAULT_VALUE);
4599
4600 /* before we allocate an interrupt, we must be ready to handle it.
4601 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4602 * as soon as we call pci_request_irq, so we have to setup our
4603 * clean_rx handler before we do so.
4604 */
4605 e1000_configure(adapter);
4606
4607 err = e1000_request_irq(adapter);
4608 if (err)
4609 goto err_req_irq;
4610
4611 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4612 * ignore e1000e MSI messages, which means we need to test our MSI
4613 * interrupt now
4614 */
4615 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4616 err = e1000_test_msi(adapter);
4617 if (err) {
4618 e_err("Interrupt allocation failed\n");
4619 goto err_req_irq;
4620 }
4621 }
4622
4623 /* From here on the code is the same as e1000e_up() */
4624 clear_bit(__E1000_DOWN, &adapter->state);
4625
4626 napi_enable(&adapter->napi);
4627
4628 e1000_irq_enable(adapter);
4629
4630 adapter->tx_hang_recheck = false;
4631 netif_start_queue(netdev);
4632
4633 hw->mac.get_link_status = true;
4634 pm_runtime_put(&pdev->dev);
4635
4636 e1000e_trigger_lsc(adapter);
4637
4638 return 0;
4639
4640 err_req_irq:
4641 pm_qos_remove_request(&adapter->pm_qos_req);
4642 e1000e_release_hw_control(adapter);
4643 e1000_power_down_phy(adapter);
4644 e1000e_free_rx_resources(adapter->rx_ring);
4645 err_setup_rx:
4646 e1000e_free_tx_resources(adapter->tx_ring);
4647 err_setup_tx:
4648 e1000e_reset(adapter);
4649 pm_runtime_put_sync(&pdev->dev);
4650
4651 return err;
4652 }
4653
4654 /**
4655 * e1000e_close - Disables a network interface
4656 * @netdev: network interface device structure
4657 *
4658 * Returns 0, this is not allowed to fail
4659 *
4660 * The close entry point is called when an interface is de-activated
4661 * by the OS. The hardware is still under the drivers control, but
4662 * needs to be disabled. A global MAC reset is issued to stop the
4663 * hardware, and all transmit and receive resources are freed.
4664 **/
4665 int e1000e_close(struct net_device *netdev)
4666 {
4667 struct e1000_adapter *adapter = netdev_priv(netdev);
4668 struct pci_dev *pdev = adapter->pdev;
4669 int count = E1000_CHECK_RESET_COUNT;
4670
4671 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4672 usleep_range(10000, 20000);
4673
4674 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4675
4676 pm_runtime_get_sync(&pdev->dev);
4677
4678 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4679 e1000e_down(adapter, true);
4680 e1000_free_irq(adapter);
4681
4682 /* Link status message must follow this format */
4683 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4684 }
4685
4686 napi_disable(&adapter->napi);
4687
4688 e1000e_free_tx_resources(adapter->tx_ring);
4689 e1000e_free_rx_resources(adapter->rx_ring);
4690
4691 /* kill manageability vlan ID if supported, but not if a vlan with
4692 * the same ID is registered on the host OS (let 8021q kill it)
4693 */
4694 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4695 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4696 adapter->mng_vlan_id);
4697
4698 /* If AMT is enabled, let the firmware know that the network
4699 * interface is now closed
4700 */
4701 if ((adapter->flags & FLAG_HAS_AMT) &&
4702 !test_bit(__E1000_TESTING, &adapter->state))
4703 e1000e_release_hw_control(adapter);
4704
4705 pm_qos_remove_request(&adapter->pm_qos_req);
4706
4707 pm_runtime_put_sync(&pdev->dev);
4708
4709 return 0;
4710 }
4711
4712 /**
4713 * e1000_set_mac - Change the Ethernet Address of the NIC
4714 * @netdev: network interface device structure
4715 * @p: pointer to an address structure
4716 *
4717 * Returns 0 on success, negative on failure
4718 **/
4719 static int e1000_set_mac(struct net_device *netdev, void *p)
4720 {
4721 struct e1000_adapter *adapter = netdev_priv(netdev);
4722 struct e1000_hw *hw = &adapter->hw;
4723 struct sockaddr *addr = p;
4724
4725 if (!is_valid_ether_addr(addr->sa_data))
4726 return -EADDRNOTAVAIL;
4727
4728 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4729 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4730
4731 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4732
4733 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4734 /* activate the work around */
4735 e1000e_set_laa_state_82571(&adapter->hw, 1);
4736
4737 /* Hold a copy of the LAA in RAR[14] This is done so that
4738 * between the time RAR[0] gets clobbered and the time it
4739 * gets fixed (in e1000_watchdog), the actual LAA is in one
4740 * of the RARs and no incoming packets directed to this port
4741 * are dropped. Eventually the LAA will be in RAR[0] and
4742 * RAR[14]
4743 */
4744 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4745 adapter->hw.mac.rar_entry_count - 1);
4746 }
4747
4748 return 0;
4749 }
4750
4751 /**
4752 * e1000e_update_phy_task - work thread to update phy
4753 * @work: pointer to our work struct
4754 *
4755 * this worker thread exists because we must acquire a
4756 * semaphore to read the phy, which we could msleep while
4757 * waiting for it, and we can't msleep in a timer.
4758 **/
4759 static void e1000e_update_phy_task(struct work_struct *work)
4760 {
4761 struct e1000_adapter *adapter = container_of(work,
4762 struct e1000_adapter,
4763 update_phy_task);
4764 struct e1000_hw *hw = &adapter->hw;
4765
4766 if (test_bit(__E1000_DOWN, &adapter->state))
4767 return;
4768
4769 e1000_get_phy_info(hw);
4770
4771 /* Enable EEE on 82579 after link up */
4772 if (hw->phy.type >= e1000_phy_82579)
4773 e1000_set_eee_pchlan(hw);
4774 }
4775
4776 /**
4777 * e1000_update_phy_info - timre call-back to update PHY info
4778 * @data: pointer to adapter cast into an unsigned long
4779 *
4780 * Need to wait a few seconds after link up to get diagnostic information from
4781 * the phy
4782 **/
4783 static void e1000_update_phy_info(unsigned long data)
4784 {
4785 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
4786
4787 if (test_bit(__E1000_DOWN, &adapter->state))
4788 return;
4789
4790 schedule_work(&adapter->update_phy_task);
4791 }
4792
4793 /**
4794 * e1000e_update_phy_stats - Update the PHY statistics counters
4795 * @adapter: board private structure
4796 *
4797 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4798 **/
4799 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4800 {
4801 struct e1000_hw *hw = &adapter->hw;
4802 s32 ret_val;
4803 u16 phy_data;
4804
4805 ret_val = hw->phy.ops.acquire(hw);
4806 if (ret_val)
4807 return;
4808
4809 /* A page set is expensive so check if already on desired page.
4810 * If not, set to the page with the PHY status registers.
4811 */
4812 hw->phy.addr = 1;
4813 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4814 &phy_data);
4815 if (ret_val)
4816 goto release;
4817 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4818 ret_val = hw->phy.ops.set_page(hw,
4819 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4820 if (ret_val)
4821 goto release;
4822 }
4823
4824 /* Single Collision Count */
4825 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4826 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4827 if (!ret_val)
4828 adapter->stats.scc += phy_data;
4829
4830 /* Excessive Collision Count */
4831 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4832 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4833 if (!ret_val)
4834 adapter->stats.ecol += phy_data;
4835
4836 /* Multiple Collision Count */
4837 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4838 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4839 if (!ret_val)
4840 adapter->stats.mcc += phy_data;
4841
4842 /* Late Collision Count */
4843 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4844 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4845 if (!ret_val)
4846 adapter->stats.latecol += phy_data;
4847
4848 /* Collision Count - also used for adaptive IFS */
4849 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4850 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4851 if (!ret_val)
4852 hw->mac.collision_delta = phy_data;
4853
4854 /* Defer Count */
4855 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4856 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4857 if (!ret_val)
4858 adapter->stats.dc += phy_data;
4859
4860 /* Transmit with no CRS */
4861 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4862 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4863 if (!ret_val)
4864 adapter->stats.tncrs += phy_data;
4865
4866 release:
4867 hw->phy.ops.release(hw);
4868 }
4869
4870 /**
4871 * e1000e_update_stats - Update the board statistics counters
4872 * @adapter: board private structure
4873 **/
4874 static void e1000e_update_stats(struct e1000_adapter *adapter)
4875 {
4876 struct net_device *netdev = adapter->netdev;
4877 struct e1000_hw *hw = &adapter->hw;
4878 struct pci_dev *pdev = adapter->pdev;
4879
4880 /* Prevent stats update while adapter is being reset, or if the pci
4881 * connection is down.
4882 */
4883 if (adapter->link_speed == 0)
4884 return;
4885 if (pci_channel_offline(pdev))
4886 return;
4887
4888 adapter->stats.crcerrs += er32(CRCERRS);
4889 adapter->stats.gprc += er32(GPRC);
4890 adapter->stats.gorc += er32(GORCL);
4891 er32(GORCH); /* Clear gorc */
4892 adapter->stats.bprc += er32(BPRC);
4893 adapter->stats.mprc += er32(MPRC);
4894 adapter->stats.roc += er32(ROC);
4895
4896 adapter->stats.mpc += er32(MPC);
4897
4898 /* Half-duplex statistics */
4899 if (adapter->link_duplex == HALF_DUPLEX) {
4900 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4901 e1000e_update_phy_stats(adapter);
4902 } else {
4903 adapter->stats.scc += er32(SCC);
4904 adapter->stats.ecol += er32(ECOL);
4905 adapter->stats.mcc += er32(MCC);
4906 adapter->stats.latecol += er32(LATECOL);
4907 adapter->stats.dc += er32(DC);
4908
4909 hw->mac.collision_delta = er32(COLC);
4910
4911 if ((hw->mac.type != e1000_82574) &&
4912 (hw->mac.type != e1000_82583))
4913 adapter->stats.tncrs += er32(TNCRS);
4914 }
4915 adapter->stats.colc += hw->mac.collision_delta;
4916 }
4917
4918 adapter->stats.xonrxc += er32(XONRXC);
4919 adapter->stats.xontxc += er32(XONTXC);
4920 adapter->stats.xoffrxc += er32(XOFFRXC);
4921 adapter->stats.xofftxc += er32(XOFFTXC);
4922 adapter->stats.gptc += er32(GPTC);
4923 adapter->stats.gotc += er32(GOTCL);
4924 er32(GOTCH); /* Clear gotc */
4925 adapter->stats.rnbc += er32(RNBC);
4926 adapter->stats.ruc += er32(RUC);
4927
4928 adapter->stats.mptc += er32(MPTC);
4929 adapter->stats.bptc += er32(BPTC);
4930
4931 /* used for adaptive IFS */
4932
4933 hw->mac.tx_packet_delta = er32(TPT);
4934 adapter->stats.tpt += hw->mac.tx_packet_delta;
4935
4936 adapter->stats.algnerrc += er32(ALGNERRC);
4937 adapter->stats.rxerrc += er32(RXERRC);
4938 adapter->stats.cexterr += er32(CEXTERR);
4939 adapter->stats.tsctc += er32(TSCTC);
4940 adapter->stats.tsctfc += er32(TSCTFC);
4941
4942 /* Fill out the OS statistics structure */
4943 netdev->stats.multicast = adapter->stats.mprc;
4944 netdev->stats.collisions = adapter->stats.colc;
4945
4946 /* Rx Errors */
4947
4948 /* RLEC on some newer hardware can be incorrect so build
4949 * our own version based on RUC and ROC
4950 */
4951 netdev->stats.rx_errors = adapter->stats.rxerrc +
4952 adapter->stats.crcerrs + adapter->stats.algnerrc +
4953 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4954 netdev->stats.rx_length_errors = adapter->stats.ruc +
4955 adapter->stats.roc;
4956 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4957 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4958 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4959
4960 /* Tx Errors */
4961 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
4962 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4963 netdev->stats.tx_window_errors = adapter->stats.latecol;
4964 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
4965
4966 /* Tx Dropped needs to be maintained elsewhere */
4967
4968 /* Management Stats */
4969 adapter->stats.mgptc += er32(MGTPTC);
4970 adapter->stats.mgprc += er32(MGTPRC);
4971 adapter->stats.mgpdc += er32(MGTPDC);
4972
4973 /* Correctable ECC Errors */
4974 if ((hw->mac.type == e1000_pch_lpt) ||
4975 (hw->mac.type == e1000_pch_spt)) {
4976 u32 pbeccsts = er32(PBECCSTS);
4977
4978 adapter->corr_errors +=
4979 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4980 adapter->uncorr_errors +=
4981 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4982 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4983 }
4984 }
4985
4986 /**
4987 * e1000_phy_read_status - Update the PHY register status snapshot
4988 * @adapter: board private structure
4989 **/
4990 static void e1000_phy_read_status(struct e1000_adapter *adapter)
4991 {
4992 struct e1000_hw *hw = &adapter->hw;
4993 struct e1000_phy_regs *phy = &adapter->phy_regs;
4994
4995 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4996 (er32(STATUS) & E1000_STATUS_LU) &&
4997 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
4998 int ret_val;
4999
5000 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5001 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5002 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5003 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5004 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5005 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5006 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5007 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5008 if (ret_val)
5009 e_warn("Error reading PHY register\n");
5010 } else {
5011 /* Do not read PHY registers if link is not up
5012 * Set values to typical power-on defaults
5013 */
5014 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5015 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5016 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5017 BMSR_ERCAP);
5018 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5019 ADVERTISE_ALL | ADVERTISE_CSMA);
5020 phy->lpa = 0;
5021 phy->expansion = EXPANSION_ENABLENPAGE;
5022 phy->ctrl1000 = ADVERTISE_1000FULL;
5023 phy->stat1000 = 0;
5024 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5025 }
5026 }
5027
5028 static void e1000_print_link_info(struct e1000_adapter *adapter)
5029 {
5030 struct e1000_hw *hw = &adapter->hw;
5031 u32 ctrl = er32(CTRL);
5032
5033 /* Link status message must follow this format for user tools */
5034 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5035 adapter->netdev->name, adapter->link_speed,
5036 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5037 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5038 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5039 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5040 }
5041
5042 static bool e1000e_has_link(struct e1000_adapter *adapter)
5043 {
5044 struct e1000_hw *hw = &adapter->hw;
5045 bool link_active = false;
5046 s32 ret_val = 0;
5047
5048 /* get_link_status is set on LSC (link status) interrupt or
5049 * Rx sequence error interrupt. get_link_status will stay
5050 * false until the check_for_link establishes link
5051 * for copper adapters ONLY
5052 */
5053 switch (hw->phy.media_type) {
5054 case e1000_media_type_copper:
5055 if (hw->mac.get_link_status) {
5056 ret_val = hw->mac.ops.check_for_link(hw);
5057 link_active = !hw->mac.get_link_status;
5058 } else {
5059 link_active = true;
5060 }
5061 break;
5062 case e1000_media_type_fiber:
5063 ret_val = hw->mac.ops.check_for_link(hw);
5064 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5065 break;
5066 case e1000_media_type_internal_serdes:
5067 ret_val = hw->mac.ops.check_for_link(hw);
5068 link_active = adapter->hw.mac.serdes_has_link;
5069 break;
5070 default:
5071 case e1000_media_type_unknown:
5072 break;
5073 }
5074
5075 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5076 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5077 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5078 e_info("Gigabit has been disabled, downgrading speed\n");
5079 }
5080
5081 return link_active;
5082 }
5083
5084 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5085 {
5086 /* make sure the receive unit is started */
5087 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5088 (adapter->flags & FLAG_RESTART_NOW)) {
5089 struct e1000_hw *hw = &adapter->hw;
5090 u32 rctl = er32(RCTL);
5091
5092 ew32(RCTL, rctl | E1000_RCTL_EN);
5093 adapter->flags &= ~FLAG_RESTART_NOW;
5094 }
5095 }
5096
5097 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5098 {
5099 struct e1000_hw *hw = &adapter->hw;
5100
5101 /* With 82574 controllers, PHY needs to be checked periodically
5102 * for hung state and reset, if two calls return true
5103 */
5104 if (e1000_check_phy_82574(hw))
5105 adapter->phy_hang_count++;
5106 else
5107 adapter->phy_hang_count = 0;
5108
5109 if (adapter->phy_hang_count > 1) {
5110 adapter->phy_hang_count = 0;
5111 e_dbg("PHY appears hung - resetting\n");
5112 schedule_work(&adapter->reset_task);
5113 }
5114 }
5115
5116 /**
5117 * e1000_watchdog - Timer Call-back
5118 * @data: pointer to adapter cast into an unsigned long
5119 **/
5120 static void e1000_watchdog(unsigned long data)
5121 {
5122 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
5123
5124 /* Do the rest outside of interrupt context */
5125 schedule_work(&adapter->watchdog_task);
5126
5127 /* TODO: make this use queue_delayed_work() */
5128 }
5129
5130 static void e1000_watchdog_task(struct work_struct *work)
5131 {
5132 struct e1000_adapter *adapter = container_of(work,
5133 struct e1000_adapter,
5134 watchdog_task);
5135 struct net_device *netdev = adapter->netdev;
5136 struct e1000_mac_info *mac = &adapter->hw.mac;
5137 struct e1000_phy_info *phy = &adapter->hw.phy;
5138 struct e1000_ring *tx_ring = adapter->tx_ring;
5139 struct e1000_hw *hw = &adapter->hw;
5140 u32 link, tctl;
5141
5142 if (test_bit(__E1000_DOWN, &adapter->state))
5143 return;
5144
5145 link = e1000e_has_link(adapter);
5146 if ((netif_carrier_ok(netdev)) && link) {
5147 /* Cancel scheduled suspend requests. */
5148 pm_runtime_resume(netdev->dev.parent);
5149
5150 e1000e_enable_receives(adapter);
5151 goto link_up;
5152 }
5153
5154 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5155 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5156 e1000_update_mng_vlan(adapter);
5157
5158 if (link) {
5159 if (!netif_carrier_ok(netdev)) {
5160 bool txb2b = true;
5161
5162 /* Cancel scheduled suspend requests. */
5163 pm_runtime_resume(netdev->dev.parent);
5164
5165 /* update snapshot of PHY registers on LSC */
5166 e1000_phy_read_status(adapter);
5167 mac->ops.get_link_up_info(&adapter->hw,
5168 &adapter->link_speed,
5169 &adapter->link_duplex);
5170 e1000_print_link_info(adapter);
5171
5172 /* check if SmartSpeed worked */
5173 e1000e_check_downshift(hw);
5174 if (phy->speed_downgraded)
5175 netdev_warn(netdev,
5176 "Link Speed was downgraded by SmartSpeed\n");
5177
5178 /* On supported PHYs, check for duplex mismatch only
5179 * if link has autonegotiated at 10/100 half
5180 */
5181 if ((hw->phy.type == e1000_phy_igp_3 ||
5182 hw->phy.type == e1000_phy_bm) &&
5183 hw->mac.autoneg &&
5184 (adapter->link_speed == SPEED_10 ||
5185 adapter->link_speed == SPEED_100) &&
5186 (adapter->link_duplex == HALF_DUPLEX)) {
5187 u16 autoneg_exp;
5188
5189 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5190
5191 if (!(autoneg_exp & EXPANSION_NWAY))
5192 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5193 }
5194
5195 /* adjust timeout factor according to speed/duplex */
5196 adapter->tx_timeout_factor = 1;
5197 switch (adapter->link_speed) {
5198 case SPEED_10:
5199 txb2b = false;
5200 adapter->tx_timeout_factor = 16;
5201 break;
5202 case SPEED_100:
5203 txb2b = false;
5204 adapter->tx_timeout_factor = 10;
5205 break;
5206 }
5207
5208 /* workaround: re-program speed mode bit after
5209 * link-up event
5210 */
5211 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5212 !txb2b) {
5213 u32 tarc0;
5214
5215 tarc0 = er32(TARC(0));
5216 tarc0 &= ~SPEED_MODE_BIT;
5217 ew32(TARC(0), tarc0);
5218 }
5219
5220 /* disable TSO for pcie and 10/100 speeds, to avoid
5221 * some hardware issues
5222 */
5223 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5224 switch (adapter->link_speed) {
5225 case SPEED_10:
5226 case SPEED_100:
5227 e_info("10/100 speed: disabling TSO\n");
5228 netdev->features &= ~NETIF_F_TSO;
5229 netdev->features &= ~NETIF_F_TSO6;
5230 break;
5231 case SPEED_1000:
5232 netdev->features |= NETIF_F_TSO;
5233 netdev->features |= NETIF_F_TSO6;
5234 break;
5235 default:
5236 /* oops */
5237 break;
5238 }
5239 }
5240
5241 /* enable transmits in the hardware, need to do this
5242 * after setting TARC(0)
5243 */
5244 tctl = er32(TCTL);
5245 tctl |= E1000_TCTL_EN;
5246 ew32(TCTL, tctl);
5247
5248 /* Perform any post-link-up configuration before
5249 * reporting link up.
5250 */
5251 if (phy->ops.cfg_on_link_up)
5252 phy->ops.cfg_on_link_up(hw);
5253
5254 netif_carrier_on(netdev);
5255
5256 if (!test_bit(__E1000_DOWN, &adapter->state))
5257 mod_timer(&adapter->phy_info_timer,
5258 round_jiffies(jiffies + 2 * HZ));
5259 }
5260 } else {
5261 if (netif_carrier_ok(netdev)) {
5262 adapter->link_speed = 0;
5263 adapter->link_duplex = 0;
5264 /* Link status message must follow this format */
5265 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5266 netif_carrier_off(netdev);
5267 if (!test_bit(__E1000_DOWN, &adapter->state))
5268 mod_timer(&adapter->phy_info_timer,
5269 round_jiffies(jiffies + 2 * HZ));
5270
5271 /* 8000ES2LAN requires a Rx packet buffer work-around
5272 * on link down event; reset the controller to flush
5273 * the Rx packet buffer.
5274 */
5275 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5276 adapter->flags |= FLAG_RESTART_NOW;
5277 else
5278 pm_schedule_suspend(netdev->dev.parent,
5279 LINK_TIMEOUT);
5280 }
5281 }
5282
5283 link_up:
5284 spin_lock(&adapter->stats64_lock);
5285 e1000e_update_stats(adapter);
5286
5287 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5288 adapter->tpt_old = adapter->stats.tpt;
5289 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5290 adapter->colc_old = adapter->stats.colc;
5291
5292 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5293 adapter->gorc_old = adapter->stats.gorc;
5294 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5295 adapter->gotc_old = adapter->stats.gotc;
5296 spin_unlock(&adapter->stats64_lock);
5297
5298 /* If the link is lost the controller stops DMA, but
5299 * if there is queued Tx work it cannot be done. So
5300 * reset the controller to flush the Tx packet buffers.
5301 */
5302 if (!netif_carrier_ok(netdev) &&
5303 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5304 adapter->flags |= FLAG_RESTART_NOW;
5305
5306 /* If reset is necessary, do it outside of interrupt context. */
5307 if (adapter->flags & FLAG_RESTART_NOW) {
5308 schedule_work(&adapter->reset_task);
5309 /* return immediately since reset is imminent */
5310 return;
5311 }
5312
5313 e1000e_update_adaptive(&adapter->hw);
5314
5315 /* Simple mode for Interrupt Throttle Rate (ITR) */
5316 if (adapter->itr_setting == 4) {
5317 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5318 * Total asymmetrical Tx or Rx gets ITR=8000;
5319 * everyone else is between 2000-8000.
5320 */
5321 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5322 u32 dif = (adapter->gotc > adapter->gorc ?
5323 adapter->gotc - adapter->gorc :
5324 adapter->gorc - adapter->gotc) / 10000;
5325 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5326
5327 e1000e_write_itr(adapter, itr);
5328 }
5329
5330 /* Cause software interrupt to ensure Rx ring is cleaned */
5331 if (adapter->msix_entries)
5332 ew32(ICS, adapter->rx_ring->ims_val);
5333 else
5334 ew32(ICS, E1000_ICS_RXDMT0);
5335
5336 /* flush pending descriptors to memory before detecting Tx hang */
5337 e1000e_flush_descriptors(adapter);
5338
5339 /* Force detection of hung controller every watchdog period */
5340 adapter->detect_tx_hung = true;
5341
5342 /* With 82571 controllers, LAA may be overwritten due to controller
5343 * reset from the other port. Set the appropriate LAA in RAR[0]
5344 */
5345 if (e1000e_get_laa_state_82571(hw))
5346 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5347
5348 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5349 e1000e_check_82574_phy_workaround(adapter);
5350
5351 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5352 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5353 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5354 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5355 er32(RXSTMPH);
5356 adapter->rx_hwtstamp_cleared++;
5357 } else {
5358 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5359 }
5360 }
5361
5362 /* Reset the timer */
5363 if (!test_bit(__E1000_DOWN, &adapter->state))
5364 mod_timer(&adapter->watchdog_timer,
5365 round_jiffies(jiffies + 2 * HZ));
5366 }
5367
5368 #define E1000_TX_FLAGS_CSUM 0x00000001
5369 #define E1000_TX_FLAGS_VLAN 0x00000002
5370 #define E1000_TX_FLAGS_TSO 0x00000004
5371 #define E1000_TX_FLAGS_IPV4 0x00000008
5372 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5373 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5374 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5375 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5376
5377 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5378 __be16 protocol)
5379 {
5380 struct e1000_context_desc *context_desc;
5381 struct e1000_buffer *buffer_info;
5382 unsigned int i;
5383 u32 cmd_length = 0;
5384 u16 ipcse = 0, mss;
5385 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5386 int err;
5387
5388 if (!skb_is_gso(skb))
5389 return 0;
5390
5391 err = skb_cow_head(skb, 0);
5392 if (err < 0)
5393 return err;
5394
5395 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5396 mss = skb_shinfo(skb)->gso_size;
5397 if (protocol == htons(ETH_P_IP)) {
5398 struct iphdr *iph = ip_hdr(skb);
5399 iph->tot_len = 0;
5400 iph->check = 0;
5401 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5402 0, IPPROTO_TCP, 0);
5403 cmd_length = E1000_TXD_CMD_IP;
5404 ipcse = skb_transport_offset(skb) - 1;
5405 } else if (skb_is_gso_v6(skb)) {
5406 ipv6_hdr(skb)->payload_len = 0;
5407 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5408 &ipv6_hdr(skb)->daddr,
5409 0, IPPROTO_TCP, 0);
5410 ipcse = 0;
5411 }
5412 ipcss = skb_network_offset(skb);
5413 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5414 tucss = skb_transport_offset(skb);
5415 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5416
5417 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5418 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5419
5420 i = tx_ring->next_to_use;
5421 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5422 buffer_info = &tx_ring->buffer_info[i];
5423
5424 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5425 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5426 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5427 context_desc->upper_setup.tcp_fields.tucss = tucss;
5428 context_desc->upper_setup.tcp_fields.tucso = tucso;
5429 context_desc->upper_setup.tcp_fields.tucse = 0;
5430 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5431 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5432 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5433
5434 buffer_info->time_stamp = jiffies;
5435 buffer_info->next_to_watch = i;
5436
5437 i++;
5438 if (i == tx_ring->count)
5439 i = 0;
5440 tx_ring->next_to_use = i;
5441
5442 return 1;
5443 }
5444
5445 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5446 __be16 protocol)
5447 {
5448 struct e1000_adapter *adapter = tx_ring->adapter;
5449 struct e1000_context_desc *context_desc;
5450 struct e1000_buffer *buffer_info;
5451 unsigned int i;
5452 u8 css;
5453 u32 cmd_len = E1000_TXD_CMD_DEXT;
5454
5455 if (skb->ip_summed != CHECKSUM_PARTIAL)
5456 return false;
5457
5458 switch (protocol) {
5459 case cpu_to_be16(ETH_P_IP):
5460 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5461 cmd_len |= E1000_TXD_CMD_TCP;
5462 break;
5463 case cpu_to_be16(ETH_P_IPV6):
5464 /* XXX not handling all IPV6 headers */
5465 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5466 cmd_len |= E1000_TXD_CMD_TCP;
5467 break;
5468 default:
5469 if (unlikely(net_ratelimit()))
5470 e_warn("checksum_partial proto=%x!\n",
5471 be16_to_cpu(protocol));
5472 break;
5473 }
5474
5475 css = skb_checksum_start_offset(skb);
5476
5477 i = tx_ring->next_to_use;
5478 buffer_info = &tx_ring->buffer_info[i];
5479 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5480
5481 context_desc->lower_setup.ip_config = 0;
5482 context_desc->upper_setup.tcp_fields.tucss = css;
5483 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5484 context_desc->upper_setup.tcp_fields.tucse = 0;
5485 context_desc->tcp_seg_setup.data = 0;
5486 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5487
5488 buffer_info->time_stamp = jiffies;
5489 buffer_info->next_to_watch = i;
5490
5491 i++;
5492 if (i == tx_ring->count)
5493 i = 0;
5494 tx_ring->next_to_use = i;
5495
5496 return true;
5497 }
5498
5499 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5500 unsigned int first, unsigned int max_per_txd,
5501 unsigned int nr_frags)
5502 {
5503 struct e1000_adapter *adapter = tx_ring->adapter;
5504 struct pci_dev *pdev = adapter->pdev;
5505 struct e1000_buffer *buffer_info;
5506 unsigned int len = skb_headlen(skb);
5507 unsigned int offset = 0, size, count = 0, i;
5508 unsigned int f, bytecount, segs;
5509
5510 i = tx_ring->next_to_use;
5511
5512 while (len) {
5513 buffer_info = &tx_ring->buffer_info[i];
5514 size = min(len, max_per_txd);
5515
5516 buffer_info->length = size;
5517 buffer_info->time_stamp = jiffies;
5518 buffer_info->next_to_watch = i;
5519 buffer_info->dma = dma_map_single(&pdev->dev,
5520 skb->data + offset,
5521 size, DMA_TO_DEVICE);
5522 buffer_info->mapped_as_page = false;
5523 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5524 goto dma_error;
5525
5526 len -= size;
5527 offset += size;
5528 count++;
5529
5530 if (len) {
5531 i++;
5532 if (i == tx_ring->count)
5533 i = 0;
5534 }
5535 }
5536
5537 for (f = 0; f < nr_frags; f++) {
5538 const struct skb_frag_struct *frag;
5539
5540 frag = &skb_shinfo(skb)->frags[f];
5541 len = skb_frag_size(frag);
5542 offset = 0;
5543
5544 while (len) {
5545 i++;
5546 if (i == tx_ring->count)
5547 i = 0;
5548
5549 buffer_info = &tx_ring->buffer_info[i];
5550 size = min(len, max_per_txd);
5551
5552 buffer_info->length = size;
5553 buffer_info->time_stamp = jiffies;
5554 buffer_info->next_to_watch = i;
5555 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5556 offset, size,
5557 DMA_TO_DEVICE);
5558 buffer_info->mapped_as_page = true;
5559 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5560 goto dma_error;
5561
5562 len -= size;
5563 offset += size;
5564 count++;
5565 }
5566 }
5567
5568 segs = skb_shinfo(skb)->gso_segs ? : 1;
5569 /* multiply data chunks by size of headers */
5570 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5571
5572 tx_ring->buffer_info[i].skb = skb;
5573 tx_ring->buffer_info[i].segs = segs;
5574 tx_ring->buffer_info[i].bytecount = bytecount;
5575 tx_ring->buffer_info[first].next_to_watch = i;
5576
5577 return count;
5578
5579 dma_error:
5580 dev_err(&pdev->dev, "Tx DMA map failed\n");
5581 buffer_info->dma = 0;
5582 if (count)
5583 count--;
5584
5585 while (count--) {
5586 if (i == 0)
5587 i += tx_ring->count;
5588 i--;
5589 buffer_info = &tx_ring->buffer_info[i];
5590 e1000_put_txbuf(tx_ring, buffer_info);
5591 }
5592
5593 return 0;
5594 }
5595
5596 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5597 {
5598 struct e1000_adapter *adapter = tx_ring->adapter;
5599 struct e1000_tx_desc *tx_desc = NULL;
5600 struct e1000_buffer *buffer_info;
5601 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5602 unsigned int i;
5603
5604 if (tx_flags & E1000_TX_FLAGS_TSO) {
5605 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5606 E1000_TXD_CMD_TSE;
5607 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5608
5609 if (tx_flags & E1000_TX_FLAGS_IPV4)
5610 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5611 }
5612
5613 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5614 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5615 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5616 }
5617
5618 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5619 txd_lower |= E1000_TXD_CMD_VLE;
5620 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5621 }
5622
5623 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5624 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5625
5626 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5627 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5628 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5629 }
5630
5631 i = tx_ring->next_to_use;
5632
5633 do {
5634 buffer_info = &tx_ring->buffer_info[i];
5635 tx_desc = E1000_TX_DESC(*tx_ring, i);
5636 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5637 tx_desc->lower.data = cpu_to_le32(txd_lower |
5638 buffer_info->length);
5639 tx_desc->upper.data = cpu_to_le32(txd_upper);
5640
5641 i++;
5642 if (i == tx_ring->count)
5643 i = 0;
5644 } while (--count > 0);
5645
5646 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5647
5648 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5649 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5650 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5651
5652 /* Force memory writes to complete before letting h/w
5653 * know there are new descriptors to fetch. (Only
5654 * applicable for weak-ordered memory model archs,
5655 * such as IA-64).
5656 */
5657 wmb();
5658
5659 tx_ring->next_to_use = i;
5660 }
5661
5662 #define MINIMUM_DHCP_PACKET_SIZE 282
5663 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5664 struct sk_buff *skb)
5665 {
5666 struct e1000_hw *hw = &adapter->hw;
5667 u16 length, offset;
5668
5669 if (skb_vlan_tag_present(skb) &&
5670 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5671 (adapter->hw.mng_cookie.status &
5672 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5673 return 0;
5674
5675 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5676 return 0;
5677
5678 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5679 return 0;
5680
5681 {
5682 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5683 struct udphdr *udp;
5684
5685 if (ip->protocol != IPPROTO_UDP)
5686 return 0;
5687
5688 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5689 if (ntohs(udp->dest) != 67)
5690 return 0;
5691
5692 offset = (u8 *)udp + 8 - skb->data;
5693 length = skb->len - offset;
5694 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5695 }
5696
5697 return 0;
5698 }
5699
5700 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5701 {
5702 struct e1000_adapter *adapter = tx_ring->adapter;
5703
5704 netif_stop_queue(adapter->netdev);
5705 /* Herbert's original patch had:
5706 * smp_mb__after_netif_stop_queue();
5707 * but since that doesn't exist yet, just open code it.
5708 */
5709 smp_mb();
5710
5711 /* We need to check again in a case another CPU has just
5712 * made room available.
5713 */
5714 if (e1000_desc_unused(tx_ring) < size)
5715 return -EBUSY;
5716
5717 /* A reprieve! */
5718 netif_start_queue(adapter->netdev);
5719 ++adapter->restart_queue;
5720 return 0;
5721 }
5722
5723 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5724 {
5725 BUG_ON(size > tx_ring->count);
5726
5727 if (e1000_desc_unused(tx_ring) >= size)
5728 return 0;
5729 return __e1000_maybe_stop_tx(tx_ring, size);
5730 }
5731
5732 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5733 struct net_device *netdev)
5734 {
5735 struct e1000_adapter *adapter = netdev_priv(netdev);
5736 struct e1000_ring *tx_ring = adapter->tx_ring;
5737 unsigned int first;
5738 unsigned int tx_flags = 0;
5739 unsigned int len = skb_headlen(skb);
5740 unsigned int nr_frags;
5741 unsigned int mss;
5742 int count = 0;
5743 int tso;
5744 unsigned int f;
5745 __be16 protocol = vlan_get_protocol(skb);
5746
5747 if (test_bit(__E1000_DOWN, &adapter->state)) {
5748 dev_kfree_skb_any(skb);
5749 return NETDEV_TX_OK;
5750 }
5751
5752 if (skb->len <= 0) {
5753 dev_kfree_skb_any(skb);
5754 return NETDEV_TX_OK;
5755 }
5756
5757 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5758 * pad skb in order to meet this minimum size requirement
5759 */
5760 if (skb_put_padto(skb, 17))
5761 return NETDEV_TX_OK;
5762
5763 mss = skb_shinfo(skb)->gso_size;
5764 if (mss) {
5765 u8 hdr_len;
5766
5767 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5768 * points to just header, pull a few bytes of payload from
5769 * frags into skb->data
5770 */
5771 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5772 /* we do this workaround for ES2LAN, but it is un-necessary,
5773 * avoiding it could save a lot of cycles
5774 */
5775 if (skb->data_len && (hdr_len == len)) {
5776 unsigned int pull_size;
5777
5778 pull_size = min_t(unsigned int, 4, skb->data_len);
5779 if (!__pskb_pull_tail(skb, pull_size)) {
5780 e_err("__pskb_pull_tail failed.\n");
5781 dev_kfree_skb_any(skb);
5782 return NETDEV_TX_OK;
5783 }
5784 len = skb_headlen(skb);
5785 }
5786 }
5787
5788 /* reserve a descriptor for the offload context */
5789 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5790 count++;
5791 count++;
5792
5793 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5794
5795 nr_frags = skb_shinfo(skb)->nr_frags;
5796 for (f = 0; f < nr_frags; f++)
5797 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5798 adapter->tx_fifo_limit);
5799
5800 if (adapter->hw.mac.tx_pkt_filtering)
5801 e1000_transfer_dhcp_info(adapter, skb);
5802
5803 /* need: count + 2 desc gap to keep tail from touching
5804 * head, otherwise try next time
5805 */
5806 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5807 return NETDEV_TX_BUSY;
5808
5809 if (skb_vlan_tag_present(skb)) {
5810 tx_flags |= E1000_TX_FLAGS_VLAN;
5811 tx_flags |= (skb_vlan_tag_get(skb) <<
5812 E1000_TX_FLAGS_VLAN_SHIFT);
5813 }
5814
5815 first = tx_ring->next_to_use;
5816
5817 tso = e1000_tso(tx_ring, skb, protocol);
5818 if (tso < 0) {
5819 dev_kfree_skb_any(skb);
5820 return NETDEV_TX_OK;
5821 }
5822
5823 if (tso)
5824 tx_flags |= E1000_TX_FLAGS_TSO;
5825 else if (e1000_tx_csum(tx_ring, skb, protocol))
5826 tx_flags |= E1000_TX_FLAGS_CSUM;
5827
5828 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5829 * 82571 hardware supports TSO capabilities for IPv6 as well...
5830 * no longer assume, we must.
5831 */
5832 if (protocol == htons(ETH_P_IP))
5833 tx_flags |= E1000_TX_FLAGS_IPV4;
5834
5835 if (unlikely(skb->no_fcs))
5836 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5837
5838 /* if count is 0 then mapping error has occurred */
5839 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5840 nr_frags);
5841 if (count) {
5842 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5843 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) &&
5844 !adapter->tx_hwtstamp_skb) {
5845 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5846 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5847 adapter->tx_hwtstamp_skb = skb_get(skb);
5848 adapter->tx_hwtstamp_start = jiffies;
5849 schedule_work(&adapter->tx_hwtstamp_work);
5850 } else {
5851 skb_tx_timestamp(skb);
5852 }
5853
5854 netdev_sent_queue(netdev, skb->len);
5855 e1000_tx_queue(tx_ring, tx_flags, count);
5856 /* Make sure there is space in the ring for the next send. */
5857 e1000_maybe_stop_tx(tx_ring,
5858 (MAX_SKB_FRAGS *
5859 DIV_ROUND_UP(PAGE_SIZE,
5860 adapter->tx_fifo_limit) + 2));
5861
5862 if (!skb->xmit_more ||
5863 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5864 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5865 e1000e_update_tdt_wa(tx_ring,
5866 tx_ring->next_to_use);
5867 else
5868 writel(tx_ring->next_to_use, tx_ring->tail);
5869
5870 /* we need this if more than one processor can write
5871 * to our tail at a time, it synchronizes IO on
5872 *IA64/Altix systems
5873 */
5874 mmiowb();
5875 }
5876 } else {
5877 dev_kfree_skb_any(skb);
5878 tx_ring->buffer_info[first].time_stamp = 0;
5879 tx_ring->next_to_use = first;
5880 }
5881
5882 return NETDEV_TX_OK;
5883 }
5884
5885 /**
5886 * e1000_tx_timeout - Respond to a Tx Hang
5887 * @netdev: network interface device structure
5888 **/
5889 static void e1000_tx_timeout(struct net_device *netdev)
5890 {
5891 struct e1000_adapter *adapter = netdev_priv(netdev);
5892
5893 /* Do the reset outside of interrupt context */
5894 adapter->tx_timeout_count++;
5895 schedule_work(&adapter->reset_task);
5896 }
5897
5898 static void e1000_reset_task(struct work_struct *work)
5899 {
5900 struct e1000_adapter *adapter;
5901 adapter = container_of(work, struct e1000_adapter, reset_task);
5902
5903 /* don't run the task if already down */
5904 if (test_bit(__E1000_DOWN, &adapter->state))
5905 return;
5906
5907 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5908 e1000e_dump(adapter);
5909 e_err("Reset adapter unexpectedly\n");
5910 }
5911 e1000e_reinit_locked(adapter);
5912 }
5913
5914 /**
5915 * e1000_get_stats64 - Get System Network Statistics
5916 * @netdev: network interface device structure
5917 * @stats: rtnl_link_stats64 pointer
5918 *
5919 * Returns the address of the device statistics structure.
5920 **/
5921 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5922 struct rtnl_link_stats64 *stats)
5923 {
5924 struct e1000_adapter *adapter = netdev_priv(netdev);
5925
5926 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5927 spin_lock(&adapter->stats64_lock);
5928 e1000e_update_stats(adapter);
5929 /* Fill out the OS statistics structure */
5930 stats->rx_bytes = adapter->stats.gorc;
5931 stats->rx_packets = adapter->stats.gprc;
5932 stats->tx_bytes = adapter->stats.gotc;
5933 stats->tx_packets = adapter->stats.gptc;
5934 stats->multicast = adapter->stats.mprc;
5935 stats->collisions = adapter->stats.colc;
5936
5937 /* Rx Errors */
5938
5939 /* RLEC on some newer hardware can be incorrect so build
5940 * our own version based on RUC and ROC
5941 */
5942 stats->rx_errors = adapter->stats.rxerrc +
5943 adapter->stats.crcerrs + adapter->stats.algnerrc +
5944 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5945 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5946 stats->rx_crc_errors = adapter->stats.crcerrs;
5947 stats->rx_frame_errors = adapter->stats.algnerrc;
5948 stats->rx_missed_errors = adapter->stats.mpc;
5949
5950 /* Tx Errors */
5951 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5952 stats->tx_aborted_errors = adapter->stats.ecol;
5953 stats->tx_window_errors = adapter->stats.latecol;
5954 stats->tx_carrier_errors = adapter->stats.tncrs;
5955
5956 /* Tx Dropped needs to be maintained elsewhere */
5957
5958 spin_unlock(&adapter->stats64_lock);
5959 return stats;
5960 }
5961
5962 /**
5963 * e1000_change_mtu - Change the Maximum Transfer Unit
5964 * @netdev: network interface device structure
5965 * @new_mtu: new value for maximum frame size
5966 *
5967 * Returns 0 on success, negative on failure
5968 **/
5969 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5970 {
5971 struct e1000_adapter *adapter = netdev_priv(netdev);
5972 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5973
5974 /* Jumbo frame support */
5975 if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
5976 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5977 e_err("Jumbo Frames not supported.\n");
5978 return -EINVAL;
5979 }
5980
5981 /* Supported frame sizes */
5982 if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
5983 (max_frame > adapter->max_hw_frame_size)) {
5984 e_err("Unsupported MTU setting\n");
5985 return -EINVAL;
5986 }
5987
5988 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5989 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
5990 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5991 (new_mtu > ETH_DATA_LEN)) {
5992 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
5993 return -EINVAL;
5994 }
5995
5996 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
5997 usleep_range(1000, 2000);
5998 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5999 adapter->max_frame_size = max_frame;
6000 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6001 netdev->mtu = new_mtu;
6002
6003 pm_runtime_get_sync(netdev->dev.parent);
6004
6005 if (netif_running(netdev))
6006 e1000e_down(adapter, true);
6007
6008 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6009 * means we reserve 2 more, this pushes us to allocate from the next
6010 * larger slab size.
6011 * i.e. RXBUFFER_2048 --> size-4096 slab
6012 * However with the new *_jumbo_rx* routines, jumbo receives will use
6013 * fragmented skbs
6014 */
6015
6016 if (max_frame <= 2048)
6017 adapter->rx_buffer_len = 2048;
6018 else
6019 adapter->rx_buffer_len = 4096;
6020
6021 /* adjust allocation if LPE protects us, and we aren't using SBP */
6022 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6023 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6024
6025 if (netif_running(netdev))
6026 e1000e_up(adapter);
6027 else
6028 e1000e_reset(adapter);
6029
6030 pm_runtime_put_sync(netdev->dev.parent);
6031
6032 clear_bit(__E1000_RESETTING, &adapter->state);
6033
6034 return 0;
6035 }
6036
6037 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6038 int cmd)
6039 {
6040 struct e1000_adapter *adapter = netdev_priv(netdev);
6041 struct mii_ioctl_data *data = if_mii(ifr);
6042
6043 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6044 return -EOPNOTSUPP;
6045
6046 switch (cmd) {
6047 case SIOCGMIIPHY:
6048 data->phy_id = adapter->hw.phy.addr;
6049 break;
6050 case SIOCGMIIREG:
6051 e1000_phy_read_status(adapter);
6052
6053 switch (data->reg_num & 0x1F) {
6054 case MII_BMCR:
6055 data->val_out = adapter->phy_regs.bmcr;
6056 break;
6057 case MII_BMSR:
6058 data->val_out = adapter->phy_regs.bmsr;
6059 break;
6060 case MII_PHYSID1:
6061 data->val_out = (adapter->hw.phy.id >> 16);
6062 break;
6063 case MII_PHYSID2:
6064 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6065 break;
6066 case MII_ADVERTISE:
6067 data->val_out = adapter->phy_regs.advertise;
6068 break;
6069 case MII_LPA:
6070 data->val_out = adapter->phy_regs.lpa;
6071 break;
6072 case MII_EXPANSION:
6073 data->val_out = adapter->phy_regs.expansion;
6074 break;
6075 case MII_CTRL1000:
6076 data->val_out = adapter->phy_regs.ctrl1000;
6077 break;
6078 case MII_STAT1000:
6079 data->val_out = adapter->phy_regs.stat1000;
6080 break;
6081 case MII_ESTATUS:
6082 data->val_out = adapter->phy_regs.estatus;
6083 break;
6084 default:
6085 return -EIO;
6086 }
6087 break;
6088 case SIOCSMIIREG:
6089 default:
6090 return -EOPNOTSUPP;
6091 }
6092 return 0;
6093 }
6094
6095 /**
6096 * e1000e_hwtstamp_ioctl - control hardware time stamping
6097 * @netdev: network interface device structure
6098 * @ifreq: interface request
6099 *
6100 * Outgoing time stamping can be enabled and disabled. Play nice and
6101 * disable it when requested, although it shouldn't cause any overhead
6102 * when no packet needs it. At most one packet in the queue may be
6103 * marked for time stamping, otherwise it would be impossible to tell
6104 * for sure to which packet the hardware time stamp belongs.
6105 *
6106 * Incoming time stamping has to be configured via the hardware filters.
6107 * Not all combinations are supported, in particular event type has to be
6108 * specified. Matching the kind of event packet is not supported, with the
6109 * exception of "all V2 events regardless of level 2 or 4".
6110 **/
6111 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6112 {
6113 struct e1000_adapter *adapter = netdev_priv(netdev);
6114 struct hwtstamp_config config;
6115 int ret_val;
6116
6117 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6118 return -EFAULT;
6119
6120 ret_val = e1000e_config_hwtstamp(adapter, &config);
6121 if (ret_val)
6122 return ret_val;
6123
6124 switch (config.rx_filter) {
6125 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6126 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6127 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6128 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6129 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6130 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6131 /* With V2 type filters which specify a Sync or Delay Request,
6132 * Path Delay Request/Response messages are also time stamped
6133 * by hardware so notify the caller the requested packets plus
6134 * some others are time stamped.
6135 */
6136 config.rx_filter = HWTSTAMP_FILTER_SOME;
6137 break;
6138 default:
6139 break;
6140 }
6141
6142 return copy_to_user(ifr->ifr_data, &config,
6143 sizeof(config)) ? -EFAULT : 0;
6144 }
6145
6146 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6147 {
6148 struct e1000_adapter *adapter = netdev_priv(netdev);
6149
6150 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6151 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6152 }
6153
6154 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6155 {
6156 switch (cmd) {
6157 case SIOCGMIIPHY:
6158 case SIOCGMIIREG:
6159 case SIOCSMIIREG:
6160 return e1000_mii_ioctl(netdev, ifr, cmd);
6161 case SIOCSHWTSTAMP:
6162 return e1000e_hwtstamp_set(netdev, ifr);
6163 case SIOCGHWTSTAMP:
6164 return e1000e_hwtstamp_get(netdev, ifr);
6165 default:
6166 return -EOPNOTSUPP;
6167 }
6168 }
6169
6170 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6171 {
6172 struct e1000_hw *hw = &adapter->hw;
6173 u32 i, mac_reg, wuc;
6174 u16 phy_reg, wuc_enable;
6175 int retval;
6176
6177 /* copy MAC RARs to PHY RARs */
6178 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6179
6180 retval = hw->phy.ops.acquire(hw);
6181 if (retval) {
6182 e_err("Could not acquire PHY\n");
6183 return retval;
6184 }
6185
6186 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6187 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6188 if (retval)
6189 goto release;
6190
6191 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6192 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6193 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6194 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6195 (u16)(mac_reg & 0xFFFF));
6196 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6197 (u16)((mac_reg >> 16) & 0xFFFF));
6198 }
6199
6200 /* configure PHY Rx Control register */
6201 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6202 mac_reg = er32(RCTL);
6203 if (mac_reg & E1000_RCTL_UPE)
6204 phy_reg |= BM_RCTL_UPE;
6205 if (mac_reg & E1000_RCTL_MPE)
6206 phy_reg |= BM_RCTL_MPE;
6207 phy_reg &= ~(BM_RCTL_MO_MASK);
6208 if (mac_reg & E1000_RCTL_MO_3)
6209 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6210 << BM_RCTL_MO_SHIFT);
6211 if (mac_reg & E1000_RCTL_BAM)
6212 phy_reg |= BM_RCTL_BAM;
6213 if (mac_reg & E1000_RCTL_PMCF)
6214 phy_reg |= BM_RCTL_PMCF;
6215 mac_reg = er32(CTRL);
6216 if (mac_reg & E1000_CTRL_RFCE)
6217 phy_reg |= BM_RCTL_RFCE;
6218 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6219
6220 wuc = E1000_WUC_PME_EN;
6221 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6222 wuc |= E1000_WUC_APME;
6223
6224 /* enable PHY wakeup in MAC register */
6225 ew32(WUFC, wufc);
6226 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6227 E1000_WUC_PME_STATUS | wuc));
6228
6229 /* configure and enable PHY wakeup in PHY registers */
6230 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6231 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6232
6233 /* activate PHY wakeup */
6234 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6235 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6236 if (retval)
6237 e_err("Could not set PHY Host Wakeup bit\n");
6238 release:
6239 hw->phy.ops.release(hw);
6240
6241 return retval;
6242 }
6243
6244 static void e1000e_flush_lpic(struct pci_dev *pdev)
6245 {
6246 struct net_device *netdev = pci_get_drvdata(pdev);
6247 struct e1000_adapter *adapter = netdev_priv(netdev);
6248 struct e1000_hw *hw = &adapter->hw;
6249 u32 ret_val;
6250
6251 pm_runtime_get_sync(netdev->dev.parent);
6252
6253 ret_val = hw->phy.ops.acquire(hw);
6254 if (ret_val)
6255 goto fl_out;
6256
6257 pr_info("EEE TX LPI TIMER: %08X\n",
6258 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6259
6260 hw->phy.ops.release(hw);
6261
6262 fl_out:
6263 pm_runtime_put_sync(netdev->dev.parent);
6264 }
6265
6266 static int e1000e_pm_freeze(struct device *dev)
6267 {
6268 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6269 struct e1000_adapter *adapter = netdev_priv(netdev);
6270
6271 netif_device_detach(netdev);
6272
6273 if (netif_running(netdev)) {
6274 int count = E1000_CHECK_RESET_COUNT;
6275
6276 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6277 usleep_range(10000, 20000);
6278
6279 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6280
6281 /* Quiesce the device without resetting the hardware */
6282 e1000e_down(adapter, false);
6283 e1000_free_irq(adapter);
6284 }
6285 e1000e_reset_interrupt_capability(adapter);
6286
6287 /* Allow time for pending master requests to run */
6288 e1000e_disable_pcie_master(&adapter->hw);
6289
6290 return 0;
6291 }
6292
6293 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6294 {
6295 struct net_device *netdev = pci_get_drvdata(pdev);
6296 struct e1000_adapter *adapter = netdev_priv(netdev);
6297 struct e1000_hw *hw = &adapter->hw;
6298 u32 ctrl, ctrl_ext, rctl, status;
6299 /* Runtime suspend should only enable wakeup for link changes */
6300 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6301 int retval = 0;
6302
6303 status = er32(STATUS);
6304 if (status & E1000_STATUS_LU)
6305 wufc &= ~E1000_WUFC_LNKC;
6306
6307 if (wufc) {
6308 e1000_setup_rctl(adapter);
6309 e1000e_set_rx_mode(netdev);
6310
6311 /* turn on all-multi mode if wake on multicast is enabled */
6312 if (wufc & E1000_WUFC_MC) {
6313 rctl = er32(RCTL);
6314 rctl |= E1000_RCTL_MPE;
6315 ew32(RCTL, rctl);
6316 }
6317
6318 ctrl = er32(CTRL);
6319 ctrl |= E1000_CTRL_ADVD3WUC;
6320 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6321 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6322 ew32(CTRL, ctrl);
6323
6324 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6325 adapter->hw.phy.media_type ==
6326 e1000_media_type_internal_serdes) {
6327 /* keep the laser running in D3 */
6328 ctrl_ext = er32(CTRL_EXT);
6329 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6330 ew32(CTRL_EXT, ctrl_ext);
6331 }
6332
6333 if (!runtime)
6334 e1000e_power_up_phy(adapter);
6335
6336 if (adapter->flags & FLAG_IS_ICH)
6337 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6338
6339 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6340 /* enable wakeup by the PHY */
6341 retval = e1000_init_phy_wakeup(adapter, wufc);
6342 if (retval)
6343 return retval;
6344 } else {
6345 /* enable wakeup by the MAC */
6346 ew32(WUFC, wufc);
6347 ew32(WUC, E1000_WUC_PME_EN);
6348 }
6349 } else {
6350 ew32(WUC, 0);
6351 ew32(WUFC, 0);
6352
6353 e1000_power_down_phy(adapter);
6354 }
6355
6356 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6357 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6358 } else if ((hw->mac.type == e1000_pch_lpt) ||
6359 (hw->mac.type == e1000_pch_spt)) {
6360 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6361 /* ULP does not support wake from unicast, multicast
6362 * or broadcast.
6363 */
6364 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6365
6366 if (retval)
6367 return retval;
6368 }
6369
6370 /* Ensure that the appropriate bits are set in LPI_CTRL
6371 * for EEE in Sx
6372 */
6373 if ((hw->phy.type >= e1000_phy_i217) &&
6374 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6375 u16 lpi_ctrl = 0;
6376
6377 retval = hw->phy.ops.acquire(hw);
6378 if (!retval) {
6379 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6380 &lpi_ctrl);
6381 if (!retval) {
6382 if (adapter->eee_advert &
6383 hw->dev_spec.ich8lan.eee_lp_ability &
6384 I82579_EEE_100_SUPPORTED)
6385 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6386 if (adapter->eee_advert &
6387 hw->dev_spec.ich8lan.eee_lp_ability &
6388 I82579_EEE_1000_SUPPORTED)
6389 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6390
6391 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6392 lpi_ctrl);
6393 }
6394 }
6395 hw->phy.ops.release(hw);
6396 }
6397
6398 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6399 * would have already happened in close and is redundant.
6400 */
6401 e1000e_release_hw_control(adapter);
6402
6403 pci_clear_master(pdev);
6404
6405 /* The pci-e switch on some quad port adapters will report a
6406 * correctable error when the MAC transitions from D0 to D3. To
6407 * prevent this we need to mask off the correctable errors on the
6408 * downstream port of the pci-e switch.
6409 *
6410 * We don't have the associated upstream bridge while assigning
6411 * the PCI device into guest. For example, the KVM on power is
6412 * one of the cases.
6413 */
6414 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6415 struct pci_dev *us_dev = pdev->bus->self;
6416 u16 devctl;
6417
6418 if (!us_dev)
6419 return 0;
6420
6421 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6422 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6423 (devctl & ~PCI_EXP_DEVCTL_CERE));
6424
6425 pci_save_state(pdev);
6426 pci_prepare_to_sleep(pdev);
6427
6428 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6429 }
6430
6431 return 0;
6432 }
6433
6434 /**
6435 * __e1000e_disable_aspm - Disable ASPM states
6436 * @pdev: pointer to PCI device struct
6437 * @state: bit-mask of ASPM states to disable
6438 * @locked: indication if this context holds pci_bus_sem locked.
6439 *
6440 * Some devices *must* have certain ASPM states disabled per hardware errata.
6441 **/
6442 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6443 {
6444 struct pci_dev *parent = pdev->bus->self;
6445 u16 aspm_dis_mask = 0;
6446 u16 pdev_aspmc, parent_aspmc;
6447
6448 switch (state) {
6449 case PCIE_LINK_STATE_L0S:
6450 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6451 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6452 /* fall-through - can't have L1 without L0s */
6453 case PCIE_LINK_STATE_L1:
6454 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6455 break;
6456 default:
6457 return;
6458 }
6459
6460 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6461 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6462
6463 if (parent) {
6464 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6465 &parent_aspmc);
6466 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6467 }
6468
6469 /* Nothing to do if the ASPM states to be disabled already are */
6470 if (!(pdev_aspmc & aspm_dis_mask) &&
6471 (!parent || !(parent_aspmc & aspm_dis_mask)))
6472 return;
6473
6474 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6475 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6476 "L0s" : "",
6477 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6478 "L1" : "");
6479
6480 #ifdef CONFIG_PCIEASPM
6481 if (locked)
6482 pci_disable_link_state_locked(pdev, state);
6483 else
6484 pci_disable_link_state(pdev, state);
6485
6486 /* Double-check ASPM control. If not disabled by the above, the
6487 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6488 * not enabled); override by writing PCI config space directly.
6489 */
6490 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6491 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6492
6493 if (!(aspm_dis_mask & pdev_aspmc))
6494 return;
6495 #endif
6496
6497 /* Both device and parent should have the same ASPM setting.
6498 * Disable ASPM in downstream component first and then upstream.
6499 */
6500 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6501
6502 if (parent)
6503 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6504 aspm_dis_mask);
6505 }
6506
6507 /**
6508 * e1000e_disable_aspm - Disable ASPM states.
6509 * @pdev: pointer to PCI device struct
6510 * @state: bit-mask of ASPM states to disable
6511 *
6512 * This function acquires the pci_bus_sem!
6513 * Some devices *must* have certain ASPM states disabled per hardware errata.
6514 **/
6515 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6516 {
6517 __e1000e_disable_aspm(pdev, state, 0);
6518 }
6519
6520 /**
6521 * e1000e_disable_aspm_locked Disable ASPM states.
6522 * @pdev: pointer to PCI device struct
6523 * @state: bit-mask of ASPM states to disable
6524 *
6525 * This function must be called with pci_bus_sem acquired!
6526 * Some devices *must* have certain ASPM states disabled per hardware errata.
6527 **/
6528 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6529 {
6530 __e1000e_disable_aspm(pdev, state, 1);
6531 }
6532
6533 #ifdef CONFIG_PM
6534 static int __e1000_resume(struct pci_dev *pdev)
6535 {
6536 struct net_device *netdev = pci_get_drvdata(pdev);
6537 struct e1000_adapter *adapter = netdev_priv(netdev);
6538 struct e1000_hw *hw = &adapter->hw;
6539 u16 aspm_disable_flag = 0;
6540
6541 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6542 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6543 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6544 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6545 if (aspm_disable_flag)
6546 e1000e_disable_aspm(pdev, aspm_disable_flag);
6547
6548 pci_set_master(pdev);
6549
6550 if (hw->mac.type >= e1000_pch2lan)
6551 e1000_resume_workarounds_pchlan(&adapter->hw);
6552
6553 e1000e_power_up_phy(adapter);
6554
6555 /* report the system wakeup cause from S3/S4 */
6556 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6557 u16 phy_data;
6558
6559 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6560 if (phy_data) {
6561 e_info("PHY Wakeup cause - %s\n",
6562 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6563 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6564 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6565 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6566 phy_data & E1000_WUS_LNKC ?
6567 "Link Status Change" : "other");
6568 }
6569 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6570 } else {
6571 u32 wus = er32(WUS);
6572
6573 if (wus) {
6574 e_info("MAC Wakeup cause - %s\n",
6575 wus & E1000_WUS_EX ? "Unicast Packet" :
6576 wus & E1000_WUS_MC ? "Multicast Packet" :
6577 wus & E1000_WUS_BC ? "Broadcast Packet" :
6578 wus & E1000_WUS_MAG ? "Magic Packet" :
6579 wus & E1000_WUS_LNKC ? "Link Status Change" :
6580 "other");
6581 }
6582 ew32(WUS, ~0);
6583 }
6584
6585 e1000e_reset(adapter);
6586
6587 e1000_init_manageability_pt(adapter);
6588
6589 /* If the controller has AMT, do not set DRV_LOAD until the interface
6590 * is up. For all other cases, let the f/w know that the h/w is now
6591 * under the control of the driver.
6592 */
6593 if (!(adapter->flags & FLAG_HAS_AMT))
6594 e1000e_get_hw_control(adapter);
6595
6596 return 0;
6597 }
6598
6599 #ifdef CONFIG_PM_SLEEP
6600 static int e1000e_pm_thaw(struct device *dev)
6601 {
6602 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6603 struct e1000_adapter *adapter = netdev_priv(netdev);
6604
6605 e1000e_set_interrupt_capability(adapter);
6606 if (netif_running(netdev)) {
6607 u32 err = e1000_request_irq(adapter);
6608
6609 if (err)
6610 return err;
6611
6612 e1000e_up(adapter);
6613 }
6614
6615 netif_device_attach(netdev);
6616
6617 return 0;
6618 }
6619
6620 static int e1000e_pm_suspend(struct device *dev)
6621 {
6622 struct pci_dev *pdev = to_pci_dev(dev);
6623
6624 e1000e_flush_lpic(pdev);
6625
6626 e1000e_pm_freeze(dev);
6627
6628 return __e1000_shutdown(pdev, false);
6629 }
6630
6631 static int e1000e_pm_resume(struct device *dev)
6632 {
6633 struct pci_dev *pdev = to_pci_dev(dev);
6634 int rc;
6635
6636 rc = __e1000_resume(pdev);
6637 if (rc)
6638 return rc;
6639
6640 return e1000e_pm_thaw(dev);
6641 }
6642 #endif /* CONFIG_PM_SLEEP */
6643
6644 static int e1000e_pm_runtime_idle(struct device *dev)
6645 {
6646 struct pci_dev *pdev = to_pci_dev(dev);
6647 struct net_device *netdev = pci_get_drvdata(pdev);
6648 struct e1000_adapter *adapter = netdev_priv(netdev);
6649 u16 eee_lp;
6650
6651 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6652
6653 if (!e1000e_has_link(adapter)) {
6654 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6655 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6656 }
6657
6658 return -EBUSY;
6659 }
6660
6661 static int e1000e_pm_runtime_resume(struct device *dev)
6662 {
6663 struct pci_dev *pdev = to_pci_dev(dev);
6664 struct net_device *netdev = pci_get_drvdata(pdev);
6665 struct e1000_adapter *adapter = netdev_priv(netdev);
6666 int rc;
6667
6668 rc = __e1000_resume(pdev);
6669 if (rc)
6670 return rc;
6671
6672 if (netdev->flags & IFF_UP)
6673 e1000e_up(adapter);
6674
6675 return rc;
6676 }
6677
6678 static int e1000e_pm_runtime_suspend(struct device *dev)
6679 {
6680 struct pci_dev *pdev = to_pci_dev(dev);
6681 struct net_device *netdev = pci_get_drvdata(pdev);
6682 struct e1000_adapter *adapter = netdev_priv(netdev);
6683
6684 if (netdev->flags & IFF_UP) {
6685 int count = E1000_CHECK_RESET_COUNT;
6686
6687 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6688 usleep_range(10000, 20000);
6689
6690 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6691
6692 /* Down the device without resetting the hardware */
6693 e1000e_down(adapter, false);
6694 }
6695
6696 if (__e1000_shutdown(pdev, true)) {
6697 e1000e_pm_runtime_resume(dev);
6698 return -EBUSY;
6699 }
6700
6701 return 0;
6702 }
6703 #endif /* CONFIG_PM */
6704
6705 static void e1000_shutdown(struct pci_dev *pdev)
6706 {
6707 e1000e_flush_lpic(pdev);
6708
6709 e1000e_pm_freeze(&pdev->dev);
6710
6711 __e1000_shutdown(pdev, false);
6712 }
6713
6714 #ifdef CONFIG_NET_POLL_CONTROLLER
6715
6716 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6717 {
6718 struct net_device *netdev = data;
6719 struct e1000_adapter *adapter = netdev_priv(netdev);
6720
6721 if (adapter->msix_entries) {
6722 int vector, msix_irq;
6723
6724 vector = 0;
6725 msix_irq = adapter->msix_entries[vector].vector;
6726 disable_irq(msix_irq);
6727 e1000_intr_msix_rx(msix_irq, netdev);
6728 enable_irq(msix_irq);
6729
6730 vector++;
6731 msix_irq = adapter->msix_entries[vector].vector;
6732 disable_irq(msix_irq);
6733 e1000_intr_msix_tx(msix_irq, netdev);
6734 enable_irq(msix_irq);
6735
6736 vector++;
6737 msix_irq = adapter->msix_entries[vector].vector;
6738 disable_irq(msix_irq);
6739 e1000_msix_other(msix_irq, netdev);
6740 enable_irq(msix_irq);
6741 }
6742
6743 return IRQ_HANDLED;
6744 }
6745
6746 /**
6747 * e1000_netpoll
6748 * @netdev: network interface device structure
6749 *
6750 * Polling 'interrupt' - used by things like netconsole to send skbs
6751 * without having to re-enable interrupts. It's not called while
6752 * the interrupt routine is executing.
6753 */
6754 static void e1000_netpoll(struct net_device *netdev)
6755 {
6756 struct e1000_adapter *adapter = netdev_priv(netdev);
6757
6758 switch (adapter->int_mode) {
6759 case E1000E_INT_MODE_MSIX:
6760 e1000_intr_msix(adapter->pdev->irq, netdev);
6761 break;
6762 case E1000E_INT_MODE_MSI:
6763 disable_irq(adapter->pdev->irq);
6764 e1000_intr_msi(adapter->pdev->irq, netdev);
6765 enable_irq(adapter->pdev->irq);
6766 break;
6767 default: /* E1000E_INT_MODE_LEGACY */
6768 disable_irq(adapter->pdev->irq);
6769 e1000_intr(adapter->pdev->irq, netdev);
6770 enable_irq(adapter->pdev->irq);
6771 break;
6772 }
6773 }
6774 #endif
6775
6776 /**
6777 * e1000_io_error_detected - called when PCI error is detected
6778 * @pdev: Pointer to PCI device
6779 * @state: The current pci connection state
6780 *
6781 * This function is called after a PCI bus error affecting
6782 * this device has been detected.
6783 */
6784 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6785 pci_channel_state_t state)
6786 {
6787 struct net_device *netdev = pci_get_drvdata(pdev);
6788 struct e1000_adapter *adapter = netdev_priv(netdev);
6789
6790 netif_device_detach(netdev);
6791
6792 if (state == pci_channel_io_perm_failure)
6793 return PCI_ERS_RESULT_DISCONNECT;
6794
6795 if (netif_running(netdev))
6796 e1000e_down(adapter, true);
6797 pci_disable_device(pdev);
6798
6799 /* Request a slot slot reset. */
6800 return PCI_ERS_RESULT_NEED_RESET;
6801 }
6802
6803 /**
6804 * e1000_io_slot_reset - called after the pci bus has been reset.
6805 * @pdev: Pointer to PCI device
6806 *
6807 * Restart the card from scratch, as if from a cold-boot. Implementation
6808 * resembles the first-half of the e1000e_pm_resume routine.
6809 */
6810 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6811 {
6812 struct net_device *netdev = pci_get_drvdata(pdev);
6813 struct e1000_adapter *adapter = netdev_priv(netdev);
6814 struct e1000_hw *hw = &adapter->hw;
6815 u16 aspm_disable_flag = 0;
6816 int err;
6817 pci_ers_result_t result;
6818
6819 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6820 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6821 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6822 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6823 if (aspm_disable_flag)
6824 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6825
6826 err = pci_enable_device_mem(pdev);
6827 if (err) {
6828 dev_err(&pdev->dev,
6829 "Cannot re-enable PCI device after reset.\n");
6830 result = PCI_ERS_RESULT_DISCONNECT;
6831 } else {
6832 pdev->state_saved = true;
6833 pci_restore_state(pdev);
6834 pci_set_master(pdev);
6835
6836 pci_enable_wake(pdev, PCI_D3hot, 0);
6837 pci_enable_wake(pdev, PCI_D3cold, 0);
6838
6839 e1000e_reset(adapter);
6840 ew32(WUS, ~0);
6841 result = PCI_ERS_RESULT_RECOVERED;
6842 }
6843
6844 pci_cleanup_aer_uncorrect_error_status(pdev);
6845
6846 return result;
6847 }
6848
6849 /**
6850 * e1000_io_resume - called when traffic can start flowing again.
6851 * @pdev: Pointer to PCI device
6852 *
6853 * This callback is called when the error recovery driver tells us that
6854 * its OK to resume normal operation. Implementation resembles the
6855 * second-half of the e1000e_pm_resume routine.
6856 */
6857 static void e1000_io_resume(struct pci_dev *pdev)
6858 {
6859 struct net_device *netdev = pci_get_drvdata(pdev);
6860 struct e1000_adapter *adapter = netdev_priv(netdev);
6861
6862 e1000_init_manageability_pt(adapter);
6863
6864 if (netif_running(netdev))
6865 e1000e_up(adapter);
6866
6867 netif_device_attach(netdev);
6868
6869 /* If the controller has AMT, do not set DRV_LOAD until the interface
6870 * is up. For all other cases, let the f/w know that the h/w is now
6871 * under the control of the driver.
6872 */
6873 if (!(adapter->flags & FLAG_HAS_AMT))
6874 e1000e_get_hw_control(adapter);
6875 }
6876
6877 static void e1000_print_device_info(struct e1000_adapter *adapter)
6878 {
6879 struct e1000_hw *hw = &adapter->hw;
6880 struct net_device *netdev = adapter->netdev;
6881 u32 ret_val;
6882 u8 pba_str[E1000_PBANUM_LENGTH];
6883
6884 /* print bus type/speed/width info */
6885 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6886 /* bus width */
6887 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6888 "Width x1"),
6889 /* MAC address */
6890 netdev->dev_addr);
6891 e_info("Intel(R) PRO/%s Network Connection\n",
6892 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6893 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6894 E1000_PBANUM_LENGTH);
6895 if (ret_val)
6896 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6897 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6898 hw->mac.type, hw->phy.type, pba_str);
6899 }
6900
6901 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6902 {
6903 struct e1000_hw *hw = &adapter->hw;
6904 int ret_val;
6905 u16 buf = 0;
6906
6907 if (hw->mac.type != e1000_82573)
6908 return;
6909
6910 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6911 le16_to_cpus(&buf);
6912 if (!ret_val && (!(buf & BIT(0)))) {
6913 /* Deep Smart Power Down (DSPD) */
6914 dev_warn(&adapter->pdev->dev,
6915 "Warning: detected DSPD enabled in EEPROM\n");
6916 }
6917 }
6918
6919 static netdev_features_t e1000_fix_features(struct net_device *netdev,
6920 netdev_features_t features)
6921 {
6922 struct e1000_adapter *adapter = netdev_priv(netdev);
6923 struct e1000_hw *hw = &adapter->hw;
6924
6925 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6926 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6927 features &= ~NETIF_F_RXFCS;
6928
6929 return features;
6930 }
6931
6932 static int e1000_set_features(struct net_device *netdev,
6933 netdev_features_t features)
6934 {
6935 struct e1000_adapter *adapter = netdev_priv(netdev);
6936 netdev_features_t changed = features ^ netdev->features;
6937
6938 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6939 adapter->flags |= FLAG_TSO_FORCE;
6940
6941 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6942 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6943 NETIF_F_RXALL)))
6944 return 0;
6945
6946 if (changed & NETIF_F_RXFCS) {
6947 if (features & NETIF_F_RXFCS) {
6948 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6949 } else {
6950 /* We need to take it back to defaults, which might mean
6951 * stripping is still disabled at the adapter level.
6952 */
6953 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6954 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6955 else
6956 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6957 }
6958 }
6959
6960 netdev->features = features;
6961
6962 if (netif_running(netdev))
6963 e1000e_reinit_locked(adapter);
6964 else
6965 e1000e_reset(adapter);
6966
6967 return 0;
6968 }
6969
6970 static const struct net_device_ops e1000e_netdev_ops = {
6971 .ndo_open = e1000e_open,
6972 .ndo_stop = e1000e_close,
6973 .ndo_start_xmit = e1000_xmit_frame,
6974 .ndo_get_stats64 = e1000e_get_stats64,
6975 .ndo_set_rx_mode = e1000e_set_rx_mode,
6976 .ndo_set_mac_address = e1000_set_mac,
6977 .ndo_change_mtu = e1000_change_mtu,
6978 .ndo_do_ioctl = e1000_ioctl,
6979 .ndo_tx_timeout = e1000_tx_timeout,
6980 .ndo_validate_addr = eth_validate_addr,
6981
6982 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6983 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6984 #ifdef CONFIG_NET_POLL_CONTROLLER
6985 .ndo_poll_controller = e1000_netpoll,
6986 #endif
6987 .ndo_set_features = e1000_set_features,
6988 .ndo_fix_features = e1000_fix_features,
6989 .ndo_features_check = passthru_features_check,
6990 };
6991
6992 /**
6993 * e1000_probe - Device Initialization Routine
6994 * @pdev: PCI device information struct
6995 * @ent: entry in e1000_pci_tbl
6996 *
6997 * Returns 0 on success, negative on failure
6998 *
6999 * e1000_probe initializes an adapter identified by a pci_dev structure.
7000 * The OS initialization, configuring of the adapter private structure,
7001 * and a hardware reset occur.
7002 **/
7003 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7004 {
7005 struct net_device *netdev;
7006 struct e1000_adapter *adapter;
7007 struct e1000_hw *hw;
7008 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7009 resource_size_t mmio_start, mmio_len;
7010 resource_size_t flash_start, flash_len;
7011 static int cards_found;
7012 u16 aspm_disable_flag = 0;
7013 int bars, i, err, pci_using_dac;
7014 u16 eeprom_data = 0;
7015 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7016 s32 ret_val = 0;
7017
7018 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7019 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7020 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7021 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7022 if (aspm_disable_flag)
7023 e1000e_disable_aspm(pdev, aspm_disable_flag);
7024
7025 err = pci_enable_device_mem(pdev);
7026 if (err)
7027 return err;
7028
7029 pci_using_dac = 0;
7030 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7031 if (!err) {
7032 pci_using_dac = 1;
7033 } else {
7034 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7035 if (err) {
7036 dev_err(&pdev->dev,
7037 "No usable DMA configuration, aborting\n");
7038 goto err_dma;
7039 }
7040 }
7041
7042 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7043 err = pci_request_selected_regions_exclusive(pdev, bars,
7044 e1000e_driver_name);
7045 if (err)
7046 goto err_pci_reg;
7047
7048 /* AER (Advanced Error Reporting) hooks */
7049 pci_enable_pcie_error_reporting(pdev);
7050
7051 pci_set_master(pdev);
7052 /* PCI config space info */
7053 err = pci_save_state(pdev);
7054 if (err)
7055 goto err_alloc_etherdev;
7056
7057 err = -ENOMEM;
7058 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7059 if (!netdev)
7060 goto err_alloc_etherdev;
7061
7062 SET_NETDEV_DEV(netdev, &pdev->dev);
7063
7064 netdev->irq = pdev->irq;
7065
7066 pci_set_drvdata(pdev, netdev);
7067 adapter = netdev_priv(netdev);
7068 hw = &adapter->hw;
7069 adapter->netdev = netdev;
7070 adapter->pdev = pdev;
7071 adapter->ei = ei;
7072 adapter->pba = ei->pba;
7073 adapter->flags = ei->flags;
7074 adapter->flags2 = ei->flags2;
7075 adapter->hw.adapter = adapter;
7076 adapter->hw.mac.type = ei->mac;
7077 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7078 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7079
7080 mmio_start = pci_resource_start(pdev, 0);
7081 mmio_len = pci_resource_len(pdev, 0);
7082
7083 err = -EIO;
7084 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7085 if (!adapter->hw.hw_addr)
7086 goto err_ioremap;
7087
7088 if ((adapter->flags & FLAG_HAS_FLASH) &&
7089 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7090 (hw->mac.type < e1000_pch_spt)) {
7091 flash_start = pci_resource_start(pdev, 1);
7092 flash_len = pci_resource_len(pdev, 1);
7093 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7094 if (!adapter->hw.flash_address)
7095 goto err_flashmap;
7096 }
7097
7098 /* Set default EEE advertisement */
7099 if (adapter->flags2 & FLAG2_HAS_EEE)
7100 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7101
7102 /* construct the net_device struct */
7103 netdev->netdev_ops = &e1000e_netdev_ops;
7104 e1000e_set_ethtool_ops(netdev);
7105 netdev->watchdog_timeo = 5 * HZ;
7106 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7107 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7108
7109 netdev->mem_start = mmio_start;
7110 netdev->mem_end = mmio_start + mmio_len;
7111
7112 adapter->bd_number = cards_found++;
7113
7114 e1000e_check_options(adapter);
7115
7116 /* setup adapter struct */
7117 err = e1000_sw_init(adapter);
7118 if (err)
7119 goto err_sw_init;
7120
7121 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7122 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7123 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7124
7125 err = ei->get_variants(adapter);
7126 if (err)
7127 goto err_hw_init;
7128
7129 if ((adapter->flags & FLAG_IS_ICH) &&
7130 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7131 (hw->mac.type < e1000_pch_spt))
7132 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7133
7134 hw->mac.ops.get_bus_info(&adapter->hw);
7135
7136 adapter->hw.phy.autoneg_wait_to_complete = 0;
7137
7138 /* Copper options */
7139 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7140 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7141 adapter->hw.phy.disable_polarity_correction = 0;
7142 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7143 }
7144
7145 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7146 dev_info(&pdev->dev,
7147 "PHY reset is blocked due to SOL/IDER session.\n");
7148
7149 /* Set initial default active device features */
7150 netdev->features = (NETIF_F_SG |
7151 NETIF_F_HW_VLAN_CTAG_RX |
7152 NETIF_F_HW_VLAN_CTAG_TX |
7153 NETIF_F_TSO |
7154 NETIF_F_TSO6 |
7155 NETIF_F_RXHASH |
7156 NETIF_F_RXCSUM |
7157 NETIF_F_HW_CSUM);
7158
7159 /* Set user-changeable features (subset of all device features) */
7160 netdev->hw_features = netdev->features;
7161 netdev->hw_features |= NETIF_F_RXFCS;
7162 netdev->priv_flags |= IFF_SUPP_NOFCS;
7163 netdev->hw_features |= NETIF_F_RXALL;
7164
7165 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7166 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7167
7168 netdev->vlan_features |= (NETIF_F_SG |
7169 NETIF_F_TSO |
7170 NETIF_F_TSO6 |
7171 NETIF_F_HW_CSUM);
7172
7173 netdev->priv_flags |= IFF_UNICAST_FLT;
7174
7175 if (pci_using_dac) {
7176 netdev->features |= NETIF_F_HIGHDMA;
7177 netdev->vlan_features |= NETIF_F_HIGHDMA;
7178 }
7179
7180 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7181 adapter->flags |= FLAG_MNG_PT_ENABLED;
7182
7183 /* before reading the NVM, reset the controller to
7184 * put the device in a known good starting state
7185 */
7186 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7187
7188 /* systems with ASPM and others may see the checksum fail on the first
7189 * attempt. Let's give it a few tries
7190 */
7191 for (i = 0;; i++) {
7192 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7193 break;
7194 if (i == 2) {
7195 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7196 err = -EIO;
7197 goto err_eeprom;
7198 }
7199 }
7200
7201 e1000_eeprom_checks(adapter);
7202
7203 /* copy the MAC address */
7204 if (e1000e_read_mac_addr(&adapter->hw))
7205 dev_err(&pdev->dev,
7206 "NVM Read Error while reading MAC address\n");
7207
7208 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7209
7210 if (!is_valid_ether_addr(netdev->dev_addr)) {
7211 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7212 netdev->dev_addr);
7213 err = -EIO;
7214 goto err_eeprom;
7215 }
7216
7217 init_timer(&adapter->watchdog_timer);
7218 adapter->watchdog_timer.function = e1000_watchdog;
7219 adapter->watchdog_timer.data = (unsigned long)adapter;
7220
7221 init_timer(&adapter->phy_info_timer);
7222 adapter->phy_info_timer.function = e1000_update_phy_info;
7223 adapter->phy_info_timer.data = (unsigned long)adapter;
7224
7225 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7226 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7227 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7228 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7229 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7230
7231 /* Initialize link parameters. User can change them with ethtool */
7232 adapter->hw.mac.autoneg = 1;
7233 adapter->fc_autoneg = true;
7234 adapter->hw.fc.requested_mode = e1000_fc_default;
7235 adapter->hw.fc.current_mode = e1000_fc_default;
7236 adapter->hw.phy.autoneg_advertised = 0x2f;
7237
7238 /* Initial Wake on LAN setting - If APM wake is enabled in
7239 * the EEPROM, enable the ACPI Magic Packet filter
7240 */
7241 if (adapter->flags & FLAG_APME_IN_WUC) {
7242 /* APME bit in EEPROM is mapped to WUC.APME */
7243 eeprom_data = er32(WUC);
7244 eeprom_apme_mask = E1000_WUC_APME;
7245 if ((hw->mac.type > e1000_ich10lan) &&
7246 (eeprom_data & E1000_WUC_PHY_WAKE))
7247 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7248 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7249 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7250 (adapter->hw.bus.func == 1))
7251 ret_val = e1000_read_nvm(&adapter->hw,
7252 NVM_INIT_CONTROL3_PORT_B,
7253 1, &eeprom_data);
7254 else
7255 ret_val = e1000_read_nvm(&adapter->hw,
7256 NVM_INIT_CONTROL3_PORT_A,
7257 1, &eeprom_data);
7258 }
7259
7260 /* fetch WoL from EEPROM */
7261 if (ret_val)
7262 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7263 else if (eeprom_data & eeprom_apme_mask)
7264 adapter->eeprom_wol |= E1000_WUFC_MAG;
7265
7266 /* now that we have the eeprom settings, apply the special cases
7267 * where the eeprom may be wrong or the board simply won't support
7268 * wake on lan on a particular port
7269 */
7270 if (!(adapter->flags & FLAG_HAS_WOL))
7271 adapter->eeprom_wol = 0;
7272
7273 /* initialize the wol settings based on the eeprom settings */
7274 adapter->wol = adapter->eeprom_wol;
7275
7276 /* make sure adapter isn't asleep if manageability is enabled */
7277 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7278 (hw->mac.ops.check_mng_mode(hw)))
7279 device_wakeup_enable(&pdev->dev);
7280
7281 /* save off EEPROM version number */
7282 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7283
7284 if (ret_val) {
7285 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7286 adapter->eeprom_vers = 0;
7287 }
7288
7289 /* init PTP hardware clock */
7290 e1000e_ptp_init(adapter);
7291
7292 /* reset the hardware with the new settings */
7293 e1000e_reset(adapter);
7294
7295 /* If the controller has AMT, do not set DRV_LOAD until the interface
7296 * is up. For all other cases, let the f/w know that the h/w is now
7297 * under the control of the driver.
7298 */
7299 if (!(adapter->flags & FLAG_HAS_AMT))
7300 e1000e_get_hw_control(adapter);
7301
7302 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7303 err = register_netdev(netdev);
7304 if (err)
7305 goto err_register;
7306
7307 /* carrier off reporting is important to ethtool even BEFORE open */
7308 netif_carrier_off(netdev);
7309
7310 e1000_print_device_info(adapter);
7311
7312 if (pci_dev_run_wake(pdev))
7313 pm_runtime_put_noidle(&pdev->dev);
7314
7315 return 0;
7316
7317 err_register:
7318 if (!(adapter->flags & FLAG_HAS_AMT))
7319 e1000e_release_hw_control(adapter);
7320 err_eeprom:
7321 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7322 e1000_phy_hw_reset(&adapter->hw);
7323 err_hw_init:
7324 kfree(adapter->tx_ring);
7325 kfree(adapter->rx_ring);
7326 err_sw_init:
7327 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7328 iounmap(adapter->hw.flash_address);
7329 e1000e_reset_interrupt_capability(adapter);
7330 err_flashmap:
7331 iounmap(adapter->hw.hw_addr);
7332 err_ioremap:
7333 free_netdev(netdev);
7334 err_alloc_etherdev:
7335 pci_release_mem_regions(pdev);
7336 err_pci_reg:
7337 err_dma:
7338 pci_disable_device(pdev);
7339 return err;
7340 }
7341
7342 /**
7343 * e1000_remove - Device Removal Routine
7344 * @pdev: PCI device information struct
7345 *
7346 * e1000_remove is called by the PCI subsystem to alert the driver
7347 * that it should release a PCI device. The could be caused by a
7348 * Hot-Plug event, or because the driver is going to be removed from
7349 * memory.
7350 **/
7351 static void e1000_remove(struct pci_dev *pdev)
7352 {
7353 struct net_device *netdev = pci_get_drvdata(pdev);
7354 struct e1000_adapter *adapter = netdev_priv(netdev);
7355 bool down = test_bit(__E1000_DOWN, &adapter->state);
7356
7357 e1000e_ptp_remove(adapter);
7358
7359 /* The timers may be rescheduled, so explicitly disable them
7360 * from being rescheduled.
7361 */
7362 if (!down)
7363 set_bit(__E1000_DOWN, &adapter->state);
7364 del_timer_sync(&adapter->watchdog_timer);
7365 del_timer_sync(&adapter->phy_info_timer);
7366
7367 cancel_work_sync(&adapter->reset_task);
7368 cancel_work_sync(&adapter->watchdog_task);
7369 cancel_work_sync(&adapter->downshift_task);
7370 cancel_work_sync(&adapter->update_phy_task);
7371 cancel_work_sync(&adapter->print_hang_task);
7372
7373 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7374 cancel_work_sync(&adapter->tx_hwtstamp_work);
7375 if (adapter->tx_hwtstamp_skb) {
7376 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7377 adapter->tx_hwtstamp_skb = NULL;
7378 }
7379 }
7380
7381 /* Don't lie to e1000_close() down the road. */
7382 if (!down)
7383 clear_bit(__E1000_DOWN, &adapter->state);
7384 unregister_netdev(netdev);
7385
7386 if (pci_dev_run_wake(pdev))
7387 pm_runtime_get_noresume(&pdev->dev);
7388
7389 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7390 * would have already happened in close and is redundant.
7391 */
7392 e1000e_release_hw_control(adapter);
7393
7394 e1000e_reset_interrupt_capability(adapter);
7395 kfree(adapter->tx_ring);
7396 kfree(adapter->rx_ring);
7397
7398 iounmap(adapter->hw.hw_addr);
7399 if ((adapter->hw.flash_address) &&
7400 (adapter->hw.mac.type < e1000_pch_spt))
7401 iounmap(adapter->hw.flash_address);
7402 pci_release_mem_regions(pdev);
7403
7404 free_netdev(netdev);
7405
7406 /* AER disable */
7407 pci_disable_pcie_error_reporting(pdev);
7408
7409 pci_disable_device(pdev);
7410 }
7411
7412 /* PCI Error Recovery (ERS) */
7413 static const struct pci_error_handlers e1000_err_handler = {
7414 .error_detected = e1000_io_error_detected,
7415 .slot_reset = e1000_io_slot_reset,
7416 .resume = e1000_io_resume,
7417 };
7418
7419 static const struct pci_device_id e1000_pci_tbl[] = {
7420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7424 board_82571 },
7425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7430
7431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7435
7436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7439
7440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7443
7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7445 board_80003es2lan },
7446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7447 board_80003es2lan },
7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7449 board_80003es2lan },
7450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7451 board_80003es2lan },
7452
7453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7461
7462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7471
7472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7475
7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7479
7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7484
7485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7487
7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7505
7506 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7507 };
7508 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7509
7510 static const struct dev_pm_ops e1000_pm_ops = {
7511 #ifdef CONFIG_PM_SLEEP
7512 .suspend = e1000e_pm_suspend,
7513 .resume = e1000e_pm_resume,
7514 .freeze = e1000e_pm_freeze,
7515 .thaw = e1000e_pm_thaw,
7516 .poweroff = e1000e_pm_suspend,
7517 .restore = e1000e_pm_resume,
7518 #endif
7519 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7520 e1000e_pm_runtime_idle)
7521 };
7522
7523 /* PCI Device API Driver */
7524 static struct pci_driver e1000_driver = {
7525 .name = e1000e_driver_name,
7526 .id_table = e1000_pci_tbl,
7527 .probe = e1000_probe,
7528 .remove = e1000_remove,
7529 .driver = {
7530 .pm = &e1000_pm_ops,
7531 },
7532 .shutdown = e1000_shutdown,
7533 .err_handler = &e1000_err_handler
7534 };
7535
7536 /**
7537 * e1000_init_module - Driver Registration Routine
7538 *
7539 * e1000_init_module is the first routine called when the driver is
7540 * loaded. All it does is register with the PCI subsystem.
7541 **/
7542 static int __init e1000_init_module(void)
7543 {
7544 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7545 e1000e_driver_version);
7546 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7547
7548 return pci_register_driver(&e1000_driver);
7549 }
7550 module_init(e1000_init_module);
7551
7552 /**
7553 * e1000_exit_module - Driver Exit Cleanup Routine
7554 *
7555 * e1000_exit_module is called just before the driver is removed
7556 * from memory.
7557 **/
7558 static void __exit e1000_exit_module(void)
7559 {
7560 pci_unregister_driver(&e1000_driver);
7561 }
7562 module_exit(e1000_exit_module);
7563
7564 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7565 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7566 MODULE_LICENSE("GPL");
7567 MODULE_VERSION(DRV_VERSION);
7568
7569 /* netdev.c */
Linux kernel - Deliverables
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