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net: ethernet: mediatek: fix RMII mode and add REVMII supported by GMAC
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54 {
55 __raw_writel(val, eth->base + reg);
56 }
57
58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59 {
60 return __raw_readl(eth->base + reg);
61 }
62
63 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64 {
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77 }
78
79 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81 {
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96 }
97
98 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99 {
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116 }
117
118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120 {
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124 }
125
126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131 }
132
133 static void mtk_phy_link_adjust(struct net_device *dev)
134 {
135 struct mtk_mac *mac = netdev_priv(dev);
136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
155 if (mac->phy_dev->duplex) {
156 mcr |= MAC_MCR_FORCE_DPX;
157
158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186 }
187
188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190 {
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
210 if (!phydev) {
211 dev_err(eth->dev, "could not connect to PHY\n");
212 return -ENODEV;
213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223 }
224
225 static int mtk_phy_connect(struct mtk_mac *mac)
226 {
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
248 case PHY_INTERFACE_MODE_REVMII:
249 ge_mode = 2;
250 break;
251 case PHY_INTERFACE_MODE_RMII:
252 if (!mac->id)
253 goto err_phy;
254 ge_mode = 3;
255 break;
256 default:
257 goto err_phy;
258 }
259
260 /* put the gmac into the right mode */
261 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
262 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
263 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
264 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
265
266 mtk_phy_connect_node(eth, mac, np);
267 mac->phy_dev->autoneg = AUTONEG_ENABLE;
268 mac->phy_dev->speed = 0;
269 mac->phy_dev->duplex = 0;
270 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
271 SUPPORTED_Asym_Pause;
272 mac->phy_dev->advertising = mac->phy_dev->supported |
273 ADVERTISED_Autoneg;
274 phy_start_aneg(mac->phy_dev);
275
276 of_node_put(np);
277
278 return 0;
279
280 err_phy:
281 of_node_put(np);
282 dev_err(eth->dev, "invalid phy_mode\n");
283 return -EINVAL;
284 }
285
286 static int mtk_mdio_init(struct mtk_eth *eth)
287 {
288 struct device_node *mii_np;
289 int err;
290
291 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
292 if (!mii_np) {
293 dev_err(eth->dev, "no %s child node found", "mdio-bus");
294 return -ENODEV;
295 }
296
297 if (!of_device_is_available(mii_np)) {
298 err = 0;
299 goto err_put_node;
300 }
301
302 eth->mii_bus = mdiobus_alloc();
303 if (!eth->mii_bus) {
304 err = -ENOMEM;
305 goto err_put_node;
306 }
307
308 eth->mii_bus->name = "mdio";
309 eth->mii_bus->read = mtk_mdio_read;
310 eth->mii_bus->write = mtk_mdio_write;
311 eth->mii_bus->priv = eth;
312 eth->mii_bus->parent = eth->dev;
313
314 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
315 err = of_mdiobus_register(eth->mii_bus, mii_np);
316 if (err)
317 goto err_free_bus;
318
319 return 0;
320
321 err_free_bus:
322 mdiobus_free(eth->mii_bus);
323
324 err_put_node:
325 of_node_put(mii_np);
326 eth->mii_bus = NULL;
327 return err;
328 }
329
330 static void mtk_mdio_cleanup(struct mtk_eth *eth)
331 {
332 if (!eth->mii_bus)
333 return;
334
335 mdiobus_unregister(eth->mii_bus);
336 of_node_put(eth->mii_bus->dev.of_node);
337 mdiobus_free(eth->mii_bus);
338 }
339
340 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
341 {
342 unsigned long flags;
343 u32 val;
344
345 spin_lock_irqsave(&eth->irq_lock, flags);
346 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
347 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
348 spin_unlock_irqrestore(&eth->irq_lock, flags);
349 }
350
351 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
352 {
353 unsigned long flags;
354 u32 val;
355
356 spin_lock_irqsave(&eth->irq_lock, flags);
357 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
358 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
359 spin_unlock_irqrestore(&eth->irq_lock, flags);
360 }
361
362 static int mtk_set_mac_address(struct net_device *dev, void *p)
363 {
364 int ret = eth_mac_addr(dev, p);
365 struct mtk_mac *mac = netdev_priv(dev);
366 const char *macaddr = dev->dev_addr;
367 unsigned long flags;
368
369 if (ret)
370 return ret;
371
372 spin_lock_irqsave(&mac->hw->page_lock, flags);
373 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
374 MTK_GDMA_MAC_ADRH(mac->id));
375 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
376 (macaddr[4] << 8) | macaddr[5],
377 MTK_GDMA_MAC_ADRL(mac->id));
378 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
379
380 return 0;
381 }
382
383 void mtk_stats_update_mac(struct mtk_mac *mac)
384 {
385 struct mtk_hw_stats *hw_stats = mac->hw_stats;
386 unsigned int base = MTK_GDM1_TX_GBCNT;
387 u64 stats;
388
389 base += hw_stats->reg_offset;
390
391 u64_stats_update_begin(&hw_stats->syncp);
392
393 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
394 stats = mtk_r32(mac->hw, base + 0x04);
395 if (stats)
396 hw_stats->rx_bytes += (stats << 32);
397 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
398 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
399 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
400 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
401 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
402 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
403 hw_stats->rx_flow_control_packets +=
404 mtk_r32(mac->hw, base + 0x24);
405 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
406 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
407 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
408 stats = mtk_r32(mac->hw, base + 0x34);
409 if (stats)
410 hw_stats->tx_bytes += (stats << 32);
411 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
412 u64_stats_update_end(&hw_stats->syncp);
413 }
414
415 static void mtk_stats_update(struct mtk_eth *eth)
416 {
417 int i;
418
419 for (i = 0; i < MTK_MAC_COUNT; i++) {
420 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
421 continue;
422 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
423 mtk_stats_update_mac(eth->mac[i]);
424 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
425 }
426 }
427 }
428
429 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
430 struct rtnl_link_stats64 *storage)
431 {
432 struct mtk_mac *mac = netdev_priv(dev);
433 struct mtk_hw_stats *hw_stats = mac->hw_stats;
434 unsigned int start;
435
436 if (netif_running(dev) && netif_device_present(dev)) {
437 if (spin_trylock(&hw_stats->stats_lock)) {
438 mtk_stats_update_mac(mac);
439 spin_unlock(&hw_stats->stats_lock);
440 }
441 }
442
443 do {
444 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
445 storage->rx_packets = hw_stats->rx_packets;
446 storage->tx_packets = hw_stats->tx_packets;
447 storage->rx_bytes = hw_stats->rx_bytes;
448 storage->tx_bytes = hw_stats->tx_bytes;
449 storage->collisions = hw_stats->tx_collisions;
450 storage->rx_length_errors = hw_stats->rx_short_errors +
451 hw_stats->rx_long_errors;
452 storage->rx_over_errors = hw_stats->rx_overflow;
453 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
454 storage->rx_errors = hw_stats->rx_checksum_errors;
455 storage->tx_aborted_errors = hw_stats->tx_skip;
456 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
457
458 storage->tx_errors = dev->stats.tx_errors;
459 storage->rx_dropped = dev->stats.rx_dropped;
460 storage->tx_dropped = dev->stats.tx_dropped;
461
462 return storage;
463 }
464
465 static inline int mtk_max_frag_size(int mtu)
466 {
467 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
468 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
469 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
470
471 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
472 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
473 }
474
475 static inline int mtk_max_buf_size(int frag_size)
476 {
477 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
478 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
479
480 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
481
482 return buf_size;
483 }
484
485 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
486 struct mtk_rx_dma *dma_rxd)
487 {
488 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
489 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
490 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
491 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
492 }
493
494 /* the qdma core needs scratch memory to be setup */
495 static int mtk_init_fq_dma(struct mtk_eth *eth)
496 {
497 dma_addr_t phy_ring_tail;
498 int cnt = MTK_DMA_SIZE;
499 dma_addr_t dma_addr;
500 int i;
501
502 eth->scratch_ring = dma_alloc_coherent(eth->dev,
503 cnt * sizeof(struct mtk_tx_dma),
504 &eth->phy_scratch_ring,
505 GFP_ATOMIC | __GFP_ZERO);
506 if (unlikely(!eth->scratch_ring))
507 return -ENOMEM;
508
509 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
510 GFP_KERNEL);
511 if (unlikely(!eth->scratch_head))
512 return -ENOMEM;
513
514 dma_addr = dma_map_single(eth->dev,
515 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
516 DMA_FROM_DEVICE);
517 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
518 return -ENOMEM;
519
520 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
521 phy_ring_tail = eth->phy_scratch_ring +
522 (sizeof(struct mtk_tx_dma) * (cnt - 1));
523
524 for (i = 0; i < cnt; i++) {
525 eth->scratch_ring[i].txd1 =
526 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
527 if (i < cnt - 1)
528 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
529 ((i + 1) * sizeof(struct mtk_tx_dma)));
530 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
531 }
532
533 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
534 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
535 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
536 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
537
538 return 0;
539 }
540
541 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
542 {
543 void *ret = ring->dma;
544
545 return ret + (desc - ring->phys);
546 }
547
548 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
549 struct mtk_tx_dma *txd)
550 {
551 int idx = txd - ring->dma;
552
553 return &ring->buf[idx];
554 }
555
556 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
557 {
558 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
559 dma_unmap_single(dev,
560 dma_unmap_addr(tx_buf, dma_addr0),
561 dma_unmap_len(tx_buf, dma_len0),
562 DMA_TO_DEVICE);
563 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
564 dma_unmap_page(dev,
565 dma_unmap_addr(tx_buf, dma_addr0),
566 dma_unmap_len(tx_buf, dma_len0),
567 DMA_TO_DEVICE);
568 }
569 tx_buf->flags = 0;
570 if (tx_buf->skb &&
571 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
572 dev_kfree_skb_any(tx_buf->skb);
573 tx_buf->skb = NULL;
574 }
575
576 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
577 int tx_num, struct mtk_tx_ring *ring, bool gso)
578 {
579 struct mtk_mac *mac = netdev_priv(dev);
580 struct mtk_eth *eth = mac->hw;
581 struct mtk_tx_dma *itxd, *txd;
582 struct mtk_tx_buf *tx_buf;
583 dma_addr_t mapped_addr;
584 unsigned int nr_frags;
585 int i, n_desc = 1;
586 u32 txd4 = 0;
587
588 itxd = ring->next_free;
589 if (itxd == ring->last_free)
590 return -ENOMEM;
591
592 /* set the forward port */
593 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
594
595 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
596 memset(tx_buf, 0, sizeof(*tx_buf));
597
598 if (gso)
599 txd4 |= TX_DMA_TSO;
600
601 /* TX Checksum offload */
602 if (skb->ip_summed == CHECKSUM_PARTIAL)
603 txd4 |= TX_DMA_CHKSUM;
604
605 /* VLAN header offload */
606 if (skb_vlan_tag_present(skb))
607 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
608
609 mapped_addr = dma_map_single(&dev->dev, skb->data,
610 skb_headlen(skb), DMA_TO_DEVICE);
611 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
612 return -ENOMEM;
613
614 WRITE_ONCE(itxd->txd1, mapped_addr);
615 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
616 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
617 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
618
619 /* TX SG offload */
620 txd = itxd;
621 nr_frags = skb_shinfo(skb)->nr_frags;
622 for (i = 0; i < nr_frags; i++) {
623 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
624 unsigned int offset = 0;
625 int frag_size = skb_frag_size(frag);
626
627 while (frag_size) {
628 bool last_frag = false;
629 unsigned int frag_map_size;
630
631 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
632 if (txd == ring->last_free)
633 goto err_dma;
634
635 n_desc++;
636 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
637 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
638 frag_map_size,
639 DMA_TO_DEVICE);
640 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
641 goto err_dma;
642
643 if (i == nr_frags - 1 &&
644 (frag_size - frag_map_size) == 0)
645 last_frag = true;
646
647 WRITE_ONCE(txd->txd1, mapped_addr);
648 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
649 TX_DMA_PLEN0(frag_map_size) |
650 last_frag * TX_DMA_LS0));
651 WRITE_ONCE(txd->txd4, 0);
652
653 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
654 tx_buf = mtk_desc_to_tx_buf(ring, txd);
655 memset(tx_buf, 0, sizeof(*tx_buf));
656
657 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
658 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
659 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
660 frag_size -= frag_map_size;
661 offset += frag_map_size;
662 }
663 }
664
665 /* store skb to cleanup */
666 tx_buf->skb = skb;
667
668 WRITE_ONCE(itxd->txd4, txd4);
669 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
670 (!nr_frags * TX_DMA_LS0)));
671
672 netdev_sent_queue(dev, skb->len);
673 skb_tx_timestamp(skb);
674
675 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
676 atomic_sub(n_desc, &ring->free_count);
677
678 /* make sure that all changes to the dma ring are flushed before we
679 * continue
680 */
681 wmb();
682
683 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
684 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
685
686 return 0;
687
688 err_dma:
689 do {
690 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
691
692 /* unmap dma */
693 mtk_tx_unmap(&dev->dev, tx_buf);
694
695 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
696 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
697 } while (itxd != txd);
698
699 return -ENOMEM;
700 }
701
702 static inline int mtk_cal_txd_req(struct sk_buff *skb)
703 {
704 int i, nfrags;
705 struct skb_frag_struct *frag;
706
707 nfrags = 1;
708 if (skb_is_gso(skb)) {
709 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
710 frag = &skb_shinfo(skb)->frags[i];
711 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
712 }
713 } else {
714 nfrags += skb_shinfo(skb)->nr_frags;
715 }
716
717 return nfrags;
718 }
719
720 static int mtk_queue_stopped(struct mtk_eth *eth)
721 {
722 int i;
723
724 for (i = 0; i < MTK_MAC_COUNT; i++) {
725 if (!eth->netdev[i])
726 continue;
727 if (netif_queue_stopped(eth->netdev[i]))
728 return 1;
729 }
730
731 return 0;
732 }
733
734 static void mtk_wake_queue(struct mtk_eth *eth)
735 {
736 int i;
737
738 for (i = 0; i < MTK_MAC_COUNT; i++) {
739 if (!eth->netdev[i])
740 continue;
741 netif_wake_queue(eth->netdev[i]);
742 }
743 }
744
745 static void mtk_stop_queue(struct mtk_eth *eth)
746 {
747 int i;
748
749 for (i = 0; i < MTK_MAC_COUNT; i++) {
750 if (!eth->netdev[i])
751 continue;
752 netif_stop_queue(eth->netdev[i]);
753 }
754 }
755
756 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
757 {
758 struct mtk_mac *mac = netdev_priv(dev);
759 struct mtk_eth *eth = mac->hw;
760 struct mtk_tx_ring *ring = &eth->tx_ring;
761 struct net_device_stats *stats = &dev->stats;
762 unsigned long flags;
763 bool gso = false;
764 int tx_num;
765
766 /* normally we can rely on the stack not calling this more than once,
767 * however we have 2 queues running on the same ring so we need to lock
768 * the ring access
769 */
770 spin_lock_irqsave(&eth->page_lock, flags);
771
772 tx_num = mtk_cal_txd_req(skb);
773 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
774 mtk_stop_queue(eth);
775 netif_err(eth, tx_queued, dev,
776 "Tx Ring full when queue awake!\n");
777 spin_unlock_irqrestore(&eth->page_lock, flags);
778 return NETDEV_TX_BUSY;
779 }
780
781 /* TSO: fill MSS info in tcp checksum field */
782 if (skb_is_gso(skb)) {
783 if (skb_cow_head(skb, 0)) {
784 netif_warn(eth, tx_err, dev,
785 "GSO expand head fail.\n");
786 goto drop;
787 }
788
789 if (skb_shinfo(skb)->gso_type &
790 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
791 gso = true;
792 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
793 }
794 }
795
796 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
797 goto drop;
798
799 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
800 mtk_stop_queue(eth);
801
802 spin_unlock_irqrestore(&eth->page_lock, flags);
803
804 return NETDEV_TX_OK;
805
806 drop:
807 spin_unlock_irqrestore(&eth->page_lock, flags);
808 stats->tx_dropped++;
809 dev_kfree_skb(skb);
810 return NETDEV_TX_OK;
811 }
812
813 static int mtk_poll_rx(struct napi_struct *napi, int budget,
814 struct mtk_eth *eth)
815 {
816 struct mtk_rx_ring *ring = &eth->rx_ring;
817 int idx = ring->calc_idx;
818 struct sk_buff *skb;
819 u8 *data, *new_data;
820 struct mtk_rx_dma *rxd, trxd;
821 int done = 0;
822
823 while (done < budget) {
824 struct net_device *netdev;
825 unsigned int pktlen;
826 dma_addr_t dma_addr;
827 int mac = 0;
828
829 idx = NEXT_RX_DESP_IDX(idx);
830 rxd = &ring->dma[idx];
831 data = ring->data[idx];
832
833 mtk_rx_get_desc(&trxd, rxd);
834 if (!(trxd.rxd2 & RX_DMA_DONE))
835 break;
836
837 /* find out which mac the packet come from. values start at 1 */
838 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
839 RX_DMA_FPORT_MASK;
840 mac--;
841
842 netdev = eth->netdev[mac];
843
844 /* alloc new buffer */
845 new_data = napi_alloc_frag(ring->frag_size);
846 if (unlikely(!new_data)) {
847 netdev->stats.rx_dropped++;
848 goto release_desc;
849 }
850 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
851 new_data + NET_SKB_PAD,
852 ring->buf_size,
853 DMA_FROM_DEVICE);
854 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
855 skb_free_frag(new_data);
856 netdev->stats.rx_dropped++;
857 goto release_desc;
858 }
859
860 /* receive data */
861 skb = build_skb(data, ring->frag_size);
862 if (unlikely(!skb)) {
863 put_page(virt_to_head_page(new_data));
864 netdev->stats.rx_dropped++;
865 goto release_desc;
866 }
867 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
868
869 dma_unmap_single(&netdev->dev, trxd.rxd1,
870 ring->buf_size, DMA_FROM_DEVICE);
871 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
872 skb->dev = netdev;
873 skb_put(skb, pktlen);
874 if (trxd.rxd4 & RX_DMA_L4_VALID)
875 skb->ip_summed = CHECKSUM_UNNECESSARY;
876 else
877 skb_checksum_none_assert(skb);
878 skb->protocol = eth_type_trans(skb, netdev);
879
880 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
881 RX_DMA_VID(trxd.rxd3))
882 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
883 RX_DMA_VID(trxd.rxd3));
884 napi_gro_receive(napi, skb);
885
886 ring->data[idx] = new_data;
887 rxd->rxd1 = (unsigned int)dma_addr;
888
889 release_desc:
890 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
891
892 ring->calc_idx = idx;
893 /* make sure that all changes to the dma ring are flushed before
894 * we continue
895 */
896 wmb();
897 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
898 done++;
899 }
900
901 if (done < budget)
902 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
903
904 return done;
905 }
906
907 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
908 {
909 struct mtk_tx_ring *ring = &eth->tx_ring;
910 struct mtk_tx_dma *desc;
911 struct sk_buff *skb;
912 struct mtk_tx_buf *tx_buf;
913 unsigned int done[MTK_MAX_DEVS];
914 unsigned int bytes[MTK_MAX_DEVS];
915 u32 cpu, dma;
916 static int condition;
917 int total = 0, i;
918
919 memset(done, 0, sizeof(done));
920 memset(bytes, 0, sizeof(bytes));
921
922 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
923 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
924
925 desc = mtk_qdma_phys_to_virt(ring, cpu);
926
927 while ((cpu != dma) && budget) {
928 u32 next_cpu = desc->txd2;
929 int mac;
930
931 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
932 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
933 break;
934
935 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
936 TX_DMA_FPORT_MASK;
937 mac--;
938
939 tx_buf = mtk_desc_to_tx_buf(ring, desc);
940 skb = tx_buf->skb;
941 if (!skb) {
942 condition = 1;
943 break;
944 }
945
946 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
947 bytes[mac] += skb->len;
948 done[mac]++;
949 budget--;
950 }
951 mtk_tx_unmap(eth->dev, tx_buf);
952
953 ring->last_free = desc;
954 atomic_inc(&ring->free_count);
955
956 cpu = next_cpu;
957 }
958
959 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
960
961 for (i = 0; i < MTK_MAC_COUNT; i++) {
962 if (!eth->netdev[i] || !done[i])
963 continue;
964 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
965 total += done[i];
966 }
967
968 if (mtk_queue_stopped(eth) &&
969 (atomic_read(&ring->free_count) > ring->thresh))
970 mtk_wake_queue(eth);
971
972 return total;
973 }
974
975 static void mtk_handle_status_irq(struct mtk_eth *eth)
976 {
977 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
978
979 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
980 mtk_stats_update(eth);
981 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
982 MTK_INT_STATUS2);
983 }
984 }
985
986 static int mtk_napi_tx(struct napi_struct *napi, int budget)
987 {
988 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
989 u32 status, mask;
990 int tx_done = 0;
991
992 mtk_handle_status_irq(eth);
993 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
994 tx_done = mtk_poll_tx(eth, budget);
995
996 if (unlikely(netif_msg_intr(eth))) {
997 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
998 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
999 dev_info(eth->dev,
1000 "done tx %d, intr 0x%08x/0x%x\n",
1001 tx_done, status, mask);
1002 }
1003
1004 if (tx_done == budget)
1005 return budget;
1006
1007 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1008 if (status & MTK_TX_DONE_INT)
1009 return budget;
1010
1011 napi_complete(napi);
1012 mtk_irq_enable(eth, MTK_TX_DONE_INT);
1013
1014 return tx_done;
1015 }
1016
1017 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1018 {
1019 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1020 u32 status, mask;
1021 int rx_done = 0;
1022
1023 mtk_handle_status_irq(eth);
1024 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
1025 rx_done = mtk_poll_rx(napi, budget, eth);
1026
1027 if (unlikely(netif_msg_intr(eth))) {
1028 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1029 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1030 dev_info(eth->dev,
1031 "done rx %d, intr 0x%08x/0x%x\n",
1032 rx_done, status, mask);
1033 }
1034
1035 if (rx_done == budget)
1036 return budget;
1037
1038 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1039 if (status & MTK_RX_DONE_INT)
1040 return budget;
1041
1042 napi_complete(napi);
1043 mtk_irq_enable(eth, MTK_RX_DONE_INT);
1044
1045 return rx_done;
1046 }
1047
1048 static int mtk_tx_alloc(struct mtk_eth *eth)
1049 {
1050 struct mtk_tx_ring *ring = &eth->tx_ring;
1051 int i, sz = sizeof(*ring->dma);
1052
1053 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1054 GFP_KERNEL);
1055 if (!ring->buf)
1056 goto no_tx_mem;
1057
1058 ring->dma = dma_alloc_coherent(eth->dev,
1059 MTK_DMA_SIZE * sz,
1060 &ring->phys,
1061 GFP_ATOMIC | __GFP_ZERO);
1062 if (!ring->dma)
1063 goto no_tx_mem;
1064
1065 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1066 for (i = 0; i < MTK_DMA_SIZE; i++) {
1067 int next = (i + 1) % MTK_DMA_SIZE;
1068 u32 next_ptr = ring->phys + next * sz;
1069
1070 ring->dma[i].txd2 = next_ptr;
1071 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1072 }
1073
1074 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1075 ring->next_free = &ring->dma[0];
1076 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1077 ring->thresh = MAX_SKB_FRAGS;
1078
1079 /* make sure that all changes to the dma ring are flushed before we
1080 * continue
1081 */
1082 wmb();
1083
1084 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1085 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1086 mtk_w32(eth,
1087 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1088 MTK_QTX_CRX_PTR);
1089 mtk_w32(eth,
1090 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1091 MTK_QTX_DRX_PTR);
1092
1093 return 0;
1094
1095 no_tx_mem:
1096 return -ENOMEM;
1097 }
1098
1099 static void mtk_tx_clean(struct mtk_eth *eth)
1100 {
1101 struct mtk_tx_ring *ring = &eth->tx_ring;
1102 int i;
1103
1104 if (ring->buf) {
1105 for (i = 0; i < MTK_DMA_SIZE; i++)
1106 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1107 kfree(ring->buf);
1108 ring->buf = NULL;
1109 }
1110
1111 if (ring->dma) {
1112 dma_free_coherent(eth->dev,
1113 MTK_DMA_SIZE * sizeof(*ring->dma),
1114 ring->dma,
1115 ring->phys);
1116 ring->dma = NULL;
1117 }
1118 }
1119
1120 static int mtk_rx_alloc(struct mtk_eth *eth)
1121 {
1122 struct mtk_rx_ring *ring = &eth->rx_ring;
1123 int i;
1124
1125 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1126 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1127 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1128 GFP_KERNEL);
1129 if (!ring->data)
1130 return -ENOMEM;
1131
1132 for (i = 0; i < MTK_DMA_SIZE; i++) {
1133 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1134 if (!ring->data[i])
1135 return -ENOMEM;
1136 }
1137
1138 ring->dma = dma_alloc_coherent(eth->dev,
1139 MTK_DMA_SIZE * sizeof(*ring->dma),
1140 &ring->phys,
1141 GFP_ATOMIC | __GFP_ZERO);
1142 if (!ring->dma)
1143 return -ENOMEM;
1144
1145 for (i = 0; i < MTK_DMA_SIZE; i++) {
1146 dma_addr_t dma_addr = dma_map_single(eth->dev,
1147 ring->data[i] + NET_SKB_PAD,
1148 ring->buf_size,
1149 DMA_FROM_DEVICE);
1150 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1151 return -ENOMEM;
1152 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1153
1154 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1155 }
1156 ring->calc_idx = MTK_DMA_SIZE - 1;
1157 /* make sure that all changes to the dma ring are flushed before we
1158 * continue
1159 */
1160 wmb();
1161
1162 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1163 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1164 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1165 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1166 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1167
1168 return 0;
1169 }
1170
1171 static void mtk_rx_clean(struct mtk_eth *eth)
1172 {
1173 struct mtk_rx_ring *ring = &eth->rx_ring;
1174 int i;
1175
1176 if (ring->data && ring->dma) {
1177 for (i = 0; i < MTK_DMA_SIZE; i++) {
1178 if (!ring->data[i])
1179 continue;
1180 if (!ring->dma[i].rxd1)
1181 continue;
1182 dma_unmap_single(eth->dev,
1183 ring->dma[i].rxd1,
1184 ring->buf_size,
1185 DMA_FROM_DEVICE);
1186 skb_free_frag(ring->data[i]);
1187 }
1188 kfree(ring->data);
1189 ring->data = NULL;
1190 }
1191
1192 if (ring->dma) {
1193 dma_free_coherent(eth->dev,
1194 MTK_DMA_SIZE * sizeof(*ring->dma),
1195 ring->dma,
1196 ring->phys);
1197 ring->dma = NULL;
1198 }
1199 }
1200
1201 /* wait for DMA to finish whatever it is doing before we start using it again */
1202 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1203 {
1204 unsigned long t_start = jiffies;
1205
1206 while (1) {
1207 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1208 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1209 return 0;
1210 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1211 break;
1212 }
1213
1214 dev_err(eth->dev, "DMA init timeout\n");
1215 return -1;
1216 }
1217
1218 static int mtk_dma_init(struct mtk_eth *eth)
1219 {
1220 int err;
1221
1222 if (mtk_dma_busy_wait(eth))
1223 return -EBUSY;
1224
1225 /* QDMA needs scratch memory for internal reordering of the
1226 * descriptors
1227 */
1228 err = mtk_init_fq_dma(eth);
1229 if (err)
1230 return err;
1231
1232 err = mtk_tx_alloc(eth);
1233 if (err)
1234 return err;
1235
1236 err = mtk_rx_alloc(eth);
1237 if (err)
1238 return err;
1239
1240 /* Enable random early drop and set drop threshold automatically */
1241 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1242 MTK_QDMA_FC_THRES);
1243 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1244
1245 return 0;
1246 }
1247
1248 static void mtk_dma_free(struct mtk_eth *eth)
1249 {
1250 int i;
1251
1252 for (i = 0; i < MTK_MAC_COUNT; i++)
1253 if (eth->netdev[i])
1254 netdev_reset_queue(eth->netdev[i]);
1255 if (eth->scratch_ring) {
1256 dma_free_coherent(eth->dev,
1257 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1258 eth->scratch_ring,
1259 eth->phy_scratch_ring);
1260 eth->scratch_ring = NULL;
1261 eth->phy_scratch_ring = 0;
1262 }
1263 mtk_tx_clean(eth);
1264 mtk_rx_clean(eth);
1265 kfree(eth->scratch_head);
1266 }
1267
1268 static void mtk_tx_timeout(struct net_device *dev)
1269 {
1270 struct mtk_mac *mac = netdev_priv(dev);
1271 struct mtk_eth *eth = mac->hw;
1272
1273 eth->netdev[mac->id]->stats.tx_errors++;
1274 netif_err(eth, tx_err, dev,
1275 "transmit timed out\n");
1276 schedule_work(&eth->pending_work);
1277 }
1278
1279 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1280 {
1281 struct mtk_eth *eth = _eth;
1282
1283 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1284 __napi_schedule(&eth->rx_napi);
1285 mtk_irq_disable(eth, MTK_RX_DONE_INT);
1286 }
1287
1288 return IRQ_HANDLED;
1289 }
1290
1291 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1292 {
1293 struct mtk_eth *eth = _eth;
1294
1295 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1296 __napi_schedule(&eth->tx_napi);
1297 mtk_irq_disable(eth, MTK_TX_DONE_INT);
1298 }
1299
1300 return IRQ_HANDLED;
1301 }
1302
1303 #ifdef CONFIG_NET_POLL_CONTROLLER
1304 static void mtk_poll_controller(struct net_device *dev)
1305 {
1306 struct mtk_mac *mac = netdev_priv(dev);
1307 struct mtk_eth *eth = mac->hw;
1308 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1309
1310 mtk_irq_disable(eth, int_mask);
1311 mtk_handle_irq_rx(eth->irq[2], dev);
1312 mtk_irq_enable(eth, int_mask);
1313 }
1314 #endif
1315
1316 static int mtk_start_dma(struct mtk_eth *eth)
1317 {
1318 int err;
1319
1320 err = mtk_dma_init(eth);
1321 if (err) {
1322 mtk_dma_free(eth);
1323 return err;
1324 }
1325
1326 mtk_w32(eth,
1327 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1328 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1329 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
1330 MTK_QDMA_GLO_CFG);
1331
1332 return 0;
1333 }
1334
1335 static int mtk_open(struct net_device *dev)
1336 {
1337 struct mtk_mac *mac = netdev_priv(dev);
1338 struct mtk_eth *eth = mac->hw;
1339
1340 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1341 if (!atomic_read(&eth->dma_refcnt)) {
1342 int err = mtk_start_dma(eth);
1343
1344 if (err)
1345 return err;
1346
1347 napi_enable(&eth->tx_napi);
1348 napi_enable(&eth->rx_napi);
1349 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1350 }
1351 atomic_inc(&eth->dma_refcnt);
1352
1353 phy_start(mac->phy_dev);
1354 netif_start_queue(dev);
1355
1356 return 0;
1357 }
1358
1359 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1360 {
1361 unsigned long flags;
1362 u32 val;
1363 int i;
1364
1365 /* stop the dma engine */
1366 spin_lock_irqsave(&eth->page_lock, flags);
1367 val = mtk_r32(eth, glo_cfg);
1368 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1369 glo_cfg);
1370 spin_unlock_irqrestore(&eth->page_lock, flags);
1371
1372 /* wait for dma stop */
1373 for (i = 0; i < 10; i++) {
1374 val = mtk_r32(eth, glo_cfg);
1375 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1376 msleep(20);
1377 continue;
1378 }
1379 break;
1380 }
1381 }
1382
1383 static int mtk_stop(struct net_device *dev)
1384 {
1385 struct mtk_mac *mac = netdev_priv(dev);
1386 struct mtk_eth *eth = mac->hw;
1387
1388 netif_tx_disable(dev);
1389 phy_stop(mac->phy_dev);
1390
1391 /* only shutdown DMA if this is the last user */
1392 if (!atomic_dec_and_test(&eth->dma_refcnt))
1393 return 0;
1394
1395 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1396 napi_disable(&eth->tx_napi);
1397 napi_disable(&eth->rx_napi);
1398
1399 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1400
1401 mtk_dma_free(eth);
1402
1403 return 0;
1404 }
1405
1406 static int __init mtk_hw_init(struct mtk_eth *eth)
1407 {
1408 int err, i;
1409
1410 /* reset the frame engine */
1411 reset_control_assert(eth->rstc);
1412 usleep_range(10, 20);
1413 reset_control_deassert(eth->rstc);
1414 usleep_range(10, 20);
1415
1416 /* Set GE2 driving and slew rate */
1417 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1418
1419 /* set GE2 TDSEL */
1420 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1421
1422 /* set GE2 TUNE */
1423 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1424
1425 /* GE1, Force 1000M/FD, FC ON */
1426 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1427
1428 /* GE2, Force 1000M/FD, FC ON */
1429 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1430
1431 /* Enable RX VLan Offloading */
1432 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1433
1434 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1435 dev_name(eth->dev), eth);
1436 if (err)
1437 return err;
1438 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
1439 dev_name(eth->dev), eth);
1440 if (err)
1441 return err;
1442
1443 err = mtk_mdio_init(eth);
1444 if (err)
1445 return err;
1446
1447 /* disable delay and normal interrupt */
1448 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1449 mtk_irq_disable(eth, ~0);
1450 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1451 mtk_w32(eth, 0, MTK_RST_GL);
1452
1453 /* FE int grouping */
1454 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1455 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1456 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1457 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1458 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1459
1460 for (i = 0; i < 2; i++) {
1461 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1462
1463 /* setup the forward port to send frame to QDMA */
1464 val &= ~0xffff;
1465 val |= 0x5555;
1466
1467 /* Enable RX checksum */
1468 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1469
1470 /* setup the mac dma */
1471 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1472 }
1473
1474 return 0;
1475 }
1476
1477 static int __init mtk_init(struct net_device *dev)
1478 {
1479 struct mtk_mac *mac = netdev_priv(dev);
1480 struct mtk_eth *eth = mac->hw;
1481 const char *mac_addr;
1482
1483 mac_addr = of_get_mac_address(mac->of_node);
1484 if (mac_addr)
1485 ether_addr_copy(dev->dev_addr, mac_addr);
1486
1487 /* If the mac address is invalid, use random mac address */
1488 if (!is_valid_ether_addr(dev->dev_addr)) {
1489 random_ether_addr(dev->dev_addr);
1490 dev_err(eth->dev, "generated random MAC address %pM\n",
1491 dev->dev_addr);
1492 dev->addr_assign_type = NET_ADDR_RANDOM;
1493 }
1494
1495 return mtk_phy_connect(mac);
1496 }
1497
1498 static void mtk_uninit(struct net_device *dev)
1499 {
1500 struct mtk_mac *mac = netdev_priv(dev);
1501 struct mtk_eth *eth = mac->hw;
1502
1503 phy_disconnect(mac->phy_dev);
1504 mtk_mdio_cleanup(eth);
1505 mtk_irq_disable(eth, ~0);
1506 free_irq(eth->irq[1], dev);
1507 free_irq(eth->irq[2], dev);
1508 }
1509
1510 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1511 {
1512 struct mtk_mac *mac = netdev_priv(dev);
1513
1514 switch (cmd) {
1515 case SIOCGMIIPHY:
1516 case SIOCGMIIREG:
1517 case SIOCSMIIREG:
1518 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1519 default:
1520 break;
1521 }
1522
1523 return -EOPNOTSUPP;
1524 }
1525
1526 static void mtk_pending_work(struct work_struct *work)
1527 {
1528 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1529 int err, i;
1530 unsigned long restart = 0;
1531
1532 rtnl_lock();
1533
1534 /* stop all devices to make sure that dma is properly shut down */
1535 for (i = 0; i < MTK_MAC_COUNT; i++) {
1536 if (!eth->netdev[i])
1537 continue;
1538 mtk_stop(eth->netdev[i]);
1539 __set_bit(i, &restart);
1540 }
1541
1542 /* restart DMA and enable IRQs */
1543 for (i = 0; i < MTK_MAC_COUNT; i++) {
1544 if (!test_bit(i, &restart))
1545 continue;
1546 err = mtk_open(eth->netdev[i]);
1547 if (err) {
1548 netif_alert(eth, ifup, eth->netdev[i],
1549 "Driver up/down cycle failed, closing device.\n");
1550 dev_close(eth->netdev[i]);
1551 }
1552 }
1553 rtnl_unlock();
1554 }
1555
1556 static int mtk_cleanup(struct mtk_eth *eth)
1557 {
1558 int i;
1559
1560 for (i = 0; i < MTK_MAC_COUNT; i++) {
1561 if (!eth->netdev[i])
1562 continue;
1563
1564 unregister_netdev(eth->netdev[i]);
1565 free_netdev(eth->netdev[i]);
1566 }
1567 cancel_work_sync(&eth->pending_work);
1568
1569 return 0;
1570 }
1571
1572 static int mtk_get_settings(struct net_device *dev,
1573 struct ethtool_cmd *cmd)
1574 {
1575 struct mtk_mac *mac = netdev_priv(dev);
1576 int err;
1577
1578 err = phy_read_status(mac->phy_dev);
1579 if (err)
1580 return -ENODEV;
1581
1582 return phy_ethtool_gset(mac->phy_dev, cmd);
1583 }
1584
1585 static int mtk_set_settings(struct net_device *dev,
1586 struct ethtool_cmd *cmd)
1587 {
1588 struct mtk_mac *mac = netdev_priv(dev);
1589
1590 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1591 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1592 cmd->phy_address);
1593 if (!mac->phy_dev)
1594 return -ENODEV;
1595 }
1596
1597 return phy_ethtool_sset(mac->phy_dev, cmd);
1598 }
1599
1600 static void mtk_get_drvinfo(struct net_device *dev,
1601 struct ethtool_drvinfo *info)
1602 {
1603 struct mtk_mac *mac = netdev_priv(dev);
1604
1605 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1606 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1607 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1608 }
1609
1610 static u32 mtk_get_msglevel(struct net_device *dev)
1611 {
1612 struct mtk_mac *mac = netdev_priv(dev);
1613
1614 return mac->hw->msg_enable;
1615 }
1616
1617 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1618 {
1619 struct mtk_mac *mac = netdev_priv(dev);
1620
1621 mac->hw->msg_enable = value;
1622 }
1623
1624 static int mtk_nway_reset(struct net_device *dev)
1625 {
1626 struct mtk_mac *mac = netdev_priv(dev);
1627
1628 return genphy_restart_aneg(mac->phy_dev);
1629 }
1630
1631 static u32 mtk_get_link(struct net_device *dev)
1632 {
1633 struct mtk_mac *mac = netdev_priv(dev);
1634 int err;
1635
1636 err = genphy_update_link(mac->phy_dev);
1637 if (err)
1638 return ethtool_op_get_link(dev);
1639
1640 return mac->phy_dev->link;
1641 }
1642
1643 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1644 {
1645 int i;
1646
1647 switch (stringset) {
1648 case ETH_SS_STATS:
1649 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1650 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1651 data += ETH_GSTRING_LEN;
1652 }
1653 break;
1654 }
1655 }
1656
1657 static int mtk_get_sset_count(struct net_device *dev, int sset)
1658 {
1659 switch (sset) {
1660 case ETH_SS_STATS:
1661 return ARRAY_SIZE(mtk_ethtool_stats);
1662 default:
1663 return -EOPNOTSUPP;
1664 }
1665 }
1666
1667 static void mtk_get_ethtool_stats(struct net_device *dev,
1668 struct ethtool_stats *stats, u64 *data)
1669 {
1670 struct mtk_mac *mac = netdev_priv(dev);
1671 struct mtk_hw_stats *hwstats = mac->hw_stats;
1672 u64 *data_src, *data_dst;
1673 unsigned int start;
1674 int i;
1675
1676 if (netif_running(dev) && netif_device_present(dev)) {
1677 if (spin_trylock(&hwstats->stats_lock)) {
1678 mtk_stats_update_mac(mac);
1679 spin_unlock(&hwstats->stats_lock);
1680 }
1681 }
1682
1683 do {
1684 data_src = (u64*)hwstats;
1685 data_dst = data;
1686 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1687
1688 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1689 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1690 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1691 }
1692
1693 static struct ethtool_ops mtk_ethtool_ops = {
1694 .get_settings = mtk_get_settings,
1695 .set_settings = mtk_set_settings,
1696 .get_drvinfo = mtk_get_drvinfo,
1697 .get_msglevel = mtk_get_msglevel,
1698 .set_msglevel = mtk_set_msglevel,
1699 .nway_reset = mtk_nway_reset,
1700 .get_link = mtk_get_link,
1701 .get_strings = mtk_get_strings,
1702 .get_sset_count = mtk_get_sset_count,
1703 .get_ethtool_stats = mtk_get_ethtool_stats,
1704 };
1705
1706 static const struct net_device_ops mtk_netdev_ops = {
1707 .ndo_init = mtk_init,
1708 .ndo_uninit = mtk_uninit,
1709 .ndo_open = mtk_open,
1710 .ndo_stop = mtk_stop,
1711 .ndo_start_xmit = mtk_start_xmit,
1712 .ndo_set_mac_address = mtk_set_mac_address,
1713 .ndo_validate_addr = eth_validate_addr,
1714 .ndo_do_ioctl = mtk_do_ioctl,
1715 .ndo_change_mtu = eth_change_mtu,
1716 .ndo_tx_timeout = mtk_tx_timeout,
1717 .ndo_get_stats64 = mtk_get_stats64,
1718 #ifdef CONFIG_NET_POLL_CONTROLLER
1719 .ndo_poll_controller = mtk_poll_controller,
1720 #endif
1721 };
1722
1723 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1724 {
1725 struct mtk_mac *mac;
1726 const __be32 *_id = of_get_property(np, "reg", NULL);
1727 int id, err;
1728
1729 if (!_id) {
1730 dev_err(eth->dev, "missing mac id\n");
1731 return -EINVAL;
1732 }
1733
1734 id = be32_to_cpup(_id);
1735 if (id >= MTK_MAC_COUNT) {
1736 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1737 return -EINVAL;
1738 }
1739
1740 if (eth->netdev[id]) {
1741 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1742 return -EINVAL;
1743 }
1744
1745 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1746 if (!eth->netdev[id]) {
1747 dev_err(eth->dev, "alloc_etherdev failed\n");
1748 return -ENOMEM;
1749 }
1750 mac = netdev_priv(eth->netdev[id]);
1751 eth->mac[id] = mac;
1752 mac->id = id;
1753 mac->hw = eth;
1754 mac->of_node = np;
1755
1756 mac->hw_stats = devm_kzalloc(eth->dev,
1757 sizeof(*mac->hw_stats),
1758 GFP_KERNEL);
1759 if (!mac->hw_stats) {
1760 dev_err(eth->dev, "failed to allocate counter memory\n");
1761 err = -ENOMEM;
1762 goto free_netdev;
1763 }
1764 spin_lock_init(&mac->hw_stats->stats_lock);
1765 u64_stats_init(&mac->hw_stats->syncp);
1766 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1767
1768 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1769 eth->netdev[id]->watchdog_timeo = 5 * HZ;
1770 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1771 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1772 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1773 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1774 eth->netdev[id]->features |= MTK_HW_FEATURES;
1775 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1776
1777 err = register_netdev(eth->netdev[id]);
1778 if (err) {
1779 dev_err(eth->dev, "error bringing up device\n");
1780 goto free_netdev;
1781 }
1782 eth->netdev[id]->irq = eth->irq[0];
1783 netif_info(eth, probe, eth->netdev[id],
1784 "mediatek frame engine at 0x%08lx, irq %d\n",
1785 eth->netdev[id]->base_addr, eth->irq[0]);
1786
1787 return 0;
1788
1789 free_netdev:
1790 free_netdev(eth->netdev[id]);
1791 return err;
1792 }
1793
1794 static int mtk_probe(struct platform_device *pdev)
1795 {
1796 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1797 struct device_node *mac_np;
1798 const struct of_device_id *match;
1799 struct mtk_soc_data *soc;
1800 struct mtk_eth *eth;
1801 int err;
1802 int i;
1803
1804 match = of_match_device(of_mtk_match, &pdev->dev);
1805 soc = (struct mtk_soc_data *)match->data;
1806
1807 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1808 if (!eth)
1809 return -ENOMEM;
1810
1811 eth->base = devm_ioremap_resource(&pdev->dev, res);
1812 if (IS_ERR(eth->base))
1813 return PTR_ERR(eth->base);
1814
1815 spin_lock_init(&eth->page_lock);
1816 spin_lock_init(&eth->irq_lock);
1817
1818 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1819 "mediatek,ethsys");
1820 if (IS_ERR(eth->ethsys)) {
1821 dev_err(&pdev->dev, "no ethsys regmap found\n");
1822 return PTR_ERR(eth->ethsys);
1823 }
1824
1825 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1826 "mediatek,pctl");
1827 if (IS_ERR(eth->pctl)) {
1828 dev_err(&pdev->dev, "no pctl regmap found\n");
1829 return PTR_ERR(eth->pctl);
1830 }
1831
1832 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1833 if (IS_ERR(eth->rstc)) {
1834 dev_err(&pdev->dev, "no eth reset found\n");
1835 return PTR_ERR(eth->rstc);
1836 }
1837
1838 for (i = 0; i < 3; i++) {
1839 eth->irq[i] = platform_get_irq(pdev, i);
1840 if (eth->irq[i] < 0) {
1841 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1842 return -ENXIO;
1843 }
1844 }
1845
1846 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1847 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1848 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1849 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1850 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1851 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1852 return -ENODEV;
1853
1854 clk_prepare_enable(eth->clk_ethif);
1855 clk_prepare_enable(eth->clk_esw);
1856 clk_prepare_enable(eth->clk_gp1);
1857 clk_prepare_enable(eth->clk_gp2);
1858
1859 eth->dev = &pdev->dev;
1860 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1861 INIT_WORK(&eth->pending_work, mtk_pending_work);
1862
1863 err = mtk_hw_init(eth);
1864 if (err)
1865 return err;
1866
1867 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1868 if (!of_device_is_compatible(mac_np,
1869 "mediatek,eth-mac"))
1870 continue;
1871
1872 if (!of_device_is_available(mac_np))
1873 continue;
1874
1875 err = mtk_add_mac(eth, mac_np);
1876 if (err)
1877 goto err_free_dev;
1878 }
1879
1880 /* we run 2 devices on the same DMA ring so we need a dummy device
1881 * for NAPI to work
1882 */
1883 init_dummy_netdev(&eth->dummy_dev);
1884 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1885 MTK_NAPI_WEIGHT);
1886 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
1887 MTK_NAPI_WEIGHT);
1888
1889 platform_set_drvdata(pdev, eth);
1890
1891 return 0;
1892
1893 err_free_dev:
1894 mtk_cleanup(eth);
1895 return err;
1896 }
1897
1898 static int mtk_remove(struct platform_device *pdev)
1899 {
1900 struct mtk_eth *eth = platform_get_drvdata(pdev);
1901
1902 clk_disable_unprepare(eth->clk_ethif);
1903 clk_disable_unprepare(eth->clk_esw);
1904 clk_disable_unprepare(eth->clk_gp1);
1905 clk_disable_unprepare(eth->clk_gp2);
1906
1907 netif_napi_del(&eth->tx_napi);
1908 netif_napi_del(&eth->rx_napi);
1909 mtk_cleanup(eth);
1910 platform_set_drvdata(pdev, NULL);
1911
1912 return 0;
1913 }
1914
1915 const struct of_device_id of_mtk_match[] = {
1916 { .compatible = "mediatek,mt7623-eth" },
1917 {},
1918 };
1919
1920 static struct platform_driver mtk_driver = {
1921 .probe = mtk_probe,
1922 .remove = mtk_remove,
1923 .driver = {
1924 .name = "mtk_soc_eth",
1925 .of_match_table = of_mtk_match,
1926 },
1927 };
1928
1929 module_platform_driver(mtk_driver);
1930
1931 MODULE_LICENSE("GPL");
1932 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1933 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
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