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qlcnic: remove private LRO flag
[deliverable/linux.git] / drivers / net / qlcnic / qlcnic_hw.c
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #include "qlcnic.h"
26
27 #include <linux/slab.h>
28 #include <net/ip.h>
29
30 #define MASK(n) ((1ULL<<(n))-1)
31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
32
33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
34
35 #define CRB_BLK(off) ((off >> 20) & 0x3f)
36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
37 #define CRB_WINDOW_2M (0x130060)
38 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
39 #define CRB_INDIRECT_2M (0x1e0000UL)
40
41
42 #ifndef readq
43 static inline u64 readq(void __iomem *addr)
44 {
45 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
46 }
47 #endif
48
49 #ifndef writeq
50 static inline void writeq(u64 val, void __iomem *addr)
51 {
52 writel(((u32) (val)), (addr));
53 writel(((u32) (val >> 32)), (addr + 4));
54 }
55 #endif
56
57 static const struct crb_128M_2M_block_map
58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
59 {{{0, 0, 0, 0} } }, /* 0: PCI */
60 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
61 {1, 0x0110000, 0x0120000, 0x130000},
62 {1, 0x0120000, 0x0122000, 0x124000},
63 {1, 0x0130000, 0x0132000, 0x126000},
64 {1, 0x0140000, 0x0142000, 0x128000},
65 {1, 0x0150000, 0x0152000, 0x12a000},
66 {1, 0x0160000, 0x0170000, 0x110000},
67 {1, 0x0170000, 0x0172000, 0x12e000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {1, 0x01e0000, 0x01e0800, 0x122000},
75 {0, 0x0000000, 0x0000000, 0x000000} } },
76 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
77 {{{0, 0, 0, 0} } }, /* 3: */
78 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
79 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
80 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
81 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
82 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {1, 0x08f0000, 0x08f2000, 0x172000} } },
98 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {1, 0x09f0000, 0x09f2000, 0x176000} } },
114 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
130 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
146 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
147 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
148 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
149 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
150 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
151 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
152 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
153 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
154 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
155 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
156 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
157 {{{0, 0, 0, 0} } }, /* 23: */
158 {{{0, 0, 0, 0} } }, /* 24: */
159 {{{0, 0, 0, 0} } }, /* 25: */
160 {{{0, 0, 0, 0} } }, /* 26: */
161 {{{0, 0, 0, 0} } }, /* 27: */
162 {{{0, 0, 0, 0} } }, /* 28: */
163 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
164 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
165 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
166 {{{0} } }, /* 32: PCI */
167 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
168 {1, 0x2110000, 0x2120000, 0x130000},
169 {1, 0x2120000, 0x2122000, 0x124000},
170 {1, 0x2130000, 0x2132000, 0x126000},
171 {1, 0x2140000, 0x2142000, 0x128000},
172 {1, 0x2150000, 0x2152000, 0x12a000},
173 {1, 0x2160000, 0x2170000, 0x110000},
174 {1, 0x2170000, 0x2172000, 0x12e000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000} } },
183 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
184 {{{0} } }, /* 35: */
185 {{{0} } }, /* 36: */
186 {{{0} } }, /* 37: */
187 {{{0} } }, /* 38: */
188 {{{0} } }, /* 39: */
189 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
190 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
191 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
192 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
193 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
194 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
195 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
196 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
197 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
198 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
199 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
200 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
201 {{{0} } }, /* 52: */
202 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
203 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
204 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
205 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
206 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
207 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
208 {{{0} } }, /* 59: I2C0 */
209 {{{0} } }, /* 60: I2C1 */
210 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
211 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
212 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 };
214
215 /*
216 * top 12 bits of crb internal address (hub, agent)
217 */
218 static const unsigned crb_hub_agt[64] = {
219 0,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
223 0,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
246 0,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
249 0,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
251 0,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
254 0,
255 0,
256 0,
257 0,
258 0,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
270 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
271 0,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
276 0,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
280 0,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
282 0,
283 };
284
285 /* PCI Windowing for DDR regions. */
286
287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
288
289 int
290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
291 {
292 int done = 0, timeout = 0;
293
294 while (!done) {
295 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
296 if (done == 1)
297 break;
298 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
299 dev_err(&adapter->pdev->dev,
300 "Failed to acquire sem=%d lock; holdby=%d\n",
301 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
302 return -EIO;
303 }
304 msleep(1);
305 }
306
307 if (id_reg)
308 QLCWR32(adapter, id_reg, adapter->portnum);
309
310 return 0;
311 }
312
313 void
314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
315 {
316 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
317 }
318
319 static int
320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
321 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
322 {
323 u32 i, producer, consumer;
324 struct qlcnic_cmd_buffer *pbuf;
325 struct cmd_desc_type0 *cmd_desc;
326 struct qlcnic_host_tx_ring *tx_ring;
327
328 i = 0;
329
330 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
331 return -EIO;
332
333 tx_ring = adapter->tx_ring;
334 __netif_tx_lock_bh(tx_ring->txq);
335
336 producer = tx_ring->producer;
337 consumer = tx_ring->sw_consumer;
338
339 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
340 netif_tx_stop_queue(tx_ring->txq);
341 smp_mb();
342 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
343 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
344 netif_tx_wake_queue(tx_ring->txq);
345 } else {
346 adapter->stats.xmit_off++;
347 __netif_tx_unlock_bh(tx_ring->txq);
348 return -EBUSY;
349 }
350 }
351
352 do {
353 cmd_desc = &cmd_desc_arr[i];
354
355 pbuf = &tx_ring->cmd_buf_arr[producer];
356 pbuf->skb = NULL;
357 pbuf->frag_count = 0;
358
359 memcpy(&tx_ring->desc_head[producer],
360 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
361
362 producer = get_next_index(producer, tx_ring->num_desc);
363 i++;
364
365 } while (i != nr_desc);
366
367 tx_ring->producer = producer;
368
369 qlcnic_update_cmd_producer(adapter, tx_ring);
370
371 __netif_tx_unlock_bh(tx_ring->txq);
372
373 return 0;
374 }
375
376 static int
377 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
378 __le16 vlan_id, unsigned op)
379 {
380 struct qlcnic_nic_req req;
381 struct qlcnic_mac_req *mac_req;
382 struct qlcnic_vlan_req *vlan_req;
383 u64 word;
384
385 memset(&req, 0, sizeof(struct qlcnic_nic_req));
386 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
387
388 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
389 req.req_hdr = cpu_to_le64(word);
390
391 mac_req = (struct qlcnic_mac_req *)&req.words[0];
392 mac_req->op = op;
393 memcpy(mac_req->mac_addr, addr, 6);
394
395 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
396 vlan_req->vlan_id = vlan_id;
397
398 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
399 }
400
401 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
402 {
403 struct list_head *head;
404 struct qlcnic_mac_list_s *cur;
405
406 /* look up if already exists */
407 list_for_each(head, &adapter->mac_list) {
408 cur = list_entry(head, struct qlcnic_mac_list_s, list);
409 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
410 return 0;
411 }
412
413 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
414 if (cur == NULL) {
415 dev_err(&adapter->netdev->dev,
416 "failed to add mac address filter\n");
417 return -ENOMEM;
418 }
419 memcpy(cur->mac_addr, addr, ETH_ALEN);
420
421 if (qlcnic_sre_macaddr_change(adapter,
422 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
423 kfree(cur);
424 return -EIO;
425 }
426
427 list_add_tail(&cur->list, &adapter->mac_list);
428 return 0;
429 }
430
431 void qlcnic_set_multi(struct net_device *netdev)
432 {
433 struct qlcnic_adapter *adapter = netdev_priv(netdev);
434 struct netdev_hw_addr *ha;
435 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
436 u32 mode = VPORT_MISS_MODE_DROP;
437
438 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
439 return;
440
441 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
442 qlcnic_nic_add_mac(adapter, bcast_addr);
443
444 if (netdev->flags & IFF_PROMISC) {
445 mode = VPORT_MISS_MODE_ACCEPT_ALL;
446 goto send_fw_cmd;
447 }
448
449 if ((netdev->flags & IFF_ALLMULTI) ||
450 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
451 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
452 goto send_fw_cmd;
453 }
454
455 if (!netdev_mc_empty(netdev)) {
456 netdev_for_each_mc_addr(ha, netdev) {
457 qlcnic_nic_add_mac(adapter, ha->addr);
458 }
459 }
460
461 send_fw_cmd:
462 qlcnic_nic_set_promisc(adapter, mode);
463 }
464
465 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
466 {
467 struct qlcnic_nic_req req;
468 u64 word;
469
470 memset(&req, 0, sizeof(struct qlcnic_nic_req));
471
472 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
473
474 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
475 ((u64)adapter->portnum << 16);
476 req.req_hdr = cpu_to_le64(word);
477
478 req.words[0] = cpu_to_le64(mode);
479
480 return qlcnic_send_cmd_descs(adapter,
481 (struct cmd_desc_type0 *)&req, 1);
482 }
483
484 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
485 {
486 struct qlcnic_mac_list_s *cur;
487 struct list_head *head = &adapter->mac_list;
488
489 while (!list_empty(head)) {
490 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
491 qlcnic_sre_macaddr_change(adapter,
492 cur->mac_addr, 0, QLCNIC_MAC_DEL);
493 list_del(&cur->list);
494 kfree(cur);
495 }
496 }
497
498 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
499 {
500 struct qlcnic_filter *tmp_fil;
501 struct hlist_node *tmp_hnode, *n;
502 struct hlist_head *head;
503 int i;
504
505 for (i = 0; i < adapter->fhash.fmax; i++) {
506 head = &(adapter->fhash.fhead[i]);
507
508 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
509 {
510 if (jiffies >
511 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
512 qlcnic_sre_macaddr_change(adapter,
513 tmp_fil->faddr, tmp_fil->vlan_id,
514 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
515 QLCNIC_MAC_DEL);
516 spin_lock_bh(&adapter->mac_learn_lock);
517 adapter->fhash.fnum--;
518 hlist_del(&tmp_fil->fnode);
519 spin_unlock_bh(&adapter->mac_learn_lock);
520 kfree(tmp_fil);
521 }
522 }
523 }
524 }
525
526 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
527 {
528 struct qlcnic_filter *tmp_fil;
529 struct hlist_node *tmp_hnode, *n;
530 struct hlist_head *head;
531 int i;
532
533 for (i = 0; i < adapter->fhash.fmax; i++) {
534 head = &(adapter->fhash.fhead[i]);
535
536 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
537 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
538 tmp_fil->vlan_id, tmp_fil->vlan_id ?
539 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
540 spin_lock_bh(&adapter->mac_learn_lock);
541 adapter->fhash.fnum--;
542 hlist_del(&tmp_fil->fnode);
543 spin_unlock_bh(&adapter->mac_learn_lock);
544 kfree(tmp_fil);
545 }
546 }
547 }
548
549 #define QLCNIC_CONFIG_INTR_COALESCE 3
550
551 /*
552 * Send the interrupt coalescing parameter set by ethtool to the card.
553 */
554 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
555 {
556 struct qlcnic_nic_req req;
557 u64 word[6];
558 int rv, i;
559
560 memset(&req, 0, sizeof(struct qlcnic_nic_req));
561
562 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
563
564 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
565 req.req_hdr = cpu_to_le64(word[0]);
566
567 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
568 for (i = 0; i < 6; i++)
569 req.words[i] = cpu_to_le64(word[i]);
570
571 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
572 if (rv != 0)
573 dev_err(&adapter->netdev->dev,
574 "Could not send interrupt coalescing parameters\n");
575
576 return rv;
577 }
578
579 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
580 {
581 struct qlcnic_nic_req req;
582 u64 word;
583 int rv;
584
585 memset(&req, 0, sizeof(struct qlcnic_nic_req));
586
587 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
588
589 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
590 req.req_hdr = cpu_to_le64(word);
591
592 req.words[0] = cpu_to_le64(enable);
593
594 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
595 if (rv != 0)
596 dev_err(&adapter->netdev->dev,
597 "Could not send configure hw lro request\n");
598
599 return rv;
600 }
601
602 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
603 {
604 struct qlcnic_nic_req req;
605 u64 word;
606 int rv;
607
608 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
609 return 0;
610
611 memset(&req, 0, sizeof(struct qlcnic_nic_req));
612
613 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
614
615 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
616 ((u64)adapter->portnum << 16);
617 req.req_hdr = cpu_to_le64(word);
618
619 req.words[0] = cpu_to_le64(enable);
620
621 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
622 if (rv != 0)
623 dev_err(&adapter->netdev->dev,
624 "Could not send configure bridge mode request\n");
625
626 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
627
628 return rv;
629 }
630
631
632 #define RSS_HASHTYPE_IP_TCP 0x3
633
634 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
635 {
636 struct qlcnic_nic_req req;
637 u64 word;
638 int i, rv;
639
640 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
641 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
642 0x255b0ec26d5a56daULL };
643
644
645 memset(&req, 0, sizeof(struct qlcnic_nic_req));
646 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
647
648 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
649 req.req_hdr = cpu_to_le64(word);
650
651 /*
652 * RSS request:
653 * bits 3-0: hash_method
654 * 5-4: hash_type_ipv4
655 * 7-6: hash_type_ipv6
656 * 8: enable
657 * 9: use indirection table
658 * 47-10: reserved
659 * 63-48: indirection table mask
660 */
661 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
662 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
663 ((u64)(enable & 0x1) << 8) |
664 ((0x7ULL) << 48);
665 req.words[0] = cpu_to_le64(word);
666 for (i = 0; i < 5; i++)
667 req.words[i+1] = cpu_to_le64(key[i]);
668
669 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
670 if (rv != 0)
671 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
672
673 return rv;
674 }
675
676 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
677 {
678 struct qlcnic_nic_req req;
679 struct qlcnic_ipaddr *ipa;
680 u64 word;
681 int rv;
682
683 memset(&req, 0, sizeof(struct qlcnic_nic_req));
684 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
685
686 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
687 req.req_hdr = cpu_to_le64(word);
688
689 req.words[0] = cpu_to_le64(cmd);
690 ipa = (struct qlcnic_ipaddr *)&req.words[1];
691 ipa->ipv4 = ip;
692
693 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
694 if (rv != 0)
695 dev_err(&adapter->netdev->dev,
696 "could not notify %s IP 0x%x reuqest\n",
697 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
698
699 return rv;
700 }
701
702 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
703 {
704 struct qlcnic_nic_req req;
705 u64 word;
706 int rv;
707
708 memset(&req, 0, sizeof(struct qlcnic_nic_req));
709 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
710
711 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
712 req.req_hdr = cpu_to_le64(word);
713 req.words[0] = cpu_to_le64(enable | (enable << 8));
714
715 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
716 if (rv != 0)
717 dev_err(&adapter->netdev->dev,
718 "could not configure link notification\n");
719
720 return rv;
721 }
722
723 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
724 {
725 struct qlcnic_nic_req req;
726 u64 word;
727 int rv;
728
729 memset(&req, 0, sizeof(struct qlcnic_nic_req));
730 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
731
732 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
733 ((u64)adapter->portnum << 16) |
734 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
735
736 req.req_hdr = cpu_to_le64(word);
737
738 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
739 if (rv != 0)
740 dev_err(&adapter->netdev->dev,
741 "could not cleanup lro flows\n");
742
743 return rv;
744 }
745
746 /*
747 * qlcnic_change_mtu - Change the Maximum Transfer Unit
748 * @returns 0 on success, negative on failure
749 */
750
751 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
752 {
753 struct qlcnic_adapter *adapter = netdev_priv(netdev);
754 int rc = 0;
755
756 if (mtu < P3_MIN_MTU || mtu > P3_MAX_MTU) {
757 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
758 " not supported\n", P3_MAX_MTU, P3_MIN_MTU);
759 return -EINVAL;
760 }
761
762 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
763
764 if (!rc)
765 netdev->mtu = mtu;
766
767 return rc;
768 }
769
770 /*
771 * Changes the CRB window to the specified window.
772 */
773 /* Returns < 0 if off is not valid,
774 * 1 if window access is needed. 'off' is set to offset from
775 * CRB space in 128M pci map
776 * 0 if no window access is needed. 'off' is set to 2M addr
777 * In: 'off' is offset from base in 128M pci map
778 */
779 static int
780 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
781 ulong off, void __iomem **addr)
782 {
783 const struct crb_128M_2M_sub_block_map *m;
784
785 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
786 return -EINVAL;
787
788 off -= QLCNIC_PCI_CRBSPACE;
789
790 /*
791 * Try direct map
792 */
793 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
794
795 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
796 *addr = adapter->ahw.pci_base0 + m->start_2M +
797 (off - m->start_128M);
798 return 0;
799 }
800
801 /*
802 * Not in direct map, use crb window
803 */
804 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
805 return 1;
806 }
807
808 /*
809 * In: 'off' is offset from CRB space in 128M pci map
810 * Out: 'off' is 2M pci map addr
811 * side effect: lock crb window
812 */
813 static int
814 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
815 {
816 u32 window;
817 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
818
819 off -= QLCNIC_PCI_CRBSPACE;
820
821 window = CRB_HI(off);
822 if (window == 0) {
823 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
824 return -EIO;
825 }
826
827 writel(window, addr);
828 if (readl(addr) != window) {
829 if (printk_ratelimit())
830 dev_warn(&adapter->pdev->dev,
831 "failed to set CRB window to %d off 0x%lx\n",
832 window, off);
833 return -EIO;
834 }
835 return 0;
836 }
837
838 int
839 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
840 {
841 unsigned long flags;
842 int rv;
843 void __iomem *addr = NULL;
844
845 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
846
847 if (rv == 0) {
848 writel(data, addr);
849 return 0;
850 }
851
852 if (rv > 0) {
853 /* indirect access */
854 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
855 crb_win_lock(adapter);
856 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
857 if (!rv)
858 writel(data, addr);
859 crb_win_unlock(adapter);
860 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
861 return rv;
862 }
863
864 dev_err(&adapter->pdev->dev,
865 "%s: invalid offset: 0x%016lx\n", __func__, off);
866 dump_stack();
867 return -EIO;
868 }
869
870 u32
871 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
872 {
873 unsigned long flags;
874 int rv;
875 u32 data = -1;
876 void __iomem *addr = NULL;
877
878 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
879
880 if (rv == 0)
881 return readl(addr);
882
883 if (rv > 0) {
884 /* indirect access */
885 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
886 crb_win_lock(adapter);
887 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
888 data = readl(addr);
889 crb_win_unlock(adapter);
890 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
891 return data;
892 }
893
894 dev_err(&adapter->pdev->dev,
895 "%s: invalid offset: 0x%016lx\n", __func__, off);
896 dump_stack();
897 return -1;
898 }
899
900
901 void __iomem *
902 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
903 {
904 void __iomem *addr = NULL;
905
906 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
907
908 return addr;
909 }
910
911
912 static int
913 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
914 u64 addr, u32 *start)
915 {
916 u32 window;
917
918 window = OCM_WIN_P3P(addr);
919
920 writel(window, adapter->ahw.ocm_win_crb);
921 /* read back to flush */
922 readl(adapter->ahw.ocm_win_crb);
923
924 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
925 return 0;
926 }
927
928 static int
929 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
930 u64 *data, int op)
931 {
932 void __iomem *addr;
933 int ret;
934 u32 start;
935
936 mutex_lock(&adapter->ahw.mem_lock);
937
938 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
939 if (ret != 0)
940 goto unlock;
941
942 addr = adapter->ahw.pci_base0 + start;
943
944 if (op == 0) /* read */
945 *data = readq(addr);
946 else /* write */
947 writeq(*data, addr);
948
949 unlock:
950 mutex_unlock(&adapter->ahw.mem_lock);
951
952 return ret;
953 }
954
955 void
956 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
957 {
958 void __iomem *addr = adapter->ahw.pci_base0 +
959 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
960
961 mutex_lock(&adapter->ahw.mem_lock);
962 *data = readq(addr);
963 mutex_unlock(&adapter->ahw.mem_lock);
964 }
965
966 void
967 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
968 {
969 void __iomem *addr = adapter->ahw.pci_base0 +
970 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
971
972 mutex_lock(&adapter->ahw.mem_lock);
973 writeq(data, addr);
974 mutex_unlock(&adapter->ahw.mem_lock);
975 }
976
977 #define MAX_CTL_CHECK 1000
978
979 int
980 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
981 u64 off, u64 data)
982 {
983 int i, j, ret;
984 u32 temp, off8;
985 void __iomem *mem_crb;
986
987 /* Only 64-bit aligned access */
988 if (off & 7)
989 return -EIO;
990
991 /* P3 onward, test agent base for MIU and SIU is same */
992 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
993 QLCNIC_ADDR_QDR_NET_MAX)) {
994 mem_crb = qlcnic_get_ioaddr(adapter,
995 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
996 goto correct;
997 }
998
999 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1000 mem_crb = qlcnic_get_ioaddr(adapter,
1001 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1002 goto correct;
1003 }
1004
1005 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1006 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1007
1008 return -EIO;
1009
1010 correct:
1011 off8 = off & ~0xf;
1012
1013 mutex_lock(&adapter->ahw.mem_lock);
1014
1015 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1016 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1017
1018 i = 0;
1019 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1020 writel((TA_CTL_START | TA_CTL_ENABLE),
1021 (mem_crb + TEST_AGT_CTRL));
1022
1023 for (j = 0; j < MAX_CTL_CHECK; j++) {
1024 temp = readl(mem_crb + TEST_AGT_CTRL);
1025 if ((temp & TA_CTL_BUSY) == 0)
1026 break;
1027 }
1028
1029 if (j >= MAX_CTL_CHECK) {
1030 ret = -EIO;
1031 goto done;
1032 }
1033
1034 i = (off & 0xf) ? 0 : 2;
1035 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1036 mem_crb + MIU_TEST_AGT_WRDATA(i));
1037 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1038 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1039 i = (off & 0xf) ? 2 : 0;
1040
1041 writel(data & 0xffffffff,
1042 mem_crb + MIU_TEST_AGT_WRDATA(i));
1043 writel((data >> 32) & 0xffffffff,
1044 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1045
1046 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1047 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1048 (mem_crb + TEST_AGT_CTRL));
1049
1050 for (j = 0; j < MAX_CTL_CHECK; j++) {
1051 temp = readl(mem_crb + TEST_AGT_CTRL);
1052 if ((temp & TA_CTL_BUSY) == 0)
1053 break;
1054 }
1055
1056 if (j >= MAX_CTL_CHECK) {
1057 if (printk_ratelimit())
1058 dev_err(&adapter->pdev->dev,
1059 "failed to write through agent\n");
1060 ret = -EIO;
1061 } else
1062 ret = 0;
1063
1064 done:
1065 mutex_unlock(&adapter->ahw.mem_lock);
1066
1067 return ret;
1068 }
1069
1070 int
1071 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1072 u64 off, u64 *data)
1073 {
1074 int j, ret;
1075 u32 temp, off8;
1076 u64 val;
1077 void __iomem *mem_crb;
1078
1079 /* Only 64-bit aligned access */
1080 if (off & 7)
1081 return -EIO;
1082
1083 /* P3 onward, test agent base for MIU and SIU is same */
1084 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1085 QLCNIC_ADDR_QDR_NET_MAX)) {
1086 mem_crb = qlcnic_get_ioaddr(adapter,
1087 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1088 goto correct;
1089 }
1090
1091 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1092 mem_crb = qlcnic_get_ioaddr(adapter,
1093 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1094 goto correct;
1095 }
1096
1097 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1098 return qlcnic_pci_mem_access_direct(adapter,
1099 off, data, 0);
1100 }
1101
1102 return -EIO;
1103
1104 correct:
1105 off8 = off & ~0xf;
1106
1107 mutex_lock(&adapter->ahw.mem_lock);
1108
1109 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1110 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1111 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1112 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1113
1114 for (j = 0; j < MAX_CTL_CHECK; j++) {
1115 temp = readl(mem_crb + TEST_AGT_CTRL);
1116 if ((temp & TA_CTL_BUSY) == 0)
1117 break;
1118 }
1119
1120 if (j >= MAX_CTL_CHECK) {
1121 if (printk_ratelimit())
1122 dev_err(&adapter->pdev->dev,
1123 "failed to read through agent\n");
1124 ret = -EIO;
1125 } else {
1126 off8 = MIU_TEST_AGT_RDDATA_LO;
1127 if (off & 0xf)
1128 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1129
1130 temp = readl(mem_crb + off8 + 4);
1131 val = (u64)temp << 32;
1132 val |= readl(mem_crb + off8);
1133 *data = val;
1134 ret = 0;
1135 }
1136
1137 mutex_unlock(&adapter->ahw.mem_lock);
1138
1139 return ret;
1140 }
1141
1142 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1143 {
1144 int offset, board_type, magic;
1145 struct pci_dev *pdev = adapter->pdev;
1146
1147 offset = QLCNIC_FW_MAGIC_OFFSET;
1148 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1149 return -EIO;
1150
1151 if (magic != QLCNIC_BDINFO_MAGIC) {
1152 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1153 magic);
1154 return -EIO;
1155 }
1156
1157 offset = QLCNIC_BRDTYPE_OFFSET;
1158 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1159 return -EIO;
1160
1161 adapter->ahw.board_type = board_type;
1162
1163 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1164 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1165 if ((gpio & 0x8000) == 0)
1166 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1167 }
1168
1169 switch (board_type) {
1170 case QLCNIC_BRDTYPE_P3_HMEZ:
1171 case QLCNIC_BRDTYPE_P3_XG_LOM:
1172 case QLCNIC_BRDTYPE_P3_10G_CX4:
1173 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1174 case QLCNIC_BRDTYPE_P3_IMEZ:
1175 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1176 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1177 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1178 case QLCNIC_BRDTYPE_P3_10G_XFP:
1179 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1180 adapter->ahw.port_type = QLCNIC_XGBE;
1181 break;
1182 case QLCNIC_BRDTYPE_P3_REF_QG:
1183 case QLCNIC_BRDTYPE_P3_4_GB:
1184 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1185 adapter->ahw.port_type = QLCNIC_GBE;
1186 break;
1187 case QLCNIC_BRDTYPE_P3_10G_TP:
1188 adapter->ahw.port_type = (adapter->portnum < 2) ?
1189 QLCNIC_XGBE : QLCNIC_GBE;
1190 break;
1191 default:
1192 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1193 adapter->ahw.port_type = QLCNIC_XGBE;
1194 break;
1195 }
1196
1197 return 0;
1198 }
1199
1200 int
1201 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1202 {
1203 u32 wol_cfg;
1204
1205 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1206 if (wol_cfg & (1UL << adapter->portnum)) {
1207 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1208 if (wol_cfg & (1 << adapter->portnum))
1209 return 1;
1210 }
1211
1212 return 0;
1213 }
1214
1215 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1216 {
1217 struct qlcnic_nic_req req;
1218 int rv;
1219 u64 word;
1220
1221 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1222 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1223
1224 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1225 req.req_hdr = cpu_to_le64(word);
1226
1227 req.words[0] = cpu_to_le64((u64)rate << 32);
1228 req.words[1] = cpu_to_le64(state);
1229
1230 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1231 if (rv)
1232 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1233
1234 return rv;
1235 }
1236
1237 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1238 {
1239 struct qlcnic_nic_req req;
1240 int rv;
1241 u64 word;
1242
1243 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1244 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1245
1246 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1247 ((u64)adapter->portnum << 16);
1248 req.req_hdr = cpu_to_le64(word);
1249 req.words[0] = cpu_to_le64(flag);
1250
1251 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1252 if (rv)
1253 dev_err(&adapter->pdev->dev,
1254 "%sting loopback mode failed.\n",
1255 flag ? "Set" : "Reset");
1256 return rv;
1257 }
1258
1259 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1260 {
1261 if (qlcnic_set_fw_loopback(adapter, 1))
1262 return -EIO;
1263
1264 if (qlcnic_nic_set_promisc(adapter,
1265 VPORT_MISS_MODE_ACCEPT_ALL)) {
1266 qlcnic_set_fw_loopback(adapter, 0);
1267 return -EIO;
1268 }
1269
1270 msleep(1000);
1271 return 0;
1272 }
1273
1274 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1275 {
1276 int mode = VPORT_MISS_MODE_DROP;
1277 struct net_device *netdev = adapter->netdev;
1278
1279 qlcnic_set_fw_loopback(adapter, 0);
1280
1281 if (netdev->flags & IFF_PROMISC)
1282 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1283 else if (netdev->flags & IFF_ALLMULTI)
1284 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1285
1286 qlcnic_nic_set_promisc(adapter, mode);
1287 msleep(1000);
1288 }
Linux kernel - Deliverables
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