2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit
= 32;
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01
= 0,
136 RTL_GIGA_MAC_NONE
= 0xff,
139 enum rtl_tx_desc_version
{
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version
;
151 } rtl_chip_infos
[] = {
153 [RTL_GIGA_MAC_VER_01
] =
154 _R("RTL8169", RTL_TD_0
, NULL
),
155 [RTL_GIGA_MAC_VER_02
] =
156 _R("RTL8169s", RTL_TD_0
, NULL
),
157 [RTL_GIGA_MAC_VER_03
] =
158 _R("RTL8110s", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_04
] =
160 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_05
] =
162 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
163 [RTL_GIGA_MAC_VER_06
] =
164 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
166 [RTL_GIGA_MAC_VER_07
] =
167 _R("RTL8102e", RTL_TD_1
, NULL
),
168 [RTL_GIGA_MAC_VER_08
] =
169 _R("RTL8102e", RTL_TD_1
, NULL
),
170 [RTL_GIGA_MAC_VER_09
] =
171 _R("RTL8102e", RTL_TD_1
, NULL
),
172 [RTL_GIGA_MAC_VER_10
] =
173 _R("RTL8101e", RTL_TD_0
, NULL
),
174 [RTL_GIGA_MAC_VER_11
] =
175 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
176 [RTL_GIGA_MAC_VER_12
] =
177 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_13
] =
179 _R("RTL8101e", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_14
] =
181 _R("RTL8100e", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_15
] =
183 _R("RTL8100e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_16
] =
185 _R("RTL8101e", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_17
] =
187 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
188 [RTL_GIGA_MAC_VER_18
] =
189 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
190 [RTL_GIGA_MAC_VER_19
] =
191 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
192 [RTL_GIGA_MAC_VER_20
] =
193 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_21
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_22
] =
197 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_23
] =
199 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_24
] =
201 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
202 [RTL_GIGA_MAC_VER_25
] =
203 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
204 [RTL_GIGA_MAC_VER_26
] =
205 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
206 [RTL_GIGA_MAC_VER_27
] =
207 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
208 [RTL_GIGA_MAC_VER_28
] =
209 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
210 [RTL_GIGA_MAC_VER_29
] =
211 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
212 [RTL_GIGA_MAC_VER_30
] =
213 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
214 [RTL_GIGA_MAC_VER_31
] =
215 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
216 [RTL_GIGA_MAC_VER_32
] =
217 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
218 [RTL_GIGA_MAC_VER_33
] =
219 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
),
220 [RTL_GIGA_MAC_VER_34
] =
221 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
)
231 static void rtl_hw_start_8169(struct net_device
*);
232 static void rtl_hw_start_8168(struct net_device
*);
233 static void rtl_hw_start_8101(struct net_device
*);
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
243 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
245 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
246 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
248 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
252 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
254 static int rx_buf_sz
= 16383;
261 MAC0
= 0, /* Ethernet hardware address. */
263 MAR0
= 8, /* Multicast filter. */
264 CounterAddrLow
= 0x10,
265 CounterAddrHigh
= 0x14,
266 TxDescStartAddrLow
= 0x20,
267 TxDescStartAddrHigh
= 0x24,
268 TxHDescStartAddrLow
= 0x28,
269 TxHDescStartAddrHigh
= 0x2c,
278 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
282 #define RX128_INT_EN (1 << 15) /* 8111c and later */
283 #define RX_MULTI_EN (1 << 14) /* 8111c only */
284 #define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287 #define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
305 RxDescAddrLow
= 0xe4,
306 RxDescAddrHigh
= 0xe8,
307 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
309 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
311 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
313 #define TxPacketMax (8064 >> 7)
316 FuncEventMask
= 0xf4,
317 FuncPresetState
= 0xf8,
318 FuncForceEvent
= 0xfc,
321 enum rtl8110_registers
{
327 enum rtl8168_8101_registers
{
330 #define CSIAR_FLAG 0x80000000
331 #define CSIAR_WRITE_CMD 0x80000000
332 #define CSIAR_BYTE_ENABLE 0x0f
333 #define CSIAR_BYTE_ENABLE_SHIFT 12
334 #define CSIAR_ADDR_MASK 0x0fff
337 #define EPHYAR_FLAG 0x80000000
338 #define EPHYAR_WRITE_CMD 0x80000000
339 #define EPHYAR_REG_MASK 0x1f
340 #define EPHYAR_REG_SHIFT 16
341 #define EPHYAR_DATA_MASK 0xffff
343 #define PFM_EN (1 << 6)
345 #define FIX_NAK_1 (1 << 4)
346 #define FIX_NAK_2 (1 << 3)
349 #define NOW_IS_OOB (1 << 7)
350 #define EN_NDP (1 << 3)
351 #define EN_OOB_RESET (1 << 2)
353 #define EFUSEAR_FLAG 0x80000000
354 #define EFUSEAR_WRITE_CMD 0x80000000
355 #define EFUSEAR_READ_CMD 0x00000000
356 #define EFUSEAR_REG_MASK 0x03ff
357 #define EFUSEAR_REG_SHIFT 8
358 #define EFUSEAR_DATA_MASK 0xff
361 enum rtl8168_registers
{
366 #define ERIAR_FLAG 0x80000000
367 #define ERIAR_WRITE_CMD 0x80000000
368 #define ERIAR_READ_CMD 0x00000000
369 #define ERIAR_ADDR_BYTE_ALIGN 4
370 #define ERIAR_TYPE_SHIFT 16
371 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_MASK_SHIFT 12
375 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
378 EPHY_RXER_NUM
= 0x7c,
379 OCPDR
= 0xb0, /* OCP GPHY access */
380 #define OCPDR_WRITE_CMD 0x80000000
381 #define OCPDR_READ_CMD 0x00000000
382 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_GPHY_REG_SHIFT 16
384 #define OCPDR_DATA_MASK 0xffff
386 #define OCPAR_FLAG 0x80000000
387 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
388 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC
= 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define PWM_EN (1 << 22)
395 enum rtl_register_content
{
396 /* InterruptStatusBits */
400 TxDescUnavail
= 0x0080,
423 /* TXPoll register p.5 */
424 HPQ
= 0x80, /* Poll cmd on the high prio queue */
425 NPQ
= 0x40, /* Poll cmd on the low prio queue */
426 FSWInt
= 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock
= 0xc0,
435 AcceptBroadcast
= 0x08,
436 AcceptMulticast
= 0x04,
438 AcceptAllPhys
= 0x01,
439 #define RX_CONFIG_ACCEPT_MASK 0x3f
442 TxInterFrameGapShift
= 24,
443 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
445 /* Config1 register p.24 */
448 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
449 Speed_down
= (1 << 4),
453 PMEnable
= (1 << 0), /* Power Management Enable */
455 /* Config2 register p. 25 */
456 PCI_Clock_66MHz
= 0x01,
457 PCI_Clock_33MHz
= 0x00,
459 /* Config3 register p.25 */
460 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
462 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
464 /* Config5 register p.27 */
465 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
467 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
469 LanWake
= (1 << 1), /* LanWake enable/disable */
470 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
473 TBIReset
= 0x80000000,
474 TBILoopback
= 0x40000000,
475 TBINwEnable
= 0x20000000,
476 TBINwRestart
= 0x10000000,
477 TBILinkOk
= 0x02000000,
478 TBINwComplete
= 0x01000000,
481 EnableBist
= (1 << 15), // 8168 8101
482 Mac_dbgo_oe
= (1 << 14), // 8168 8101
483 Normal_mode
= (1 << 13), // unused
484 Force_half_dup
= (1 << 12), // 8168 8101
485 Force_rxflow_en
= (1 << 11), // 8168 8101
486 Force_txflow_en
= (1 << 10), // 8168 8101
487 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
488 ASF
= (1 << 8), // 8168 8101
489 PktCntrDisable
= (1 << 7), // 8168 8101
490 Mac_dbgo_sel
= 0x001c, // 8168
495 INTT_0
= 0x0000, // 8168
496 INTT_1
= 0x0001, // 8168
497 INTT_2
= 0x0002, // 8168
498 INTT_3
= 0x0003, // 8168
500 /* rtl8169_PHYstatus */
511 TBILinkOK
= 0x02000000,
513 /* DumpCounterCommand */
518 /* First doubleword. */
519 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
520 RingEnd
= (1 << 30), /* End of descriptor ring */
521 FirstFrag
= (1 << 29), /* First segment of a packet */
522 LastFrag
= (1 << 28), /* Final segment of a packet */
526 enum rtl_tx_desc_bit
{
527 /* First doubleword. */
528 TD_LSO
= (1 << 27), /* Large Send Offload */
529 #define TD_MSS_MAX 0x07ffu /* MSS value */
531 /* Second doubleword. */
532 TxVlanTag
= (1 << 17), /* Add VLAN tag */
535 /* 8169, 8168b and 810x except 8102e. */
536 enum rtl_tx_desc_bit_0
{
537 /* First doubleword. */
538 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
539 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
540 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
541 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
544 /* 8102e, 8168c and beyond. */
545 enum rtl_tx_desc_bit_1
{
546 /* Second doubleword. */
547 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
549 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
553 static const struct rtl_tx_desc_info
{
560 } tx_desc_info
[] = {
563 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
564 .tcp
= TD0_IP_CS
| TD0_TCP_CS
566 .mss_shift
= TD0_MSS_SHIFT
,
571 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
572 .tcp
= TD1_IP_CS
| TD1_TCP_CS
574 .mss_shift
= TD1_MSS_SHIFT
,
579 enum rtl_rx_desc_bit
{
581 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
582 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
584 #define RxProtoUDP (PID1)
585 #define RxProtoTCP (PID0)
586 #define RxProtoIP (PID1 | PID0)
587 #define RxProtoMask RxProtoIP
589 IPFail
= (1 << 16), /* IP checksum failed */
590 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
591 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
592 RxVlanTag
= (1 << 16), /* VLAN tag available */
595 #define RsvdMask 0x3fffc000
612 u8 __pad
[sizeof(void *) - sizeof(u32
)];
616 RTL_FEATURE_WOL
= (1 << 0),
617 RTL_FEATURE_MSI
= (1 << 1),
618 RTL_FEATURE_GMII
= (1 << 2),
621 struct rtl8169_counters
{
628 __le32 tx_one_collision
;
629 __le32 tx_multi_collision
;
637 struct rtl8169_private
{
638 void __iomem
*mmio_addr
; /* memory map physical address */
639 struct pci_dev
*pci_dev
;
640 struct net_device
*dev
;
641 struct napi_struct napi
;
646 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
647 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
650 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
651 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr
;
653 dma_addr_t RxPhyAddr
;
654 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
655 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
656 struct timer_list timer
;
663 void (*write
)(void __iomem
*, int, int);
664 int (*read
)(void __iomem
*, int);
667 struct pll_power_ops
{
668 void (*down
)(struct rtl8169_private
*);
669 void (*up
)(struct rtl8169_private
*);
672 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
673 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
674 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
675 void (*hw_start
)(struct net_device
*);
676 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
677 unsigned int (*link_ok
)(void __iomem
*);
678 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
679 struct delayed_work task
;
682 struct mii_if_info mii
;
683 struct rtl8169_counters counters
;
687 const struct firmware
*fw
;
689 #define RTL_VER_SIZE 32
691 char version
[RTL_VER_SIZE
];
693 struct rtl_fw_phy_action
{
698 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
701 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
702 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
703 module_param(use_dac
, int, 0);
704 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
705 module_param_named(debug
, debug
.msg_enable
, int, 0);
706 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
707 MODULE_LICENSE("GPL");
708 MODULE_VERSION(RTL8169_VERSION
);
709 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
710 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
711 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
712 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
713 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
715 static int rtl8169_open(struct net_device
*dev
);
716 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
717 struct net_device
*dev
);
718 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
719 static int rtl8169_init_ring(struct net_device
*dev
);
720 static void rtl_hw_start(struct net_device
*dev
);
721 static int rtl8169_close(struct net_device
*dev
);
722 static void rtl_set_rx_mode(struct net_device
*dev
);
723 static void rtl8169_tx_timeout(struct net_device
*dev
);
724 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
725 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
726 void __iomem
*, u32 budget
);
727 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
728 static void rtl8169_down(struct net_device
*dev
);
729 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
730 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
732 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
734 void __iomem
*ioaddr
= tp
->mmio_addr
;
737 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
738 for (i
= 0; i
< 20; i
++) {
740 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
743 return RTL_R32(OCPDR
);
746 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
748 void __iomem
*ioaddr
= tp
->mmio_addr
;
751 RTL_W32(OCPDR
, data
);
752 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
753 for (i
= 0; i
< 20; i
++) {
755 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
760 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
762 void __iomem
*ioaddr
= tp
->mmio_addr
;
766 RTL_W32(ERIAR
, 0x800010e8);
768 for (i
= 0; i
< 5; i
++) {
770 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
774 ocp_write(tp
, 0x1, 0x30, 0x00000001);
777 #define OOB_CMD_RESET 0x00
778 #define OOB_CMD_DRIVER_START 0x05
779 #define OOB_CMD_DRIVER_STOP 0x06
781 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
783 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
786 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
791 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
793 reg
= rtl8168_get_ocp_reg(tp
);
795 for (i
= 0; i
< 10; i
++) {
797 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
802 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
807 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
809 reg
= rtl8168_get_ocp_reg(tp
);
811 for (i
= 0; i
< 10; i
++) {
813 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
818 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
820 u16 reg
= rtl8168_get_ocp_reg(tp
);
822 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
825 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
829 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
831 for (i
= 20; i
> 0; i
--) {
833 * Check if the RTL8169 has completed writing to the specified
836 if (!(RTL_R32(PHYAR
) & 0x80000000))
841 * According to hardware specs a 20us delay is required after write
842 * complete indication, but before sending next command.
847 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
851 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
853 for (i
= 20; i
> 0; i
--) {
855 * Check if the RTL8169 has completed retrieving data from
856 * the specified MII register.
858 if (RTL_R32(PHYAR
) & 0x80000000) {
859 value
= RTL_R32(PHYAR
) & 0xffff;
865 * According to hardware specs a 20us delay is required after read
866 * complete indication, but before sending next command.
873 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
877 RTL_W32(OCPDR
, data
|
878 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
879 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
880 RTL_W32(EPHY_RXER_NUM
, 0);
882 for (i
= 0; i
< 100; i
++) {
884 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
889 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
891 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
892 (value
& OCPDR_DATA_MASK
));
895 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
899 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
902 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
903 RTL_W32(EPHY_RXER_NUM
, 0);
905 for (i
= 0; i
< 100; i
++) {
907 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
911 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
914 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
916 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
918 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
921 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
923 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
926 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
928 r8168dp_2_mdio_start(ioaddr
);
930 r8169_mdio_write(ioaddr
, reg_addr
, value
);
932 r8168dp_2_mdio_stop(ioaddr
);
935 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
939 r8168dp_2_mdio_start(ioaddr
);
941 value
= r8169_mdio_read(ioaddr
, reg_addr
);
943 r8168dp_2_mdio_stop(ioaddr
);
948 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
950 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
953 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
955 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
958 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
960 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
963 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
967 val
= rtl_readphy(tp
, reg_addr
);
968 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
971 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
974 struct rtl8169_private
*tp
= netdev_priv(dev
);
976 rtl_writephy(tp
, location
, val
);
979 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
981 struct rtl8169_private
*tp
= netdev_priv(dev
);
983 return rtl_readphy(tp
, location
);
986 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
990 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
991 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
993 for (i
= 0; i
< 100; i
++) {
994 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1000 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1005 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1007 for (i
= 0; i
< 100; i
++) {
1008 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1009 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1018 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1022 RTL_W32(CSIDR
, value
);
1023 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1024 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1026 for (i
= 0; i
< 100; i
++) {
1027 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1033 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1038 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1039 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1041 for (i
= 0; i
< 100; i
++) {
1042 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1043 value
= RTL_R32(CSIDR
);
1053 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1057 BUG_ON((addr
& 3) || (mask
== 0));
1058 RTL_W32(ERIDR
, val
);
1059 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1061 for (i
= 0; i
< 100; i
++) {
1062 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1068 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1073 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1075 for (i
= 0; i
< 100; i
++) {
1076 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1077 value
= RTL_R32(ERIDR
);
1087 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1091 val
= rtl_eri_read(ioaddr
, addr
, type
);
1092 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1095 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1100 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1102 for (i
= 0; i
< 300; i
++) {
1103 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1104 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1113 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1115 RTL_W16(IntrMask
, 0x0000);
1117 RTL_W16(IntrStatus
, 0xffff);
1120 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1122 void __iomem
*ioaddr
= tp
->mmio_addr
;
1124 return RTL_R32(TBICSR
) & TBIReset
;
1127 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1129 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1132 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1134 return RTL_R32(TBICSR
) & TBILinkOk
;
1137 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1139 return RTL_R8(PHYstatus
) & LinkStatus
;
1142 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1144 void __iomem
*ioaddr
= tp
->mmio_addr
;
1146 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1149 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1153 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1154 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1157 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1159 void __iomem
*ioaddr
= tp
->mmio_addr
;
1160 struct net_device
*dev
= tp
->dev
;
1162 if (!netif_running(dev
))
1165 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1166 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1167 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1168 0x00000011, ERIAR_EXGMAC
);
1169 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1170 0x00000005, ERIAR_EXGMAC
);
1171 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1172 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1173 0x0000001f, ERIAR_EXGMAC
);
1174 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1175 0x00000005, ERIAR_EXGMAC
);
1177 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1178 0x0000001f, ERIAR_EXGMAC
);
1179 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1180 0x0000003f, ERIAR_EXGMAC
);
1182 /* Reset packet filter */
1183 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1185 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1190 static void __rtl8169_check_link_status(struct net_device
*dev
,
1191 struct rtl8169_private
*tp
,
1192 void __iomem
*ioaddr
, bool pm
)
1194 unsigned long flags
;
1196 spin_lock_irqsave(&tp
->lock
, flags
);
1197 if (tp
->link_ok(ioaddr
)) {
1198 rtl_link_chg_patch(tp
);
1199 /* This is to cancel a scheduled suspend if there's one. */
1201 pm_request_resume(&tp
->pci_dev
->dev
);
1202 netif_carrier_on(dev
);
1203 if (net_ratelimit())
1204 netif_info(tp
, ifup
, dev
, "link up\n");
1206 netif_carrier_off(dev
);
1207 netif_info(tp
, ifdown
, dev
, "link down\n");
1209 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1211 spin_unlock_irqrestore(&tp
->lock
, flags
);
1214 static void rtl8169_check_link_status(struct net_device
*dev
,
1215 struct rtl8169_private
*tp
,
1216 void __iomem
*ioaddr
)
1218 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1221 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1223 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1225 void __iomem
*ioaddr
= tp
->mmio_addr
;
1229 options
= RTL_R8(Config1
);
1230 if (!(options
& PMEnable
))
1233 options
= RTL_R8(Config3
);
1234 if (options
& LinkUp
)
1235 wolopts
|= WAKE_PHY
;
1236 if (options
& MagicPacket
)
1237 wolopts
|= WAKE_MAGIC
;
1239 options
= RTL_R8(Config5
);
1241 wolopts
|= WAKE_UCAST
;
1243 wolopts
|= WAKE_BCAST
;
1245 wolopts
|= WAKE_MCAST
;
1250 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1252 struct rtl8169_private
*tp
= netdev_priv(dev
);
1254 spin_lock_irq(&tp
->lock
);
1256 wol
->supported
= WAKE_ANY
;
1257 wol
->wolopts
= __rtl8169_get_wol(tp
);
1259 spin_unlock_irq(&tp
->lock
);
1262 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1264 void __iomem
*ioaddr
= tp
->mmio_addr
;
1266 static const struct {
1271 { WAKE_ANY
, Config1
, PMEnable
},
1272 { WAKE_PHY
, Config3
, LinkUp
},
1273 { WAKE_MAGIC
, Config3
, MagicPacket
},
1274 { WAKE_UCAST
, Config5
, UWF
},
1275 { WAKE_BCAST
, Config5
, BWF
},
1276 { WAKE_MCAST
, Config5
, MWF
},
1277 { WAKE_ANY
, Config5
, LanWake
}
1280 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1282 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1283 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1284 if (wolopts
& cfg
[i
].opt
)
1285 options
|= cfg
[i
].mask
;
1286 RTL_W8(cfg
[i
].reg
, options
);
1289 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1292 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1294 struct rtl8169_private
*tp
= netdev_priv(dev
);
1296 spin_lock_irq(&tp
->lock
);
1299 tp
->features
|= RTL_FEATURE_WOL
;
1301 tp
->features
&= ~RTL_FEATURE_WOL
;
1302 __rtl8169_set_wol(tp
, wol
->wolopts
);
1303 spin_unlock_irq(&tp
->lock
);
1305 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1310 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1312 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1315 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1316 struct ethtool_drvinfo
*info
)
1318 struct rtl8169_private
*tp
= netdev_priv(dev
);
1319 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1321 strcpy(info
->driver
, MODULENAME
);
1322 strcpy(info
->version
, RTL8169_VERSION
);
1323 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1324 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1325 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1329 static int rtl8169_get_regs_len(struct net_device
*dev
)
1331 return R8169_REGS_SIZE
;
1334 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1335 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1337 struct rtl8169_private
*tp
= netdev_priv(dev
);
1338 void __iomem
*ioaddr
= tp
->mmio_addr
;
1342 reg
= RTL_R32(TBICSR
);
1343 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1344 (duplex
== DUPLEX_FULL
)) {
1345 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1346 } else if (autoneg
== AUTONEG_ENABLE
)
1347 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1349 netif_warn(tp
, link
, dev
,
1350 "incorrect speed setting refused in TBI mode\n");
1357 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1358 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1360 struct rtl8169_private
*tp
= netdev_priv(dev
);
1361 int giga_ctrl
, bmcr
;
1364 rtl_writephy(tp
, 0x1f, 0x0000);
1366 if (autoneg
== AUTONEG_ENABLE
) {
1369 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1370 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1371 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1373 if (adv
& ADVERTISED_10baseT_Half
)
1374 auto_nego
|= ADVERTISE_10HALF
;
1375 if (adv
& ADVERTISED_10baseT_Full
)
1376 auto_nego
|= ADVERTISE_10FULL
;
1377 if (adv
& ADVERTISED_100baseT_Half
)
1378 auto_nego
|= ADVERTISE_100HALF
;
1379 if (adv
& ADVERTISED_100baseT_Full
)
1380 auto_nego
|= ADVERTISE_100FULL
;
1382 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1384 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1385 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1387 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1388 if (tp
->mii
.supports_gmii
) {
1389 if (adv
& ADVERTISED_1000baseT_Half
)
1390 giga_ctrl
|= ADVERTISE_1000HALF
;
1391 if (adv
& ADVERTISED_1000baseT_Full
)
1392 giga_ctrl
|= ADVERTISE_1000FULL
;
1393 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1394 ADVERTISED_1000baseT_Full
)) {
1395 netif_info(tp
, link
, dev
,
1396 "PHY does not support 1000Mbps\n");
1400 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1402 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1403 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1407 if (speed
== SPEED_10
)
1409 else if (speed
== SPEED_100
)
1410 bmcr
= BMCR_SPEED100
;
1414 if (duplex
== DUPLEX_FULL
)
1415 bmcr
|= BMCR_FULLDPLX
;
1418 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1420 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1421 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1422 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1423 rtl_writephy(tp
, 0x17, 0x2138);
1424 rtl_writephy(tp
, 0x0e, 0x0260);
1426 rtl_writephy(tp
, 0x17, 0x2108);
1427 rtl_writephy(tp
, 0x0e, 0x0000);
1436 static int rtl8169_set_speed(struct net_device
*dev
,
1437 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1439 struct rtl8169_private
*tp
= netdev_priv(dev
);
1442 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1446 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1447 (advertising
& ADVERTISED_1000baseT_Full
)) {
1448 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1454 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1456 struct rtl8169_private
*tp
= netdev_priv(dev
);
1457 unsigned long flags
;
1460 del_timer_sync(&tp
->timer
);
1462 spin_lock_irqsave(&tp
->lock
, flags
);
1463 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1464 cmd
->duplex
, cmd
->advertising
);
1465 spin_unlock_irqrestore(&tp
->lock
, flags
);
1470 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1472 if (dev
->mtu
> TD_MSS_MAX
)
1473 features
&= ~NETIF_F_ALL_TSO
;
1478 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1480 struct rtl8169_private
*tp
= netdev_priv(dev
);
1481 void __iomem
*ioaddr
= tp
->mmio_addr
;
1482 unsigned long flags
;
1484 spin_lock_irqsave(&tp
->lock
, flags
);
1486 if (features
& NETIF_F_RXCSUM
)
1487 tp
->cp_cmd
|= RxChkSum
;
1489 tp
->cp_cmd
&= ~RxChkSum
;
1491 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1492 tp
->cp_cmd
|= RxVlan
;
1494 tp
->cp_cmd
&= ~RxVlan
;
1496 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1499 spin_unlock_irqrestore(&tp
->lock
, flags
);
1504 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1505 struct sk_buff
*skb
)
1507 return (vlan_tx_tag_present(skb
)) ?
1508 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1511 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1513 u32 opts2
= le32_to_cpu(desc
->opts2
);
1515 if (opts2
& RxVlanTag
)
1516 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1521 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1523 struct rtl8169_private
*tp
= netdev_priv(dev
);
1524 void __iomem
*ioaddr
= tp
->mmio_addr
;
1528 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1529 cmd
->port
= PORT_FIBRE
;
1530 cmd
->transceiver
= XCVR_INTERNAL
;
1532 status
= RTL_R32(TBICSR
);
1533 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1534 cmd
->autoneg
= !!(status
& TBINwEnable
);
1536 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1537 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1542 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1544 struct rtl8169_private
*tp
= netdev_priv(dev
);
1546 return mii_ethtool_gset(&tp
->mii
, cmd
);
1549 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1551 struct rtl8169_private
*tp
= netdev_priv(dev
);
1552 unsigned long flags
;
1555 spin_lock_irqsave(&tp
->lock
, flags
);
1557 rc
= tp
->get_settings(dev
, cmd
);
1559 spin_unlock_irqrestore(&tp
->lock
, flags
);
1563 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1566 struct rtl8169_private
*tp
= netdev_priv(dev
);
1567 unsigned long flags
;
1569 if (regs
->len
> R8169_REGS_SIZE
)
1570 regs
->len
= R8169_REGS_SIZE
;
1572 spin_lock_irqsave(&tp
->lock
, flags
);
1573 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1574 spin_unlock_irqrestore(&tp
->lock
, flags
);
1577 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1579 struct rtl8169_private
*tp
= netdev_priv(dev
);
1581 return tp
->msg_enable
;
1584 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1586 struct rtl8169_private
*tp
= netdev_priv(dev
);
1588 tp
->msg_enable
= value
;
1591 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1598 "tx_single_collisions",
1599 "tx_multi_collisions",
1607 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1611 return ARRAY_SIZE(rtl8169_gstrings
);
1617 static void rtl8169_update_counters(struct net_device
*dev
)
1619 struct rtl8169_private
*tp
= netdev_priv(dev
);
1620 void __iomem
*ioaddr
= tp
->mmio_addr
;
1621 struct device
*d
= &tp
->pci_dev
->dev
;
1622 struct rtl8169_counters
*counters
;
1628 * Some chips are unable to dump tally counters when the receiver
1631 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1634 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1638 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1639 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1640 RTL_W32(CounterAddrLow
, cmd
);
1641 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1644 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1645 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1651 RTL_W32(CounterAddrLow
, 0);
1652 RTL_W32(CounterAddrHigh
, 0);
1654 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1657 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1658 struct ethtool_stats
*stats
, u64
*data
)
1660 struct rtl8169_private
*tp
= netdev_priv(dev
);
1664 rtl8169_update_counters(dev
);
1666 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1667 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1668 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1669 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1670 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1671 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1672 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1673 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1674 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1675 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1676 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1677 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1678 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1681 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1685 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1690 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1691 .get_drvinfo
= rtl8169_get_drvinfo
,
1692 .get_regs_len
= rtl8169_get_regs_len
,
1693 .get_link
= ethtool_op_get_link
,
1694 .get_settings
= rtl8169_get_settings
,
1695 .set_settings
= rtl8169_set_settings
,
1696 .get_msglevel
= rtl8169_get_msglevel
,
1697 .set_msglevel
= rtl8169_set_msglevel
,
1698 .get_regs
= rtl8169_get_regs
,
1699 .get_wol
= rtl8169_get_wol
,
1700 .set_wol
= rtl8169_set_wol
,
1701 .get_strings
= rtl8169_get_strings
,
1702 .get_sset_count
= rtl8169_get_sset_count
,
1703 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1706 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1707 struct net_device
*dev
, u8 default_version
)
1709 void __iomem
*ioaddr
= tp
->mmio_addr
;
1711 * The driver currently handles the 8168Bf and the 8168Be identically
1712 * but they can be identified more specifically through the test below
1715 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1717 * Same thing for the 8101Eb and the 8101Ec:
1719 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1721 static const struct rtl_mac_info
{
1727 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1728 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1729 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1730 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1733 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1734 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1735 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1737 /* 8168DP family. */
1738 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1739 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1740 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1743 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1744 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1745 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1746 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1747 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1748 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1749 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1750 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1751 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1754 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1755 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1756 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1757 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1760 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1761 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1762 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1763 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1764 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1765 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1766 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1767 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1768 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1769 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1770 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1771 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1772 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1773 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1774 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1775 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1776 /* FIXME: where did these entries come from ? -- FR */
1777 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1778 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1781 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1782 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1783 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1784 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1785 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1786 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1789 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1791 const struct rtl_mac_info
*p
= mac_info
;
1794 reg
= RTL_R32(TxConfig
);
1795 while ((reg
& p
->mask
) != p
->val
)
1797 tp
->mac_version
= p
->mac_version
;
1799 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1800 netif_notice(tp
, probe
, dev
,
1801 "unknown MAC, using family default\n");
1802 tp
->mac_version
= default_version
;
1806 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1808 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1816 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1817 const struct phy_reg
*regs
, int len
)
1820 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1825 #define PHY_READ 0x00000000
1826 #define PHY_DATA_OR 0x10000000
1827 #define PHY_DATA_AND 0x20000000
1828 #define PHY_BJMPN 0x30000000
1829 #define PHY_READ_EFUSE 0x40000000
1830 #define PHY_READ_MAC_BYTE 0x50000000
1831 #define PHY_WRITE_MAC_BYTE 0x60000000
1832 #define PHY_CLEAR_READCOUNT 0x70000000
1833 #define PHY_WRITE 0x80000000
1834 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1835 #define PHY_COMP_EQ_SKIPN 0xa0000000
1836 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1837 #define PHY_WRITE_PREVIOUS 0xc0000000
1838 #define PHY_SKIPN 0xd0000000
1839 #define PHY_DELAY_MS 0xe0000000
1840 #define PHY_WRITE_ERI_WORD 0xf0000000
1844 char version
[RTL_VER_SIZE
];
1850 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1852 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1854 const struct firmware
*fw
= rtl_fw
->fw
;
1855 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1856 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1857 char *version
= rtl_fw
->version
;
1860 if (fw
->size
< FW_OPCODE_SIZE
)
1863 if (!fw_info
->magic
) {
1864 size_t i
, size
, start
;
1867 if (fw
->size
< sizeof(*fw_info
))
1870 for (i
= 0; i
< fw
->size
; i
++)
1871 checksum
+= fw
->data
[i
];
1875 start
= le32_to_cpu(fw_info
->fw_start
);
1876 if (start
> fw
->size
)
1879 size
= le32_to_cpu(fw_info
->fw_len
);
1880 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1883 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1885 pa
->code
= (__le32
*)(fw
->data
+ start
);
1888 if (fw
->size
% FW_OPCODE_SIZE
)
1891 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1893 pa
->code
= (__le32
*)fw
->data
;
1894 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1896 version
[RTL_VER_SIZE
- 1] = 0;
1903 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
1904 struct rtl_fw_phy_action
*pa
)
1909 for (index
= 0; index
< pa
->size
; index
++) {
1910 u32 action
= le32_to_cpu(pa
->code
[index
]);
1911 u32 regno
= (action
& 0x0fff0000) >> 16;
1913 switch(action
& 0xf0000000) {
1917 case PHY_READ_EFUSE
:
1918 case PHY_CLEAR_READCOUNT
:
1920 case PHY_WRITE_PREVIOUS
:
1925 if (regno
> index
) {
1926 netif_err(tp
, ifup
, tp
->dev
,
1927 "Out of range of firmware\n");
1931 case PHY_READCOUNT_EQ_SKIP
:
1932 if (index
+ 2 >= pa
->size
) {
1933 netif_err(tp
, ifup
, tp
->dev
,
1934 "Out of range of firmware\n");
1938 case PHY_COMP_EQ_SKIPN
:
1939 case PHY_COMP_NEQ_SKIPN
:
1941 if (index
+ 1 + regno
>= pa
->size
) {
1942 netif_err(tp
, ifup
, tp
->dev
,
1943 "Out of range of firmware\n");
1948 case PHY_READ_MAC_BYTE
:
1949 case PHY_WRITE_MAC_BYTE
:
1950 case PHY_WRITE_ERI_WORD
:
1952 netif_err(tp
, ifup
, tp
->dev
,
1953 "Invalid action 0x%08x\n", action
);
1962 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1964 struct net_device
*dev
= tp
->dev
;
1967 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
1968 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
1972 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
1978 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1980 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1984 predata
= count
= 0;
1986 for (index
= 0; index
< pa
->size
; ) {
1987 u32 action
= le32_to_cpu(pa
->code
[index
]);
1988 u32 data
= action
& 0x0000ffff;
1989 u32 regno
= (action
& 0x0fff0000) >> 16;
1994 switch(action
& 0xf0000000) {
1996 predata
= rtl_readphy(tp
, regno
);
2011 case PHY_READ_EFUSE
:
2012 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2015 case PHY_CLEAR_READCOUNT
:
2020 rtl_writephy(tp
, regno
, data
);
2023 case PHY_READCOUNT_EQ_SKIP
:
2024 index
+= (count
== data
) ? 2 : 1;
2026 case PHY_COMP_EQ_SKIPN
:
2027 if (predata
== data
)
2031 case PHY_COMP_NEQ_SKIPN
:
2032 if (predata
!= data
)
2036 case PHY_WRITE_PREVIOUS
:
2037 rtl_writephy(tp
, regno
, predata
);
2048 case PHY_READ_MAC_BYTE
:
2049 case PHY_WRITE_MAC_BYTE
:
2050 case PHY_WRITE_ERI_WORD
:
2057 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2059 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2060 release_firmware(tp
->rtl_fw
->fw
);
2063 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2066 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2068 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2070 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2071 if (!IS_ERR_OR_NULL(rtl_fw
))
2072 rtl_phy_write_fw(tp
, rtl_fw
);
2075 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2077 if (rtl_readphy(tp
, reg
) != val
)
2078 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2080 rtl_apply_firmware(tp
);
2083 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2085 static const struct phy_reg phy_reg_init
[] = {
2147 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2150 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2152 static const struct phy_reg phy_reg_init
[] = {
2158 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2161 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2163 struct pci_dev
*pdev
= tp
->pci_dev
;
2165 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2166 (pdev
->subsystem_device
!= 0xe000))
2169 rtl_writephy(tp
, 0x1f, 0x0001);
2170 rtl_writephy(tp
, 0x10, 0xf01b);
2171 rtl_writephy(tp
, 0x1f, 0x0000);
2174 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2176 static const struct phy_reg phy_reg_init
[] = {
2216 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2218 rtl8169scd_hw_phy_config_quirk(tp
);
2221 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2223 static const struct phy_reg phy_reg_init
[] = {
2271 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2274 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2276 static const struct phy_reg phy_reg_init
[] = {
2281 rtl_writephy(tp
, 0x1f, 0x0001);
2282 rtl_patchphy(tp
, 0x16, 1 << 0);
2284 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2287 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2289 static const struct phy_reg phy_reg_init
[] = {
2295 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2298 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2300 static const struct phy_reg phy_reg_init
[] = {
2308 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2311 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2313 static const struct phy_reg phy_reg_init
[] = {
2319 rtl_writephy(tp
, 0x1f, 0x0000);
2320 rtl_patchphy(tp
, 0x14, 1 << 5);
2321 rtl_patchphy(tp
, 0x0d, 1 << 5);
2323 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2326 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2328 static const struct phy_reg phy_reg_init
[] = {
2348 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2350 rtl_patchphy(tp
, 0x14, 1 << 5);
2351 rtl_patchphy(tp
, 0x0d, 1 << 5);
2352 rtl_writephy(tp
, 0x1f, 0x0000);
2355 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2357 static const struct phy_reg phy_reg_init
[] = {
2375 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2377 rtl_patchphy(tp
, 0x16, 1 << 0);
2378 rtl_patchphy(tp
, 0x14, 1 << 5);
2379 rtl_patchphy(tp
, 0x0d, 1 << 5);
2380 rtl_writephy(tp
, 0x1f, 0x0000);
2383 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2385 static const struct phy_reg phy_reg_init
[] = {
2397 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2399 rtl_patchphy(tp
, 0x16, 1 << 0);
2400 rtl_patchphy(tp
, 0x14, 1 << 5);
2401 rtl_patchphy(tp
, 0x0d, 1 << 5);
2402 rtl_writephy(tp
, 0x1f, 0x0000);
2405 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2407 rtl8168c_3_hw_phy_config(tp
);
2410 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2412 static const struct phy_reg phy_reg_init_0
[] = {
2413 /* Channel Estimation */
2434 * Enhance line driver power
2443 * Can not link to 1Gbps with bad cable
2444 * Decrease SNR threshold form 21.07dB to 19.04dB
2452 void __iomem
*ioaddr
= tp
->mmio_addr
;
2454 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2458 * Fine Tune Switching regulator parameter
2460 rtl_writephy(tp
, 0x1f, 0x0002);
2461 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2462 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2464 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2465 static const struct phy_reg phy_reg_init
[] = {
2475 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2477 val
= rtl_readphy(tp
, 0x0d);
2479 if ((val
& 0x00ff) != 0x006c) {
2480 static const u32 set
[] = {
2481 0x0065, 0x0066, 0x0067, 0x0068,
2482 0x0069, 0x006a, 0x006b, 0x006c
2486 rtl_writephy(tp
, 0x1f, 0x0002);
2489 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2490 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2493 static const struct phy_reg phy_reg_init
[] = {
2501 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2504 /* RSET couple improve */
2505 rtl_writephy(tp
, 0x1f, 0x0002);
2506 rtl_patchphy(tp
, 0x0d, 0x0300);
2507 rtl_patchphy(tp
, 0x0f, 0x0010);
2509 /* Fine tune PLL performance */
2510 rtl_writephy(tp
, 0x1f, 0x0002);
2511 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2512 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2514 rtl_writephy(tp
, 0x1f, 0x0005);
2515 rtl_writephy(tp
, 0x05, 0x001b);
2517 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2519 rtl_writephy(tp
, 0x1f, 0x0000);
2522 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2524 static const struct phy_reg phy_reg_init_0
[] = {
2525 /* Channel Estimation */
2546 * Enhance line driver power
2555 * Can not link to 1Gbps with bad cable
2556 * Decrease SNR threshold form 21.07dB to 19.04dB
2564 void __iomem
*ioaddr
= tp
->mmio_addr
;
2566 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2568 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2569 static const struct phy_reg phy_reg_init
[] = {
2580 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2582 val
= rtl_readphy(tp
, 0x0d);
2583 if ((val
& 0x00ff) != 0x006c) {
2584 static const u32 set
[] = {
2585 0x0065, 0x0066, 0x0067, 0x0068,
2586 0x0069, 0x006a, 0x006b, 0x006c
2590 rtl_writephy(tp
, 0x1f, 0x0002);
2593 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2594 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2597 static const struct phy_reg phy_reg_init
[] = {
2605 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2608 /* Fine tune PLL performance */
2609 rtl_writephy(tp
, 0x1f, 0x0002);
2610 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2611 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2613 /* Switching regulator Slew rate */
2614 rtl_writephy(tp
, 0x1f, 0x0002);
2615 rtl_patchphy(tp
, 0x0f, 0x0017);
2617 rtl_writephy(tp
, 0x1f, 0x0005);
2618 rtl_writephy(tp
, 0x05, 0x001b);
2620 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2622 rtl_writephy(tp
, 0x1f, 0x0000);
2625 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2627 static const struct phy_reg phy_reg_init
[] = {
2683 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2686 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2688 static const struct phy_reg phy_reg_init
[] = {
2698 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2699 rtl_patchphy(tp
, 0x0d, 1 << 5);
2702 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2704 static const struct phy_reg phy_reg_init
[] = {
2705 /* Enable Delay cap */
2711 /* Channel estimation fine tune */
2720 /* Update PFM & 10M TX idle timer */
2732 rtl_apply_firmware(tp
);
2734 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2736 /* DCO enable for 10M IDLE Power */
2737 rtl_writephy(tp
, 0x1f, 0x0007);
2738 rtl_writephy(tp
, 0x1e, 0x0023);
2739 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2740 rtl_writephy(tp
, 0x1f, 0x0000);
2742 /* For impedance matching */
2743 rtl_writephy(tp
, 0x1f, 0x0002);
2744 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2745 rtl_writephy(tp
, 0x1f, 0x0000);
2747 /* PHY auto speed down */
2748 rtl_writephy(tp
, 0x1f, 0x0007);
2749 rtl_writephy(tp
, 0x1e, 0x002d);
2750 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2751 rtl_writephy(tp
, 0x1f, 0x0000);
2752 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2754 rtl_writephy(tp
, 0x1f, 0x0005);
2755 rtl_writephy(tp
, 0x05, 0x8b86);
2756 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2757 rtl_writephy(tp
, 0x1f, 0x0000);
2759 rtl_writephy(tp
, 0x1f, 0x0005);
2760 rtl_writephy(tp
, 0x05, 0x8b85);
2761 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2762 rtl_writephy(tp
, 0x1f, 0x0007);
2763 rtl_writephy(tp
, 0x1e, 0x0020);
2764 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2765 rtl_writephy(tp
, 0x1f, 0x0006);
2766 rtl_writephy(tp
, 0x00, 0x5a00);
2767 rtl_writephy(tp
, 0x1f, 0x0000);
2768 rtl_writephy(tp
, 0x0d, 0x0007);
2769 rtl_writephy(tp
, 0x0e, 0x003c);
2770 rtl_writephy(tp
, 0x0d, 0x4007);
2771 rtl_writephy(tp
, 0x0e, 0x0000);
2772 rtl_writephy(tp
, 0x0d, 0x0000);
2775 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2777 static const struct phy_reg phy_reg_init
[] = {
2778 /* Enable Delay cap */
2787 /* Channel estimation fine tune */
2804 rtl_apply_firmware(tp
);
2806 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2808 /* For 4-corner performance improve */
2809 rtl_writephy(tp
, 0x1f, 0x0005);
2810 rtl_writephy(tp
, 0x05, 0x8b80);
2811 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2812 rtl_writephy(tp
, 0x1f, 0x0000);
2814 /* PHY auto speed down */
2815 rtl_writephy(tp
, 0x1f, 0x0004);
2816 rtl_writephy(tp
, 0x1f, 0x0007);
2817 rtl_writephy(tp
, 0x1e, 0x002d);
2818 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2819 rtl_writephy(tp
, 0x1f, 0x0002);
2820 rtl_writephy(tp
, 0x1f, 0x0000);
2821 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2823 /* improve 10M EEE waveform */
2824 rtl_writephy(tp
, 0x1f, 0x0005);
2825 rtl_writephy(tp
, 0x05, 0x8b86);
2826 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2827 rtl_writephy(tp
, 0x1f, 0x0000);
2829 /* Improve 2-pair detection performance */
2830 rtl_writephy(tp
, 0x1f, 0x0005);
2831 rtl_writephy(tp
, 0x05, 0x8b85);
2832 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2833 rtl_writephy(tp
, 0x1f, 0x0000);
2836 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2838 rtl_writephy(tp
, 0x1f, 0x0005);
2839 rtl_writephy(tp
, 0x05, 0x8b85);
2840 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2841 rtl_writephy(tp
, 0x1f, 0x0004);
2842 rtl_writephy(tp
, 0x1f, 0x0007);
2843 rtl_writephy(tp
, 0x1e, 0x0020);
2844 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
2845 rtl_writephy(tp
, 0x1f, 0x0002);
2846 rtl_writephy(tp
, 0x1f, 0x0000);
2847 rtl_writephy(tp
, 0x0d, 0x0007);
2848 rtl_writephy(tp
, 0x0e, 0x003c);
2849 rtl_writephy(tp
, 0x0d, 0x4007);
2850 rtl_writephy(tp
, 0x0e, 0x0000);
2851 rtl_writephy(tp
, 0x0d, 0x0000);
2854 rtl_writephy(tp
, 0x1f, 0x0003);
2855 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2856 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2857 rtl_writephy(tp
, 0x1f, 0x0000);
2860 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2862 static const struct phy_reg phy_reg_init
[] = {
2869 rtl_writephy(tp
, 0x1f, 0x0000);
2870 rtl_patchphy(tp
, 0x11, 1 << 12);
2871 rtl_patchphy(tp
, 0x19, 1 << 13);
2872 rtl_patchphy(tp
, 0x10, 1 << 15);
2874 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2877 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2879 static const struct phy_reg phy_reg_init
[] = {
2893 /* Disable ALDPS before ram code */
2894 rtl_writephy(tp
, 0x1f, 0x0000);
2895 rtl_writephy(tp
, 0x18, 0x0310);
2898 rtl_apply_firmware(tp
);
2900 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2903 static void rtl_hw_phy_config(struct net_device
*dev
)
2905 struct rtl8169_private
*tp
= netdev_priv(dev
);
2907 rtl8169_print_mac_version(tp
);
2909 switch (tp
->mac_version
) {
2910 case RTL_GIGA_MAC_VER_01
:
2912 case RTL_GIGA_MAC_VER_02
:
2913 case RTL_GIGA_MAC_VER_03
:
2914 rtl8169s_hw_phy_config(tp
);
2916 case RTL_GIGA_MAC_VER_04
:
2917 rtl8169sb_hw_phy_config(tp
);
2919 case RTL_GIGA_MAC_VER_05
:
2920 rtl8169scd_hw_phy_config(tp
);
2922 case RTL_GIGA_MAC_VER_06
:
2923 rtl8169sce_hw_phy_config(tp
);
2925 case RTL_GIGA_MAC_VER_07
:
2926 case RTL_GIGA_MAC_VER_08
:
2927 case RTL_GIGA_MAC_VER_09
:
2928 rtl8102e_hw_phy_config(tp
);
2930 case RTL_GIGA_MAC_VER_11
:
2931 rtl8168bb_hw_phy_config(tp
);
2933 case RTL_GIGA_MAC_VER_12
:
2934 rtl8168bef_hw_phy_config(tp
);
2936 case RTL_GIGA_MAC_VER_17
:
2937 rtl8168bef_hw_phy_config(tp
);
2939 case RTL_GIGA_MAC_VER_18
:
2940 rtl8168cp_1_hw_phy_config(tp
);
2942 case RTL_GIGA_MAC_VER_19
:
2943 rtl8168c_1_hw_phy_config(tp
);
2945 case RTL_GIGA_MAC_VER_20
:
2946 rtl8168c_2_hw_phy_config(tp
);
2948 case RTL_GIGA_MAC_VER_21
:
2949 rtl8168c_3_hw_phy_config(tp
);
2951 case RTL_GIGA_MAC_VER_22
:
2952 rtl8168c_4_hw_phy_config(tp
);
2954 case RTL_GIGA_MAC_VER_23
:
2955 case RTL_GIGA_MAC_VER_24
:
2956 rtl8168cp_2_hw_phy_config(tp
);
2958 case RTL_GIGA_MAC_VER_25
:
2959 rtl8168d_1_hw_phy_config(tp
);
2961 case RTL_GIGA_MAC_VER_26
:
2962 rtl8168d_2_hw_phy_config(tp
);
2964 case RTL_GIGA_MAC_VER_27
:
2965 rtl8168d_3_hw_phy_config(tp
);
2967 case RTL_GIGA_MAC_VER_28
:
2968 rtl8168d_4_hw_phy_config(tp
);
2970 case RTL_GIGA_MAC_VER_29
:
2971 case RTL_GIGA_MAC_VER_30
:
2972 rtl8105e_hw_phy_config(tp
);
2974 case RTL_GIGA_MAC_VER_31
:
2977 case RTL_GIGA_MAC_VER_32
:
2978 case RTL_GIGA_MAC_VER_33
:
2979 rtl8168e_1_hw_phy_config(tp
);
2981 case RTL_GIGA_MAC_VER_34
:
2982 rtl8168e_2_hw_phy_config(tp
);
2990 static void rtl8169_phy_timer(unsigned long __opaque
)
2992 struct net_device
*dev
= (struct net_device
*)__opaque
;
2993 struct rtl8169_private
*tp
= netdev_priv(dev
);
2994 struct timer_list
*timer
= &tp
->timer
;
2995 void __iomem
*ioaddr
= tp
->mmio_addr
;
2996 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2998 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3000 spin_lock_irq(&tp
->lock
);
3002 if (tp
->phy_reset_pending(tp
)) {
3004 * A busy loop could burn quite a few cycles on nowadays CPU.
3005 * Let's delay the execution of the timer for a few ticks.
3011 if (tp
->link_ok(ioaddr
))
3014 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3016 tp
->phy_reset_enable(tp
);
3019 mod_timer(timer
, jiffies
+ timeout
);
3021 spin_unlock_irq(&tp
->lock
);
3024 #ifdef CONFIG_NET_POLL_CONTROLLER
3026 * Polling 'interrupt' - used by things like netconsole to send skbs
3027 * without having to re-enable interrupts. It's not called while
3028 * the interrupt routine is executing.
3030 static void rtl8169_netpoll(struct net_device
*dev
)
3032 struct rtl8169_private
*tp
= netdev_priv(dev
);
3033 struct pci_dev
*pdev
= tp
->pci_dev
;
3035 disable_irq(pdev
->irq
);
3036 rtl8169_interrupt(pdev
->irq
, dev
);
3037 enable_irq(pdev
->irq
);
3041 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3042 void __iomem
*ioaddr
)
3045 pci_release_regions(pdev
);
3046 pci_clear_mwi(pdev
);
3047 pci_disable_device(pdev
);
3051 static void rtl8169_phy_reset(struct net_device
*dev
,
3052 struct rtl8169_private
*tp
)
3056 tp
->phy_reset_enable(tp
);
3057 for (i
= 0; i
< 100; i
++) {
3058 if (!tp
->phy_reset_pending(tp
))
3062 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3065 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3067 void __iomem
*ioaddr
= tp
->mmio_addr
;
3069 rtl_hw_phy_config(dev
);
3071 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3072 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3076 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3078 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3079 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3081 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3082 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3084 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3085 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3088 rtl8169_phy_reset(dev
, tp
);
3090 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3091 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3092 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3093 (tp
->mii
.supports_gmii
?
3094 ADVERTISED_1000baseT_Half
|
3095 ADVERTISED_1000baseT_Full
: 0));
3097 if (RTL_R8(PHYstatus
) & TBI_Enable
)
3098 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3101 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3103 void __iomem
*ioaddr
= tp
->mmio_addr
;
3107 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3108 high
= addr
[4] | (addr
[5] << 8);
3110 spin_lock_irq(&tp
->lock
);
3112 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3114 RTL_W32(MAC4
, high
);
3120 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3122 spin_unlock_irq(&tp
->lock
);
3125 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3127 struct rtl8169_private
*tp
= netdev_priv(dev
);
3128 struct sockaddr
*addr
= p
;
3130 if (!is_valid_ether_addr(addr
->sa_data
))
3131 return -EADDRNOTAVAIL
;
3133 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3135 rtl_rar_set(tp
, dev
->dev_addr
);
3140 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3142 struct rtl8169_private
*tp
= netdev_priv(dev
);
3143 struct mii_ioctl_data
*data
= if_mii(ifr
);
3145 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3148 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3149 struct mii_ioctl_data
*data
, int cmd
)
3153 data
->phy_id
= 32; /* Internal PHY */
3157 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3161 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3167 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3172 static const struct rtl_cfg_info
{
3173 void (*hw_start
)(struct net_device
*);
3174 unsigned int region
;
3180 } rtl_cfg_infos
[] = {
3182 .hw_start
= rtl_hw_start_8169
,
3185 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3186 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3187 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3188 .features
= RTL_FEATURE_GMII
,
3189 .default_ver
= RTL_GIGA_MAC_VER_01
,
3192 .hw_start
= rtl_hw_start_8168
,
3195 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3196 TxErr
| TxOK
| RxOK
| RxErr
,
3197 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3198 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3199 .default_ver
= RTL_GIGA_MAC_VER_11
,
3202 .hw_start
= rtl_hw_start_8101
,
3205 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3206 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3207 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3208 .features
= RTL_FEATURE_MSI
,
3209 .default_ver
= RTL_GIGA_MAC_VER_13
,
3213 /* Cfg9346_Unlock assumed. */
3214 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3215 const struct rtl_cfg_info
*cfg
)
3220 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3221 if (cfg
->features
& RTL_FEATURE_MSI
) {
3222 if (pci_enable_msi(pdev
)) {
3223 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3226 msi
= RTL_FEATURE_MSI
;
3229 RTL_W8(Config2
, cfg2
);
3233 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3235 if (tp
->features
& RTL_FEATURE_MSI
) {
3236 pci_disable_msi(pdev
);
3237 tp
->features
&= ~RTL_FEATURE_MSI
;
3241 static const struct net_device_ops rtl8169_netdev_ops
= {
3242 .ndo_open
= rtl8169_open
,
3243 .ndo_stop
= rtl8169_close
,
3244 .ndo_get_stats
= rtl8169_get_stats
,
3245 .ndo_start_xmit
= rtl8169_start_xmit
,
3246 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3247 .ndo_validate_addr
= eth_validate_addr
,
3248 .ndo_change_mtu
= rtl8169_change_mtu
,
3249 .ndo_fix_features
= rtl8169_fix_features
,
3250 .ndo_set_features
= rtl8169_set_features
,
3251 .ndo_set_mac_address
= rtl_set_mac_address
,
3252 .ndo_do_ioctl
= rtl8169_ioctl
,
3253 .ndo_set_multicast_list
= rtl_set_rx_mode
,
3254 #ifdef CONFIG_NET_POLL_CONTROLLER
3255 .ndo_poll_controller
= rtl8169_netpoll
,
3260 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3262 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3264 switch (tp
->mac_version
) {
3265 case RTL_GIGA_MAC_VER_27
:
3266 ops
->write
= r8168dp_1_mdio_write
;
3267 ops
->read
= r8168dp_1_mdio_read
;
3269 case RTL_GIGA_MAC_VER_28
:
3270 case RTL_GIGA_MAC_VER_31
:
3271 ops
->write
= r8168dp_2_mdio_write
;
3272 ops
->read
= r8168dp_2_mdio_read
;
3275 ops
->write
= r8169_mdio_write
;
3276 ops
->read
= r8169_mdio_read
;
3281 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3283 rtl_writephy(tp
, 0x1f, 0x0000);
3284 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3287 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3289 rtl_writephy(tp
, 0x1f, 0x0000);
3290 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3293 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3295 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3296 rtl_writephy(tp
, 0x1f, 0x0000);
3297 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3301 r810x_phy_power_down(tp
);
3304 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3306 r810x_phy_power_up(tp
);
3309 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3311 rtl_writephy(tp
, 0x1f, 0x0000);
3312 switch (tp
->mac_version
) {
3313 case RTL_GIGA_MAC_VER_11
:
3314 case RTL_GIGA_MAC_VER_12
:
3315 case RTL_GIGA_MAC_VER_17
:
3316 case RTL_GIGA_MAC_VER_18
:
3317 case RTL_GIGA_MAC_VER_19
:
3318 case RTL_GIGA_MAC_VER_20
:
3319 case RTL_GIGA_MAC_VER_21
:
3320 case RTL_GIGA_MAC_VER_22
:
3321 case RTL_GIGA_MAC_VER_23
:
3322 case RTL_GIGA_MAC_VER_24
:
3323 case RTL_GIGA_MAC_VER_25
:
3324 case RTL_GIGA_MAC_VER_26
:
3325 case RTL_GIGA_MAC_VER_27
:
3326 case RTL_GIGA_MAC_VER_28
:
3327 case RTL_GIGA_MAC_VER_31
:
3328 rtl_writephy(tp
, 0x0e, 0x0000);
3333 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3336 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3338 rtl_writephy(tp
, 0x1f, 0x0000);
3339 switch (tp
->mac_version
) {
3340 case RTL_GIGA_MAC_VER_32
:
3341 case RTL_GIGA_MAC_VER_33
:
3342 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3345 case RTL_GIGA_MAC_VER_11
:
3346 case RTL_GIGA_MAC_VER_12
:
3347 case RTL_GIGA_MAC_VER_17
:
3348 case RTL_GIGA_MAC_VER_18
:
3349 case RTL_GIGA_MAC_VER_19
:
3350 case RTL_GIGA_MAC_VER_20
:
3351 case RTL_GIGA_MAC_VER_21
:
3352 case RTL_GIGA_MAC_VER_22
:
3353 case RTL_GIGA_MAC_VER_23
:
3354 case RTL_GIGA_MAC_VER_24
:
3355 case RTL_GIGA_MAC_VER_25
:
3356 case RTL_GIGA_MAC_VER_26
:
3357 case RTL_GIGA_MAC_VER_27
:
3358 case RTL_GIGA_MAC_VER_28
:
3359 case RTL_GIGA_MAC_VER_31
:
3360 rtl_writephy(tp
, 0x0e, 0x0200);
3362 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3367 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3369 void __iomem
*ioaddr
= tp
->mmio_addr
;
3371 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3372 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3373 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3374 r8168dp_check_dash(tp
)) {
3378 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3379 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3380 (RTL_R16(CPlusCmd
) & ASF
)) {
3384 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3385 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3386 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3388 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3389 rtl_writephy(tp
, 0x1f, 0x0000);
3390 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3392 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3393 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3394 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3395 AcceptMulticast
| AcceptMyPhys
);
3399 r8168_phy_power_down(tp
);
3401 switch (tp
->mac_version
) {
3402 case RTL_GIGA_MAC_VER_25
:
3403 case RTL_GIGA_MAC_VER_26
:
3404 case RTL_GIGA_MAC_VER_27
:
3405 case RTL_GIGA_MAC_VER_28
:
3406 case RTL_GIGA_MAC_VER_31
:
3407 case RTL_GIGA_MAC_VER_32
:
3408 case RTL_GIGA_MAC_VER_33
:
3409 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3414 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3416 void __iomem
*ioaddr
= tp
->mmio_addr
;
3418 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3419 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3420 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3421 r8168dp_check_dash(tp
)) {
3425 switch (tp
->mac_version
) {
3426 case RTL_GIGA_MAC_VER_25
:
3427 case RTL_GIGA_MAC_VER_26
:
3428 case RTL_GIGA_MAC_VER_27
:
3429 case RTL_GIGA_MAC_VER_28
:
3430 case RTL_GIGA_MAC_VER_31
:
3431 case RTL_GIGA_MAC_VER_32
:
3432 case RTL_GIGA_MAC_VER_33
:
3433 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3437 r8168_phy_power_up(tp
);
3440 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3441 void (*op
)(struct rtl8169_private
*))
3447 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3449 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3452 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3454 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3457 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3459 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3461 switch (tp
->mac_version
) {
3462 case RTL_GIGA_MAC_VER_07
:
3463 case RTL_GIGA_MAC_VER_08
:
3464 case RTL_GIGA_MAC_VER_09
:
3465 case RTL_GIGA_MAC_VER_10
:
3466 case RTL_GIGA_MAC_VER_16
:
3467 case RTL_GIGA_MAC_VER_29
:
3468 case RTL_GIGA_MAC_VER_30
:
3469 ops
->down
= r810x_pll_power_down
;
3470 ops
->up
= r810x_pll_power_up
;
3473 case RTL_GIGA_MAC_VER_11
:
3474 case RTL_GIGA_MAC_VER_12
:
3475 case RTL_GIGA_MAC_VER_17
:
3476 case RTL_GIGA_MAC_VER_18
:
3477 case RTL_GIGA_MAC_VER_19
:
3478 case RTL_GIGA_MAC_VER_20
:
3479 case RTL_GIGA_MAC_VER_21
:
3480 case RTL_GIGA_MAC_VER_22
:
3481 case RTL_GIGA_MAC_VER_23
:
3482 case RTL_GIGA_MAC_VER_24
:
3483 case RTL_GIGA_MAC_VER_25
:
3484 case RTL_GIGA_MAC_VER_26
:
3485 case RTL_GIGA_MAC_VER_27
:
3486 case RTL_GIGA_MAC_VER_28
:
3487 case RTL_GIGA_MAC_VER_31
:
3488 case RTL_GIGA_MAC_VER_32
:
3489 case RTL_GIGA_MAC_VER_33
:
3490 case RTL_GIGA_MAC_VER_34
:
3491 ops
->down
= r8168_pll_power_down
;
3492 ops
->up
= r8168_pll_power_up
;
3502 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3504 void __iomem
*ioaddr
= tp
->mmio_addr
;
3506 switch (tp
->mac_version
) {
3507 case RTL_GIGA_MAC_VER_01
:
3508 case RTL_GIGA_MAC_VER_02
:
3509 case RTL_GIGA_MAC_VER_03
:
3510 case RTL_GIGA_MAC_VER_04
:
3511 case RTL_GIGA_MAC_VER_05
:
3512 case RTL_GIGA_MAC_VER_06
:
3513 case RTL_GIGA_MAC_VER_10
:
3514 case RTL_GIGA_MAC_VER_11
:
3515 case RTL_GIGA_MAC_VER_12
:
3516 case RTL_GIGA_MAC_VER_13
:
3517 case RTL_GIGA_MAC_VER_14
:
3518 case RTL_GIGA_MAC_VER_15
:
3519 case RTL_GIGA_MAC_VER_16
:
3520 case RTL_GIGA_MAC_VER_17
:
3521 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3523 case RTL_GIGA_MAC_VER_18
:
3524 case RTL_GIGA_MAC_VER_19
:
3525 case RTL_GIGA_MAC_VER_20
:
3526 case RTL_GIGA_MAC_VER_21
:
3527 case RTL_GIGA_MAC_VER_22
:
3528 case RTL_GIGA_MAC_VER_23
:
3529 case RTL_GIGA_MAC_VER_24
:
3530 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3533 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3538 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3540 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3543 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3545 void __iomem
*ioaddr
= tp
->mmio_addr
;
3548 /* Soft reset the chip. */
3549 RTL_W8(ChipCmd
, CmdReset
);
3551 /* Check that the chip has finished the reset. */
3552 for (i
= 0; i
< 100; i
++) {
3553 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3558 rtl8169_init_ring_indexes(tp
);
3561 static int __devinit
3562 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3564 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3565 const unsigned int region
= cfg
->region
;
3566 struct rtl8169_private
*tp
;
3567 struct mii_if_info
*mii
;
3568 struct net_device
*dev
;
3569 void __iomem
*ioaddr
;
3573 if (netif_msg_drv(&debug
)) {
3574 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3575 MODULENAME
, RTL8169_VERSION
);
3578 dev
= alloc_etherdev(sizeof (*tp
));
3580 if (netif_msg_drv(&debug
))
3581 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3586 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3587 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3588 tp
= netdev_priv(dev
);
3591 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3595 mii
->mdio_read
= rtl_mdio_read
;
3596 mii
->mdio_write
= rtl_mdio_write
;
3597 mii
->phy_id_mask
= 0x1f;
3598 mii
->reg_num_mask
= 0x1f;
3599 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3601 /* disable ASPM completely as that cause random device stop working
3602 * problems as well as full system hangs for some PCIe devices users */
3603 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3604 PCIE_LINK_STATE_CLKPM
);
3606 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3607 rc
= pci_enable_device(pdev
);
3609 netif_err(tp
, probe
, dev
, "enable failure\n");
3610 goto err_out_free_dev_1
;
3613 if (pci_set_mwi(pdev
) < 0)
3614 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3616 /* make sure PCI base addr 1 is MMIO */
3617 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3618 netif_err(tp
, probe
, dev
,
3619 "region #%d not an MMIO resource, aborting\n",
3625 /* check for weird/broken PCI region reporting */
3626 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3627 netif_err(tp
, probe
, dev
,
3628 "Invalid PCI region size(s), aborting\n");
3633 rc
= pci_request_regions(pdev
, MODULENAME
);
3635 netif_err(tp
, probe
, dev
, "could not request regions\n");
3639 tp
->cp_cmd
= RxChkSum
;
3641 if ((sizeof(dma_addr_t
) > 4) &&
3642 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3643 tp
->cp_cmd
|= PCIDAC
;
3644 dev
->features
|= NETIF_F_HIGHDMA
;
3646 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3648 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3649 goto err_out_free_res_3
;
3653 /* ioremap MMIO region */
3654 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3656 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3658 goto err_out_free_res_3
;
3660 tp
->mmio_addr
= ioaddr
;
3662 if (!pci_is_pcie(pdev
))
3663 netif_info(tp
, probe
, dev
, "not PCI Express\n");
3665 /* Identify chip attached to board */
3666 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3670 RTL_W16(IntrMask
, 0x0000);
3674 RTL_W16(IntrStatus
, 0xffff);
3676 pci_set_master(pdev
);
3679 * Pretend we are using VLANs; This bypasses a nasty bug where
3680 * Interrupts stop flowing on high load on 8110SCd controllers.
3682 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3683 tp
->cp_cmd
|= RxVlan
;
3685 rtl_init_mdio_ops(tp
);
3686 rtl_init_pll_power_ops(tp
);
3688 rtl8169_print_mac_version(tp
);
3690 chipset
= tp
->mac_version
;
3691 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3693 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3694 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3695 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3696 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3697 tp
->features
|= RTL_FEATURE_WOL
;
3698 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3699 tp
->features
|= RTL_FEATURE_WOL
;
3700 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3701 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3703 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3704 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3705 tp
->set_speed
= rtl8169_set_speed_tbi
;
3706 tp
->get_settings
= rtl8169_gset_tbi
;
3707 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3708 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3709 tp
->link_ok
= rtl8169_tbi_link_ok
;
3710 tp
->do_ioctl
= rtl_tbi_ioctl
;
3712 tp
->set_speed
= rtl8169_set_speed_xmii
;
3713 tp
->get_settings
= rtl8169_gset_xmii
;
3714 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3715 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3716 tp
->link_ok
= rtl8169_xmii_link_ok
;
3717 tp
->do_ioctl
= rtl_xmii_ioctl
;
3720 spin_lock_init(&tp
->lock
);
3722 /* Get MAC address */
3723 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3724 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3725 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3727 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3728 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3729 dev
->irq
= pdev
->irq
;
3730 dev
->base_addr
= (unsigned long) ioaddr
;
3732 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3734 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3735 * properly for all devices */
3736 dev
->features
|= NETIF_F_RXCSUM
|
3737 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3739 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3740 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3741 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3744 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3745 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3746 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3748 tp
->intr_mask
= 0xffff;
3749 tp
->hw_start
= cfg
->hw_start
;
3750 tp
->intr_event
= cfg
->intr_event
;
3751 tp
->napi_event
= cfg
->napi_event
;
3753 init_timer(&tp
->timer
);
3754 tp
->timer
.data
= (unsigned long) dev
;
3755 tp
->timer
.function
= rtl8169_phy_timer
;
3757 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3759 rc
= register_netdev(dev
);
3763 pci_set_drvdata(pdev
, dev
);
3765 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3766 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3767 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3769 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3770 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3771 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3772 rtl8168_driver_start(tp
);
3775 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3777 if (pci_dev_run_wake(pdev
))
3778 pm_runtime_put_noidle(&pdev
->dev
);
3780 netif_carrier_off(dev
);
3786 rtl_disable_msi(pdev
, tp
);
3789 pci_release_regions(pdev
);
3791 pci_clear_mwi(pdev
);
3792 pci_disable_device(pdev
);
3798 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3800 struct net_device
*dev
= pci_get_drvdata(pdev
);
3801 struct rtl8169_private
*tp
= netdev_priv(dev
);
3803 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3804 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3805 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3806 rtl8168_driver_stop(tp
);
3809 cancel_delayed_work_sync(&tp
->task
);
3811 unregister_netdev(dev
);
3813 rtl_release_firmware(tp
);
3815 if (pci_dev_run_wake(pdev
))
3816 pm_runtime_get_noresume(&pdev
->dev
);
3818 /* restore original MAC address */
3819 rtl_rar_set(tp
, dev
->perm_addr
);
3821 rtl_disable_msi(pdev
, tp
);
3822 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3823 pci_set_drvdata(pdev
, NULL
);
3826 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
3828 struct rtl_fw
*rtl_fw
;
3832 name
= rtl_lookup_firmware_name(tp
);
3834 goto out_no_firmware
;
3836 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3840 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
3844 rc
= rtl_check_firmware(tp
, rtl_fw
);
3846 goto err_release_firmware
;
3848 tp
->rtl_fw
= rtl_fw
;
3852 err_release_firmware
:
3853 release_firmware(rtl_fw
->fw
);
3857 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
3864 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3866 if (IS_ERR(tp
->rtl_fw
))
3867 rtl_request_uncached_firmware(tp
);
3870 static int rtl8169_open(struct net_device
*dev
)
3872 struct rtl8169_private
*tp
= netdev_priv(dev
);
3873 void __iomem
*ioaddr
= tp
->mmio_addr
;
3874 struct pci_dev
*pdev
= tp
->pci_dev
;
3875 int retval
= -ENOMEM
;
3877 pm_runtime_get_sync(&pdev
->dev
);
3880 * Rx and Tx desscriptors needs 256 bytes alignment.
3881 * dma_alloc_coherent provides more.
3883 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3884 &tp
->TxPhyAddr
, GFP_KERNEL
);
3885 if (!tp
->TxDescArray
)
3886 goto err_pm_runtime_put
;
3888 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3889 &tp
->RxPhyAddr
, GFP_KERNEL
);
3890 if (!tp
->RxDescArray
)
3893 retval
= rtl8169_init_ring(dev
);
3897 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3901 rtl_request_firmware(tp
);
3903 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3904 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3907 goto err_release_fw_2
;
3909 napi_enable(&tp
->napi
);
3911 rtl8169_init_phy(dev
, tp
);
3913 rtl8169_set_features(dev
, dev
->features
);
3915 rtl_pll_power_up(tp
);
3919 tp
->saved_wolopts
= 0;
3920 pm_runtime_put_noidle(&pdev
->dev
);
3922 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3927 rtl_release_firmware(tp
);
3928 rtl8169_rx_clear(tp
);
3930 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3932 tp
->RxDescArray
= NULL
;
3934 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3936 tp
->TxDescArray
= NULL
;
3938 pm_runtime_put_noidle(&pdev
->dev
);
3942 static void rtl_rx_close(struct rtl8169_private
*tp
)
3944 void __iomem
*ioaddr
= tp
->mmio_addr
;
3946 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
3949 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3951 void __iomem
*ioaddr
= tp
->mmio_addr
;
3953 /* Disable interrupts */
3954 rtl8169_irq_mask_and_ack(ioaddr
);
3958 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3959 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3960 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3961 while (RTL_R8(TxPoll
) & NPQ
)
3963 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3964 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
3967 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
3974 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3976 void __iomem
*ioaddr
= tp
->mmio_addr
;
3978 /* Set DMA burst size and Interframe Gap Time */
3979 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3980 (InterFrameGap
<< TxInterFrameGapShift
));
3983 static void rtl_hw_start(struct net_device
*dev
)
3985 struct rtl8169_private
*tp
= netdev_priv(dev
);
3989 netif_start_queue(dev
);
3992 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3993 void __iomem
*ioaddr
)
3996 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3997 * register to be written before TxDescAddrLow to work.
3998 * Switching from MMIO to I/O access fixes the issue as well.
4000 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4001 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4002 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4003 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4006 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4010 cmd
= RTL_R16(CPlusCmd
);
4011 RTL_W16(CPlusCmd
, cmd
);
4015 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4017 /* Low hurts. Let's disable the filtering. */
4018 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4021 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4023 static const struct rtl_cfg2_info
{
4028 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4029 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4030 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4031 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4033 const struct rtl_cfg2_info
*p
= cfg2_info
;
4037 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4038 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4039 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4040 RTL_W32(0x7c, p
->val
);
4046 static void rtl_hw_start_8169(struct net_device
*dev
)
4048 struct rtl8169_private
*tp
= netdev_priv(dev
);
4049 void __iomem
*ioaddr
= tp
->mmio_addr
;
4050 struct pci_dev
*pdev
= tp
->pci_dev
;
4052 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4053 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4054 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4057 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4058 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4059 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4060 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4061 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4062 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4066 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4068 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4070 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4071 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4072 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4073 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4074 rtl_set_rx_tx_config_registers(tp
);
4076 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4078 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4079 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4080 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4081 "Bit-3 and bit-14 MUST be 1\n");
4082 tp
->cp_cmd
|= (1 << 14);
4085 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4087 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4090 * Undocumented corner. Supposedly:
4091 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4093 RTL_W16(IntrMitigate
, 0x0000);
4095 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4097 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4098 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4099 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4100 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4101 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4102 rtl_set_rx_tx_config_registers(tp
);
4105 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4107 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4110 RTL_W32(RxMissed
, 0);
4112 rtl_set_rx_mode(dev
);
4114 /* no early-rx interrupts */
4115 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4117 /* Enable all known interrupts by setting the interrupt mask. */
4118 RTL_W16(IntrMask
, tp
->intr_event
);
4121 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
4123 int cap
= pci_pcie_cap(pdev
);
4128 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
4129 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
4130 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
4134 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4138 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4139 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4142 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4144 rtl_csi_access_enable(ioaddr
, 0x17000000);
4147 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4149 rtl_csi_access_enable(ioaddr
, 0x27000000);
4153 unsigned int offset
;
4158 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4163 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4164 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4169 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4171 int cap
= pci_pcie_cap(pdev
);
4176 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4177 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4178 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4182 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4184 int cap
= pci_pcie_cap(pdev
);
4189 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4190 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4191 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4195 #define R8168_CPCMD_QUIRK_MASK (\
4206 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4208 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4210 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4212 rtl_tx_performance_tweak(pdev
,
4213 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4216 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4218 rtl_hw_start_8168bb(ioaddr
, pdev
);
4220 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4222 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4225 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4227 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4229 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4231 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4233 rtl_disable_clock_request(pdev
);
4235 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4238 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4240 static const struct ephy_info e_info_8168cp
[] = {
4241 { 0x01, 0, 0x0001 },
4242 { 0x02, 0x0800, 0x1000 },
4243 { 0x03, 0, 0x0042 },
4244 { 0x06, 0x0080, 0x0000 },
4248 rtl_csi_access_enable_2(ioaddr
);
4250 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4252 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4255 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4257 rtl_csi_access_enable_2(ioaddr
);
4259 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4261 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4263 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4266 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4268 rtl_csi_access_enable_2(ioaddr
);
4270 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4273 RTL_W8(DBG_REG
, 0x20);
4275 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4277 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4279 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4282 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4284 static const struct ephy_info e_info_8168c_1
[] = {
4285 { 0x02, 0x0800, 0x1000 },
4286 { 0x03, 0, 0x0002 },
4287 { 0x06, 0x0080, 0x0000 }
4290 rtl_csi_access_enable_2(ioaddr
);
4292 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4294 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4296 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4299 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4301 static const struct ephy_info e_info_8168c_2
[] = {
4302 { 0x01, 0, 0x0001 },
4303 { 0x03, 0x0400, 0x0220 }
4306 rtl_csi_access_enable_2(ioaddr
);
4308 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4310 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4313 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4315 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4318 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4320 rtl_csi_access_enable_2(ioaddr
);
4322 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4325 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4327 rtl_csi_access_enable_2(ioaddr
);
4329 rtl_disable_clock_request(pdev
);
4331 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4333 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4335 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4338 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4340 rtl_csi_access_enable_1(ioaddr
);
4342 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4344 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4346 rtl_disable_clock_request(pdev
);
4349 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4351 static const struct ephy_info e_info_8168d_4
[] = {
4353 { 0x19, 0x20, 0x50 },
4358 rtl_csi_access_enable_1(ioaddr
);
4360 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4362 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4364 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4365 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4368 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4369 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4372 rtl_enable_clock_request(pdev
);
4375 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4377 static const struct ephy_info e_info_8168e_1
[] = {
4378 { 0x00, 0x0200, 0x0100 },
4379 { 0x00, 0x0000, 0x0004 },
4380 { 0x06, 0x0002, 0x0001 },
4381 { 0x06, 0x0000, 0x0030 },
4382 { 0x07, 0x0000, 0x2000 },
4383 { 0x00, 0x0000, 0x0020 },
4384 { 0x03, 0x5800, 0x2000 },
4385 { 0x03, 0x0000, 0x0001 },
4386 { 0x01, 0x0800, 0x1000 },
4387 { 0x07, 0x0000, 0x4000 },
4388 { 0x1e, 0x0000, 0x2000 },
4389 { 0x19, 0xffff, 0xfe6c },
4390 { 0x0a, 0x0000, 0x0040 }
4393 rtl_csi_access_enable_2(ioaddr
);
4395 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4397 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4399 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4401 rtl_disable_clock_request(pdev
);
4403 /* Reset tx FIFO pointer */
4404 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4405 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4407 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4410 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4412 static const struct ephy_info e_info_8168e_2
[] = {
4413 { 0x09, 0x0000, 0x0080 },
4414 { 0x19, 0x0000, 0x0224 }
4417 rtl_csi_access_enable_1(ioaddr
);
4419 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4421 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4423 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4424 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4425 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4426 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4427 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4428 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4429 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4430 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4433 RTL_W8(MaxTxPacketSize
, 0x27);
4435 rtl_disable_clock_request(pdev
);
4437 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4438 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4440 /* Adjust EEE LED frequency */
4441 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4443 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4444 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4445 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4448 static void rtl_hw_start_8168(struct net_device
*dev
)
4450 struct rtl8169_private
*tp
= netdev_priv(dev
);
4451 void __iomem
*ioaddr
= tp
->mmio_addr
;
4452 struct pci_dev
*pdev
= tp
->pci_dev
;
4454 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4456 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4458 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4460 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4462 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4464 RTL_W16(IntrMitigate
, 0x5151);
4466 /* Work around for RxFIFO overflow. */
4467 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4468 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4469 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4470 tp
->intr_event
&= ~RxOverflow
;
4473 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4475 rtl_set_rx_mode(dev
);
4477 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4478 (InterFrameGap
<< TxInterFrameGapShift
));
4482 switch (tp
->mac_version
) {
4483 case RTL_GIGA_MAC_VER_11
:
4484 rtl_hw_start_8168bb(ioaddr
, pdev
);
4487 case RTL_GIGA_MAC_VER_12
:
4488 case RTL_GIGA_MAC_VER_17
:
4489 rtl_hw_start_8168bef(ioaddr
, pdev
);
4492 case RTL_GIGA_MAC_VER_18
:
4493 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4496 case RTL_GIGA_MAC_VER_19
:
4497 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4500 case RTL_GIGA_MAC_VER_20
:
4501 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4504 case RTL_GIGA_MAC_VER_21
:
4505 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4508 case RTL_GIGA_MAC_VER_22
:
4509 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4512 case RTL_GIGA_MAC_VER_23
:
4513 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4516 case RTL_GIGA_MAC_VER_24
:
4517 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4520 case RTL_GIGA_MAC_VER_25
:
4521 case RTL_GIGA_MAC_VER_26
:
4522 case RTL_GIGA_MAC_VER_27
:
4523 rtl_hw_start_8168d(ioaddr
, pdev
);
4526 case RTL_GIGA_MAC_VER_28
:
4527 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4530 case RTL_GIGA_MAC_VER_31
:
4531 rtl_hw_start_8168dp(ioaddr
, pdev
);
4534 case RTL_GIGA_MAC_VER_32
:
4535 case RTL_GIGA_MAC_VER_33
:
4536 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4538 case RTL_GIGA_MAC_VER_34
:
4539 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4543 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4544 dev
->name
, tp
->mac_version
);
4548 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4550 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4552 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4554 RTL_W16(IntrMask
, tp
->intr_event
);
4557 #define R810X_CPCMD_QUIRK_MASK (\
4568 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4570 static const struct ephy_info e_info_8102e_1
[] = {
4571 { 0x01, 0, 0x6e65 },
4572 { 0x02, 0, 0x091f },
4573 { 0x03, 0, 0xc2f9 },
4574 { 0x06, 0, 0xafb5 },
4575 { 0x07, 0, 0x0e00 },
4576 { 0x19, 0, 0xec80 },
4577 { 0x01, 0, 0x2e65 },
4582 rtl_csi_access_enable_2(ioaddr
);
4584 RTL_W8(DBG_REG
, FIX_NAK_1
);
4586 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4589 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4590 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4592 cfg1
= RTL_R8(Config1
);
4593 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4594 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4596 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4599 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4601 rtl_csi_access_enable_2(ioaddr
);
4603 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4605 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4606 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4609 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4611 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4613 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4616 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4618 static const struct ephy_info e_info_8105e_1
[] = {
4619 { 0x07, 0, 0x4000 },
4620 { 0x19, 0, 0x0200 },
4621 { 0x19, 0, 0x0020 },
4622 { 0x1e, 0, 0x2000 },
4623 { 0x03, 0, 0x0001 },
4624 { 0x19, 0, 0x0100 },
4625 { 0x19, 0, 0x0004 },
4629 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4630 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4632 /* Disable Early Tally Counter */
4633 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4635 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4636 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4638 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4641 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4643 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4644 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4647 static void rtl_hw_start_8101(struct net_device
*dev
)
4649 struct rtl8169_private
*tp
= netdev_priv(dev
);
4650 void __iomem
*ioaddr
= tp
->mmio_addr
;
4651 struct pci_dev
*pdev
= tp
->pci_dev
;
4653 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4654 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4655 int cap
= pci_pcie_cap(pdev
);
4658 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4659 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4663 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4665 switch (tp
->mac_version
) {
4666 case RTL_GIGA_MAC_VER_07
:
4667 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4670 case RTL_GIGA_MAC_VER_08
:
4671 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4674 case RTL_GIGA_MAC_VER_09
:
4675 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4678 case RTL_GIGA_MAC_VER_29
:
4679 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4681 case RTL_GIGA_MAC_VER_30
:
4682 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4686 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4688 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4690 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4692 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4693 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4695 RTL_W16(IntrMitigate
, 0x0000);
4697 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4699 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4700 rtl_set_rx_tx_config_registers(tp
);
4704 rtl_set_rx_mode(dev
);
4706 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4708 RTL_W16(IntrMask
, tp
->intr_event
);
4711 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4713 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4717 netdev_update_features(dev
);
4722 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4724 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4725 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4728 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4729 void **data_buff
, struct RxDesc
*desc
)
4731 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4736 rtl8169_make_unusable_by_asic(desc
);
4739 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4741 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4743 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4746 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4749 desc
->addr
= cpu_to_le64(mapping
);
4751 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4754 static inline void *rtl8169_align(void *data
)
4756 return (void *)ALIGN((long)data
, 16);
4759 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4760 struct RxDesc
*desc
)
4764 struct device
*d
= &tp
->pci_dev
->dev
;
4765 struct net_device
*dev
= tp
->dev
;
4766 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4768 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4772 if (rtl8169_align(data
) != data
) {
4774 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4779 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4781 if (unlikely(dma_mapping_error(d
, mapping
))) {
4782 if (net_ratelimit())
4783 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4787 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4795 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4799 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4800 if (tp
->Rx_databuff
[i
]) {
4801 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4802 tp
->RxDescArray
+ i
);
4807 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4809 desc
->opts1
|= cpu_to_le32(RingEnd
);
4812 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4816 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4819 if (tp
->Rx_databuff
[i
])
4822 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4824 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4827 tp
->Rx_databuff
[i
] = data
;
4830 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4834 rtl8169_rx_clear(tp
);
4838 static int rtl8169_init_ring(struct net_device
*dev
)
4840 struct rtl8169_private
*tp
= netdev_priv(dev
);
4842 rtl8169_init_ring_indexes(tp
);
4844 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4845 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4847 return rtl8169_rx_fill(tp
);
4850 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4851 struct TxDesc
*desc
)
4853 unsigned int len
= tx_skb
->len
;
4855 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4863 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4868 for (i
= 0; i
< n
; i
++) {
4869 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4870 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4871 unsigned int len
= tx_skb
->len
;
4874 struct sk_buff
*skb
= tx_skb
->skb
;
4876 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4877 tp
->TxDescArray
+ entry
);
4879 tp
->dev
->stats
.tx_dropped
++;
4887 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4889 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4890 tp
->cur_tx
= tp
->dirty_tx
= 0;
4893 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4895 struct rtl8169_private
*tp
= netdev_priv(dev
);
4897 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4898 schedule_delayed_work(&tp
->task
, 4);
4901 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4903 struct rtl8169_private
*tp
= netdev_priv(dev
);
4904 void __iomem
*ioaddr
= tp
->mmio_addr
;
4906 synchronize_irq(dev
->irq
);
4908 /* Wait for any pending NAPI task to complete */
4909 napi_disable(&tp
->napi
);
4911 rtl8169_irq_mask_and_ack(ioaddr
);
4913 tp
->intr_mask
= 0xffff;
4914 RTL_W16(IntrMask
, tp
->intr_event
);
4915 napi_enable(&tp
->napi
);
4918 static void rtl8169_reinit_task(struct work_struct
*work
)
4920 struct rtl8169_private
*tp
=
4921 container_of(work
, struct rtl8169_private
, task
.work
);
4922 struct net_device
*dev
= tp
->dev
;
4927 if (!netif_running(dev
))
4930 rtl8169_wait_for_quiescence(dev
);
4933 ret
= rtl8169_open(dev
);
4934 if (unlikely(ret
< 0)) {
4935 if (net_ratelimit())
4936 netif_err(tp
, drv
, dev
,
4937 "reinit failure (status = %d). Rescheduling\n",
4939 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4946 static void rtl8169_reset_task(struct work_struct
*work
)
4948 struct rtl8169_private
*tp
=
4949 container_of(work
, struct rtl8169_private
, task
.work
);
4950 struct net_device
*dev
= tp
->dev
;
4955 if (!netif_running(dev
))
4958 rtl8169_wait_for_quiescence(dev
);
4960 for (i
= 0; i
< NUM_RX_DESC
; i
++)
4961 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
4963 rtl8169_tx_clear(tp
);
4965 rtl8169_hw_reset(tp
);
4967 netif_wake_queue(dev
);
4968 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4974 static void rtl8169_tx_timeout(struct net_device
*dev
)
4976 struct rtl8169_private
*tp
= netdev_priv(dev
);
4978 rtl8169_hw_reset(tp
);
4980 /* Let's wait a bit while any (async) irq lands on */
4981 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4984 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4987 struct skb_shared_info
*info
= skb_shinfo(skb
);
4988 unsigned int cur_frag
, entry
;
4989 struct TxDesc
* uninitialized_var(txd
);
4990 struct device
*d
= &tp
->pci_dev
->dev
;
4993 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4994 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4999 entry
= (entry
+ 1) % NUM_TX_DESC
;
5001 txd
= tp
->TxDescArray
+ entry
;
5003 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
5004 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5005 if (unlikely(dma_mapping_error(d
, mapping
))) {
5006 if (net_ratelimit())
5007 netif_err(tp
, drv
, tp
->dev
,
5008 "Failed to map TX fragments DMA!\n");
5012 /* Anti gcc 2.95.3 bugware (sic) */
5013 status
= opts
[0] | len
|
5014 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5016 txd
->opts1
= cpu_to_le32(status
);
5017 txd
->opts2
= cpu_to_le32(opts
[1]);
5018 txd
->addr
= cpu_to_le64(mapping
);
5020 tp
->tx_skb
[entry
].len
= len
;
5024 tp
->tx_skb
[entry
].skb
= skb
;
5025 txd
->opts1
|= cpu_to_le32(LastFrag
);
5031 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5035 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5036 struct sk_buff
*skb
, u32
*opts
)
5038 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5039 u32 mss
= skb_shinfo(skb
)->gso_size
;
5040 int offset
= info
->opts_offset
;
5044 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5045 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5046 const struct iphdr
*ip
= ip_hdr(skb
);
5048 if (ip
->protocol
== IPPROTO_TCP
)
5049 opts
[offset
] |= info
->checksum
.tcp
;
5050 else if (ip
->protocol
== IPPROTO_UDP
)
5051 opts
[offset
] |= info
->checksum
.udp
;
5057 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5058 struct net_device
*dev
)
5060 struct rtl8169_private
*tp
= netdev_priv(dev
);
5061 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5062 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5063 void __iomem
*ioaddr
= tp
->mmio_addr
;
5064 struct device
*d
= &tp
->pci_dev
->dev
;
5070 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5071 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5075 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5078 len
= skb_headlen(skb
);
5079 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5080 if (unlikely(dma_mapping_error(d
, mapping
))) {
5081 if (net_ratelimit())
5082 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5086 tp
->tx_skb
[entry
].len
= len
;
5087 txd
->addr
= cpu_to_le64(mapping
);
5089 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5092 rtl8169_tso_csum(tp
, skb
, opts
);
5094 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5098 opts
[0] |= FirstFrag
;
5100 opts
[0] |= FirstFrag
| LastFrag
;
5101 tp
->tx_skb
[entry
].skb
= skb
;
5104 txd
->opts2
= cpu_to_le32(opts
[1]);
5108 /* Anti gcc 2.95.3 bugware (sic) */
5109 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5110 txd
->opts1
= cpu_to_le32(status
);
5112 tp
->cur_tx
+= frags
+ 1;
5116 RTL_W8(TxPoll
, NPQ
);
5118 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5119 netif_stop_queue(dev
);
5121 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5122 netif_wake_queue(dev
);
5125 return NETDEV_TX_OK
;
5128 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5131 dev
->stats
.tx_dropped
++;
5132 return NETDEV_TX_OK
;
5135 netif_stop_queue(dev
);
5136 dev
->stats
.tx_dropped
++;
5137 return NETDEV_TX_BUSY
;
5140 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5142 struct rtl8169_private
*tp
= netdev_priv(dev
);
5143 struct pci_dev
*pdev
= tp
->pci_dev
;
5144 u16 pci_status
, pci_cmd
;
5146 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5147 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5149 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5150 pci_cmd
, pci_status
);
5153 * The recovery sequence below admits a very elaborated explanation:
5154 * - it seems to work;
5155 * - I did not see what else could be done;
5156 * - it makes iop3xx happy.
5158 * Feel free to adjust to your needs.
5160 if (pdev
->broken_parity_status
)
5161 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5163 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5165 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5167 pci_write_config_word(pdev
, PCI_STATUS
,
5168 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5169 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5170 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5172 /* The infamous DAC f*ckup only happens at boot time */
5173 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5174 void __iomem
*ioaddr
= tp
->mmio_addr
;
5176 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5177 tp
->cp_cmd
&= ~PCIDAC
;
5178 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5179 dev
->features
&= ~NETIF_F_HIGHDMA
;
5182 rtl8169_hw_reset(tp
);
5184 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5187 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5188 struct rtl8169_private
*tp
,
5189 void __iomem
*ioaddr
)
5191 unsigned int dirty_tx
, tx_left
;
5193 dirty_tx
= tp
->dirty_tx
;
5195 tx_left
= tp
->cur_tx
- dirty_tx
;
5197 while (tx_left
> 0) {
5198 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5199 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5203 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5204 if (status
& DescOwn
)
5207 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5208 tp
->TxDescArray
+ entry
);
5209 if (status
& LastFrag
) {
5210 dev
->stats
.tx_packets
++;
5211 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5212 dev_kfree_skb(tx_skb
->skb
);
5219 if (tp
->dirty_tx
!= dirty_tx
) {
5220 tp
->dirty_tx
= dirty_tx
;
5222 if (netif_queue_stopped(dev
) &&
5223 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5224 netif_wake_queue(dev
);
5227 * 8168 hack: TxPoll requests are lost when the Tx packets are
5228 * too close. Let's kick an extra TxPoll request when a burst
5229 * of start_xmit activity is detected (if it is not detected,
5230 * it is slow enough). -- FR
5233 if (tp
->cur_tx
!= dirty_tx
)
5234 RTL_W8(TxPoll
, NPQ
);
5238 static inline int rtl8169_fragmented_frame(u32 status
)
5240 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5243 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5245 u32 status
= opts1
& RxProtoMask
;
5247 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5248 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5249 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5251 skb_checksum_none_assert(skb
);
5254 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5255 struct rtl8169_private
*tp
,
5259 struct sk_buff
*skb
;
5260 struct device
*d
= &tp
->pci_dev
->dev
;
5262 data
= rtl8169_align(data
);
5263 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5265 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5267 memcpy(skb
->data
, data
, pkt_size
);
5268 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5273 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5274 struct rtl8169_private
*tp
,
5275 void __iomem
*ioaddr
, u32 budget
)
5277 unsigned int cur_rx
, rx_left
;
5280 cur_rx
= tp
->cur_rx
;
5281 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5282 rx_left
= min(rx_left
, budget
);
5284 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5285 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5286 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5290 status
= le32_to_cpu(desc
->opts1
);
5292 if (status
& DescOwn
)
5294 if (unlikely(status
& RxRES
)) {
5295 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5297 dev
->stats
.rx_errors
++;
5298 if (status
& (RxRWT
| RxRUNT
))
5299 dev
->stats
.rx_length_errors
++;
5301 dev
->stats
.rx_crc_errors
++;
5302 if (status
& RxFOVF
) {
5303 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5304 dev
->stats
.rx_fifo_errors
++;
5306 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5308 struct sk_buff
*skb
;
5309 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5310 int pkt_size
= (status
& 0x00001FFF) - 4;
5313 * The driver does not support incoming fragmented
5314 * frames. They are seen as a symptom of over-mtu
5317 if (unlikely(rtl8169_fragmented_frame(status
))) {
5318 dev
->stats
.rx_dropped
++;
5319 dev
->stats
.rx_length_errors
++;
5320 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5324 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5325 tp
, pkt_size
, addr
);
5326 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5328 dev
->stats
.rx_dropped
++;
5332 rtl8169_rx_csum(skb
, status
);
5333 skb_put(skb
, pkt_size
);
5334 skb
->protocol
= eth_type_trans(skb
, dev
);
5336 rtl8169_rx_vlan_tag(desc
, skb
);
5338 napi_gro_receive(&tp
->napi
, skb
);
5340 dev
->stats
.rx_bytes
+= pkt_size
;
5341 dev
->stats
.rx_packets
++;
5344 /* Work around for AMD plateform. */
5345 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5346 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5352 count
= cur_rx
- tp
->cur_rx
;
5353 tp
->cur_rx
= cur_rx
;
5355 tp
->dirty_rx
+= count
;
5360 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5362 struct net_device
*dev
= dev_instance
;
5363 struct rtl8169_private
*tp
= netdev_priv(dev
);
5364 void __iomem
*ioaddr
= tp
->mmio_addr
;
5368 /* loop handling interrupts until we have no new ones or
5369 * we hit a invalid/hotplug case.
5371 status
= RTL_R16(IntrStatus
);
5372 while (status
&& status
!= 0xffff) {
5375 /* Handle all of the error cases first. These will reset
5376 * the chip, so just exit the loop.
5378 if (unlikely(!netif_running(dev
))) {
5379 rtl8169_hw_reset(tp
);
5383 if (unlikely(status
& RxFIFOOver
)) {
5384 switch (tp
->mac_version
) {
5385 /* Work around for rx fifo overflow */
5386 case RTL_GIGA_MAC_VER_11
:
5387 case RTL_GIGA_MAC_VER_22
:
5388 case RTL_GIGA_MAC_VER_26
:
5389 netif_stop_queue(dev
);
5390 rtl8169_tx_timeout(dev
);
5392 /* Testers needed. */
5393 case RTL_GIGA_MAC_VER_17
:
5394 case RTL_GIGA_MAC_VER_19
:
5395 case RTL_GIGA_MAC_VER_20
:
5396 case RTL_GIGA_MAC_VER_21
:
5397 case RTL_GIGA_MAC_VER_23
:
5398 case RTL_GIGA_MAC_VER_24
:
5399 case RTL_GIGA_MAC_VER_27
:
5400 case RTL_GIGA_MAC_VER_28
:
5401 case RTL_GIGA_MAC_VER_31
:
5402 /* Experimental science. Pktgen proof. */
5403 case RTL_GIGA_MAC_VER_12
:
5404 case RTL_GIGA_MAC_VER_25
:
5405 if (status
== RxFIFOOver
)
5413 if (unlikely(status
& SYSErr
)) {
5414 rtl8169_pcierr_interrupt(dev
);
5418 if (status
& LinkChg
)
5419 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5421 /* We need to see the lastest version of tp->intr_mask to
5422 * avoid ignoring an MSI interrupt and having to wait for
5423 * another event which may never come.
5426 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5427 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5428 tp
->intr_mask
= ~tp
->napi_event
;
5430 if (likely(napi_schedule_prep(&tp
->napi
)))
5431 __napi_schedule(&tp
->napi
);
5433 netif_info(tp
, intr
, dev
,
5434 "interrupt %04x in poll\n", status
);
5437 /* We only get a new MSI interrupt when all active irq
5438 * sources on the chip have been acknowledged. So, ack
5439 * everything we've seen and check if new sources have become
5440 * active to avoid blocking all interrupts from the chip.
5443 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5444 status
= RTL_R16(IntrStatus
);
5447 return IRQ_RETVAL(handled
);
5450 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5452 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5453 struct net_device
*dev
= tp
->dev
;
5454 void __iomem
*ioaddr
= tp
->mmio_addr
;
5457 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5458 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5460 if (work_done
< budget
) {
5461 napi_complete(napi
);
5463 /* We need for force the visibility of tp->intr_mask
5464 * for other CPUs, as we can loose an MSI interrupt
5465 * and potentially wait for a retransmit timeout if we don't.
5466 * The posted write to IntrMask is safe, as it will
5467 * eventually make it to the chip and we won't loose anything
5470 tp
->intr_mask
= 0xffff;
5472 RTL_W16(IntrMask
, tp
->intr_event
);
5478 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5480 struct rtl8169_private
*tp
= netdev_priv(dev
);
5482 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5485 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5486 RTL_W32(RxMissed
, 0);
5489 static void rtl8169_down(struct net_device
*dev
)
5491 struct rtl8169_private
*tp
= netdev_priv(dev
);
5492 void __iomem
*ioaddr
= tp
->mmio_addr
;
5494 del_timer_sync(&tp
->timer
);
5496 netif_stop_queue(dev
);
5498 napi_disable(&tp
->napi
);
5500 spin_lock_irq(&tp
->lock
);
5502 rtl8169_hw_reset(tp
);
5504 * At this point device interrupts can not be enabled in any function,
5505 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5506 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5508 rtl8169_rx_missed(dev
, ioaddr
);
5510 spin_unlock_irq(&tp
->lock
);
5512 synchronize_irq(dev
->irq
);
5514 /* Give a racing hard_start_xmit a few cycles to complete. */
5515 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5517 rtl8169_tx_clear(tp
);
5519 rtl8169_rx_clear(tp
);
5521 rtl_pll_power_down(tp
);
5524 static int rtl8169_close(struct net_device
*dev
)
5526 struct rtl8169_private
*tp
= netdev_priv(dev
);
5527 struct pci_dev
*pdev
= tp
->pci_dev
;
5529 pm_runtime_get_sync(&pdev
->dev
);
5531 /* Update counters before going down */
5532 rtl8169_update_counters(dev
);
5536 free_irq(dev
->irq
, dev
);
5538 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5540 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5542 tp
->TxDescArray
= NULL
;
5543 tp
->RxDescArray
= NULL
;
5545 pm_runtime_put_sync(&pdev
->dev
);
5550 static void rtl_set_rx_mode(struct net_device
*dev
)
5552 struct rtl8169_private
*tp
= netdev_priv(dev
);
5553 void __iomem
*ioaddr
= tp
->mmio_addr
;
5554 unsigned long flags
;
5555 u32 mc_filter
[2]; /* Multicast hash filter */
5559 if (dev
->flags
& IFF_PROMISC
) {
5560 /* Unconditionally log net taps. */
5561 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5563 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5565 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5566 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5567 (dev
->flags
& IFF_ALLMULTI
)) {
5568 /* Too many to filter perfectly -- accept all multicasts. */
5569 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5570 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5572 struct netdev_hw_addr
*ha
;
5574 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5575 mc_filter
[1] = mc_filter
[0] = 0;
5576 netdev_for_each_mc_addr(ha
, dev
) {
5577 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5578 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5579 rx_mode
|= AcceptMulticast
;
5583 spin_lock_irqsave(&tp
->lock
, flags
);
5585 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5587 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5588 u32 data
= mc_filter
[0];
5590 mc_filter
[0] = swab32(mc_filter
[1]);
5591 mc_filter
[1] = swab32(data
);
5594 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5595 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5597 RTL_W32(RxConfig
, tmp
);
5599 spin_unlock_irqrestore(&tp
->lock
, flags
);
5603 * rtl8169_get_stats - Get rtl8169 read/write statistics
5604 * @dev: The Ethernet Device to get statistics for
5606 * Get TX/RX statistics for rtl8169
5608 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5610 struct rtl8169_private
*tp
= netdev_priv(dev
);
5611 void __iomem
*ioaddr
= tp
->mmio_addr
;
5612 unsigned long flags
;
5614 if (netif_running(dev
)) {
5615 spin_lock_irqsave(&tp
->lock
, flags
);
5616 rtl8169_rx_missed(dev
, ioaddr
);
5617 spin_unlock_irqrestore(&tp
->lock
, flags
);
5623 static void rtl8169_net_suspend(struct net_device
*dev
)
5625 struct rtl8169_private
*tp
= netdev_priv(dev
);
5627 if (!netif_running(dev
))
5630 rtl_pll_power_down(tp
);
5632 netif_device_detach(dev
);
5633 netif_stop_queue(dev
);
5638 static int rtl8169_suspend(struct device
*device
)
5640 struct pci_dev
*pdev
= to_pci_dev(device
);
5641 struct net_device
*dev
= pci_get_drvdata(pdev
);
5643 rtl8169_net_suspend(dev
);
5648 static void __rtl8169_resume(struct net_device
*dev
)
5650 struct rtl8169_private
*tp
= netdev_priv(dev
);
5652 netif_device_attach(dev
);
5654 rtl_pll_power_up(tp
);
5656 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5659 static int rtl8169_resume(struct device
*device
)
5661 struct pci_dev
*pdev
= to_pci_dev(device
);
5662 struct net_device
*dev
= pci_get_drvdata(pdev
);
5663 struct rtl8169_private
*tp
= netdev_priv(dev
);
5665 rtl8169_init_phy(dev
, tp
);
5667 if (netif_running(dev
))
5668 __rtl8169_resume(dev
);
5673 static int rtl8169_runtime_suspend(struct device
*device
)
5675 struct pci_dev
*pdev
= to_pci_dev(device
);
5676 struct net_device
*dev
= pci_get_drvdata(pdev
);
5677 struct rtl8169_private
*tp
= netdev_priv(dev
);
5679 if (!tp
->TxDescArray
)
5682 spin_lock_irq(&tp
->lock
);
5683 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5684 __rtl8169_set_wol(tp
, WAKE_ANY
);
5685 spin_unlock_irq(&tp
->lock
);
5687 rtl8169_net_suspend(dev
);
5692 static int rtl8169_runtime_resume(struct device
*device
)
5694 struct pci_dev
*pdev
= to_pci_dev(device
);
5695 struct net_device
*dev
= pci_get_drvdata(pdev
);
5696 struct rtl8169_private
*tp
= netdev_priv(dev
);
5698 if (!tp
->TxDescArray
)
5701 spin_lock_irq(&tp
->lock
);
5702 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5703 tp
->saved_wolopts
= 0;
5704 spin_unlock_irq(&tp
->lock
);
5706 rtl8169_init_phy(dev
, tp
);
5708 __rtl8169_resume(dev
);
5713 static int rtl8169_runtime_idle(struct device
*device
)
5715 struct pci_dev
*pdev
= to_pci_dev(device
);
5716 struct net_device
*dev
= pci_get_drvdata(pdev
);
5717 struct rtl8169_private
*tp
= netdev_priv(dev
);
5719 return tp
->TxDescArray
? -EBUSY
: 0;
5722 static const struct dev_pm_ops rtl8169_pm_ops
= {
5723 .suspend
= rtl8169_suspend
,
5724 .resume
= rtl8169_resume
,
5725 .freeze
= rtl8169_suspend
,
5726 .thaw
= rtl8169_resume
,
5727 .poweroff
= rtl8169_suspend
,
5728 .restore
= rtl8169_resume
,
5729 .runtime_suspend
= rtl8169_runtime_suspend
,
5730 .runtime_resume
= rtl8169_runtime_resume
,
5731 .runtime_idle
= rtl8169_runtime_idle
,
5734 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5736 #else /* !CONFIG_PM */
5738 #define RTL8169_PM_OPS NULL
5740 #endif /* !CONFIG_PM */
5742 static void rtl_shutdown(struct pci_dev
*pdev
)
5744 struct net_device
*dev
= pci_get_drvdata(pdev
);
5745 struct rtl8169_private
*tp
= netdev_priv(dev
);
5746 void __iomem
*ioaddr
= tp
->mmio_addr
;
5748 rtl8169_net_suspend(dev
);
5750 /* Restore original MAC address */
5751 rtl_rar_set(tp
, dev
->perm_addr
);
5753 spin_lock_irq(&tp
->lock
);
5755 rtl8169_hw_reset(tp
);
5757 spin_unlock_irq(&tp
->lock
);
5759 if (system_state
== SYSTEM_POWER_OFF
) {
5760 /* WoL fails with 8168b when the receiver is disabled. */
5761 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
5762 tp
->mac_version
== RTL_GIGA_MAC_VER_12
||
5763 tp
->mac_version
== RTL_GIGA_MAC_VER_17
) &&
5764 (tp
->features
& RTL_FEATURE_WOL
)) {
5765 pci_clear_master(pdev
);
5767 RTL_W8(ChipCmd
, CmdRxEnb
);
5772 pci_wake_from_d3(pdev
, true);
5773 pci_set_power_state(pdev
, PCI_D3hot
);
5777 static struct pci_driver rtl8169_pci_driver
= {
5779 .id_table
= rtl8169_pci_tbl
,
5780 .probe
= rtl8169_init_one
,
5781 .remove
= __devexit_p(rtl8169_remove_one
),
5782 .shutdown
= rtl_shutdown
,
5783 .driver
.pm
= RTL8169_PM_OPS
,
5786 static int __init
rtl8169_init_module(void)
5788 return pci_register_driver(&rtl8169_pci_driver
);
5791 static void __exit
rtl8169_cleanup_module(void)
5793 pci_unregister_driver(&rtl8169_pci_driver
);
5796 module_init(rtl8169_init_module
);
5797 module_exit(rtl8169_cleanup_module
);