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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / s2io.c
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/stddef.h>
70 #include <linux/ioctl.h>
71 #include <linux/timex.h>
72 #include <linux/ethtool.h>
73 #include <linux/workqueue.h>
74 #include <linux/if_vlan.h>
75 #include <linux/ip.h>
76 #include <linux/tcp.h>
77 #include <net/tcp.h>
78
79 #include <asm/system.h>
80 #include <asm/uaccess.h>
81 #include <asm/io.h>
82 #include <asm/div64.h>
83 #include <asm/irq.h>
84
85 /* local include */
86 #include "s2io.h"
87 #include "s2io-regs.h"
88
89 #define DRV_VERSION "2.0.26.25"
90
91 /* S2io Driver name & version. */
92 static char s2io_driver_name[] = "Neterion";
93 static char s2io_driver_version[] = DRV_VERSION;
94
95 static int rxd_size[2] = {32,48};
96 static int rxd_count[2] = {127,85};
97
98 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
99 {
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106 }
107
108 /*
109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
117
118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
120
121 static inline int is_s2io_card_up(const struct s2io_nic * sp)
122 {
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133 };
134
135 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
207 {"rmac_pause_cnt"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
229 {"rxf_wr_cnt"}
230 };
231
232 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
240 {"rmac_vlan_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
243 {"rmac_pf_discard"},
244 {"rmac_da_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
248 {"link_fault_cnt"}
249 };
250
251 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
255 {"parity_err_cnt"},
256 {"serious_err_cnt"},
257 {"soft_reset_cnt"},
258 {"fifo_full_cnt"},
259 {"ring_0_full_cnt"},
260 {"ring_1_full_cnt"},
261 {"ring_2_full_cnt"},
262 {"ring_3_full_cnt"},
263 {"ring_4_full_cnt"},
264 {"ring_5_full_cnt"},
265 {"ring_6_full_cnt"},
266 {"ring_7_full_cnt"},
267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
287 {"mem_allocated"},
288 {"mem_freed"},
289 {"link_up_cnt"},
290 {"link_down_cnt"},
291 {"link_up_time"},
292 {"link_down_time"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
307 {"tda_err_cnt"},
308 {"pfc_err_cnt"},
309 {"pcc_err_cnt"},
310 {"tti_err_cnt"},
311 {"tpa_err_cnt"},
312 {"sm_err_cnt"},
313 {"lso_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
318 {"rc_err_cnt"},
319 {"prc_pcix_err_cnt"},
320 {"rpa_err_cnt"},
321 {"rda_err_cnt"},
322 {"rti_err_cnt"},
323 {"mc_err_cnt"}
324 };
325
326 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
329
330 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
332
333 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
335
336 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
337 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
338
339 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
344
345 /* copy mac addr to def_mac_addr array */
346 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
347 {
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
354 }
355
356 /* Add the vlan */
357 static void s2io_vlan_rx_register(struct net_device *dev,
358 struct vlan_group *grp)
359 {
360 int i;
361 struct s2io_nic *nic = netdev_priv(dev);
362 unsigned long flags[MAX_TX_FIFOS];
363 struct mac_info *mac_control = &nic->mac_control;
364 struct config_param *config = &nic->config;
365
366 for (i = 0; i < config->tx_fifo_num; i++)
367 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
368
369 nic->vlgrp = grp;
370 for (i = config->tx_fifo_num - 1; i >= 0; i--)
371 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
372 flags[i]);
373 }
374
375 /* Unregister the vlan */
376 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
377 {
378 int i;
379 struct s2io_nic *nic = netdev_priv(dev);
380 unsigned long flags[MAX_TX_FIFOS];
381 struct mac_info *mac_control = &nic->mac_control;
382 struct config_param *config = &nic->config;
383
384 for (i = 0; i < config->tx_fifo_num; i++)
385 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
386
387 if (nic->vlgrp)
388 vlan_group_set_device(nic->vlgrp, vid, NULL);
389
390 for (i = config->tx_fifo_num - 1; i >= 0; i--)
391 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
392 flags[i]);
393 }
394
395 /*
396 * Constants to be programmed into the Xena's registers, to configure
397 * the XAUI.
398 */
399
400 #define END_SIGN 0x0
401 static const u64 herc_act_dtx_cfg[] = {
402 /* Set address */
403 0x8000051536750000ULL, 0x80000515367500E0ULL,
404 /* Write data */
405 0x8000051536750004ULL, 0x80000515367500E4ULL,
406 /* Set address */
407 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
408 /* Write data */
409 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
410 /* Set address */
411 0x801205150D440000ULL, 0x801205150D4400E0ULL,
412 /* Write data */
413 0x801205150D440004ULL, 0x801205150D4400E4ULL,
414 /* Set address */
415 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
416 /* Write data */
417 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
418 /* Done */
419 END_SIGN
420 };
421
422 static const u64 xena_dtx_cfg[] = {
423 /* Set address */
424 0x8000051500000000ULL, 0x80000515000000E0ULL,
425 /* Write data */
426 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
427 /* Set address */
428 0x8001051500000000ULL, 0x80010515000000E0ULL,
429 /* Write data */
430 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
431 /* Set address */
432 0x8002051500000000ULL, 0x80020515000000E0ULL,
433 /* Write data */
434 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
435 END_SIGN
436 };
437
438 /*
439 * Constants for Fixing the MacAddress problem seen mostly on
440 * Alpha machines.
441 */
442 static const u64 fix_mac[] = {
443 0x0060000000000000ULL, 0x0060600000000000ULL,
444 0x0040600000000000ULL, 0x0000600000000000ULL,
445 0x0020600000000000ULL, 0x0060600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0000600000000000ULL,
456 0x0040600000000000ULL, 0x0060600000000000ULL,
457 END_SIGN
458 };
459
460 MODULE_LICENSE("GPL");
461 MODULE_VERSION(DRV_VERSION);
462
463
464 /* Module Loadable parameters. */
465 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
466 S2IO_PARM_INT(rx_ring_num, 1);
467 S2IO_PARM_INT(multiq, 0);
468 S2IO_PARM_INT(rx_ring_mode, 1);
469 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
470 S2IO_PARM_INT(rmac_pause_time, 0x100);
471 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
472 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
473 S2IO_PARM_INT(shared_splits, 0);
474 S2IO_PARM_INT(tmac_util_period, 5);
475 S2IO_PARM_INT(rmac_util_period, 5);
476 S2IO_PARM_INT(l3l4hdr_size, 128);
477 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
478 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
479 /* Frequency of Rx desc syncs expressed as power of 2 */
480 S2IO_PARM_INT(rxsync_frequency, 3);
481 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
482 S2IO_PARM_INT(intr_type, 2);
483 /* Large receive offload feature */
484 static unsigned int lro_enable;
485 module_param_named(lro, lro_enable, uint, 0);
486
487 /* Max pkts to be aggregated by LRO at one time. If not specified,
488 * aggregation happens until we hit max IP pkt size(64K)
489 */
490 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
491 S2IO_PARM_INT(indicate_max_pkts, 0);
492
493 S2IO_PARM_INT(napi, 1);
494 S2IO_PARM_INT(ufo, 0);
495 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
496
497 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
498 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
499 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
500 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
501 static unsigned int rts_frm_len[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
503
504 module_param_array(tx_fifo_len, uint, NULL, 0);
505 module_param_array(rx_ring_sz, uint, NULL, 0);
506 module_param_array(rts_frm_len, uint, NULL, 0);
507
508 /*
509 * S2IO device table.
510 * This table lists all the devices that this driver supports.
511 */
512 static struct pci_device_id s2io_tbl[] __devinitdata = {
513 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
514 PCI_ANY_ID, PCI_ANY_ID},
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
520 PCI_ANY_ID, PCI_ANY_ID},
521 {0,}
522 };
523
524 MODULE_DEVICE_TABLE(pci, s2io_tbl);
525
526 static struct pci_error_handlers s2io_err_handler = {
527 .error_detected = s2io_io_error_detected,
528 .slot_reset = s2io_io_slot_reset,
529 .resume = s2io_io_resume,
530 };
531
532 static struct pci_driver s2io_driver = {
533 .name = "S2IO",
534 .id_table = s2io_tbl,
535 .probe = s2io_init_nic,
536 .remove = __devexit_p(s2io_rem_nic),
537 .err_handler = &s2io_err_handler,
538 };
539
540 /* A simplifier macro used both by init and free shared_mem Fns(). */
541 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
542
543 /* netqueue manipulation helper functions */
544 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
545 {
546 if (!sp->config.multiq) {
547 int i;
548
549 for (i = 0; i < sp->config.tx_fifo_num; i++)
550 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
551 }
552 netif_tx_stop_all_queues(sp->dev);
553 }
554
555 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
556 {
557 if (!sp->config.multiq)
558 sp->mac_control.fifos[fifo_no].queue_state =
559 FIFO_QUEUE_STOP;
560
561 netif_tx_stop_all_queues(sp->dev);
562 }
563
564 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
565 {
566 if (!sp->config.multiq) {
567 int i;
568
569 for (i = 0; i < sp->config.tx_fifo_num; i++)
570 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
571 }
572 netif_tx_start_all_queues(sp->dev);
573 }
574
575 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
576 {
577 if (!sp->config.multiq)
578 sp->mac_control.fifos[fifo_no].queue_state =
579 FIFO_QUEUE_START;
580
581 netif_tx_start_all_queues(sp->dev);
582 }
583
584 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
585 {
586 if (!sp->config.multiq) {
587 int i;
588
589 for (i = 0; i < sp->config.tx_fifo_num; i++)
590 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
591 }
592 netif_tx_wake_all_queues(sp->dev);
593 }
594
595 static inline void s2io_wake_tx_queue(
596 struct fifo_info *fifo, int cnt, u8 multiq)
597 {
598
599 if (multiq) {
600 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
601 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
602 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
603 if (netif_queue_stopped(fifo->dev)) {
604 fifo->queue_state = FIFO_QUEUE_START;
605 netif_wake_queue(fifo->dev);
606 }
607 }
608 }
609
610 /**
611 * init_shared_mem - Allocation and Initialization of Memory
612 * @nic: Device private variable.
613 * Description: The function allocates all the memory areas shared
614 * between the NIC and the driver. This includes Tx descriptors,
615 * Rx descriptors and the statistics block.
616 */
617
618 static int init_shared_mem(struct s2io_nic *nic)
619 {
620 u32 size;
621 void *tmp_v_addr, *tmp_v_addr_next;
622 dma_addr_t tmp_p_addr, tmp_p_addr_next;
623 struct RxD_block *pre_rxd_blk = NULL;
624 int i, j, blk_cnt;
625 int lst_size, lst_per_page;
626 struct net_device *dev = nic->dev;
627 unsigned long tmp;
628 struct buffAdd *ba;
629
630 struct mac_info *mac_control;
631 struct config_param *config;
632 unsigned long long mem_allocated = 0;
633
634 mac_control = &nic->mac_control;
635 config = &nic->config;
636
637
638 /* Allocation and initialization of TXDLs in FIOFs */
639 size = 0;
640 for (i = 0; i < config->tx_fifo_num; i++) {
641 size += config->tx_cfg[i].fifo_len;
642 }
643 if (size > MAX_AVAILABLE_TXDS) {
644 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
645 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
646 return -EINVAL;
647 }
648
649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
651 size = config->tx_cfg[i].fifo_len;
652 /*
653 * Legal values are from 2 to 8192
654 */
655 if (size < 2) {
656 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
657 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
658 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
659 "are 2 to 8192\n");
660 return -EINVAL;
661 }
662 }
663
664 lst_size = (sizeof(struct TxD) * config->max_txds);
665 lst_per_page = PAGE_SIZE / lst_size;
666
667 for (i = 0; i < config->tx_fifo_num; i++) {
668 int fifo_len = config->tx_cfg[i].fifo_len;
669 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
670 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
671 GFP_KERNEL);
672 if (!mac_control->fifos[i].list_info) {
673 DBG_PRINT(INFO_DBG,
674 "Malloc failed for list_info\n");
675 return -ENOMEM;
676 }
677 mem_allocated += list_holder_size;
678 }
679 for (i = 0; i < config->tx_fifo_num; i++) {
680 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
681 lst_per_page);
682 mac_control->fifos[i].tx_curr_put_info.offset = 0;
683 mac_control->fifos[i].tx_curr_put_info.fifo_len =
684 config->tx_cfg[i].fifo_len - 1;
685 mac_control->fifos[i].tx_curr_get_info.offset = 0;
686 mac_control->fifos[i].tx_curr_get_info.fifo_len =
687 config->tx_cfg[i].fifo_len - 1;
688 mac_control->fifos[i].fifo_no = i;
689 mac_control->fifos[i].nic = nic;
690 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
691 mac_control->fifos[i].dev = dev;
692
693 for (j = 0; j < page_num; j++) {
694 int k = 0;
695 dma_addr_t tmp_p;
696 void *tmp_v;
697 tmp_v = pci_alloc_consistent(nic->pdev,
698 PAGE_SIZE, &tmp_p);
699 if (!tmp_v) {
700 DBG_PRINT(INFO_DBG,
701 "pci_alloc_consistent ");
702 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
703 return -ENOMEM;
704 }
705 /* If we got a zero DMA address(can happen on
706 * certain platforms like PPC), reallocate.
707 * Store virtual address of page we don't want,
708 * to be freed later.
709 */
710 if (!tmp_p) {
711 mac_control->zerodma_virt_addr = tmp_v;
712 DBG_PRINT(INIT_DBG,
713 "%s: Zero DMA address for TxDL. ", dev->name);
714 DBG_PRINT(INIT_DBG,
715 "Virtual address %p\n", tmp_v);
716 tmp_v = pci_alloc_consistent(nic->pdev,
717 PAGE_SIZE, &tmp_p);
718 if (!tmp_v) {
719 DBG_PRINT(INFO_DBG,
720 "pci_alloc_consistent ");
721 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
722 return -ENOMEM;
723 }
724 mem_allocated += PAGE_SIZE;
725 }
726 while (k < lst_per_page) {
727 int l = (j * lst_per_page) + k;
728 if (l == config->tx_cfg[i].fifo_len)
729 break;
730 mac_control->fifos[i].list_info[l].list_virt_addr =
731 tmp_v + (k * lst_size);
732 mac_control->fifos[i].list_info[l].list_phy_addr =
733 tmp_p + (k * lst_size);
734 k++;
735 }
736 }
737 }
738
739 for (i = 0; i < config->tx_fifo_num; i++) {
740 size = config->tx_cfg[i].fifo_len;
741 mac_control->fifos[i].ufo_in_band_v
742 = kcalloc(size, sizeof(u64), GFP_KERNEL);
743 if (!mac_control->fifos[i].ufo_in_band_v)
744 return -ENOMEM;
745 mem_allocated += (size * sizeof(u64));
746 }
747
748 /* Allocation and initialization of RXDs in Rings */
749 size = 0;
750 for (i = 0; i < config->rx_ring_num; i++) {
751 if (config->rx_cfg[i].num_rxd %
752 (rxd_count[nic->rxd_mode] + 1)) {
753 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
754 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
755 i);
756 DBG_PRINT(ERR_DBG, "RxDs per Block");
757 return FAILURE;
758 }
759 size += config->rx_cfg[i].num_rxd;
760 mac_control->rings[i].block_count =
761 config->rx_cfg[i].num_rxd /
762 (rxd_count[nic->rxd_mode] + 1 );
763 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
764 mac_control->rings[i].block_count;
765 }
766 if (nic->rxd_mode == RXD_MODE_1)
767 size = (size * (sizeof(struct RxD1)));
768 else
769 size = (size * (sizeof(struct RxD3)));
770
771 for (i = 0; i < config->rx_ring_num; i++) {
772 mac_control->rings[i].rx_curr_get_info.block_index = 0;
773 mac_control->rings[i].rx_curr_get_info.offset = 0;
774 mac_control->rings[i].rx_curr_get_info.ring_len =
775 config->rx_cfg[i].num_rxd - 1;
776 mac_control->rings[i].rx_curr_put_info.block_index = 0;
777 mac_control->rings[i].rx_curr_put_info.offset = 0;
778 mac_control->rings[i].rx_curr_put_info.ring_len =
779 config->rx_cfg[i].num_rxd - 1;
780 mac_control->rings[i].nic = nic;
781 mac_control->rings[i].ring_no = i;
782 mac_control->rings[i].lro = lro_enable;
783
784 blk_cnt = config->rx_cfg[i].num_rxd /
785 (rxd_count[nic->rxd_mode] + 1);
786 /* Allocating all the Rx blocks */
787 for (j = 0; j < blk_cnt; j++) {
788 struct rx_block_info *rx_blocks;
789 int l;
790
791 rx_blocks = &mac_control->rings[i].rx_blocks[j];
792 size = SIZE_OF_BLOCK; //size is always page size
793 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
794 &tmp_p_addr);
795 if (tmp_v_addr == NULL) {
796 /*
797 * In case of failure, free_shared_mem()
798 * is called, which should free any
799 * memory that was alloced till the
800 * failure happened.
801 */
802 rx_blocks->block_virt_addr = tmp_v_addr;
803 return -ENOMEM;
804 }
805 mem_allocated += size;
806 memset(tmp_v_addr, 0, size);
807 rx_blocks->block_virt_addr = tmp_v_addr;
808 rx_blocks->block_dma_addr = tmp_p_addr;
809 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
810 rxd_count[nic->rxd_mode],
811 GFP_KERNEL);
812 if (!rx_blocks->rxds)
813 return -ENOMEM;
814 mem_allocated +=
815 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
816 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
817 rx_blocks->rxds[l].virt_addr =
818 rx_blocks->block_virt_addr +
819 (rxd_size[nic->rxd_mode] * l);
820 rx_blocks->rxds[l].dma_addr =
821 rx_blocks->block_dma_addr +
822 (rxd_size[nic->rxd_mode] * l);
823 }
824 }
825 /* Interlinking all Rx Blocks */
826 for (j = 0; j < blk_cnt; j++) {
827 tmp_v_addr =
828 mac_control->rings[i].rx_blocks[j].block_virt_addr;
829 tmp_v_addr_next =
830 mac_control->rings[i].rx_blocks[(j + 1) %
831 blk_cnt].block_virt_addr;
832 tmp_p_addr =
833 mac_control->rings[i].rx_blocks[j].block_dma_addr;
834 tmp_p_addr_next =
835 mac_control->rings[i].rx_blocks[(j + 1) %
836 blk_cnt].block_dma_addr;
837
838 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
839 pre_rxd_blk->reserved_2_pNext_RxD_block =
840 (unsigned long) tmp_v_addr_next;
841 pre_rxd_blk->pNext_RxD_Blk_physical =
842 (u64) tmp_p_addr_next;
843 }
844 }
845 if (nic->rxd_mode == RXD_MODE_3B) {
846 /*
847 * Allocation of Storages for buffer addresses in 2BUFF mode
848 * and the buffers as well.
849 */
850 for (i = 0; i < config->rx_ring_num; i++) {
851 blk_cnt = config->rx_cfg[i].num_rxd /
852 (rxd_count[nic->rxd_mode]+ 1);
853 mac_control->rings[i].ba =
854 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
855 GFP_KERNEL);
856 if (!mac_control->rings[i].ba)
857 return -ENOMEM;
858 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
859 for (j = 0; j < blk_cnt; j++) {
860 int k = 0;
861 mac_control->rings[i].ba[j] =
862 kmalloc((sizeof(struct buffAdd) *
863 (rxd_count[nic->rxd_mode] + 1)),
864 GFP_KERNEL);
865 if (!mac_control->rings[i].ba[j])
866 return -ENOMEM;
867 mem_allocated += (sizeof(struct buffAdd) * \
868 (rxd_count[nic->rxd_mode] + 1));
869 while (k != rxd_count[nic->rxd_mode]) {
870 ba = &mac_control->rings[i].ba[j][k];
871
872 ba->ba_0_org = (void *) kmalloc
873 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
874 if (!ba->ba_0_org)
875 return -ENOMEM;
876 mem_allocated +=
877 (BUF0_LEN + ALIGN_SIZE);
878 tmp = (unsigned long)ba->ba_0_org;
879 tmp += ALIGN_SIZE;
880 tmp &= ~((unsigned long) ALIGN_SIZE);
881 ba->ba_0 = (void *) tmp;
882
883 ba->ba_1_org = (void *) kmalloc
884 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
885 if (!ba->ba_1_org)
886 return -ENOMEM;
887 mem_allocated
888 += (BUF1_LEN + ALIGN_SIZE);
889 tmp = (unsigned long) ba->ba_1_org;
890 tmp += ALIGN_SIZE;
891 tmp &= ~((unsigned long) ALIGN_SIZE);
892 ba->ba_1 = (void *) tmp;
893 k++;
894 }
895 }
896 }
897 }
898
899 /* Allocation and initialization of Statistics block */
900 size = sizeof(struct stat_block);
901 mac_control->stats_mem = pci_alloc_consistent
902 (nic->pdev, size, &mac_control->stats_mem_phy);
903
904 if (!mac_control->stats_mem) {
905 /*
906 * In case of failure, free_shared_mem() is called, which
907 * should free any memory that was alloced till the
908 * failure happened.
909 */
910 return -ENOMEM;
911 }
912 mem_allocated += size;
913 mac_control->stats_mem_sz = size;
914
915 tmp_v_addr = mac_control->stats_mem;
916 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
917 memset(tmp_v_addr, 0, size);
918 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
919 (unsigned long long) tmp_p_addr);
920 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
921 return SUCCESS;
922 }
923
924 /**
925 * free_shared_mem - Free the allocated Memory
926 * @nic: Device private variable.
927 * Description: This function is to free all memory locations allocated by
928 * the init_shared_mem() function and return it to the kernel.
929 */
930
931 static void free_shared_mem(struct s2io_nic *nic)
932 {
933 int i, j, blk_cnt, size;
934 void *tmp_v_addr;
935 dma_addr_t tmp_p_addr;
936 struct mac_info *mac_control;
937 struct config_param *config;
938 int lst_size, lst_per_page;
939 struct net_device *dev;
940 int page_num = 0;
941
942 if (!nic)
943 return;
944
945 dev = nic->dev;
946
947 mac_control = &nic->mac_control;
948 config = &nic->config;
949
950 lst_size = (sizeof(struct TxD) * config->max_txds);
951 lst_per_page = PAGE_SIZE / lst_size;
952
953 for (i = 0; i < config->tx_fifo_num; i++) {
954 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
955 lst_per_page);
956 for (j = 0; j < page_num; j++) {
957 int mem_blks = (j * lst_per_page);
958 if (!mac_control->fifos[i].list_info)
959 return;
960 if (!mac_control->fifos[i].list_info[mem_blks].
961 list_virt_addr)
962 break;
963 pci_free_consistent(nic->pdev, PAGE_SIZE,
964 mac_control->fifos[i].
965 list_info[mem_blks].
966 list_virt_addr,
967 mac_control->fifos[i].
968 list_info[mem_blks].
969 list_phy_addr);
970 nic->mac_control.stats_info->sw_stat.mem_freed
971 += PAGE_SIZE;
972 }
973 /* If we got a zero DMA address during allocation,
974 * free the page now
975 */
976 if (mac_control->zerodma_virt_addr) {
977 pci_free_consistent(nic->pdev, PAGE_SIZE,
978 mac_control->zerodma_virt_addr,
979 (dma_addr_t)0);
980 DBG_PRINT(INIT_DBG,
981 "%s: Freeing TxDL with zero DMA addr. ",
982 dev->name);
983 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
984 mac_control->zerodma_virt_addr);
985 nic->mac_control.stats_info->sw_stat.mem_freed
986 += PAGE_SIZE;
987 }
988 kfree(mac_control->fifos[i].list_info);
989 nic->mac_control.stats_info->sw_stat.mem_freed +=
990 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
991 }
992
993 size = SIZE_OF_BLOCK;
994 for (i = 0; i < config->rx_ring_num; i++) {
995 blk_cnt = mac_control->rings[i].block_count;
996 for (j = 0; j < blk_cnt; j++) {
997 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
998 block_virt_addr;
999 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1000 block_dma_addr;
1001 if (tmp_v_addr == NULL)
1002 break;
1003 pci_free_consistent(nic->pdev, size,
1004 tmp_v_addr, tmp_p_addr);
1005 nic->mac_control.stats_info->sw_stat.mem_freed += size;
1006 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1007 nic->mac_control.stats_info->sw_stat.mem_freed +=
1008 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1009 }
1010 }
1011
1012 if (nic->rxd_mode == RXD_MODE_3B) {
1013 /* Freeing buffer storage addresses in 2BUFF mode. */
1014 for (i = 0; i < config->rx_ring_num; i++) {
1015 blk_cnt = config->rx_cfg[i].num_rxd /
1016 (rxd_count[nic->rxd_mode] + 1);
1017 for (j = 0; j < blk_cnt; j++) {
1018 int k = 0;
1019 if (!mac_control->rings[i].ba[j])
1020 continue;
1021 while (k != rxd_count[nic->rxd_mode]) {
1022 struct buffAdd *ba =
1023 &mac_control->rings[i].ba[j][k];
1024 kfree(ba->ba_0_org);
1025 nic->mac_control.stats_info->sw_stat.\
1026 mem_freed += (BUF0_LEN + ALIGN_SIZE);
1027 kfree(ba->ba_1_org);
1028 nic->mac_control.stats_info->sw_stat.\
1029 mem_freed += (BUF1_LEN + ALIGN_SIZE);
1030 k++;
1031 }
1032 kfree(mac_control->rings[i].ba[j]);
1033 nic->mac_control.stats_info->sw_stat.mem_freed +=
1034 (sizeof(struct buffAdd) *
1035 (rxd_count[nic->rxd_mode] + 1));
1036 }
1037 kfree(mac_control->rings[i].ba);
1038 nic->mac_control.stats_info->sw_stat.mem_freed +=
1039 (sizeof(struct buffAdd *) * blk_cnt);
1040 }
1041 }
1042
1043 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1044 if (mac_control->fifos[i].ufo_in_band_v) {
1045 nic->mac_control.stats_info->sw_stat.mem_freed
1046 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1047 kfree(mac_control->fifos[i].ufo_in_band_v);
1048 }
1049 }
1050
1051 if (mac_control->stats_mem) {
1052 nic->mac_control.stats_info->sw_stat.mem_freed +=
1053 mac_control->stats_mem_sz;
1054 pci_free_consistent(nic->pdev,
1055 mac_control->stats_mem_sz,
1056 mac_control->stats_mem,
1057 mac_control->stats_mem_phy);
1058 }
1059 }
1060
1061 /**
1062 * s2io_verify_pci_mode -
1063 */
1064
1065 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1066 {
1067 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1068 register u64 val64 = 0;
1069 int mode;
1070
1071 val64 = readq(&bar0->pci_mode);
1072 mode = (u8)GET_PCI_MODE(val64);
1073
1074 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1075 return -1; /* Unknown PCI mode */
1076 return mode;
1077 }
1078
1079 #define NEC_VENID 0x1033
1080 #define NEC_DEVID 0x0125
1081 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1082 {
1083 struct pci_dev *tdev = NULL;
1084 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1085 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1086 if (tdev->bus == s2io_pdev->bus->parent) {
1087 pci_dev_put(tdev);
1088 return 1;
1089 }
1090 }
1091 }
1092 return 0;
1093 }
1094
1095 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1096 /**
1097 * s2io_print_pci_mode -
1098 */
1099 static int s2io_print_pci_mode(struct s2io_nic *nic)
1100 {
1101 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1102 register u64 val64 = 0;
1103 int mode;
1104 struct config_param *config = &nic->config;
1105
1106 val64 = readq(&bar0->pci_mode);
1107 mode = (u8)GET_PCI_MODE(val64);
1108
1109 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1110 return -1; /* Unknown PCI mode */
1111
1112 config->bus_speed = bus_speed[mode];
1113
1114 if (s2io_on_nec_bridge(nic->pdev)) {
1115 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1116 nic->dev->name);
1117 return mode;
1118 }
1119
1120 if (val64 & PCI_MODE_32_BITS) {
1121 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1122 } else {
1123 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1124 }
1125
1126 switch(mode) {
1127 case PCI_MODE_PCI_33:
1128 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1129 break;
1130 case PCI_MODE_PCI_66:
1131 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1132 break;
1133 case PCI_MODE_PCIX_M1_66:
1134 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1135 break;
1136 case PCI_MODE_PCIX_M1_100:
1137 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1138 break;
1139 case PCI_MODE_PCIX_M1_133:
1140 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1141 break;
1142 case PCI_MODE_PCIX_M2_66:
1143 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1144 break;
1145 case PCI_MODE_PCIX_M2_100:
1146 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1147 break;
1148 case PCI_MODE_PCIX_M2_133:
1149 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1150 break;
1151 default:
1152 return -1; /* Unsupported bus speed */
1153 }
1154
1155 return mode;
1156 }
1157
1158 /**
1159 * init_tti - Initialization transmit traffic interrupt scheme
1160 * @nic: device private variable
1161 * @link: link status (UP/DOWN) used to enable/disable continuous
1162 * transmit interrupts
1163 * Description: The function configures transmit traffic interrupts
1164 * Return Value: SUCCESS on success and
1165 * '-1' on failure
1166 */
1167
1168 static int init_tti(struct s2io_nic *nic, int link)
1169 {
1170 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1171 register u64 val64 = 0;
1172 int i;
1173 struct config_param *config;
1174
1175 config = &nic->config;
1176
1177 for (i = 0; i < config->tx_fifo_num; i++) {
1178 /*
1179 * TTI Initialization. Default Tx timer gets us about
1180 * 250 interrupts per sec. Continuous interrupts are enabled
1181 * by default.
1182 */
1183 if (nic->device_type == XFRAME_II_DEVICE) {
1184 int count = (nic->config.bus_speed * 125)/2;
1185 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1186 } else
1187 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1188
1189 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1190 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1191 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1192 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1193 if (i == 0)
1194 if (use_continuous_tx_intrs && (link == LINK_UP))
1195 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1196 writeq(val64, &bar0->tti_data1_mem);
1197
1198 if (nic->config.intr_type == MSI_X) {
1199 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1200 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1201 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1202 TTI_DATA2_MEM_TX_UFC_D(0x300);
1203 } else {
1204 if ((nic->config.tx_steering_type ==
1205 TX_DEFAULT_STEERING) &&
1206 (config->tx_fifo_num > 1) &&
1207 (i >= nic->udp_fifo_idx) &&
1208 (i < (nic->udp_fifo_idx +
1209 nic->total_udp_fifos)))
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x120);
1214 else
1215 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1216 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1217 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1218 TTI_DATA2_MEM_TX_UFC_D(0x80);
1219 }
1220
1221 writeq(val64, &bar0->tti_data2_mem);
1222
1223 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1224 TTI_CMD_MEM_OFFSET(i);
1225 writeq(val64, &bar0->tti_command_mem);
1226
1227 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1228 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1229 return FAILURE;
1230 }
1231
1232 return SUCCESS;
1233 }
1234
1235 /**
1236 * init_nic - Initialization of hardware
1237 * @nic: device private variable
1238 * Description: The function sequentially configures every block
1239 * of the H/W from their reset values.
1240 * Return Value: SUCCESS on success and
1241 * '-1' on failure (endian settings incorrect).
1242 */
1243
1244 static int init_nic(struct s2io_nic *nic)
1245 {
1246 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1247 struct net_device *dev = nic->dev;
1248 register u64 val64 = 0;
1249 void __iomem *add;
1250 u32 time;
1251 int i, j;
1252 struct mac_info *mac_control;
1253 struct config_param *config;
1254 int dtx_cnt = 0;
1255 unsigned long long mem_share;
1256 int mem_size;
1257
1258 mac_control = &nic->mac_control;
1259 config = &nic->config;
1260
1261 /* to set the swapper controle on the card */
1262 if(s2io_set_swapper(nic)) {
1263 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1264 return -EIO;
1265 }
1266
1267 /*
1268 * Herc requires EOI to be removed from reset before XGXS, so..
1269 */
1270 if (nic->device_type & XFRAME_II_DEVICE) {
1271 val64 = 0xA500000000ULL;
1272 writeq(val64, &bar0->sw_reset);
1273 msleep(500);
1274 val64 = readq(&bar0->sw_reset);
1275 }
1276
1277 /* Remove XGXS from reset state */
1278 val64 = 0;
1279 writeq(val64, &bar0->sw_reset);
1280 msleep(500);
1281 val64 = readq(&bar0->sw_reset);
1282
1283 /* Ensure that it's safe to access registers by checking
1284 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1285 */
1286 if (nic->device_type == XFRAME_II_DEVICE) {
1287 for (i = 0; i < 50; i++) {
1288 val64 = readq(&bar0->adapter_status);
1289 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1290 break;
1291 msleep(10);
1292 }
1293 if (i == 50)
1294 return -ENODEV;
1295 }
1296
1297 /* Enable Receiving broadcasts */
1298 add = &bar0->mac_cfg;
1299 val64 = readq(&bar0->mac_cfg);
1300 val64 |= MAC_RMAC_BCAST_ENABLE;
1301 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1302 writel((u32) val64, add);
1303 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1304 writel((u32) (val64 >> 32), (add + 4));
1305
1306 /* Read registers in all blocks */
1307 val64 = readq(&bar0->mac_int_mask);
1308 val64 = readq(&bar0->mc_int_mask);
1309 val64 = readq(&bar0->xgxs_int_mask);
1310
1311 /* Set MTU */
1312 val64 = dev->mtu;
1313 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1314
1315 if (nic->device_type & XFRAME_II_DEVICE) {
1316 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1317 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1318 &bar0->dtx_control, UF);
1319 if (dtx_cnt & 0x1)
1320 msleep(1); /* Necessary!! */
1321 dtx_cnt++;
1322 }
1323 } else {
1324 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1325 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1326 &bar0->dtx_control, UF);
1327 val64 = readq(&bar0->dtx_control);
1328 dtx_cnt++;
1329 }
1330 }
1331
1332 /* Tx DMA Initialization */
1333 val64 = 0;
1334 writeq(val64, &bar0->tx_fifo_partition_0);
1335 writeq(val64, &bar0->tx_fifo_partition_1);
1336 writeq(val64, &bar0->tx_fifo_partition_2);
1337 writeq(val64, &bar0->tx_fifo_partition_3);
1338
1339
1340 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1341 val64 |=
1342 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1343 13) | vBIT(config->tx_cfg[i].fifo_priority,
1344 ((j * 32) + 5), 3);
1345
1346 if (i == (config->tx_fifo_num - 1)) {
1347 if (i % 2 == 0)
1348 i++;
1349 }
1350
1351 switch (i) {
1352 case 1:
1353 writeq(val64, &bar0->tx_fifo_partition_0);
1354 val64 = 0;
1355 j = 0;
1356 break;
1357 case 3:
1358 writeq(val64, &bar0->tx_fifo_partition_1);
1359 val64 = 0;
1360 j = 0;
1361 break;
1362 case 5:
1363 writeq(val64, &bar0->tx_fifo_partition_2);
1364 val64 = 0;
1365 j = 0;
1366 break;
1367 case 7:
1368 writeq(val64, &bar0->tx_fifo_partition_3);
1369 val64 = 0;
1370 j = 0;
1371 break;
1372 default:
1373 j++;
1374 break;
1375 }
1376 }
1377
1378 /*
1379 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1380 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1381 */
1382 if ((nic->device_type == XFRAME_I_DEVICE) &&
1383 (nic->pdev->revision < 4))
1384 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1385
1386 val64 = readq(&bar0->tx_fifo_partition_0);
1387 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1388 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1389
1390 /*
1391 * Initialization of Tx_PA_CONFIG register to ignore packet
1392 * integrity checking.
1393 */
1394 val64 = readq(&bar0->tx_pa_cfg);
1395 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1396 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1397 writeq(val64, &bar0->tx_pa_cfg);
1398
1399 /* Rx DMA intialization. */
1400 val64 = 0;
1401 for (i = 0; i < config->rx_ring_num; i++) {
1402 val64 |=
1403 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1404 3);
1405 }
1406 writeq(val64, &bar0->rx_queue_priority);
1407
1408 /*
1409 * Allocating equal share of memory to all the
1410 * configured Rings.
1411 */
1412 val64 = 0;
1413 if (nic->device_type & XFRAME_II_DEVICE)
1414 mem_size = 32;
1415 else
1416 mem_size = 64;
1417
1418 for (i = 0; i < config->rx_ring_num; i++) {
1419 switch (i) {
1420 case 0:
1421 mem_share = (mem_size / config->rx_ring_num +
1422 mem_size % config->rx_ring_num);
1423 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1424 continue;
1425 case 1:
1426 mem_share = (mem_size / config->rx_ring_num);
1427 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1428 continue;
1429 case 2:
1430 mem_share = (mem_size / config->rx_ring_num);
1431 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1432 continue;
1433 case 3:
1434 mem_share = (mem_size / config->rx_ring_num);
1435 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1436 continue;
1437 case 4:
1438 mem_share = (mem_size / config->rx_ring_num);
1439 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1440 continue;
1441 case 5:
1442 mem_share = (mem_size / config->rx_ring_num);
1443 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1444 continue;
1445 case 6:
1446 mem_share = (mem_size / config->rx_ring_num);
1447 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1448 continue;
1449 case 7:
1450 mem_share = (mem_size / config->rx_ring_num);
1451 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1452 continue;
1453 }
1454 }
1455 writeq(val64, &bar0->rx_queue_cfg);
1456
1457 /*
1458 * Filling Tx round robin registers
1459 * as per the number of FIFOs for equal scheduling priority
1460 */
1461 switch (config->tx_fifo_num) {
1462 case 1:
1463 val64 = 0x0;
1464 writeq(val64, &bar0->tx_w_round_robin_0);
1465 writeq(val64, &bar0->tx_w_round_robin_1);
1466 writeq(val64, &bar0->tx_w_round_robin_2);
1467 writeq(val64, &bar0->tx_w_round_robin_3);
1468 writeq(val64, &bar0->tx_w_round_robin_4);
1469 break;
1470 case 2:
1471 val64 = 0x0001000100010001ULL;
1472 writeq(val64, &bar0->tx_w_round_robin_0);
1473 writeq(val64, &bar0->tx_w_round_robin_1);
1474 writeq(val64, &bar0->tx_w_round_robin_2);
1475 writeq(val64, &bar0->tx_w_round_robin_3);
1476 val64 = 0x0001000100000000ULL;
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1478 break;
1479 case 3:
1480 val64 = 0x0001020001020001ULL;
1481 writeq(val64, &bar0->tx_w_round_robin_0);
1482 val64 = 0x0200010200010200ULL;
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 val64 = 0x0102000102000102ULL;
1485 writeq(val64, &bar0->tx_w_round_robin_2);
1486 val64 = 0x0001020001020001ULL;
1487 writeq(val64, &bar0->tx_w_round_robin_3);
1488 val64 = 0x0200010200000000ULL;
1489 writeq(val64, &bar0->tx_w_round_robin_4);
1490 break;
1491 case 4:
1492 val64 = 0x0001020300010203ULL;
1493 writeq(val64, &bar0->tx_w_round_robin_0);
1494 writeq(val64, &bar0->tx_w_round_robin_1);
1495 writeq(val64, &bar0->tx_w_round_robin_2);
1496 writeq(val64, &bar0->tx_w_round_robin_3);
1497 val64 = 0x0001020300000000ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 5:
1501 val64 = 0x0001020304000102ULL;
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 val64 = 0x0304000102030400ULL;
1504 writeq(val64, &bar0->tx_w_round_robin_1);
1505 val64 = 0x0102030400010203ULL;
1506 writeq(val64, &bar0->tx_w_round_robin_2);
1507 val64 = 0x0400010203040001ULL;
1508 writeq(val64, &bar0->tx_w_round_robin_3);
1509 val64 = 0x0203040000000000ULL;
1510 writeq(val64, &bar0->tx_w_round_robin_4);
1511 break;
1512 case 6:
1513 val64 = 0x0001020304050001ULL;
1514 writeq(val64, &bar0->tx_w_round_robin_0);
1515 val64 = 0x0203040500010203ULL;
1516 writeq(val64, &bar0->tx_w_round_robin_1);
1517 val64 = 0x0405000102030405ULL;
1518 writeq(val64, &bar0->tx_w_round_robin_2);
1519 val64 = 0x0001020304050001ULL;
1520 writeq(val64, &bar0->tx_w_round_robin_3);
1521 val64 = 0x0203040500000000ULL;
1522 writeq(val64, &bar0->tx_w_round_robin_4);
1523 break;
1524 case 7:
1525 val64 = 0x0001020304050600ULL;
1526 writeq(val64, &bar0->tx_w_round_robin_0);
1527 val64 = 0x0102030405060001ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_1);
1529 val64 = 0x0203040506000102ULL;
1530 writeq(val64, &bar0->tx_w_round_robin_2);
1531 val64 = 0x0304050600010203ULL;
1532 writeq(val64, &bar0->tx_w_round_robin_3);
1533 val64 = 0x0405060000000000ULL;
1534 writeq(val64, &bar0->tx_w_round_robin_4);
1535 break;
1536 case 8:
1537 val64 = 0x0001020304050607ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_0);
1539 writeq(val64, &bar0->tx_w_round_robin_1);
1540 writeq(val64, &bar0->tx_w_round_robin_2);
1541 writeq(val64, &bar0->tx_w_round_robin_3);
1542 val64 = 0x0001020300000000ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_4);
1544 break;
1545 }
1546
1547 /* Enable all configured Tx FIFO partitions */
1548 val64 = readq(&bar0->tx_fifo_partition_0);
1549 val64 |= (TX_FIFO_PARTITION_EN);
1550 writeq(val64, &bar0->tx_fifo_partition_0);
1551
1552 /* Filling the Rx round robin registers as per the
1553 * number of Rings and steering based on QoS with
1554 * equal priority.
1555 */
1556 switch (config->rx_ring_num) {
1557 case 1:
1558 val64 = 0x0;
1559 writeq(val64, &bar0->rx_w_round_robin_0);
1560 writeq(val64, &bar0->rx_w_round_robin_1);
1561 writeq(val64, &bar0->rx_w_round_robin_2);
1562 writeq(val64, &bar0->rx_w_round_robin_3);
1563 writeq(val64, &bar0->rx_w_round_robin_4);
1564
1565 val64 = 0x8080808080808080ULL;
1566 writeq(val64, &bar0->rts_qos_steering);
1567 break;
1568 case 2:
1569 val64 = 0x0001000100010001ULL;
1570 writeq(val64, &bar0->rx_w_round_robin_0);
1571 writeq(val64, &bar0->rx_w_round_robin_1);
1572 writeq(val64, &bar0->rx_w_round_robin_2);
1573 writeq(val64, &bar0->rx_w_round_robin_3);
1574 val64 = 0x0001000100000000ULL;
1575 writeq(val64, &bar0->rx_w_round_robin_4);
1576
1577 val64 = 0x8080808040404040ULL;
1578 writeq(val64, &bar0->rts_qos_steering);
1579 break;
1580 case 3:
1581 val64 = 0x0001020001020001ULL;
1582 writeq(val64, &bar0->rx_w_round_robin_0);
1583 val64 = 0x0200010200010200ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_1);
1585 val64 = 0x0102000102000102ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_2);
1587 val64 = 0x0001020001020001ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_3);
1589 val64 = 0x0200010200000000ULL;
1590 writeq(val64, &bar0->rx_w_round_robin_4);
1591
1592 val64 = 0x8080804040402020ULL;
1593 writeq(val64, &bar0->rts_qos_steering);
1594 break;
1595 case 4:
1596 val64 = 0x0001020300010203ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_0);
1598 writeq(val64, &bar0->rx_w_round_robin_1);
1599 writeq(val64, &bar0->rx_w_round_robin_2);
1600 writeq(val64, &bar0->rx_w_round_robin_3);
1601 val64 = 0x0001020300000000ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_4);
1603
1604 val64 = 0x8080404020201010ULL;
1605 writeq(val64, &bar0->rts_qos_steering);
1606 break;
1607 case 5:
1608 val64 = 0x0001020304000102ULL;
1609 writeq(val64, &bar0->rx_w_round_robin_0);
1610 val64 = 0x0304000102030400ULL;
1611 writeq(val64, &bar0->rx_w_round_robin_1);
1612 val64 = 0x0102030400010203ULL;
1613 writeq(val64, &bar0->rx_w_round_robin_2);
1614 val64 = 0x0400010203040001ULL;
1615 writeq(val64, &bar0->rx_w_round_robin_3);
1616 val64 = 0x0203040000000000ULL;
1617 writeq(val64, &bar0->rx_w_round_robin_4);
1618
1619 val64 = 0x8080404020201008ULL;
1620 writeq(val64, &bar0->rts_qos_steering);
1621 break;
1622 case 6:
1623 val64 = 0x0001020304050001ULL;
1624 writeq(val64, &bar0->rx_w_round_robin_0);
1625 val64 = 0x0203040500010203ULL;
1626 writeq(val64, &bar0->rx_w_round_robin_1);
1627 val64 = 0x0405000102030405ULL;
1628 writeq(val64, &bar0->rx_w_round_robin_2);
1629 val64 = 0x0001020304050001ULL;
1630 writeq(val64, &bar0->rx_w_round_robin_3);
1631 val64 = 0x0203040500000000ULL;
1632 writeq(val64, &bar0->rx_w_round_robin_4);
1633
1634 val64 = 0x8080404020100804ULL;
1635 writeq(val64, &bar0->rts_qos_steering);
1636 break;
1637 case 7:
1638 val64 = 0x0001020304050600ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_0);
1640 val64 = 0x0102030405060001ULL;
1641 writeq(val64, &bar0->rx_w_round_robin_1);
1642 val64 = 0x0203040506000102ULL;
1643 writeq(val64, &bar0->rx_w_round_robin_2);
1644 val64 = 0x0304050600010203ULL;
1645 writeq(val64, &bar0->rx_w_round_robin_3);
1646 val64 = 0x0405060000000000ULL;
1647 writeq(val64, &bar0->rx_w_round_robin_4);
1648
1649 val64 = 0x8080402010080402ULL;
1650 writeq(val64, &bar0->rts_qos_steering);
1651 break;
1652 case 8:
1653 val64 = 0x0001020304050607ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_0);
1655 writeq(val64, &bar0->rx_w_round_robin_1);
1656 writeq(val64, &bar0->rx_w_round_robin_2);
1657 writeq(val64, &bar0->rx_w_round_robin_3);
1658 val64 = 0x0001020300000000ULL;
1659 writeq(val64, &bar0->rx_w_round_robin_4);
1660
1661 val64 = 0x8040201008040201ULL;
1662 writeq(val64, &bar0->rts_qos_steering);
1663 break;
1664 }
1665
1666 /* UDP Fix */
1667 val64 = 0;
1668 for (i = 0; i < 8; i++)
1669 writeq(val64, &bar0->rts_frm_len_n[i]);
1670
1671 /* Set the default rts frame length for the rings configured */
1672 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1673 for (i = 0 ; i < config->rx_ring_num ; i++)
1674 writeq(val64, &bar0->rts_frm_len_n[i]);
1675
1676 /* Set the frame length for the configured rings
1677 * desired by the user
1678 */
1679 for (i = 0; i < config->rx_ring_num; i++) {
1680 /* If rts_frm_len[i] == 0 then it is assumed that user not
1681 * specified frame length steering.
1682 * If the user provides the frame length then program
1683 * the rts_frm_len register for those values or else
1684 * leave it as it is.
1685 */
1686 if (rts_frm_len[i] != 0) {
1687 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1688 &bar0->rts_frm_len_n[i]);
1689 }
1690 }
1691
1692 /* Disable differentiated services steering logic */
1693 for (i = 0; i < 64; i++) {
1694 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1695 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1696 dev->name);
1697 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1698 return -ENODEV;
1699 }
1700 }
1701
1702 /* Program statistics memory */
1703 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1704
1705 if (nic->device_type == XFRAME_II_DEVICE) {
1706 val64 = STAT_BC(0x320);
1707 writeq(val64, &bar0->stat_byte_cnt);
1708 }
1709
1710 /*
1711 * Initializing the sampling rate for the device to calculate the
1712 * bandwidth utilization.
1713 */
1714 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1715 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1716 writeq(val64, &bar0->mac_link_util);
1717
1718 /*
1719 * Initializing the Transmit and Receive Traffic Interrupt
1720 * Scheme.
1721 */
1722
1723 /* Initialize TTI */
1724 if (SUCCESS != init_tti(nic, nic->last_link_state))
1725 return -ENODEV;
1726
1727 /* RTI Initialization */
1728 if (nic->device_type == XFRAME_II_DEVICE) {
1729 /*
1730 * Programmed to generate Apprx 500 Intrs per
1731 * second
1732 */
1733 int count = (nic->config.bus_speed * 125)/4;
1734 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1735 } else
1736 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1737 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1738 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1739 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1740
1741 writeq(val64, &bar0->rti_data1_mem);
1742
1743 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1744 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1745 if (nic->config.intr_type == MSI_X)
1746 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1747 RTI_DATA2_MEM_RX_UFC_D(0x40));
1748 else
1749 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1750 RTI_DATA2_MEM_RX_UFC_D(0x80));
1751 writeq(val64, &bar0->rti_data2_mem);
1752
1753 for (i = 0; i < config->rx_ring_num; i++) {
1754 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1755 | RTI_CMD_MEM_OFFSET(i);
1756 writeq(val64, &bar0->rti_command_mem);
1757
1758 /*
1759 * Once the operation completes, the Strobe bit of the
1760 * command register will be reset. We poll for this
1761 * particular condition. We wait for a maximum of 500ms
1762 * for the operation to complete, if it's not complete
1763 * by then we return error.
1764 */
1765 time = 0;
1766 while (TRUE) {
1767 val64 = readq(&bar0->rti_command_mem);
1768 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1769 break;
1770
1771 if (time > 10) {
1772 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1773 dev->name);
1774 return -ENODEV;
1775 }
1776 time++;
1777 msleep(50);
1778 }
1779 }
1780
1781 /*
1782 * Initializing proper values as Pause threshold into all
1783 * the 8 Queues on Rx side.
1784 */
1785 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1786 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1787
1788 /* Disable RMAC PAD STRIPPING */
1789 add = &bar0->mac_cfg;
1790 val64 = readq(&bar0->mac_cfg);
1791 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1792 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1793 writel((u32) (val64), add);
1794 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1795 writel((u32) (val64 >> 32), (add + 4));
1796 val64 = readq(&bar0->mac_cfg);
1797
1798 /* Enable FCS stripping by adapter */
1799 add = &bar0->mac_cfg;
1800 val64 = readq(&bar0->mac_cfg);
1801 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1802 if (nic->device_type == XFRAME_II_DEVICE)
1803 writeq(val64, &bar0->mac_cfg);
1804 else {
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64), add);
1807 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1808 writel((u32) (val64 >> 32), (add + 4));
1809 }
1810
1811 /*
1812 * Set the time value to be inserted in the pause frame
1813 * generated by xena.
1814 */
1815 val64 = readq(&bar0->rmac_pause_cfg);
1816 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1817 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1818 writeq(val64, &bar0->rmac_pause_cfg);
1819
1820 /*
1821 * Set the Threshold Limit for Generating the pause frame
1822 * If the amount of data in any Queue exceeds ratio of
1823 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1824 * pause frame is generated
1825 */
1826 val64 = 0;
1827 for (i = 0; i < 4; i++) {
1828 val64 |=
1829 (((u64) 0xFF00 | nic->mac_control.
1830 mc_pause_threshold_q0q3)
1831 << (i * 2 * 8));
1832 }
1833 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1834
1835 val64 = 0;
1836 for (i = 0; i < 4; i++) {
1837 val64 |=
1838 (((u64) 0xFF00 | nic->mac_control.
1839 mc_pause_threshold_q4q7)
1840 << (i * 2 * 8));
1841 }
1842 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1843
1844 /*
1845 * TxDMA will stop Read request if the number of read split has
1846 * exceeded the limit pointed by shared_splits
1847 */
1848 val64 = readq(&bar0->pic_control);
1849 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1850 writeq(val64, &bar0->pic_control);
1851
1852 if (nic->config.bus_speed == 266) {
1853 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1854 writeq(0x0, &bar0->read_retry_delay);
1855 writeq(0x0, &bar0->write_retry_delay);
1856 }
1857
1858 /*
1859 * Programming the Herc to split every write transaction
1860 * that does not start on an ADB to reduce disconnects.
1861 */
1862 if (nic->device_type == XFRAME_II_DEVICE) {
1863 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1864 MISC_LINK_STABILITY_PRD(3);
1865 writeq(val64, &bar0->misc_control);
1866 val64 = readq(&bar0->pic_control2);
1867 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1868 writeq(val64, &bar0->pic_control2);
1869 }
1870 if (strstr(nic->product_name, "CX4")) {
1871 val64 = TMAC_AVG_IPG(0x17);
1872 writeq(val64, &bar0->tmac_avg_ipg);
1873 }
1874
1875 return SUCCESS;
1876 }
1877 #define LINK_UP_DOWN_INTERRUPT 1
1878 #define MAC_RMAC_ERR_TIMER 2
1879
1880 static int s2io_link_fault_indication(struct s2io_nic *nic)
1881 {
1882 if (nic->device_type == XFRAME_II_DEVICE)
1883 return LINK_UP_DOWN_INTERRUPT;
1884 else
1885 return MAC_RMAC_ERR_TIMER;
1886 }
1887
1888 /**
1889 * do_s2io_write_bits - update alarm bits in alarm register
1890 * @value: alarm bits
1891 * @flag: interrupt status
1892 * @addr: address value
1893 * Description: update alarm bits in alarm register
1894 * Return Value:
1895 * NONE.
1896 */
1897 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1898 {
1899 u64 temp64;
1900
1901 temp64 = readq(addr);
1902
1903 if(flag == ENABLE_INTRS)
1904 temp64 &= ~((u64) value);
1905 else
1906 temp64 |= ((u64) value);
1907 writeq(temp64, addr);
1908 }
1909
1910 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1911 {
1912 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1913 register u64 gen_int_mask = 0;
1914 u64 interruptible;
1915
1916 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1917 if (mask & TX_DMA_INTR) {
1918
1919 gen_int_mask |= TXDMA_INT_M;
1920
1921 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1922 TXDMA_PCC_INT | TXDMA_TTI_INT |
1923 TXDMA_LSO_INT | TXDMA_TPA_INT |
1924 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1925
1926 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1927 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1928 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1929 &bar0->pfc_err_mask);
1930
1931 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1932 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1933 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1934
1935 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1936 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1937 PCC_N_SERR | PCC_6_COF_OV_ERR |
1938 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1939 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1940 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1941
1942 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1943 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1944
1945 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1946 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1947 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1948 flag, &bar0->lso_err_mask);
1949
1950 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1951 flag, &bar0->tpa_err_mask);
1952
1953 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1954
1955 }
1956
1957 if (mask & TX_MAC_INTR) {
1958 gen_int_mask |= TXMAC_INT_M;
1959 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1960 &bar0->mac_int_mask);
1961 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1962 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1963 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1964 flag, &bar0->mac_tmac_err_mask);
1965 }
1966
1967 if (mask & TX_XGXS_INTR) {
1968 gen_int_mask |= TXXGXS_INT_M;
1969 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1970 &bar0->xgxs_int_mask);
1971 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1972 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1973 flag, &bar0->xgxs_txgxs_err_mask);
1974 }
1975
1976 if (mask & RX_DMA_INTR) {
1977 gen_int_mask |= RXDMA_INT_M;
1978 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1979 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1980 flag, &bar0->rxdma_int_mask);
1981 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1982 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1983 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1984 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1985 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1986 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1987 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1988 &bar0->prc_pcix_err_mask);
1989 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1990 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1991 &bar0->rpa_err_mask);
1992 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1993 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1994 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1995 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1996 flag, &bar0->rda_err_mask);
1997 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1998 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1999 flag, &bar0->rti_err_mask);
2000 }
2001
2002 if (mask & RX_MAC_INTR) {
2003 gen_int_mask |= RXMAC_INT_M;
2004 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2005 &bar0->mac_int_mask);
2006 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2007 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2008 RMAC_DOUBLE_ECC_ERR;
2009 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2010 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2011 do_s2io_write_bits(interruptible,
2012 flag, &bar0->mac_rmac_err_mask);
2013 }
2014
2015 if (mask & RX_XGXS_INTR)
2016 {
2017 gen_int_mask |= RXXGXS_INT_M;
2018 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2019 &bar0->xgxs_int_mask);
2020 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2021 &bar0->xgxs_rxgxs_err_mask);
2022 }
2023
2024 if (mask & MC_INTR) {
2025 gen_int_mask |= MC_INT_M;
2026 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2027 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2028 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2029 &bar0->mc_err_mask);
2030 }
2031 nic->general_int_mask = gen_int_mask;
2032
2033 /* Remove this line when alarm interrupts are enabled */
2034 nic->general_int_mask = 0;
2035 }
2036 /**
2037 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2038 * @nic: device private variable,
2039 * @mask: A mask indicating which Intr block must be modified and,
2040 * @flag: A flag indicating whether to enable or disable the Intrs.
2041 * Description: This function will either disable or enable the interrupts
2042 * depending on the flag argument. The mask argument can be used to
2043 * enable/disable any Intr block.
2044 * Return Value: NONE.
2045 */
2046
2047 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2048 {
2049 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2050 register u64 temp64 = 0, intr_mask = 0;
2051
2052 intr_mask = nic->general_int_mask;
2053
2054 /* Top level interrupt classification */
2055 /* PIC Interrupts */
2056 if (mask & TX_PIC_INTR) {
2057 /* Enable PIC Intrs in the general intr mask register */
2058 intr_mask |= TXPIC_INT_M;
2059 if (flag == ENABLE_INTRS) {
2060 /*
2061 * If Hercules adapter enable GPIO otherwise
2062 * disable all PCIX, Flash, MDIO, IIC and GPIO
2063 * interrupts for now.
2064 * TODO
2065 */
2066 if (s2io_link_fault_indication(nic) ==
2067 LINK_UP_DOWN_INTERRUPT ) {
2068 do_s2io_write_bits(PIC_INT_GPIO, flag,
2069 &bar0->pic_int_mask);
2070 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2071 &bar0->gpio_int_mask);
2072 } else
2073 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2074 } else if (flag == DISABLE_INTRS) {
2075 /*
2076 * Disable PIC Intrs in the general
2077 * intr mask register
2078 */
2079 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2080 }
2081 }
2082
2083 /* Tx traffic interrupts */
2084 if (mask & TX_TRAFFIC_INTR) {
2085 intr_mask |= TXTRAFFIC_INT_M;
2086 if (flag == ENABLE_INTRS) {
2087 /*
2088 * Enable all the Tx side interrupts
2089 * writing 0 Enables all 64 TX interrupt levels
2090 */
2091 writeq(0x0, &bar0->tx_traffic_mask);
2092 } else if (flag == DISABLE_INTRS) {
2093 /*
2094 * Disable Tx Traffic Intrs in the general intr mask
2095 * register.
2096 */
2097 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2098 }
2099 }
2100
2101 /* Rx traffic interrupts */
2102 if (mask & RX_TRAFFIC_INTR) {
2103 intr_mask |= RXTRAFFIC_INT_M;
2104 if (flag == ENABLE_INTRS) {
2105 /* writing 0 Enables all 8 RX interrupt levels */
2106 writeq(0x0, &bar0->rx_traffic_mask);
2107 } else if (flag == DISABLE_INTRS) {
2108 /*
2109 * Disable Rx Traffic Intrs in the general intr mask
2110 * register.
2111 */
2112 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2113 }
2114 }
2115
2116 temp64 = readq(&bar0->general_int_mask);
2117 if (flag == ENABLE_INTRS)
2118 temp64 &= ~((u64) intr_mask);
2119 else
2120 temp64 = DISABLE_ALL_INTRS;
2121 writeq(temp64, &bar0->general_int_mask);
2122
2123 nic->general_int_mask = readq(&bar0->general_int_mask);
2124 }
2125
2126 /**
2127 * verify_pcc_quiescent- Checks for PCC quiescent state
2128 * Return: 1 If PCC is quiescence
2129 * 0 If PCC is not quiescence
2130 */
2131 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2132 {
2133 int ret = 0, herc;
2134 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2135 u64 val64 = readq(&bar0->adapter_status);
2136
2137 herc = (sp->device_type == XFRAME_II_DEVICE);
2138
2139 if (flag == FALSE) {
2140 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2141 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2142 ret = 1;
2143 } else {
2144 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2145 ret = 1;
2146 }
2147 } else {
2148 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2149 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2150 ADAPTER_STATUS_RMAC_PCC_IDLE))
2151 ret = 1;
2152 } else {
2153 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2154 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2155 ret = 1;
2156 }
2157 }
2158
2159 return ret;
2160 }
2161 /**
2162 * verify_xena_quiescence - Checks whether the H/W is ready
2163 * Description: Returns whether the H/W is ready to go or not. Depending
2164 * on whether adapter enable bit was written or not the comparison
2165 * differs and the calling function passes the input argument flag to
2166 * indicate this.
2167 * Return: 1 If xena is quiescence
2168 * 0 If Xena is not quiescence
2169 */
2170
2171 static int verify_xena_quiescence(struct s2io_nic *sp)
2172 {
2173 int mode;
2174 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2175 u64 val64 = readq(&bar0->adapter_status);
2176 mode = s2io_verify_pci_mode(sp);
2177
2178 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2179 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2180 return 0;
2181 }
2182 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2183 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2184 return 0;
2185 }
2186 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2187 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2188 return 0;
2189 }
2190 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2191 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2192 return 0;
2193 }
2194 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2195 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2196 return 0;
2197 }
2198 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2199 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2200 return 0;
2201 }
2202 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2203 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2204 return 0;
2205 }
2206 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2207 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2208 return 0;
2209 }
2210
2211 /*
2212 * In PCI 33 mode, the P_PLL is not used, and therefore,
2213 * the the P_PLL_LOCK bit in the adapter_status register will
2214 * not be asserted.
2215 */
2216 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2217 sp->device_type == XFRAME_II_DEVICE && mode !=
2218 PCI_MODE_PCI_33) {
2219 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2220 return 0;
2221 }
2222 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2223 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2224 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2225 return 0;
2226 }
2227 return 1;
2228 }
2229
2230 /**
2231 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2232 * @sp: Pointer to device specifc structure
2233 * Description :
2234 * New procedure to clear mac address reading problems on Alpha platforms
2235 *
2236 */
2237
2238 static void fix_mac_address(struct s2io_nic * sp)
2239 {
2240 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2241 u64 val64;
2242 int i = 0;
2243
2244 while (fix_mac[i] != END_SIGN) {
2245 writeq(fix_mac[i++], &bar0->gpio_control);
2246 udelay(10);
2247 val64 = readq(&bar0->gpio_control);
2248 }
2249 }
2250
2251 /**
2252 * start_nic - Turns the device on
2253 * @nic : device private variable.
2254 * Description:
2255 * This function actually turns the device on. Before this function is
2256 * called,all Registers are configured from their reset states
2257 * and shared memory is allocated but the NIC is still quiescent. On
2258 * calling this function, the device interrupts are cleared and the NIC is
2259 * literally switched on by writing into the adapter control register.
2260 * Return Value:
2261 * SUCCESS on success and -1 on failure.
2262 */
2263
2264 static int start_nic(struct s2io_nic *nic)
2265 {
2266 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2267 struct net_device *dev = nic->dev;
2268 register u64 val64 = 0;
2269 u16 subid, i;
2270 struct mac_info *mac_control;
2271 struct config_param *config;
2272
2273 mac_control = &nic->mac_control;
2274 config = &nic->config;
2275
2276 /* PRC Initialization and configuration */
2277 for (i = 0; i < config->rx_ring_num; i++) {
2278 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2279 &bar0->prc_rxd0_n[i]);
2280
2281 val64 = readq(&bar0->prc_ctrl_n[i]);
2282 if (nic->rxd_mode == RXD_MODE_1)
2283 val64 |= PRC_CTRL_RC_ENABLED;
2284 else
2285 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2286 if (nic->device_type == XFRAME_II_DEVICE)
2287 val64 |= PRC_CTRL_GROUP_READS;
2288 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2289 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2290 writeq(val64, &bar0->prc_ctrl_n[i]);
2291 }
2292
2293 if (nic->rxd_mode == RXD_MODE_3B) {
2294 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2295 val64 = readq(&bar0->rx_pa_cfg);
2296 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2297 writeq(val64, &bar0->rx_pa_cfg);
2298 }
2299
2300 if (vlan_tag_strip == 0) {
2301 val64 = readq(&bar0->rx_pa_cfg);
2302 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2303 writeq(val64, &bar0->rx_pa_cfg);
2304 nic->vlan_strip_flag = 0;
2305 }
2306
2307 /*
2308 * Enabling MC-RLDRAM. After enabling the device, we timeout
2309 * for around 100ms, which is approximately the time required
2310 * for the device to be ready for operation.
2311 */
2312 val64 = readq(&bar0->mc_rldram_mrs);
2313 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2314 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2315 val64 = readq(&bar0->mc_rldram_mrs);
2316
2317 msleep(100); /* Delay by around 100 ms. */
2318
2319 /* Enabling ECC Protection. */
2320 val64 = readq(&bar0->adapter_control);
2321 val64 &= ~ADAPTER_ECC_EN;
2322 writeq(val64, &bar0->adapter_control);
2323
2324 /*
2325 * Verify if the device is ready to be enabled, if so enable
2326 * it.
2327 */
2328 val64 = readq(&bar0->adapter_status);
2329 if (!verify_xena_quiescence(nic)) {
2330 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2331 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2332 (unsigned long long) val64);
2333 return FAILURE;
2334 }
2335
2336 /*
2337 * With some switches, link might be already up at this point.
2338 * Because of this weird behavior, when we enable laser,
2339 * we may not get link. We need to handle this. We cannot
2340 * figure out which switch is misbehaving. So we are forced to
2341 * make a global change.
2342 */
2343
2344 /* Enabling Laser. */
2345 val64 = readq(&bar0->adapter_control);
2346 val64 |= ADAPTER_EOI_TX_ON;
2347 writeq(val64, &bar0->adapter_control);
2348
2349 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2350 /*
2351 * Dont see link state interrupts initally on some switches,
2352 * so directly scheduling the link state task here.
2353 */
2354 schedule_work(&nic->set_link_task);
2355 }
2356 /* SXE-002: Initialize link and activity LED */
2357 subid = nic->pdev->subsystem_device;
2358 if (((subid & 0xFF) >= 0x07) &&
2359 (nic->device_type == XFRAME_I_DEVICE)) {
2360 val64 = readq(&bar0->gpio_control);
2361 val64 |= 0x0000800000000000ULL;
2362 writeq(val64, &bar0->gpio_control);
2363 val64 = 0x0411040400000000ULL;
2364 writeq(val64, (void __iomem *)bar0 + 0x2700);
2365 }
2366
2367 return SUCCESS;
2368 }
2369 /**
2370 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2371 */
2372 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2373 TxD *txdlp, int get_off)
2374 {
2375 struct s2io_nic *nic = fifo_data->nic;
2376 struct sk_buff *skb;
2377 struct TxD *txds;
2378 u16 j, frg_cnt;
2379
2380 txds = txdlp;
2381 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2382 pci_unmap_single(nic->pdev, (dma_addr_t)
2383 txds->Buffer_Pointer, sizeof(u64),
2384 PCI_DMA_TODEVICE);
2385 txds++;
2386 }
2387
2388 skb = (struct sk_buff *) ((unsigned long)
2389 txds->Host_Control);
2390 if (!skb) {
2391 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2392 return NULL;
2393 }
2394 pci_unmap_single(nic->pdev, (dma_addr_t)
2395 txds->Buffer_Pointer,
2396 skb->len - skb->data_len,
2397 PCI_DMA_TODEVICE);
2398 frg_cnt = skb_shinfo(skb)->nr_frags;
2399 if (frg_cnt) {
2400 txds++;
2401 for (j = 0; j < frg_cnt; j++, txds++) {
2402 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2403 if (!txds->Buffer_Pointer)
2404 break;
2405 pci_unmap_page(nic->pdev, (dma_addr_t)
2406 txds->Buffer_Pointer,
2407 frag->size, PCI_DMA_TODEVICE);
2408 }
2409 }
2410 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2411 return(skb);
2412 }
2413
2414 /**
2415 * free_tx_buffers - Free all queued Tx buffers
2416 * @nic : device private variable.
2417 * Description:
2418 * Free all queued Tx buffers.
2419 * Return Value: void
2420 */
2421
2422 static void free_tx_buffers(struct s2io_nic *nic)
2423 {
2424 struct net_device *dev = nic->dev;
2425 struct sk_buff *skb;
2426 struct TxD *txdp;
2427 int i, j;
2428 struct mac_info *mac_control;
2429 struct config_param *config;
2430 int cnt = 0;
2431
2432 mac_control = &nic->mac_control;
2433 config = &nic->config;
2434
2435 for (i = 0; i < config->tx_fifo_num; i++) {
2436 unsigned long flags;
2437 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2438 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
2439 txdp = (struct TxD *) \
2440 mac_control->fifos[i].list_info[j].list_virt_addr;
2441 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2442 if (skb) {
2443 nic->mac_control.stats_info->sw_stat.mem_freed
2444 += skb->truesize;
2445 dev_kfree_skb(skb);
2446 cnt++;
2447 }
2448 }
2449 DBG_PRINT(INTR_DBG,
2450 "%s:forcibly freeing %d skbs on FIFO%d\n",
2451 dev->name, cnt, i);
2452 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2453 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2454 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2455 }
2456 }
2457
2458 /**
2459 * stop_nic - To stop the nic
2460 * @nic ; device private variable.
2461 * Description:
2462 * This function does exactly the opposite of what the start_nic()
2463 * function does. This function is called to stop the device.
2464 * Return Value:
2465 * void.
2466 */
2467
2468 static void stop_nic(struct s2io_nic *nic)
2469 {
2470 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2471 register u64 val64 = 0;
2472 u16 interruptible;
2473 struct mac_info *mac_control;
2474 struct config_param *config;
2475
2476 mac_control = &nic->mac_control;
2477 config = &nic->config;
2478
2479 /* Disable all interrupts */
2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482 interruptible |= TX_PIC_INTR;
2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
2489 }
2490
2491 /**
2492 * fill_rx_buffers - Allocates the Rx side skbs
2493 * @ring_info: per ring structure
2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
2497 * Description:
2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2502 * 1. single buffer,
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2509 * supported.
2510 * Return Value:
2511 * SUCCESS on success or an appropriate -ve value on failure.
2512 */
2513 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2514 int from_card_up)
2515 {
2516 struct sk_buff *skb;
2517 struct RxD_t *rxdp;
2518 int off, size, block_no, block_no1;
2519 u32 alloc_tab = 0;
2520 u32 alloc_cnt;
2521 u64 tmp;
2522 struct buffAdd *ba;
2523 struct RxD_t *first_rxdp = NULL;
2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2525 int rxd_index = 0;
2526 struct RxD1 *rxdp1;
2527 struct RxD3 *rxdp3;
2528 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2529
2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2531
2532 block_no1 = ring->rx_curr_get_info.block_index;
2533 while (alloc_tab < alloc_cnt) {
2534 block_no = ring->rx_curr_put_info.block_index;
2535
2536 off = ring->rx_curr_put_info.offset;
2537
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540 rxd_index = off + 1;
2541 if (block_no)
2542 rxd_index += (block_no * ring->rxd_count);
2543
2544 if ((block_no == block_no1) &&
2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
2547 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2548 ring->dev->name);
2549 DBG_PRINT(INTR_DBG, " info equated\n");
2550 goto end;
2551 }
2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
2555 ring->block_count)
2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2558 off = 0;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2562 ring->dev->name, rxdp);
2563
2564 }
2565
2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
2569 ring->rx_curr_put_info.offset = off;
2570 goto end;
2571 }
2572 /* calculate size of skb based on ring mode */
2573 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575 if (ring->rxd_mode == RXD_MODE_1)
2576 size += NET_IP_ALIGN;
2577 else
2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2579
2580 /* allocate skb */
2581 skb = dev_alloc_skb(size);
2582 if(!skb) {
2583 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2584 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2585 if (first_rxdp) {
2586 wmb();
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588 }
2589 stats->mem_alloc_fail_cnt++;
2590
2591 return -ENOMEM ;
2592 }
2593 stats->mem_allocated += skb->truesize;
2594
2595 if (ring->rxd_mode == RXD_MODE_1) {
2596 /* 1 buffer mode - normal operation mode */
2597 rxdp1 = (struct RxD1*)rxdp;
2598 memset(rxdp, 0, sizeof(struct RxD1));
2599 skb_reserve(skb, NET_IP_ALIGN);
2600 rxdp1->Buffer0_ptr = pci_map_single
2601 (ring->pdev, skb->data, size - NET_IP_ALIGN,
2602 PCI_DMA_FROMDEVICE);
2603 if (pci_dma_mapping_error(nic->pdev,
2604 rxdp1->Buffer0_ptr))
2605 goto pci_map_failed;
2606
2607 rxdp->Control_2 =
2608 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2609 rxdp->Host_Control = (unsigned long) (skb);
2610 } else if (ring->rxd_mode == RXD_MODE_3B) {
2611 /*
2612 * 2 buffer mode -
2613 * 2 buffer mode provides 128
2614 * byte aligned receive buffers.
2615 */
2616
2617 rxdp3 = (struct RxD3*)rxdp;
2618 /* save buffer pointers to avoid frequent dma mapping */
2619 Buffer0_ptr = rxdp3->Buffer0_ptr;
2620 Buffer1_ptr = rxdp3->Buffer1_ptr;
2621 memset(rxdp, 0, sizeof(struct RxD3));
2622 /* restore the buffer pointers for dma sync*/
2623 rxdp3->Buffer0_ptr = Buffer0_ptr;
2624 rxdp3->Buffer1_ptr = Buffer1_ptr;
2625
2626 ba = &ring->ba[block_no][off];
2627 skb_reserve(skb, BUF0_LEN);
2628 tmp = (u64)(unsigned long) skb->data;
2629 tmp += ALIGN_SIZE;
2630 tmp &= ~ALIGN_SIZE;
2631 skb->data = (void *) (unsigned long)tmp;
2632 skb_reset_tail_pointer(skb);
2633
2634 if (from_card_up) {
2635 rxdp3->Buffer0_ptr =
2636 pci_map_single(ring->pdev, ba->ba_0,
2637 BUF0_LEN, PCI_DMA_FROMDEVICE);
2638 if (pci_dma_mapping_error(nic->pdev,
2639 rxdp3->Buffer0_ptr))
2640 goto pci_map_failed;
2641 } else
2642 pci_dma_sync_single_for_device(ring->pdev,
2643 (dma_addr_t) rxdp3->Buffer0_ptr,
2644 BUF0_LEN, PCI_DMA_FROMDEVICE);
2645
2646 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2647 if (ring->rxd_mode == RXD_MODE_3B) {
2648 /* Two buffer mode */
2649
2650 /*
2651 * Buffer2 will have L3/L4 header plus
2652 * L4 payload
2653 */
2654 rxdp3->Buffer2_ptr = pci_map_single
2655 (ring->pdev, skb->data, ring->mtu + 4,
2656 PCI_DMA_FROMDEVICE);
2657
2658 if (pci_dma_mapping_error(nic->pdev,
2659 rxdp3->Buffer2_ptr))
2660 goto pci_map_failed;
2661
2662 if (from_card_up) {
2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
2665 ba->ba_1, BUF1_LEN,
2666 PCI_DMA_FROMDEVICE);
2667
2668 if (pci_dma_mapping_error(nic->pdev,
2669 rxdp3->Buffer1_ptr)) {
2670 pci_unmap_single
2671 (ring->pdev,
2672 (dma_addr_t)(unsigned long)
2673 skb->data,
2674 ring->mtu + 4,
2675 PCI_DMA_FROMDEVICE);
2676 goto pci_map_failed;
2677 }
2678 }
2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2681 (ring->mtu + 4);
2682 }
2683 rxdp->Control_2 |= s2BIT(0);
2684 rxdp->Host_Control = (unsigned long) (skb);
2685 }
2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
2688 off++;
2689 if (off == (ring->rxd_count + 1))
2690 off = 0;
2691 ring->rx_curr_put_info.offset = off;
2692
2693 rxdp->Control_2 |= SET_RXD_MARKER;
2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2695 if (first_rxdp) {
2696 wmb();
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2698 }
2699 first_rxdp = rxdp;
2700 }
2701 ring->rx_bufs_left += 1;
2702 alloc_tab++;
2703 }
2704
2705 end:
2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2709 */
2710 if (first_rxdp) {
2711 wmb();
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2713 }
2714
2715 return SUCCESS;
2716 pci_map_failed:
2717 stats->pci_map_fail_cnt++;
2718 stats->mem_freed += skb->truesize;
2719 dev_kfree_skb_irq(skb);
2720 return -ENOMEM;
2721 }
2722
2723 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2724 {
2725 struct net_device *dev = sp->dev;
2726 int j;
2727 struct sk_buff *skb;
2728 struct RxD_t *rxdp;
2729 struct mac_info *mac_control;
2730 struct buffAdd *ba;
2731 struct RxD1 *rxdp1;
2732 struct RxD3 *rxdp3;
2733
2734 mac_control = &sp->mac_control;
2735 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2736 rxdp = mac_control->rings[ring_no].
2737 rx_blocks[blk].rxds[j].virt_addr;
2738 skb = (struct sk_buff *)
2739 ((unsigned long) rxdp->Host_Control);
2740 if (!skb) {
2741 continue;
2742 }
2743 if (sp->rxd_mode == RXD_MODE_1) {
2744 rxdp1 = (struct RxD1*)rxdp;
2745 pci_unmap_single(sp->pdev, (dma_addr_t)
2746 rxdp1->Buffer0_ptr,
2747 dev->mtu +
2748 HEADER_ETHERNET_II_802_3_SIZE
2749 + HEADER_802_2_SIZE +
2750 HEADER_SNAP_SIZE,
2751 PCI_DMA_FROMDEVICE);
2752 memset(rxdp, 0, sizeof(struct RxD1));
2753 } else if(sp->rxd_mode == RXD_MODE_3B) {
2754 rxdp3 = (struct RxD3*)rxdp;
2755 ba = &mac_control->rings[ring_no].
2756 ba[blk][j];
2757 pci_unmap_single(sp->pdev, (dma_addr_t)
2758 rxdp3->Buffer0_ptr,
2759 BUF0_LEN,
2760 PCI_DMA_FROMDEVICE);
2761 pci_unmap_single(sp->pdev, (dma_addr_t)
2762 rxdp3->Buffer1_ptr,
2763 BUF1_LEN,
2764 PCI_DMA_FROMDEVICE);
2765 pci_unmap_single(sp->pdev, (dma_addr_t)
2766 rxdp3->Buffer2_ptr,
2767 dev->mtu + 4,
2768 PCI_DMA_FROMDEVICE);
2769 memset(rxdp, 0, sizeof(struct RxD3));
2770 }
2771 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2772 dev_kfree_skb(skb);
2773 mac_control->rings[ring_no].rx_bufs_left -= 1;
2774 }
2775 }
2776
2777 /**
2778 * free_rx_buffers - Frees all Rx buffers
2779 * @sp: device private variable.
2780 * Description:
2781 * This function will free all Rx buffers allocated by host.
2782 * Return Value:
2783 * NONE.
2784 */
2785
2786 static void free_rx_buffers(struct s2io_nic *sp)
2787 {
2788 struct net_device *dev = sp->dev;
2789 int i, blk = 0, buf_cnt = 0;
2790 struct mac_info *mac_control;
2791 struct config_param *config;
2792
2793 mac_control = &sp->mac_control;
2794 config = &sp->config;
2795
2796 for (i = 0; i < config->rx_ring_num; i++) {
2797 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2798 free_rxd_blk(sp,i,blk);
2799
2800 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2801 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2802 mac_control->rings[i].rx_curr_put_info.offset = 0;
2803 mac_control->rings[i].rx_curr_get_info.offset = 0;
2804 mac_control->rings[i].rx_bufs_left = 0;
2805 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2806 dev->name, buf_cnt, i);
2807 }
2808 }
2809
2810 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2811 {
2812 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2813 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2814 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2815 }
2816 return 0;
2817 }
2818
2819 /**
2820 * s2io_poll - Rx interrupt handler for NAPI support
2821 * @napi : pointer to the napi structure.
2822 * @budget : The number of packets that were budgeted to be processed
2823 * during one pass through the 'Poll" function.
2824 * Description:
2825 * Comes into picture only if NAPI support has been incorporated. It does
2826 * the same thing that rx_intr_handler does, but not in a interrupt context
2827 * also It will process only a given number of packets.
2828 * Return value:
2829 * 0 on success and 1 if there are No Rx packets to be processed.
2830 */
2831
2832 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2833 {
2834 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2835 struct net_device *dev = ring->dev;
2836 struct config_param *config;
2837 struct mac_info *mac_control;
2838 int pkts_processed = 0;
2839 u8 __iomem *addr = NULL;
2840 u8 val8 = 0;
2841 struct s2io_nic *nic = netdev_priv(dev);
2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843 int budget_org = budget;
2844
2845 config = &nic->config;
2846 mac_control = &nic->mac_control;
2847
2848 if (unlikely(!is_s2io_card_up(nic)))
2849 return 0;
2850
2851 pkts_processed = rx_intr_handler(ring, budget);
2852 s2io_chk_rx_buffers(nic, ring);
2853
2854 if (pkts_processed < budget_org) {
2855 netif_rx_complete(napi);
2856 /*Re Enable MSI-Rx Vector*/
2857 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2858 addr += 7 - ring->ring_no;
2859 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2860 writeb(val8, addr);
2861 val8 = readb(addr);
2862 }
2863 return pkts_processed;
2864 }
2865 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2866 {
2867 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2868 struct ring_info *ring;
2869 struct net_device *dev = nic->dev;
2870 struct config_param *config;
2871 struct mac_info *mac_control;
2872 int pkts_processed = 0;
2873 int ring_pkts_processed, i;
2874 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2875 int budget_org = budget;
2876
2877 config = &nic->config;
2878 mac_control = &nic->mac_control;
2879
2880 if (unlikely(!is_s2io_card_up(nic)))
2881 return 0;
2882
2883 for (i = 0; i < config->rx_ring_num; i++) {
2884 ring = &mac_control->rings[i];
2885 ring_pkts_processed = rx_intr_handler(ring, budget);
2886 s2io_chk_rx_buffers(nic, ring);
2887 pkts_processed += ring_pkts_processed;
2888 budget -= ring_pkts_processed;
2889 if (budget <= 0)
2890 break;
2891 }
2892 if (pkts_processed < budget_org) {
2893 netif_rx_complete(napi);
2894 /* Re enable the Rx interrupts for the ring */
2895 writeq(0, &bar0->rx_traffic_mask);
2896 readl(&bar0->rx_traffic_mask);
2897 }
2898 return pkts_processed;
2899 }
2900
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 /**
2903 * s2io_netpoll - netpoll event handler entry point
2904 * @dev : pointer to the device structure.
2905 * Description:
2906 * This function will be called by upper layer to check for events on the
2907 * interface in situations where interrupts are disabled. It is used for
2908 * specific in-kernel networking tasks, such as remote consoles and kernel
2909 * debugging over the network (example netdump in RedHat).
2910 */
2911 static void s2io_netpoll(struct net_device *dev)
2912 {
2913 struct s2io_nic *nic = netdev_priv(dev);
2914 struct mac_info *mac_control;
2915 struct config_param *config;
2916 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2917 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2918 int i;
2919
2920 if (pci_channel_offline(nic->pdev))
2921 return;
2922
2923 disable_irq(dev->irq);
2924
2925 mac_control = &nic->mac_control;
2926 config = &nic->config;
2927
2928 writeq(val64, &bar0->rx_traffic_int);
2929 writeq(val64, &bar0->tx_traffic_int);
2930
2931 /* we need to free up the transmitted skbufs or else netpoll will
2932 * run out of skbs and will fail and eventually netpoll application such
2933 * as netdump will fail.
2934 */
2935 for (i = 0; i < config->tx_fifo_num; i++)
2936 tx_intr_handler(&mac_control->fifos[i]);
2937
2938 /* check for received packet and indicate up to network */
2939 for (i = 0; i < config->rx_ring_num; i++)
2940 rx_intr_handler(&mac_control->rings[i], 0);
2941
2942 for (i = 0; i < config->rx_ring_num; i++) {
2943 if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
2944 -ENOMEM) {
2945 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2946 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2947 break;
2948 }
2949 }
2950 enable_irq(dev->irq);
2951 return;
2952 }
2953 #endif
2954
2955 /**
2956 * rx_intr_handler - Rx interrupt handler
2957 * @ring_info: per ring structure.
2958 * @budget: budget for napi processing.
2959 * Description:
2960 * If the interrupt is because of a received frame or if the
2961 * receive ring contains fresh as yet un-processed frames,this function is
2962 * called. It picks out the RxD at which place the last Rx processing had
2963 * stopped and sends the skb to the OSM's Rx handler and then increments
2964 * the offset.
2965 * Return Value:
2966 * No. of napi packets processed.
2967 */
2968 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2969 {
2970 int get_block, put_block;
2971 struct rx_curr_get_info get_info, put_info;
2972 struct RxD_t *rxdp;
2973 struct sk_buff *skb;
2974 int pkt_cnt = 0, napi_pkts = 0;
2975 int i;
2976 struct RxD1* rxdp1;
2977 struct RxD3* rxdp3;
2978
2979 get_info = ring_data->rx_curr_get_info;
2980 get_block = get_info.block_index;
2981 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2982 put_block = put_info.block_index;
2983 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2984
2985 while (RXD_IS_UP2DT(rxdp)) {
2986 /*
2987 * If your are next to put index then it's
2988 * FIFO full condition
2989 */
2990 if ((get_block == put_block) &&
2991 (get_info.offset + 1) == put_info.offset) {
2992 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2993 ring_data->dev->name);
2994 break;
2995 }
2996 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2997 if (skb == NULL) {
2998 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2999 ring_data->dev->name);
3000 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3001 return 0;
3002 }
3003 if (ring_data->rxd_mode == RXD_MODE_1) {
3004 rxdp1 = (struct RxD1*)rxdp;
3005 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3006 rxdp1->Buffer0_ptr,
3007 ring_data->mtu +
3008 HEADER_ETHERNET_II_802_3_SIZE +
3009 HEADER_802_2_SIZE +
3010 HEADER_SNAP_SIZE,
3011 PCI_DMA_FROMDEVICE);
3012 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3013 rxdp3 = (struct RxD3*)rxdp;
3014 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
3015 rxdp3->Buffer0_ptr,
3016 BUF0_LEN, PCI_DMA_FROMDEVICE);
3017 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3018 rxdp3->Buffer2_ptr,
3019 ring_data->mtu + 4,
3020 PCI_DMA_FROMDEVICE);
3021 }
3022 prefetch(skb->data);
3023 rx_osm_handler(ring_data, rxdp);
3024 get_info.offset++;
3025 ring_data->rx_curr_get_info.offset = get_info.offset;
3026 rxdp = ring_data->rx_blocks[get_block].
3027 rxds[get_info.offset].virt_addr;
3028 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3029 get_info.offset = 0;
3030 ring_data->rx_curr_get_info.offset = get_info.offset;
3031 get_block++;
3032 if (get_block == ring_data->block_count)
3033 get_block = 0;
3034 ring_data->rx_curr_get_info.block_index = get_block;
3035 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3036 }
3037
3038 if (ring_data->nic->config.napi) {
3039 budget--;
3040 napi_pkts++;
3041 if (!budget)
3042 break;
3043 }
3044 pkt_cnt++;
3045 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3046 break;
3047 }
3048 if (ring_data->lro) {
3049 /* Clear all LRO sessions before exiting */
3050 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3051 struct lro *lro = &ring_data->lro0_n[i];
3052 if (lro->in_use) {
3053 update_L3L4_header(ring_data->nic, lro);
3054 queue_rx_frame(lro->parent, lro->vlan_tag);
3055 clear_lro_session(lro);
3056 }
3057 }
3058 }
3059 return(napi_pkts);
3060 }
3061
3062 /**
3063 * tx_intr_handler - Transmit interrupt handler
3064 * @nic : device private variable
3065 * Description:
3066 * If an interrupt was raised to indicate DMA complete of the
3067 * Tx packet, this function is called. It identifies the last TxD
3068 * whose buffer was freed and frees all skbs whose data have already
3069 * DMA'ed into the NICs internal memory.
3070 * Return Value:
3071 * NONE
3072 */
3073
3074 static void tx_intr_handler(struct fifo_info *fifo_data)
3075 {
3076 struct s2io_nic *nic = fifo_data->nic;
3077 struct tx_curr_get_info get_info, put_info;
3078 struct sk_buff *skb = NULL;
3079 struct TxD *txdlp;
3080 int pkt_cnt = 0;
3081 unsigned long flags = 0;
3082 u8 err_mask;
3083
3084 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3085 return;
3086
3087 get_info = fifo_data->tx_curr_get_info;
3088 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3089 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3090 list_virt_addr;
3091 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3092 (get_info.offset != put_info.offset) &&
3093 (txdlp->Host_Control)) {
3094 /* Check for TxD errors */
3095 if (txdlp->Control_1 & TXD_T_CODE) {
3096 unsigned long long err;
3097 err = txdlp->Control_1 & TXD_T_CODE;
3098 if (err & 0x1) {
3099 nic->mac_control.stats_info->sw_stat.
3100 parity_err_cnt++;
3101 }
3102
3103 /* update t_code statistics */
3104 err_mask = err >> 48;
3105 switch(err_mask) {
3106 case 2:
3107 nic->mac_control.stats_info->sw_stat.
3108 tx_buf_abort_cnt++;
3109 break;
3110
3111 case 3:
3112 nic->mac_control.stats_info->sw_stat.
3113 tx_desc_abort_cnt++;
3114 break;
3115
3116 case 7:
3117 nic->mac_control.stats_info->sw_stat.
3118 tx_parity_err_cnt++;
3119 break;
3120
3121 case 10:
3122 nic->mac_control.stats_info->sw_stat.
3123 tx_link_loss_cnt++;
3124 break;
3125
3126 case 15:
3127 nic->mac_control.stats_info->sw_stat.
3128 tx_list_proc_err_cnt++;
3129 break;
3130 }
3131 }
3132
3133 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3134 if (skb == NULL) {
3135 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3136 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3137 __func__);
3138 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3139 return;
3140 }
3141 pkt_cnt++;
3142
3143 /* Updating the statistics block */
3144 nic->dev->stats.tx_bytes += skb->len;
3145 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3146 dev_kfree_skb_irq(skb);
3147
3148 get_info.offset++;
3149 if (get_info.offset == get_info.fifo_len + 1)
3150 get_info.offset = 0;
3151 txdlp = (struct TxD *) fifo_data->list_info
3152 [get_info.offset].list_virt_addr;
3153 fifo_data->tx_curr_get_info.offset =
3154 get_info.offset;
3155 }
3156
3157 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3158
3159 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3160 }
3161
3162 /**
3163 * s2io_mdio_write - Function to write in to MDIO registers
3164 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3165 * @addr : address value
3166 * @value : data value
3167 * @dev : pointer to net_device structure
3168 * Description:
3169 * This function is used to write values to the MDIO registers
3170 * NONE
3171 */
3172 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3173 {
3174 u64 val64 = 0x0;
3175 struct s2io_nic *sp = netdev_priv(dev);
3176 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3177
3178 //address transaction
3179 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3180 | MDIO_MMD_DEV_ADDR(mmd_type)
3181 | MDIO_MMS_PRT_ADDR(0x0);
3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
3187 //Data transaction
3188 val64 = 0x0;
3189 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3190 | MDIO_MMD_DEV_ADDR(mmd_type)
3191 | MDIO_MMS_PRT_ADDR(0x0)
3192 | MDIO_MDIO_DATA(value)
3193 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3194 writeq(val64, &bar0->mdio_control);
3195 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3196 writeq(val64, &bar0->mdio_control);
3197 udelay(100);
3198
3199 val64 = 0x0;
3200 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3201 | MDIO_MMD_DEV_ADDR(mmd_type)
3202 | MDIO_MMS_PRT_ADDR(0x0)
3203 | MDIO_OP(MDIO_OP_READ_TRANS);
3204 writeq(val64, &bar0->mdio_control);
3205 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3206 writeq(val64, &bar0->mdio_control);
3207 udelay(100);
3208
3209 }
3210
3211 /**
3212 * s2io_mdio_read - Function to write in to MDIO registers
3213 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3214 * @addr : address value
3215 * @dev : pointer to net_device structure
3216 * Description:
3217 * This function is used to read values to the MDIO registers
3218 * NONE
3219 */
3220 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3221 {
3222 u64 val64 = 0x0;
3223 u64 rval64 = 0x0;
3224 struct s2io_nic *sp = netdev_priv(dev);
3225 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3226
3227 /* address transaction */
3228 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3229 | MDIO_MMD_DEV_ADDR(mmd_type)
3230 | MDIO_MMS_PRT_ADDR(0x0);
3231 writeq(val64, &bar0->mdio_control);
3232 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3233 writeq(val64, &bar0->mdio_control);
3234 udelay(100);
3235
3236 /* Data transaction */
3237 val64 = 0x0;
3238 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3239 | MDIO_MMD_DEV_ADDR(mmd_type)
3240 | MDIO_MMS_PRT_ADDR(0x0)
3241 | MDIO_OP(MDIO_OP_READ_TRANS);
3242 writeq(val64, &bar0->mdio_control);
3243 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3244 writeq(val64, &bar0->mdio_control);
3245 udelay(100);
3246
3247 /* Read the value from regs */
3248 rval64 = readq(&bar0->mdio_control);
3249 rval64 = rval64 & 0xFFFF0000;
3250 rval64 = rval64 >> 16;
3251 return rval64;
3252 }
3253 /**
3254 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3255 * @counter : couter value to be updated
3256 * @flag : flag to indicate the status
3257 * @type : counter type
3258 * Description:
3259 * This function is to check the status of the xpak counters value
3260 * NONE
3261 */
3262
3263 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3264 {
3265 u64 mask = 0x3;
3266 u64 val64;
3267 int i;
3268 for(i = 0; i <index; i++)
3269 mask = mask << 0x2;
3270
3271 if(flag > 0)
3272 {
3273 *counter = *counter + 1;
3274 val64 = *regs_stat & mask;
3275 val64 = val64 >> (index * 0x2);
3276 val64 = val64 + 1;
3277 if(val64 == 3)
3278 {
3279 switch(type)
3280 {
3281 case 1:
3282 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3283 "service. Excessive temperatures may "
3284 "result in premature transceiver "
3285 "failure \n");
3286 break;
3287 case 2:
3288 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3289 "service Excessive bias currents may "
3290 "indicate imminent laser diode "
3291 "failure \n");
3292 break;
3293 case 3:
3294 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3295 "service Excessive laser output "
3296 "power may saturate far-end "
3297 "receiver\n");
3298 break;
3299 default:
3300 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3301 "type \n");
3302 }
3303 val64 = 0x0;
3304 }
3305 val64 = val64 << (index * 0x2);
3306 *regs_stat = (*regs_stat & (~mask)) | (val64);
3307
3308 } else {
3309 *regs_stat = *regs_stat & (~mask);
3310 }
3311 }
3312
3313 /**
3314 * s2io_updt_xpak_counter - Function to update the xpak counters
3315 * @dev : pointer to net_device struct
3316 * Description:
3317 * This function is to upate the status of the xpak counters value
3318 * NONE
3319 */
3320 static void s2io_updt_xpak_counter(struct net_device *dev)
3321 {
3322 u16 flag = 0x0;
3323 u16 type = 0x0;
3324 u16 val16 = 0x0;
3325 u64 val64 = 0x0;
3326 u64 addr = 0x0;
3327
3328 struct s2io_nic *sp = netdev_priv(dev);
3329 struct stat_block *stat_info = sp->mac_control.stats_info;
3330
3331 /* Check the communication with the MDIO slave */
3332 addr = 0x0000;
3333 val64 = 0x0;
3334 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3335 if((val64 == 0xFFFF) || (val64 == 0x0000))
3336 {
3337 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3338 "Returned %llx\n", (unsigned long long)val64);
3339 return;
3340 }
3341
3342 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3343 if(val64 != 0x2040)
3344 {
3345 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3346 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3347 (unsigned long long)val64);
3348 return;
3349 }
3350
3351 /* Loading the DOM register to MDIO register */
3352 addr = 0xA100;
3353 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3354 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3355
3356 /* Reading the Alarm flags */
3357 addr = 0xA070;
3358 val64 = 0x0;
3359 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3360
3361 flag = CHECKBIT(val64, 0x7);
3362 type = 1;
3363 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3364 &stat_info->xpak_stat.xpak_regs_stat,
3365 0x0, flag, type);
3366
3367 if(CHECKBIT(val64, 0x6))
3368 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3369
3370 flag = CHECKBIT(val64, 0x3);
3371 type = 2;
3372 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3373 &stat_info->xpak_stat.xpak_regs_stat,
3374 0x2, flag, type);
3375
3376 if(CHECKBIT(val64, 0x2))
3377 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3378
3379 flag = CHECKBIT(val64, 0x1);
3380 type = 3;
3381 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3382 &stat_info->xpak_stat.xpak_regs_stat,
3383 0x4, flag, type);
3384
3385 if(CHECKBIT(val64, 0x0))
3386 stat_info->xpak_stat.alarm_laser_output_power_low++;
3387
3388 /* Reading the Warning flags */
3389 addr = 0xA074;
3390 val64 = 0x0;
3391 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3392
3393 if(CHECKBIT(val64, 0x7))
3394 stat_info->xpak_stat.warn_transceiver_temp_high++;
3395
3396 if(CHECKBIT(val64, 0x6))
3397 stat_info->xpak_stat.warn_transceiver_temp_low++;
3398
3399 if(CHECKBIT(val64, 0x3))
3400 stat_info->xpak_stat.warn_laser_bias_current_high++;
3401
3402 if(CHECKBIT(val64, 0x2))
3403 stat_info->xpak_stat.warn_laser_bias_current_low++;
3404
3405 if(CHECKBIT(val64, 0x1))
3406 stat_info->xpak_stat.warn_laser_output_power_high++;
3407
3408 if(CHECKBIT(val64, 0x0))
3409 stat_info->xpak_stat.warn_laser_output_power_low++;
3410 }
3411
3412 /**
3413 * wait_for_cmd_complete - waits for a command to complete.
3414 * @sp : private member of the device structure, which is a pointer to the
3415 * s2io_nic structure.
3416 * Description: Function that waits for a command to Write into RMAC
3417 * ADDR DATA registers to be completed and returns either success or
3418 * error depending on whether the command was complete or not.
3419 * Return value:
3420 * SUCCESS on success and FAILURE on failure.
3421 */
3422
3423 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3424 int bit_state)
3425 {
3426 int ret = FAILURE, cnt = 0, delay = 1;
3427 u64 val64;
3428
3429 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3430 return FAILURE;
3431
3432 do {
3433 val64 = readq(addr);
3434 if (bit_state == S2IO_BIT_RESET) {
3435 if (!(val64 & busy_bit)) {
3436 ret = SUCCESS;
3437 break;
3438 }
3439 } else {
3440 if (!(val64 & busy_bit)) {
3441 ret = SUCCESS;
3442 break;
3443 }
3444 }
3445
3446 if(in_interrupt())
3447 mdelay(delay);
3448 else
3449 msleep(delay);
3450
3451 if (++cnt >= 10)
3452 delay = 50;
3453 } while (cnt < 20);
3454 return ret;
3455 }
3456 /*
3457 * check_pci_device_id - Checks if the device id is supported
3458 * @id : device id
3459 * Description: Function to check if the pci device id is supported by driver.
3460 * Return value: Actual device id if supported else PCI_ANY_ID
3461 */
3462 static u16 check_pci_device_id(u16 id)
3463 {
3464 switch (id) {
3465 case PCI_DEVICE_ID_HERC_WIN:
3466 case PCI_DEVICE_ID_HERC_UNI:
3467 return XFRAME_II_DEVICE;
3468 case PCI_DEVICE_ID_S2IO_UNI:
3469 case PCI_DEVICE_ID_S2IO_WIN:
3470 return XFRAME_I_DEVICE;
3471 default:
3472 return PCI_ANY_ID;
3473 }
3474 }
3475
3476 /**
3477 * s2io_reset - Resets the card.
3478 * @sp : private member of the device structure.
3479 * Description: Function to Reset the card. This function then also
3480 * restores the previously saved PCI configuration space registers as
3481 * the card reset also resets the configuration space.
3482 * Return value:
3483 * void.
3484 */
3485
3486 static void s2io_reset(struct s2io_nic * sp)
3487 {
3488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3489 u64 val64;
3490 u16 subid, pci_cmd;
3491 int i;
3492 u16 val16;
3493 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3494 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3495
3496 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3497 __func__, sp->dev->name);
3498
3499 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3500 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3501
3502 val64 = SW_RESET_ALL;
3503 writeq(val64, &bar0->sw_reset);
3504 if (strstr(sp->product_name, "CX4")) {
3505 msleep(750);
3506 }
3507 msleep(250);
3508 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3509
3510 /* Restore the PCI state saved during initialization. */
3511 pci_restore_state(sp->pdev);
3512 pci_read_config_word(sp->pdev, 0x2, &val16);
3513 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3514 break;
3515 msleep(200);
3516 }
3517
3518 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3519 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
3520 }
3521
3522 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3523
3524 s2io_init_pci(sp);
3525
3526 /* Set swapper to enable I/O register access */
3527 s2io_set_swapper(sp);
3528
3529 /* restore mac_addr entries */
3530 do_s2io_restore_unicast_mc(sp);
3531
3532 /* Restore the MSIX table entries from local variables */
3533 restore_xmsi_data(sp);
3534
3535 /* Clear certain PCI/PCI-X fields after reset */
3536 if (sp->device_type == XFRAME_II_DEVICE) {
3537 /* Clear "detected parity error" bit */
3538 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3539
3540 /* Clearing PCIX Ecc status register */
3541 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3542
3543 /* Clearing PCI_STATUS error reflected here */
3544 writeq(s2BIT(62), &bar0->txpic_int_reg);
3545 }
3546
3547 /* Reset device statistics maintained by OS */
3548 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3549
3550 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3551 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3552 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3553 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3554 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3555 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3556 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3557 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3558 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3559 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3560 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3561 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3562 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3563 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3564 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3565 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3566 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3567 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3568 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3569
3570 /* SXE-002: Configure link and activity LED to turn it off */
3571 subid = sp->pdev->subsystem_device;
3572 if (((subid & 0xFF) >= 0x07) &&
3573 (sp->device_type == XFRAME_I_DEVICE)) {
3574 val64 = readq(&bar0->gpio_control);
3575 val64 |= 0x0000800000000000ULL;
3576 writeq(val64, &bar0->gpio_control);
3577 val64 = 0x0411040400000000ULL;
3578 writeq(val64, (void __iomem *)bar0 + 0x2700);
3579 }
3580
3581 /*
3582 * Clear spurious ECC interrupts that would have occured on
3583 * XFRAME II cards after reset.
3584 */
3585 if (sp->device_type == XFRAME_II_DEVICE) {
3586 val64 = readq(&bar0->pcc_err_reg);
3587 writeq(val64, &bar0->pcc_err_reg);
3588 }
3589
3590 sp->device_enabled_once = FALSE;
3591 }
3592
3593 /**
3594 * s2io_set_swapper - to set the swapper controle on the card
3595 * @sp : private member of the device structure,
3596 * pointer to the s2io_nic structure.
3597 * Description: Function to set the swapper control on the card
3598 * correctly depending on the 'endianness' of the system.
3599 * Return value:
3600 * SUCCESS on success and FAILURE on failure.
3601 */
3602
3603 static int s2io_set_swapper(struct s2io_nic * sp)
3604 {
3605 struct net_device *dev = sp->dev;
3606 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3607 u64 val64, valt, valr;
3608
3609 /*
3610 * Set proper endian settings and verify the same by reading
3611 * the PIF Feed-back register.
3612 */
3613
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 != 0x0123456789ABCDEFULL) {
3616 int i = 0;
3617 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3618 0x8100008181000081ULL, /* FE=1, SE=0 */
3619 0x4200004242000042ULL, /* FE=0, SE=1 */
3620 0}; /* FE=0, SE=0 */
3621
3622 while(i<4) {
3623 writeq(value[i], &bar0->swapper_ctrl);
3624 val64 = readq(&bar0->pif_rd_swapper_fb);
3625 if (val64 == 0x0123456789ABCDEFULL)
3626 break;
3627 i++;
3628 }
3629 if (i == 4) {
3630 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3631 dev->name);
3632 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3633 (unsigned long long) val64);
3634 return FAILURE;
3635 }
3636 valr = value[i];
3637 } else {
3638 valr = readq(&bar0->swapper_ctrl);
3639 }
3640
3641 valt = 0x0123456789ABCDEFULL;
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
3644
3645 if(val64 != valt) {
3646 int i = 0;
3647 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3648 0x0081810000818100ULL, /* FE=1, SE=0 */
3649 0x0042420000424200ULL, /* FE=0, SE=1 */
3650 0}; /* FE=0, SE=0 */
3651
3652 while(i<4) {
3653 writeq((value[i] | valr), &bar0->swapper_ctrl);
3654 writeq(valt, &bar0->xmsi_address);
3655 val64 = readq(&bar0->xmsi_address);
3656 if(val64 == valt)
3657 break;
3658 i++;
3659 }
3660 if(i == 4) {
3661 unsigned long long x = val64;
3662 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3663 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3664 return FAILURE;
3665 }
3666 }
3667 val64 = readq(&bar0->swapper_ctrl);
3668 val64 &= 0xFFFF000000000000ULL;
3669
3670 #ifdef __BIG_ENDIAN
3671 /*
3672 * The device by default set to a big endian format, so a
3673 * big endian driver need not set anything.
3674 */
3675 val64 |= (SWAPPER_CTRL_TXP_FE |
3676 SWAPPER_CTRL_TXP_SE |
3677 SWAPPER_CTRL_TXD_R_FE |
3678 SWAPPER_CTRL_TXD_W_FE |
3679 SWAPPER_CTRL_TXF_R_FE |
3680 SWAPPER_CTRL_RXD_R_FE |
3681 SWAPPER_CTRL_RXD_W_FE |
3682 SWAPPER_CTRL_RXF_W_FE |
3683 SWAPPER_CTRL_XMSI_FE |
3684 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3685 if (sp->config.intr_type == INTA)
3686 val64 |= SWAPPER_CTRL_XMSI_SE;
3687 writeq(val64, &bar0->swapper_ctrl);
3688 #else
3689 /*
3690 * Initially we enable all bits to make it accessible by the
3691 * driver, then we selectively enable only those bits that
3692 * we want to set.
3693 */
3694 val64 |= (SWAPPER_CTRL_TXP_FE |
3695 SWAPPER_CTRL_TXP_SE |
3696 SWAPPER_CTRL_TXD_R_FE |
3697 SWAPPER_CTRL_TXD_R_SE |
3698 SWAPPER_CTRL_TXD_W_FE |
3699 SWAPPER_CTRL_TXD_W_SE |
3700 SWAPPER_CTRL_TXF_R_FE |
3701 SWAPPER_CTRL_RXD_R_FE |
3702 SWAPPER_CTRL_RXD_R_SE |
3703 SWAPPER_CTRL_RXD_W_FE |
3704 SWAPPER_CTRL_RXD_W_SE |
3705 SWAPPER_CTRL_RXF_W_FE |
3706 SWAPPER_CTRL_XMSI_FE |
3707 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3708 if (sp->config.intr_type == INTA)
3709 val64 |= SWAPPER_CTRL_XMSI_SE;
3710 writeq(val64, &bar0->swapper_ctrl);
3711 #endif
3712 val64 = readq(&bar0->swapper_ctrl);
3713
3714 /*
3715 * Verifying if endian settings are accurate by reading a
3716 * feedback register.
3717 */
3718 val64 = readq(&bar0->pif_rd_swapper_fb);
3719 if (val64 != 0x0123456789ABCDEFULL) {
3720 /* Endian settings are incorrect, calls for another dekko. */
3721 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3722 dev->name);
3723 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3724 (unsigned long long) val64);
3725 return FAILURE;
3726 }
3727
3728 return SUCCESS;
3729 }
3730
3731 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3732 {
3733 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3734 u64 val64;
3735 int ret = 0, cnt = 0;
3736
3737 do {
3738 val64 = readq(&bar0->xmsi_access);
3739 if (!(val64 & s2BIT(15)))
3740 break;
3741 mdelay(1);
3742 cnt++;
3743 } while(cnt < 5);
3744 if (cnt == 5) {
3745 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3746 ret = 1;
3747 }
3748
3749 return ret;
3750 }
3751
3752 static void restore_xmsi_data(struct s2io_nic *nic)
3753 {
3754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3755 u64 val64;
3756 int i, msix_index;
3757
3758
3759 if (nic->device_type == XFRAME_I_DEVICE)
3760 return;
3761
3762 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3763 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3764 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3765 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3766 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3767 writeq(val64, &bar0->xmsi_access);
3768 if (wait_for_msix_trans(nic, msix_index)) {
3769 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3770 continue;
3771 }
3772 }
3773 }
3774
3775 static void store_xmsi_data(struct s2io_nic *nic)
3776 {
3777 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3778 u64 val64, addr, data;
3779 int i, msix_index;
3780
3781 if (nic->device_type == XFRAME_I_DEVICE)
3782 return;
3783
3784 /* Store and display */
3785 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3786 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3787 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3788 writeq(val64, &bar0->xmsi_access);
3789 if (wait_for_msix_trans(nic, msix_index)) {
3790 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3791 continue;
3792 }
3793 addr = readq(&bar0->xmsi_address);
3794 data = readq(&bar0->xmsi_data);
3795 if (addr && data) {
3796 nic->msix_info[i].addr = addr;
3797 nic->msix_info[i].data = data;
3798 }
3799 }
3800 }
3801
3802 static int s2io_enable_msi_x(struct s2io_nic *nic)
3803 {
3804 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3805 u64 rx_mat;
3806 u16 msi_control; /* Temp variable */
3807 int ret, i, j, msix_indx = 1;
3808
3809 nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
3810 GFP_KERNEL);
3811 if (!nic->entries) {
3812 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3813 __func__);
3814 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3815 return -ENOMEM;
3816 }
3817 nic->mac_control.stats_info->sw_stat.mem_allocated
3818 += (nic->num_entries * sizeof(struct msix_entry));
3819
3820 memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
3821
3822 nic->s2io_entries =
3823 kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
3824 GFP_KERNEL);
3825 if (!nic->s2io_entries) {
3826 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3827 __func__);
3828 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3829 kfree(nic->entries);
3830 nic->mac_control.stats_info->sw_stat.mem_freed
3831 += (nic->num_entries * sizeof(struct msix_entry));
3832 return -ENOMEM;
3833 }
3834 nic->mac_control.stats_info->sw_stat.mem_allocated
3835 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3836 memset(nic->s2io_entries, 0,
3837 nic->num_entries * sizeof(struct s2io_msix_entry));
3838
3839 nic->entries[0].entry = 0;
3840 nic->s2io_entries[0].entry = 0;
3841 nic->s2io_entries[0].in_use = MSIX_FLG;
3842 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3843 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3844
3845 for (i = 1; i < nic->num_entries; i++) {
3846 nic->entries[i].entry = ((i - 1) * 8) + 1;
3847 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3848 nic->s2io_entries[i].arg = NULL;
3849 nic->s2io_entries[i].in_use = 0;
3850 }
3851
3852 rx_mat = readq(&bar0->rx_mat);
3853 for (j = 0; j < nic->config.rx_ring_num; j++) {
3854 rx_mat |= RX_MAT_SET(j, msix_indx);
3855 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3856 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3857 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3858 msix_indx += 8;
3859 }
3860 writeq(rx_mat, &bar0->rx_mat);
3861 readq(&bar0->rx_mat);
3862
3863 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3864 /* We fail init if error or we get less vectors than min required */
3865 if (ret) {
3866 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3867 kfree(nic->entries);
3868 nic->mac_control.stats_info->sw_stat.mem_freed
3869 += (nic->num_entries * sizeof(struct msix_entry));
3870 kfree(nic->s2io_entries);
3871 nic->mac_control.stats_info->sw_stat.mem_freed
3872 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3873 nic->entries = NULL;
3874 nic->s2io_entries = NULL;
3875 return -ENOMEM;
3876 }
3877
3878 /*
3879 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3880 * in the herc NIC. (Temp change, needs to be removed later)
3881 */
3882 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3883 msi_control |= 0x1; /* Enable MSI */
3884 pci_write_config_word(nic->pdev, 0x42, msi_control);
3885
3886 return 0;
3887 }
3888
3889 /* Handle software interrupt used during MSI(X) test */
3890 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3891 {
3892 struct s2io_nic *sp = dev_id;
3893
3894 sp->msi_detected = 1;
3895 wake_up(&sp->msi_wait);
3896
3897 return IRQ_HANDLED;
3898 }
3899
3900 /* Test interrupt path by forcing a a software IRQ */
3901 static int s2io_test_msi(struct s2io_nic *sp)
3902 {
3903 struct pci_dev *pdev = sp->pdev;
3904 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3905 int err;
3906 u64 val64, saved64;
3907
3908 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3909 sp->name, sp);
3910 if (err) {
3911 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3912 sp->dev->name, pci_name(pdev), pdev->irq);
3913 return err;
3914 }
3915
3916 init_waitqueue_head (&sp->msi_wait);
3917 sp->msi_detected = 0;
3918
3919 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3920 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3921 val64 |= SCHED_INT_CTRL_TIMER_EN;
3922 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3923 writeq(val64, &bar0->scheduled_int_ctrl);
3924
3925 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3926
3927 if (!sp->msi_detected) {
3928 /* MSI(X) test failed, go back to INTx mode */
3929 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3930 "using MSI(X) during test\n", sp->dev->name,
3931 pci_name(pdev));
3932
3933 err = -EOPNOTSUPP;
3934 }
3935
3936 free_irq(sp->entries[1].vector, sp);
3937
3938 writeq(saved64, &bar0->scheduled_int_ctrl);
3939
3940 return err;
3941 }
3942
3943 static void remove_msix_isr(struct s2io_nic *sp)
3944 {
3945 int i;
3946 u16 msi_control;
3947
3948 for (i = 0; i < sp->num_entries; i++) {
3949 if (sp->s2io_entries[i].in_use ==
3950 MSIX_REGISTERED_SUCCESS) {
3951 int vector = sp->entries[i].vector;
3952 void *arg = sp->s2io_entries[i].arg;
3953 free_irq(vector, arg);
3954 }
3955 }
3956
3957 kfree(sp->entries);
3958 kfree(sp->s2io_entries);
3959 sp->entries = NULL;
3960 sp->s2io_entries = NULL;
3961
3962 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3963 msi_control &= 0xFFFE; /* Disable MSI */
3964 pci_write_config_word(sp->pdev, 0x42, msi_control);
3965
3966 pci_disable_msix(sp->pdev);
3967 }
3968
3969 static void remove_inta_isr(struct s2io_nic *sp)
3970 {
3971 struct net_device *dev = sp->dev;
3972
3973 free_irq(sp->pdev->irq, dev);
3974 }
3975
3976 /* ********************************************************* *
3977 * Functions defined below concern the OS part of the driver *
3978 * ********************************************************* */
3979
3980 /**
3981 * s2io_open - open entry point of the driver
3982 * @dev : pointer to the device structure.
3983 * Description:
3984 * This function is the open entry point of the driver. It mainly calls a
3985 * function to allocate Rx buffers and inserts them into the buffer
3986 * descriptors and then enables the Rx part of the NIC.
3987 * Return value:
3988 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3989 * file on failure.
3990 */
3991
3992 static int s2io_open(struct net_device *dev)
3993 {
3994 struct s2io_nic *sp = netdev_priv(dev);
3995 int err = 0;
3996
3997 /*
3998 * Make sure you have link off by default every time
3999 * Nic is initialized
4000 */
4001 netif_carrier_off(dev);
4002 sp->last_link_state = 0;
4003
4004 /* Initialize H/W and enable interrupts */
4005 err = s2io_card_up(sp);
4006 if (err) {
4007 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4008 dev->name);
4009 goto hw_init_failed;
4010 }
4011
4012 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4013 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4014 s2io_card_down(sp);
4015 err = -ENODEV;
4016 goto hw_init_failed;
4017 }
4018 s2io_start_all_tx_queue(sp);
4019 return 0;
4020
4021 hw_init_failed:
4022 if (sp->config.intr_type == MSI_X) {
4023 if (sp->entries) {
4024 kfree(sp->entries);
4025 sp->mac_control.stats_info->sw_stat.mem_freed
4026 += (sp->num_entries * sizeof(struct msix_entry));
4027 }
4028 if (sp->s2io_entries) {
4029 kfree(sp->s2io_entries);
4030 sp->mac_control.stats_info->sw_stat.mem_freed
4031 += (sp->num_entries * sizeof(struct s2io_msix_entry));
4032 }
4033 }
4034 return err;
4035 }
4036
4037 /**
4038 * s2io_close -close entry point of the driver
4039 * @dev : device pointer.
4040 * Description:
4041 * This is the stop entry point of the driver. It needs to undo exactly
4042 * whatever was done by the open entry point,thus it's usually referred to
4043 * as the close function.Among other things this function mainly stops the
4044 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4045 * Return value:
4046 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4047 * file on failure.
4048 */
4049
4050 static int s2io_close(struct net_device *dev)
4051 {
4052 struct s2io_nic *sp = netdev_priv(dev);
4053 struct config_param *config = &sp->config;
4054 u64 tmp64;
4055 int offset;
4056
4057 /* Return if the device is already closed *
4058 * Can happen when s2io_card_up failed in change_mtu *
4059 */
4060 if (!is_s2io_card_up(sp))
4061 return 0;
4062
4063 s2io_stop_all_tx_queue(sp);
4064 /* delete all populated mac entries */
4065 for (offset = 1; offset < config->max_mc_addr; offset++) {
4066 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4067 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4068 do_s2io_delete_unicast_mc(sp, tmp64);
4069 }
4070
4071 s2io_card_down(sp);
4072
4073 return 0;
4074 }
4075
4076 /**
4077 * s2io_xmit - Tx entry point of te driver
4078 * @skb : the socket buffer containing the Tx data.
4079 * @dev : device pointer.
4080 * Description :
4081 * This function is the Tx entry point of the driver. S2IO NIC supports
4082 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4083 * NOTE: when device cant queue the pkt,just the trans_start variable will
4084 * not be upadted.
4085 * Return value:
4086 * 0 on success & 1 on failure.
4087 */
4088
4089 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4090 {
4091 struct s2io_nic *sp = netdev_priv(dev);
4092 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4093 register u64 val64;
4094 struct TxD *txdp;
4095 struct TxFIFO_element __iomem *tx_fifo;
4096 unsigned long flags = 0;
4097 u16 vlan_tag = 0;
4098 struct fifo_info *fifo = NULL;
4099 struct mac_info *mac_control;
4100 struct config_param *config;
4101 int do_spin_lock = 1;
4102 int offload_type;
4103 int enable_per_list_interrupt = 0;
4104 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4105
4106 mac_control = &sp->mac_control;
4107 config = &sp->config;
4108
4109 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4110
4111 if (unlikely(skb->len <= 0)) {
4112 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4113 dev_kfree_skb_any(skb);
4114 return 0;
4115 }
4116
4117 if (!is_s2io_card_up(sp)) {
4118 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4119 dev->name);
4120 dev_kfree_skb(skb);
4121 return 0;
4122 }
4123
4124 queue = 0;
4125 if (sp->vlgrp && vlan_tx_tag_present(skb))
4126 vlan_tag = vlan_tx_tag_get(skb);
4127 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4128 if (skb->protocol == htons(ETH_P_IP)) {
4129 struct iphdr *ip;
4130 struct tcphdr *th;
4131 ip = ip_hdr(skb);
4132
4133 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4134 th = (struct tcphdr *)(((unsigned char *)ip) +
4135 ip->ihl*4);
4136
4137 if (ip->protocol == IPPROTO_TCP) {
4138 queue_len = sp->total_tcp_fifos;
4139 queue = (ntohs(th->source) +
4140 ntohs(th->dest)) &
4141 sp->fifo_selector[queue_len - 1];
4142 if (queue >= queue_len)
4143 queue = queue_len - 1;
4144 } else if (ip->protocol == IPPROTO_UDP) {
4145 queue_len = sp->total_udp_fifos;
4146 queue = (ntohs(th->source) +
4147 ntohs(th->dest)) &
4148 sp->fifo_selector[queue_len - 1];
4149 if (queue >= queue_len)
4150 queue = queue_len - 1;
4151 queue += sp->udp_fifo_idx;
4152 if (skb->len > 1024)
4153 enable_per_list_interrupt = 1;
4154 do_spin_lock = 0;
4155 }
4156 }
4157 }
4158 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4159 /* get fifo number based on skb->priority value */
4160 queue = config->fifo_mapping
4161 [skb->priority & (MAX_TX_FIFOS - 1)];
4162 fifo = &mac_control->fifos[queue];
4163
4164 if (do_spin_lock)
4165 spin_lock_irqsave(&fifo->tx_lock, flags);
4166 else {
4167 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4168 return NETDEV_TX_LOCKED;
4169 }
4170
4171 if (sp->config.multiq) {
4172 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4173 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4174 return NETDEV_TX_BUSY;
4175 }
4176 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4177 if (netif_queue_stopped(dev)) {
4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179 return NETDEV_TX_BUSY;
4180 }
4181 }
4182
4183 put_off = (u16) fifo->tx_curr_put_info.offset;
4184 get_off = (u16) fifo->tx_curr_get_info.offset;
4185 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4186
4187 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4188 /* Avoid "put" pointer going beyond "get" pointer */
4189 if (txdp->Host_Control ||
4190 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4191 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4192 s2io_stop_tx_queue(sp, fifo->fifo_no);
4193 dev_kfree_skb(skb);
4194 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4195 return 0;
4196 }
4197
4198 offload_type = s2io_offload_type(skb);
4199 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4200 txdp->Control_1 |= TXD_TCP_LSO_EN;
4201 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4202 }
4203 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4204 txdp->Control_2 |=
4205 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4206 TXD_TX_CKO_UDP_EN);
4207 }
4208 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4209 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4210 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4211 if (enable_per_list_interrupt)
4212 if (put_off & (queue_len >> 5))
4213 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4214 if (vlan_tag) {
4215 txdp->Control_2 |= TXD_VLAN_ENABLE;
4216 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4217 }
4218
4219 frg_len = skb->len - skb->data_len;
4220 if (offload_type == SKB_GSO_UDP) {
4221 int ufo_size;
4222
4223 ufo_size = s2io_udp_mss(skb);
4224 ufo_size &= ~7;
4225 txdp->Control_1 |= TXD_UFO_EN;
4226 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4227 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4228 #ifdef __BIG_ENDIAN
4229 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4230 fifo->ufo_in_band_v[put_off] =
4231 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4232 #else
4233 fifo->ufo_in_band_v[put_off] =
4234 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4235 #endif
4236 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4237 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4238 fifo->ufo_in_band_v,
4239 sizeof(u64), PCI_DMA_TODEVICE);
4240 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4241 goto pci_map_failed;
4242 txdp++;
4243 }
4244
4245 txdp->Buffer_Pointer = pci_map_single
4246 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4247 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4248 goto pci_map_failed;
4249
4250 txdp->Host_Control = (unsigned long) skb;
4251 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4252 if (offload_type == SKB_GSO_UDP)
4253 txdp->Control_1 |= TXD_UFO_EN;
4254
4255 frg_cnt = skb_shinfo(skb)->nr_frags;
4256 /* For fragmented SKB. */
4257 for (i = 0; i < frg_cnt; i++) {
4258 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4259 /* A '0' length fragment will be ignored */
4260 if (!frag->size)
4261 continue;
4262 txdp++;
4263 txdp->Buffer_Pointer = (u64) pci_map_page
4264 (sp->pdev, frag->page, frag->page_offset,
4265 frag->size, PCI_DMA_TODEVICE);
4266 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4267 if (offload_type == SKB_GSO_UDP)
4268 txdp->Control_1 |= TXD_UFO_EN;
4269 }
4270 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4271
4272 if (offload_type == SKB_GSO_UDP)
4273 frg_cnt++; /* as Txd0 was used for inband header */
4274
4275 tx_fifo = mac_control->tx_FIFO_start[queue];
4276 val64 = fifo->list_info[put_off].list_phy_addr;
4277 writeq(val64, &tx_fifo->TxDL_Pointer);
4278
4279 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4280 TX_FIFO_LAST_LIST);
4281 if (offload_type)
4282 val64 |= TX_FIFO_SPECIAL_FUNC;
4283
4284 writeq(val64, &tx_fifo->List_Control);
4285
4286 mmiowb();
4287
4288 put_off++;
4289 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4290 put_off = 0;
4291 fifo->tx_curr_put_info.offset = put_off;
4292
4293 /* Avoid "put" pointer going beyond "get" pointer */
4294 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4295 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4296 DBG_PRINT(TX_DBG,
4297 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4298 put_off, get_off);
4299 s2io_stop_tx_queue(sp, fifo->fifo_no);
4300 }
4301 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4302 dev->trans_start = jiffies;
4303 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4304
4305 if (sp->config.intr_type == MSI_X)
4306 tx_intr_handler(fifo);
4307
4308 return 0;
4309 pci_map_failed:
4310 stats->pci_map_fail_cnt++;
4311 s2io_stop_tx_queue(sp, fifo->fifo_no);
4312 stats->mem_freed += skb->truesize;
4313 dev_kfree_skb(skb);
4314 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4315 return 0;
4316 }
4317
4318 static void
4319 s2io_alarm_handle(unsigned long data)
4320 {
4321 struct s2io_nic *sp = (struct s2io_nic *)data;
4322 struct net_device *dev = sp->dev;
4323
4324 s2io_handle_errors(dev);
4325 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4326 }
4327
4328 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4329 {
4330 struct ring_info *ring = (struct ring_info *)dev_id;
4331 struct s2io_nic *sp = ring->nic;
4332 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4333 struct net_device *dev = sp->dev;
4334
4335 if (unlikely(!is_s2io_card_up(sp)))
4336 return IRQ_HANDLED;
4337
4338 if (sp->config.napi) {
4339 u8 __iomem *addr = NULL;
4340 u8 val8 = 0;
4341
4342 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4343 addr += (7 - ring->ring_no);
4344 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4345 writeb(val8, addr);
4346 val8 = readb(addr);
4347 netif_rx_schedule(&ring->napi);
4348 } else {
4349 rx_intr_handler(ring, 0);
4350 s2io_chk_rx_buffers(sp, ring);
4351 }
4352
4353 return IRQ_HANDLED;
4354 }
4355
4356 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4357 {
4358 int i;
4359 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4360 struct s2io_nic *sp = fifos->nic;
4361 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4362 struct config_param *config = &sp->config;
4363 u64 reason;
4364
4365 if (unlikely(!is_s2io_card_up(sp)))
4366 return IRQ_NONE;
4367
4368 reason = readq(&bar0->general_int_status);
4369 if (unlikely(reason == S2IO_MINUS_ONE))
4370 /* Nothing much can be done. Get out */
4371 return IRQ_HANDLED;
4372
4373 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4374 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4375
4376 if (reason & GEN_INTR_TXPIC)
4377 s2io_txpic_intr_handle(sp);
4378
4379 if (reason & GEN_INTR_TXTRAFFIC)
4380 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4381
4382 for (i = 0; i < config->tx_fifo_num; i++)
4383 tx_intr_handler(&fifos[i]);
4384
4385 writeq(sp->general_int_mask, &bar0->general_int_mask);
4386 readl(&bar0->general_int_status);
4387 return IRQ_HANDLED;
4388 }
4389 /* The interrupt was not raised by us */
4390 return IRQ_NONE;
4391 }
4392
4393 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4394 {
4395 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4396 u64 val64;
4397
4398 val64 = readq(&bar0->pic_int_status);
4399 if (val64 & PIC_INT_GPIO) {
4400 val64 = readq(&bar0->gpio_int_reg);
4401 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4402 (val64 & GPIO_INT_REG_LINK_UP)) {
4403 /*
4404 * This is unstable state so clear both up/down
4405 * interrupt and adapter to re-evaluate the link state.
4406 */
4407 val64 |= GPIO_INT_REG_LINK_DOWN;
4408 val64 |= GPIO_INT_REG_LINK_UP;
4409 writeq(val64, &bar0->gpio_int_reg);
4410 val64 = readq(&bar0->gpio_int_mask);
4411 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4412 GPIO_INT_MASK_LINK_DOWN);
4413 writeq(val64, &bar0->gpio_int_mask);
4414 }
4415 else if (val64 & GPIO_INT_REG_LINK_UP) {
4416 val64 = readq(&bar0->adapter_status);
4417 /* Enable Adapter */
4418 val64 = readq(&bar0->adapter_control);
4419 val64 |= ADAPTER_CNTL_EN;
4420 writeq(val64, &bar0->adapter_control);
4421 val64 |= ADAPTER_LED_ON;
4422 writeq(val64, &bar0->adapter_control);
4423 if (!sp->device_enabled_once)
4424 sp->device_enabled_once = 1;
4425
4426 s2io_link(sp, LINK_UP);
4427 /*
4428 * unmask link down interrupt and mask link-up
4429 * intr
4430 */
4431 val64 = readq(&bar0->gpio_int_mask);
4432 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4433 val64 |= GPIO_INT_MASK_LINK_UP;
4434 writeq(val64, &bar0->gpio_int_mask);
4435
4436 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4437 val64 = readq(&bar0->adapter_status);
4438 s2io_link(sp, LINK_DOWN);
4439 /* Link is down so unmaks link up interrupt */
4440 val64 = readq(&bar0->gpio_int_mask);
4441 val64 &= ~GPIO_INT_MASK_LINK_UP;
4442 val64 |= GPIO_INT_MASK_LINK_DOWN;
4443 writeq(val64, &bar0->gpio_int_mask);
4444
4445 /* turn off LED */
4446 val64 = readq(&bar0->adapter_control);
4447 val64 = val64 &(~ADAPTER_LED_ON);
4448 writeq(val64, &bar0->adapter_control);
4449 }
4450 }
4451 val64 = readq(&bar0->gpio_int_mask);
4452 }
4453
4454 /**
4455 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4456 * @value: alarm bits
4457 * @addr: address value
4458 * @cnt: counter variable
4459 * Description: Check for alarm and increment the counter
4460 * Return Value:
4461 * 1 - if alarm bit set
4462 * 0 - if alarm bit is not set
4463 */
4464 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4465 unsigned long long *cnt)
4466 {
4467 u64 val64;
4468 val64 = readq(addr);
4469 if ( val64 & value ) {
4470 writeq(val64, addr);
4471 (*cnt)++;
4472 return 1;
4473 }
4474 return 0;
4475
4476 }
4477
4478 /**
4479 * s2io_handle_errors - Xframe error indication handler
4480 * @nic: device private variable
4481 * Description: Handle alarms such as loss of link, single or
4482 * double ECC errors, critical and serious errors.
4483 * Return Value:
4484 * NONE
4485 */
4486 static void s2io_handle_errors(void * dev_id)
4487 {
4488 struct net_device *dev = (struct net_device *) dev_id;
4489 struct s2io_nic *sp = netdev_priv(dev);
4490 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4491 u64 temp64 = 0,val64=0;
4492 int i = 0;
4493
4494 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4495 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4496
4497 if (!is_s2io_card_up(sp))
4498 return;
4499
4500 if (pci_channel_offline(sp->pdev))
4501 return;
4502
4503 memset(&sw_stat->ring_full_cnt, 0,
4504 sizeof(sw_stat->ring_full_cnt));
4505
4506 /* Handling the XPAK counters update */
4507 if(stats->xpak_timer_count < 72000) {
4508 /* waiting for an hour */
4509 stats->xpak_timer_count++;
4510 } else {
4511 s2io_updt_xpak_counter(dev);
4512 /* reset the count to zero */
4513 stats->xpak_timer_count = 0;
4514 }
4515
4516 /* Handling link status change error Intr */
4517 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4518 val64 = readq(&bar0->mac_rmac_err_reg);
4519 writeq(val64, &bar0->mac_rmac_err_reg);
4520 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4521 schedule_work(&sp->set_link_task);
4522 }
4523
4524 /* In case of a serious error, the device will be Reset. */
4525 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4526 &sw_stat->serious_err_cnt))
4527 goto reset;
4528
4529 /* Check for data parity error */
4530 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4531 &sw_stat->parity_err_cnt))
4532 goto reset;
4533
4534 /* Check for ring full counter */
4535 if (sp->device_type == XFRAME_II_DEVICE) {
4536 val64 = readq(&bar0->ring_bump_counter1);
4537 for (i=0; i<4; i++) {
4538 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4539 temp64 >>= 64 - ((i+1)*16);
4540 sw_stat->ring_full_cnt[i] += temp64;
4541 }
4542
4543 val64 = readq(&bar0->ring_bump_counter2);
4544 for (i=0; i<4; i++) {
4545 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4546 temp64 >>= 64 - ((i+1)*16);
4547 sw_stat->ring_full_cnt[i+4] += temp64;
4548 }
4549 }
4550
4551 val64 = readq(&bar0->txdma_int_status);
4552 /*check for pfc_err*/
4553 if (val64 & TXDMA_PFC_INT) {
4554 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4555 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4556 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4557 &sw_stat->pfc_err_cnt))
4558 goto reset;
4559 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4560 &sw_stat->pfc_err_cnt);
4561 }
4562
4563 /*check for tda_err*/
4564 if (val64 & TXDMA_TDA_INT) {
4565 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4566 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4567 &sw_stat->tda_err_cnt))
4568 goto reset;
4569 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4570 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4571 }
4572 /*check for pcc_err*/
4573 if (val64 & TXDMA_PCC_INT) {
4574 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4575 | PCC_N_SERR | PCC_6_COF_OV_ERR
4576 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4577 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4578 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4579 &sw_stat->pcc_err_cnt))
4580 goto reset;
4581 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4582 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4583 }
4584
4585 /*check for tti_err*/
4586 if (val64 & TXDMA_TTI_INT) {
4587 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4588 &sw_stat->tti_err_cnt))
4589 goto reset;
4590 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4591 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4592 }
4593
4594 /*check for lso_err*/
4595 if (val64 & TXDMA_LSO_INT) {
4596 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4597 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4598 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4599 goto reset;
4600 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4601 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4602 }
4603
4604 /*check for tpa_err*/
4605 if (val64 & TXDMA_TPA_INT) {
4606 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4607 &sw_stat->tpa_err_cnt))
4608 goto reset;
4609 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4610 &sw_stat->tpa_err_cnt);
4611 }
4612
4613 /*check for sm_err*/
4614 if (val64 & TXDMA_SM_INT) {
4615 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4616 &sw_stat->sm_err_cnt))
4617 goto reset;
4618 }
4619
4620 val64 = readq(&bar0->mac_int_status);
4621 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4622 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4623 &bar0->mac_tmac_err_reg,
4624 &sw_stat->mac_tmac_err_cnt))
4625 goto reset;
4626 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4627 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4628 &bar0->mac_tmac_err_reg,
4629 &sw_stat->mac_tmac_err_cnt);
4630 }
4631
4632 val64 = readq(&bar0->xgxs_int_status);
4633 if (val64 & XGXS_INT_STATUS_TXGXS) {
4634 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4635 &bar0->xgxs_txgxs_err_reg,
4636 &sw_stat->xgxs_txgxs_err_cnt))
4637 goto reset;
4638 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4639 &bar0->xgxs_txgxs_err_reg,
4640 &sw_stat->xgxs_txgxs_err_cnt);
4641 }
4642
4643 val64 = readq(&bar0->rxdma_int_status);
4644 if (val64 & RXDMA_INT_RC_INT_M) {
4645 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4646 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4647 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4648 goto reset;
4649 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4650 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4651 &sw_stat->rc_err_cnt);
4652 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4653 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4654 &sw_stat->prc_pcix_err_cnt))
4655 goto reset;
4656 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4657 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4658 &sw_stat->prc_pcix_err_cnt);
4659 }
4660
4661 if (val64 & RXDMA_INT_RPA_INT_M) {
4662 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4663 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4664 goto reset;
4665 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4666 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4667 }
4668
4669 if (val64 & RXDMA_INT_RDA_INT_M) {
4670 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4671 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4672 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4673 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4674 goto reset;
4675 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4676 | RDA_MISC_ERR | RDA_PCIX_ERR,
4677 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4678 }
4679
4680 if (val64 & RXDMA_INT_RTI_INT_M) {
4681 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4682 &sw_stat->rti_err_cnt))
4683 goto reset;
4684 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4685 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4686 }
4687
4688 val64 = readq(&bar0->mac_int_status);
4689 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4690 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4691 &bar0->mac_rmac_err_reg,
4692 &sw_stat->mac_rmac_err_cnt))
4693 goto reset;
4694 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4695 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4696 &sw_stat->mac_rmac_err_cnt);
4697 }
4698
4699 val64 = readq(&bar0->xgxs_int_status);
4700 if (val64 & XGXS_INT_STATUS_RXGXS) {
4701 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4702 &bar0->xgxs_rxgxs_err_reg,
4703 &sw_stat->xgxs_rxgxs_err_cnt))
4704 goto reset;
4705 }
4706
4707 val64 = readq(&bar0->mc_int_status);
4708 if(val64 & MC_INT_STATUS_MC_INT) {
4709 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4710 &sw_stat->mc_err_cnt))
4711 goto reset;
4712
4713 /* Handling Ecc errors */
4714 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4715 writeq(val64, &bar0->mc_err_reg);
4716 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4717 sw_stat->double_ecc_errs++;
4718 if (sp->device_type != XFRAME_II_DEVICE) {
4719 /*
4720 * Reset XframeI only if critical error
4721 */
4722 if (val64 &
4723 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4724 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4725 goto reset;
4726 }
4727 } else
4728 sw_stat->single_ecc_errs++;
4729 }
4730 }
4731 return;
4732
4733 reset:
4734 s2io_stop_all_tx_queue(sp);
4735 schedule_work(&sp->rst_timer_task);
4736 sw_stat->soft_reset_cnt++;
4737 return;
4738 }
4739
4740 /**
4741 * s2io_isr - ISR handler of the device .
4742 * @irq: the irq of the device.
4743 * @dev_id: a void pointer to the dev structure of the NIC.
4744 * Description: This function is the ISR handler of the device. It
4745 * identifies the reason for the interrupt and calls the relevant
4746 * service routines. As a contongency measure, this ISR allocates the
4747 * recv buffers, if their numbers are below the panic value which is
4748 * presently set to 25% of the original number of rcv buffers allocated.
4749 * Return value:
4750 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4751 * IRQ_NONE: will be returned if interrupt is not from our device
4752 */
4753 static irqreturn_t s2io_isr(int irq, void *dev_id)
4754 {
4755 struct net_device *dev = (struct net_device *) dev_id;
4756 struct s2io_nic *sp = netdev_priv(dev);
4757 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4758 int i;
4759 u64 reason = 0;
4760 struct mac_info *mac_control;
4761 struct config_param *config;
4762
4763 /* Pretend we handled any irq's from a disconnected card */
4764 if (pci_channel_offline(sp->pdev))
4765 return IRQ_NONE;
4766
4767 if (!is_s2io_card_up(sp))
4768 return IRQ_NONE;
4769
4770 mac_control = &sp->mac_control;
4771 config = &sp->config;
4772
4773 /*
4774 * Identify the cause for interrupt and call the appropriate
4775 * interrupt handler. Causes for the interrupt could be;
4776 * 1. Rx of packet.
4777 * 2. Tx complete.
4778 * 3. Link down.
4779 */
4780 reason = readq(&bar0->general_int_status);
4781
4782 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4783 /* Nothing much can be done. Get out */
4784 return IRQ_HANDLED;
4785 }
4786
4787 if (reason & (GEN_INTR_RXTRAFFIC |
4788 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4789 {
4790 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4791
4792 if (config->napi) {
4793 if (reason & GEN_INTR_RXTRAFFIC) {
4794 netif_rx_schedule(&sp->napi);
4795 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4796 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4797 readl(&bar0->rx_traffic_int);
4798 }
4799 } else {
4800 /*
4801 * rx_traffic_int reg is an R1 register, writing all 1's
4802 * will ensure that the actual interrupt causing bit
4803 * get's cleared and hence a read can be avoided.
4804 */
4805 if (reason & GEN_INTR_RXTRAFFIC)
4806 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4807
4808 for (i = 0; i < config->rx_ring_num; i++)
4809 rx_intr_handler(&mac_control->rings[i], 0);
4810 }
4811
4812 /*
4813 * tx_traffic_int reg is an R1 register, writing all 1's
4814 * will ensure that the actual interrupt causing bit get's
4815 * cleared and hence a read can be avoided.
4816 */
4817 if (reason & GEN_INTR_TXTRAFFIC)
4818 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4819
4820 for (i = 0; i < config->tx_fifo_num; i++)
4821 tx_intr_handler(&mac_control->fifos[i]);
4822
4823 if (reason & GEN_INTR_TXPIC)
4824 s2io_txpic_intr_handle(sp);
4825
4826 /*
4827 * Reallocate the buffers from the interrupt handler itself.
4828 */
4829 if (!config->napi) {
4830 for (i = 0; i < config->rx_ring_num; i++)
4831 s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
4832 }
4833 writeq(sp->general_int_mask, &bar0->general_int_mask);
4834 readl(&bar0->general_int_status);
4835
4836 return IRQ_HANDLED;
4837
4838 }
4839 else if (!reason) {
4840 /* The interrupt was not raised by us */
4841 return IRQ_NONE;
4842 }
4843
4844 return IRQ_HANDLED;
4845 }
4846
4847 /**
4848 * s2io_updt_stats -
4849 */
4850 static void s2io_updt_stats(struct s2io_nic *sp)
4851 {
4852 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4853 u64 val64;
4854 int cnt = 0;
4855
4856 if (is_s2io_card_up(sp)) {
4857 /* Apprx 30us on a 133 MHz bus */
4858 val64 = SET_UPDT_CLICKS(10) |
4859 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4860 writeq(val64, &bar0->stat_cfg);
4861 do {
4862 udelay(100);
4863 val64 = readq(&bar0->stat_cfg);
4864 if (!(val64 & s2BIT(0)))
4865 break;
4866 cnt++;
4867 if (cnt == 5)
4868 break; /* Updt failed */
4869 } while(1);
4870 }
4871 }
4872
4873 /**
4874 * s2io_get_stats - Updates the device statistics structure.
4875 * @dev : pointer to the device structure.
4876 * Description:
4877 * This function updates the device statistics structure in the s2io_nic
4878 * structure and returns a pointer to the same.
4879 * Return value:
4880 * pointer to the updated net_device_stats structure.
4881 */
4882
4883 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4884 {
4885 struct s2io_nic *sp = netdev_priv(dev);
4886 struct mac_info *mac_control;
4887 struct config_param *config;
4888 int i;
4889
4890
4891 mac_control = &sp->mac_control;
4892 config = &sp->config;
4893
4894 /* Configure Stats for immediate updt */
4895 s2io_updt_stats(sp);
4896
4897 /* Using sp->stats as a staging area, because reset (due to mtu
4898 change, for example) will clear some hardware counters */
4899 dev->stats.tx_packets +=
4900 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4901 sp->stats.tx_packets;
4902 sp->stats.tx_packets =
4903 le32_to_cpu(mac_control->stats_info->tmac_frms);
4904 dev->stats.tx_errors +=
4905 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4906 sp->stats.tx_errors;
4907 sp->stats.tx_errors =
4908 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4909 dev->stats.rx_errors +=
4910 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4911 sp->stats.rx_errors;
4912 sp->stats.rx_errors =
4913 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4914 dev->stats.multicast =
4915 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4916 sp->stats.multicast;
4917 sp->stats.multicast =
4918 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4919 dev->stats.rx_length_errors =
4920 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4921 sp->stats.rx_length_errors;
4922 sp->stats.rx_length_errors =
4923 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4924
4925 /* collect per-ring rx_packets and rx_bytes */
4926 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4927 for (i = 0; i < config->rx_ring_num; i++) {
4928 dev->stats.rx_packets += mac_control->rings[i].rx_packets;
4929 dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4930 }
4931
4932 return (&dev->stats);
4933 }
4934
4935 /**
4936 * s2io_set_multicast - entry point for multicast address enable/disable.
4937 * @dev : pointer to the device structure
4938 * Description:
4939 * This function is a driver entry point which gets called by the kernel
4940 * whenever multicast addresses must be enabled/disabled. This also gets
4941 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4942 * determine, if multicast address must be enabled or if promiscuous mode
4943 * is to be disabled etc.
4944 * Return value:
4945 * void.
4946 */
4947
4948 static void s2io_set_multicast(struct net_device *dev)
4949 {
4950 int i, j, prev_cnt;
4951 struct dev_mc_list *mclist;
4952 struct s2io_nic *sp = netdev_priv(dev);
4953 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4954 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4955 0xfeffffffffffULL;
4956 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4957 void __iomem *add;
4958 struct config_param *config = &sp->config;
4959
4960 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4961 /* Enable all Multicast addresses */
4962 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4963 &bar0->rmac_addr_data0_mem);
4964 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4965 &bar0->rmac_addr_data1_mem);
4966 val64 = RMAC_ADDR_CMD_MEM_WE |
4967 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4968 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4969 writeq(val64, &bar0->rmac_addr_cmd_mem);
4970 /* Wait till command completes */
4971 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4972 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4973 S2IO_BIT_RESET);
4974
4975 sp->m_cast_flg = 1;
4976 sp->all_multi_pos = config->max_mc_addr - 1;
4977 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4978 /* Disable all Multicast addresses */
4979 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4980 &bar0->rmac_addr_data0_mem);
4981 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4982 &bar0->rmac_addr_data1_mem);
4983 val64 = RMAC_ADDR_CMD_MEM_WE |
4984 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4985 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4986 writeq(val64, &bar0->rmac_addr_cmd_mem);
4987 /* Wait till command completes */
4988 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4989 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4990 S2IO_BIT_RESET);
4991
4992 sp->m_cast_flg = 0;
4993 sp->all_multi_pos = 0;
4994 }
4995
4996 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4997 /* Put the NIC into promiscuous mode */
4998 add = &bar0->mac_cfg;
4999 val64 = readq(&bar0->mac_cfg);
5000 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5001
5002 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5003 writel((u32) val64, add);
5004 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5005 writel((u32) (val64 >> 32), (add + 4));
5006
5007 if (vlan_tag_strip != 1) {
5008 val64 = readq(&bar0->rx_pa_cfg);
5009 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5010 writeq(val64, &bar0->rx_pa_cfg);
5011 sp->vlan_strip_flag = 0;
5012 }
5013
5014 val64 = readq(&bar0->mac_cfg);
5015 sp->promisc_flg = 1;
5016 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5017 dev->name);
5018 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5019 /* Remove the NIC from promiscuous mode */
5020 add = &bar0->mac_cfg;
5021 val64 = readq(&bar0->mac_cfg);
5022 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5023
5024 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5025 writel((u32) val64, add);
5026 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5027 writel((u32) (val64 >> 32), (add + 4));
5028
5029 if (vlan_tag_strip != 0) {
5030 val64 = readq(&bar0->rx_pa_cfg);
5031 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5032 writeq(val64, &bar0->rx_pa_cfg);
5033 sp->vlan_strip_flag = 1;
5034 }
5035
5036 val64 = readq(&bar0->mac_cfg);
5037 sp->promisc_flg = 0;
5038 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5039 dev->name);
5040 }
5041
5042 /* Update individual M_CAST address list */
5043 if ((!sp->m_cast_flg) && dev->mc_count) {
5044 if (dev->mc_count >
5045 (config->max_mc_addr - config->max_mac_addr)) {
5046 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5047 dev->name);
5048 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5049 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5050 return;
5051 }
5052
5053 prev_cnt = sp->mc_addr_count;
5054 sp->mc_addr_count = dev->mc_count;
5055
5056 /* Clear out the previous list of Mc in the H/W. */
5057 for (i = 0; i < prev_cnt; i++) {
5058 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5059 &bar0->rmac_addr_data0_mem);
5060 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5061 &bar0->rmac_addr_data1_mem);
5062 val64 = RMAC_ADDR_CMD_MEM_WE |
5063 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5064 RMAC_ADDR_CMD_MEM_OFFSET
5065 (config->mc_start_offset + i);
5066 writeq(val64, &bar0->rmac_addr_cmd_mem);
5067
5068 /* Wait for command completes */
5069 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5070 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5071 S2IO_BIT_RESET)) {
5072 DBG_PRINT(ERR_DBG, "%s: Adding ",
5073 dev->name);
5074 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5075 return;
5076 }
5077 }
5078
5079 /* Create the new Rx filter list and update the same in H/W. */
5080 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5081 i++, mclist = mclist->next) {
5082 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5083 ETH_ALEN);
5084 mac_addr = 0;
5085 for (j = 0; j < ETH_ALEN; j++) {
5086 mac_addr |= mclist->dmi_addr[j];
5087 mac_addr <<= 8;
5088 }
5089 mac_addr >>= 8;
5090 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5091 &bar0->rmac_addr_data0_mem);
5092 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5093 &bar0->rmac_addr_data1_mem);
5094 val64 = RMAC_ADDR_CMD_MEM_WE |
5095 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5096 RMAC_ADDR_CMD_MEM_OFFSET
5097 (i + config->mc_start_offset);
5098 writeq(val64, &bar0->rmac_addr_cmd_mem);
5099
5100 /* Wait for command completes */
5101 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5102 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5103 S2IO_BIT_RESET)) {
5104 DBG_PRINT(ERR_DBG, "%s: Adding ",
5105 dev->name);
5106 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5107 return;
5108 }
5109 }
5110 }
5111 }
5112
5113 /* read from CAM unicast & multicast addresses and store it in
5114 * def_mac_addr structure
5115 */
5116 void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5117 {
5118 int offset;
5119 u64 mac_addr = 0x0;
5120 struct config_param *config = &sp->config;
5121
5122 /* store unicast & multicast mac addresses */
5123 for (offset = 0; offset < config->max_mc_addr; offset++) {
5124 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5125 /* if read fails disable the entry */
5126 if (mac_addr == FAILURE)
5127 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5128 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5129 }
5130 }
5131
5132 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5133 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5134 {
5135 int offset;
5136 struct config_param *config = &sp->config;
5137 /* restore unicast mac address */
5138 for (offset = 0; offset < config->max_mac_addr; offset++)
5139 do_s2io_prog_unicast(sp->dev,
5140 sp->def_mac_addr[offset].mac_addr);
5141
5142 /* restore multicast mac address */
5143 for (offset = config->mc_start_offset;
5144 offset < config->max_mc_addr; offset++)
5145 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5146 }
5147
5148 /* add a multicast MAC address to CAM */
5149 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5150 {
5151 int i;
5152 u64 mac_addr = 0;
5153 struct config_param *config = &sp->config;
5154
5155 for (i = 0; i < ETH_ALEN; i++) {
5156 mac_addr <<= 8;
5157 mac_addr |= addr[i];
5158 }
5159 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5160 return SUCCESS;
5161
5162 /* check if the multicast mac already preset in CAM */
5163 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5164 u64 tmp64;
5165 tmp64 = do_s2io_read_unicast_mc(sp, i);
5166 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5167 break;
5168
5169 if (tmp64 == mac_addr)
5170 return SUCCESS;
5171 }
5172 if (i == config->max_mc_addr) {
5173 DBG_PRINT(ERR_DBG,
5174 "CAM full no space left for multicast MAC\n");
5175 return FAILURE;
5176 }
5177 /* Update the internal structure with this new mac address */
5178 do_s2io_copy_mac_addr(sp, i, mac_addr);
5179
5180 return (do_s2io_add_mac(sp, mac_addr, i));
5181 }
5182
5183 /* add MAC address to CAM */
5184 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5185 {
5186 u64 val64;
5187 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5188
5189 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5190 &bar0->rmac_addr_data0_mem);
5191
5192 val64 =
5193 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5194 RMAC_ADDR_CMD_MEM_OFFSET(off);
5195 writeq(val64, &bar0->rmac_addr_cmd_mem);
5196
5197 /* Wait till command completes */
5198 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5199 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5200 S2IO_BIT_RESET)) {
5201 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5202 return FAILURE;
5203 }
5204 return SUCCESS;
5205 }
5206 /* deletes a specified unicast/multicast mac entry from CAM */
5207 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5208 {
5209 int offset;
5210 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5211 struct config_param *config = &sp->config;
5212
5213 for (offset = 1;
5214 offset < config->max_mc_addr; offset++) {
5215 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5216 if (tmp64 == addr) {
5217 /* disable the entry by writing 0xffffffffffffULL */
5218 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5219 return FAILURE;
5220 /* store the new mac list from CAM */
5221 do_s2io_store_unicast_mc(sp);
5222 return SUCCESS;
5223 }
5224 }
5225 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5226 (unsigned long long)addr);
5227 return FAILURE;
5228 }
5229
5230 /* read mac entries from CAM */
5231 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5232 {
5233 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5234 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5235
5236 /* read mac addr */
5237 val64 =
5238 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5239 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5240 writeq(val64, &bar0->rmac_addr_cmd_mem);
5241
5242 /* Wait till command completes */
5243 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5244 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5245 S2IO_BIT_RESET)) {
5246 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5247 return FAILURE;
5248 }
5249 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5250 return (tmp64 >> 16);
5251 }
5252
5253 /**
5254 * s2io_set_mac_addr driver entry point
5255 */
5256
5257 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5258 {
5259 struct sockaddr *addr = p;
5260
5261 if (!is_valid_ether_addr(addr->sa_data))
5262 return -EINVAL;
5263
5264 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5265
5266 /* store the MAC address in CAM */
5267 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5268 }
5269 /**
5270 * do_s2io_prog_unicast - Programs the Xframe mac address
5271 * @dev : pointer to the device structure.
5272 * @addr: a uchar pointer to the new mac address which is to be set.
5273 * Description : This procedure will program the Xframe to receive
5274 * frames with new Mac Address
5275 * Return value: SUCCESS on success and an appropriate (-)ve integer
5276 * as defined in errno.h file on failure.
5277 */
5278
5279 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5280 {
5281 struct s2io_nic *sp = netdev_priv(dev);
5282 register u64 mac_addr = 0, perm_addr = 0;
5283 int i;
5284 u64 tmp64;
5285 struct config_param *config = &sp->config;
5286
5287 /*
5288 * Set the new MAC address as the new unicast filter and reflect this
5289 * change on the device address registered with the OS. It will be
5290 * at offset 0.
5291 */
5292 for (i = 0; i < ETH_ALEN; i++) {
5293 mac_addr <<= 8;
5294 mac_addr |= addr[i];
5295 perm_addr <<= 8;
5296 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5297 }
5298
5299 /* check if the dev_addr is different than perm_addr */
5300 if (mac_addr == perm_addr)
5301 return SUCCESS;
5302
5303 /* check if the mac already preset in CAM */
5304 for (i = 1; i < config->max_mac_addr; i++) {
5305 tmp64 = do_s2io_read_unicast_mc(sp, i);
5306 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5307 break;
5308
5309 if (tmp64 == mac_addr) {
5310 DBG_PRINT(INFO_DBG,
5311 "MAC addr:0x%llx already present in CAM\n",
5312 (unsigned long long)mac_addr);
5313 return SUCCESS;
5314 }
5315 }
5316 if (i == config->max_mac_addr) {
5317 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5318 return FAILURE;
5319 }
5320 /* Update the internal structure with this new mac address */
5321 do_s2io_copy_mac_addr(sp, i, mac_addr);
5322 return (do_s2io_add_mac(sp, mac_addr, i));
5323 }
5324
5325 /**
5326 * s2io_ethtool_sset - Sets different link parameters.
5327 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5328 * @info: pointer to the structure with parameters given by ethtool to set
5329 * link information.
5330 * Description:
5331 * The function sets different link parameters provided by the user onto
5332 * the NIC.
5333 * Return value:
5334 * 0 on success.
5335 */
5336
5337 static int s2io_ethtool_sset(struct net_device *dev,
5338 struct ethtool_cmd *info)
5339 {
5340 struct s2io_nic *sp = netdev_priv(dev);
5341 if ((info->autoneg == AUTONEG_ENABLE) ||
5342 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5343 return -EINVAL;
5344 else {
5345 s2io_close(sp->dev);
5346 s2io_open(sp->dev);
5347 }
5348
5349 return 0;
5350 }
5351
5352 /**
5353 * s2io_ethtol_gset - Return link specific information.
5354 * @sp : private member of the device structure, pointer to the
5355 * s2io_nic structure.
5356 * @info : pointer to the structure with parameters given by ethtool
5357 * to return link information.
5358 * Description:
5359 * Returns link specific information like speed, duplex etc.. to ethtool.
5360 * Return value :
5361 * return 0 on success.
5362 */
5363
5364 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5365 {
5366 struct s2io_nic *sp = netdev_priv(dev);
5367 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5368 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5369 info->port = PORT_FIBRE;
5370
5371 /* info->transceiver */
5372 info->transceiver = XCVR_EXTERNAL;
5373
5374 if (netif_carrier_ok(sp->dev)) {
5375 info->speed = 10000;
5376 info->duplex = DUPLEX_FULL;
5377 } else {
5378 info->speed = -1;
5379 info->duplex = -1;
5380 }
5381
5382 info->autoneg = AUTONEG_DISABLE;
5383 return 0;
5384 }
5385
5386 /**
5387 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5388 * @sp : private member of the device structure, which is a pointer to the
5389 * s2io_nic structure.
5390 * @info : pointer to the structure with parameters given by ethtool to
5391 * return driver information.
5392 * Description:
5393 * Returns driver specefic information like name, version etc.. to ethtool.
5394 * Return value:
5395 * void
5396 */
5397
5398 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5399 struct ethtool_drvinfo *info)
5400 {
5401 struct s2io_nic *sp = netdev_priv(dev);
5402
5403 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5404 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5405 strncpy(info->fw_version, "", sizeof(info->fw_version));
5406 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5407 info->regdump_len = XENA_REG_SPACE;
5408 info->eedump_len = XENA_EEPROM_SPACE;
5409 }
5410
5411 /**
5412 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5413 * @sp: private member of the device structure, which is a pointer to the
5414 * s2io_nic structure.
5415 * @regs : pointer to the structure with parameters given by ethtool for
5416 * dumping the registers.
5417 * @reg_space: The input argumnet into which all the registers are dumped.
5418 * Description:
5419 * Dumps the entire register space of xFrame NIC into the user given
5420 * buffer area.
5421 * Return value :
5422 * void .
5423 */
5424
5425 static void s2io_ethtool_gregs(struct net_device *dev,
5426 struct ethtool_regs *regs, void *space)
5427 {
5428 int i;
5429 u64 reg;
5430 u8 *reg_space = (u8 *) space;
5431 struct s2io_nic *sp = netdev_priv(dev);
5432
5433 regs->len = XENA_REG_SPACE;
5434 regs->version = sp->pdev->subsystem_device;
5435
5436 for (i = 0; i < regs->len; i += 8) {
5437 reg = readq(sp->bar0 + i);
5438 memcpy((reg_space + i), &reg, 8);
5439 }
5440 }
5441
5442 /**
5443 * s2io_phy_id - timer function that alternates adapter LED.
5444 * @data : address of the private member of the device structure, which
5445 * is a pointer to the s2io_nic structure, provided as an u32.
5446 * Description: This is actually the timer function that alternates the
5447 * adapter LED bit of the adapter control bit to set/reset every time on
5448 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5449 * once every second.
5450 */
5451 static void s2io_phy_id(unsigned long data)
5452 {
5453 struct s2io_nic *sp = (struct s2io_nic *) data;
5454 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5455 u64 val64 = 0;
5456 u16 subid;
5457
5458 subid = sp->pdev->subsystem_device;
5459 if ((sp->device_type == XFRAME_II_DEVICE) ||
5460 ((subid & 0xFF) >= 0x07)) {
5461 val64 = readq(&bar0->gpio_control);
5462 val64 ^= GPIO_CTRL_GPIO_0;
5463 writeq(val64, &bar0->gpio_control);
5464 } else {
5465 val64 = readq(&bar0->adapter_control);
5466 val64 ^= ADAPTER_LED_ON;
5467 writeq(val64, &bar0->adapter_control);
5468 }
5469
5470 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5471 }
5472
5473 /**
5474 * s2io_ethtool_idnic - To physically identify the nic on the system.
5475 * @sp : private member of the device structure, which is a pointer to the
5476 * s2io_nic structure.
5477 * @id : pointer to the structure with identification parameters given by
5478 * ethtool.
5479 * Description: Used to physically identify the NIC on the system.
5480 * The Link LED will blink for a time specified by the user for
5481 * identification.
5482 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5483 * identification is possible only if it's link is up.
5484 * Return value:
5485 * int , returns 0 on success
5486 */
5487
5488 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5489 {
5490 u64 val64 = 0, last_gpio_ctrl_val;
5491 struct s2io_nic *sp = netdev_priv(dev);
5492 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5493 u16 subid;
5494
5495 subid = sp->pdev->subsystem_device;
5496 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5497 if ((sp->device_type == XFRAME_I_DEVICE) &&
5498 ((subid & 0xFF) < 0x07)) {
5499 val64 = readq(&bar0->adapter_control);
5500 if (!(val64 & ADAPTER_CNTL_EN)) {
5501 printk(KERN_ERR
5502 "Adapter Link down, cannot blink LED\n");
5503 return -EFAULT;
5504 }
5505 }
5506 if (sp->id_timer.function == NULL) {
5507 init_timer(&sp->id_timer);
5508 sp->id_timer.function = s2io_phy_id;
5509 sp->id_timer.data = (unsigned long) sp;
5510 }
5511 mod_timer(&sp->id_timer, jiffies);
5512 if (data)
5513 msleep_interruptible(data * HZ);
5514 else
5515 msleep_interruptible(MAX_FLICKER_TIME);
5516 del_timer_sync(&sp->id_timer);
5517
5518 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5519 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5520 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5521 }
5522
5523 return 0;
5524 }
5525
5526 static void s2io_ethtool_gringparam(struct net_device *dev,
5527 struct ethtool_ringparam *ering)
5528 {
5529 struct s2io_nic *sp = netdev_priv(dev);
5530 int i,tx_desc_count=0,rx_desc_count=0;
5531
5532 if (sp->rxd_mode == RXD_MODE_1)
5533 ering->rx_max_pending = MAX_RX_DESC_1;
5534 else if (sp->rxd_mode == RXD_MODE_3B)
5535 ering->rx_max_pending = MAX_RX_DESC_2;
5536
5537 ering->tx_max_pending = MAX_TX_DESC;
5538 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5539 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5540
5541 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5542 ering->tx_pending = tx_desc_count;
5543 rx_desc_count = 0;
5544 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5545 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5546
5547 ering->rx_pending = rx_desc_count;
5548
5549 ering->rx_mini_max_pending = 0;
5550 ering->rx_mini_pending = 0;
5551 if(sp->rxd_mode == RXD_MODE_1)
5552 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5553 else if (sp->rxd_mode == RXD_MODE_3B)
5554 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5555 ering->rx_jumbo_pending = rx_desc_count;
5556 }
5557
5558 /**
5559 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5560 * @sp : private member of the device structure, which is a pointer to the
5561 * s2io_nic structure.
5562 * @ep : pointer to the structure with pause parameters given by ethtool.
5563 * Description:
5564 * Returns the Pause frame generation and reception capability of the NIC.
5565 * Return value:
5566 * void
5567 */
5568 static void s2io_ethtool_getpause_data(struct net_device *dev,
5569 struct ethtool_pauseparam *ep)
5570 {
5571 u64 val64;
5572 struct s2io_nic *sp = netdev_priv(dev);
5573 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5574
5575 val64 = readq(&bar0->rmac_pause_cfg);
5576 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5577 ep->tx_pause = TRUE;
5578 if (val64 & RMAC_PAUSE_RX_ENABLE)
5579 ep->rx_pause = TRUE;
5580 ep->autoneg = FALSE;
5581 }
5582
5583 /**
5584 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5585 * @sp : private member of the device structure, which is a pointer to the
5586 * s2io_nic structure.
5587 * @ep : pointer to the structure with pause parameters given by ethtool.
5588 * Description:
5589 * It can be used to set or reset Pause frame generation or reception
5590 * support of the NIC.
5591 * Return value:
5592 * int, returns 0 on Success
5593 */
5594
5595 static int s2io_ethtool_setpause_data(struct net_device *dev,
5596 struct ethtool_pauseparam *ep)
5597 {
5598 u64 val64;
5599 struct s2io_nic *sp = netdev_priv(dev);
5600 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5601
5602 val64 = readq(&bar0->rmac_pause_cfg);
5603 if (ep->tx_pause)
5604 val64 |= RMAC_PAUSE_GEN_ENABLE;
5605 else
5606 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5607 if (ep->rx_pause)
5608 val64 |= RMAC_PAUSE_RX_ENABLE;
5609 else
5610 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5611 writeq(val64, &bar0->rmac_pause_cfg);
5612 return 0;
5613 }
5614
5615 /**
5616 * read_eeprom - reads 4 bytes of data from user given offset.
5617 * @sp : private member of the device structure, which is a pointer to the
5618 * s2io_nic structure.
5619 * @off : offset at which the data must be written
5620 * @data : Its an output parameter where the data read at the given
5621 * offset is stored.
5622 * Description:
5623 * Will read 4 bytes of data from the user given offset and return the
5624 * read data.
5625 * NOTE: Will allow to read only part of the EEPROM visible through the
5626 * I2C bus.
5627 * Return value:
5628 * -1 on failure and 0 on success.
5629 */
5630
5631 #define S2IO_DEV_ID 5
5632 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5633 {
5634 int ret = -1;
5635 u32 exit_cnt = 0;
5636 u64 val64;
5637 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5638
5639 if (sp->device_type == XFRAME_I_DEVICE) {
5640 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5641 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5642 I2C_CONTROL_CNTL_START;
5643 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5644
5645 while (exit_cnt < 5) {
5646 val64 = readq(&bar0->i2c_control);
5647 if (I2C_CONTROL_CNTL_END(val64)) {
5648 *data = I2C_CONTROL_GET_DATA(val64);
5649 ret = 0;
5650 break;
5651 }
5652 msleep(50);
5653 exit_cnt++;
5654 }
5655 }
5656
5657 if (sp->device_type == XFRAME_II_DEVICE) {
5658 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5659 SPI_CONTROL_BYTECNT(0x3) |
5660 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5661 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5662 val64 |= SPI_CONTROL_REQ;
5663 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5664 while (exit_cnt < 5) {
5665 val64 = readq(&bar0->spi_control);
5666 if (val64 & SPI_CONTROL_NACK) {
5667 ret = 1;
5668 break;
5669 } else if (val64 & SPI_CONTROL_DONE) {
5670 *data = readq(&bar0->spi_data);
5671 *data &= 0xffffff;
5672 ret = 0;
5673 break;
5674 }
5675 msleep(50);
5676 exit_cnt++;
5677 }
5678 }
5679 return ret;
5680 }
5681
5682 /**
5683 * write_eeprom - actually writes the relevant part of the data value.
5684 * @sp : private member of the device structure, which is a pointer to the
5685 * s2io_nic structure.
5686 * @off : offset at which the data must be written
5687 * @data : The data that is to be written
5688 * @cnt : Number of bytes of the data that are actually to be written into
5689 * the Eeprom. (max of 3)
5690 * Description:
5691 * Actually writes the relevant part of the data value into the Eeprom
5692 * through the I2C bus.
5693 * Return value:
5694 * 0 on success, -1 on failure.
5695 */
5696
5697 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5698 {
5699 int exit_cnt = 0, ret = -1;
5700 u64 val64;
5701 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5702
5703 if (sp->device_type == XFRAME_I_DEVICE) {
5704 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5705 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5706 I2C_CONTROL_CNTL_START;
5707 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5708
5709 while (exit_cnt < 5) {
5710 val64 = readq(&bar0->i2c_control);
5711 if (I2C_CONTROL_CNTL_END(val64)) {
5712 if (!(val64 & I2C_CONTROL_NACK))
5713 ret = 0;
5714 break;
5715 }
5716 msleep(50);
5717 exit_cnt++;
5718 }
5719 }
5720
5721 if (sp->device_type == XFRAME_II_DEVICE) {
5722 int write_cnt = (cnt == 8) ? 0 : cnt;
5723 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5724
5725 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5726 SPI_CONTROL_BYTECNT(write_cnt) |
5727 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5728 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5729 val64 |= SPI_CONTROL_REQ;
5730 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5731 while (exit_cnt < 5) {
5732 val64 = readq(&bar0->spi_control);
5733 if (val64 & SPI_CONTROL_NACK) {
5734 ret = 1;
5735 break;
5736 } else if (val64 & SPI_CONTROL_DONE) {
5737 ret = 0;
5738 break;
5739 }
5740 msleep(50);
5741 exit_cnt++;
5742 }
5743 }
5744 return ret;
5745 }
5746 static void s2io_vpd_read(struct s2io_nic *nic)
5747 {
5748 u8 *vpd_data;
5749 u8 data;
5750 int i=0, cnt, fail = 0;
5751 int vpd_addr = 0x80;
5752
5753 if (nic->device_type == XFRAME_II_DEVICE) {
5754 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5755 vpd_addr = 0x80;
5756 }
5757 else {
5758 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5759 vpd_addr = 0x50;
5760 }
5761 strcpy(nic->serial_num, "NOT AVAILABLE");
5762
5763 vpd_data = kmalloc(256, GFP_KERNEL);
5764 if (!vpd_data) {
5765 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5766 return;
5767 }
5768 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5769
5770 for (i = 0; i < 256; i +=4 ) {
5771 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5772 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5773 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5774 for (cnt = 0; cnt <5; cnt++) {
5775 msleep(2);
5776 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5777 if (data == 0x80)
5778 break;
5779 }
5780 if (cnt >= 5) {
5781 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5782 fail = 1;
5783 break;
5784 }
5785 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5786 (u32 *)&vpd_data[i]);
5787 }
5788
5789 if(!fail) {
5790 /* read serial number of adapter */
5791 for (cnt = 0; cnt < 256; cnt++) {
5792 if ((vpd_data[cnt] == 'S') &&
5793 (vpd_data[cnt+1] == 'N') &&
5794 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5795 memset(nic->serial_num, 0, VPD_STRING_LEN);
5796 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5797 vpd_data[cnt+2]);
5798 break;
5799 }
5800 }
5801 }
5802
5803 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5804 memset(nic->product_name, 0, vpd_data[1]);
5805 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5806 }
5807 kfree(vpd_data);
5808 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5809 }
5810
5811 /**
5812 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5813 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5814 * @eeprom : pointer to the user level structure provided by ethtool,
5815 * containing all relevant information.
5816 * @data_buf : user defined value to be written into Eeprom.
5817 * Description: Reads the values stored in the Eeprom at given offset
5818 * for a given length. Stores these values int the input argument data
5819 * buffer 'data_buf' and returns these to the caller (ethtool.)
5820 * Return value:
5821 * int 0 on success
5822 */
5823
5824 static int s2io_ethtool_geeprom(struct net_device *dev,
5825 struct ethtool_eeprom *eeprom, u8 * data_buf)
5826 {
5827 u32 i, valid;
5828 u64 data;
5829 struct s2io_nic *sp = netdev_priv(dev);
5830
5831 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5832
5833 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5834 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5835
5836 for (i = 0; i < eeprom->len; i += 4) {
5837 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5838 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5839 return -EFAULT;
5840 }
5841 valid = INV(data);
5842 memcpy((data_buf + i), &valid, 4);
5843 }
5844 return 0;
5845 }
5846
5847 /**
5848 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5849 * @sp : private member of the device structure, which is a pointer to the
5850 * s2io_nic structure.
5851 * @eeprom : pointer to the user level structure provided by ethtool,
5852 * containing all relevant information.
5853 * @data_buf ; user defined value to be written into Eeprom.
5854 * Description:
5855 * Tries to write the user provided value in the Eeprom, at the offset
5856 * given by the user.
5857 * Return value:
5858 * 0 on success, -EFAULT on failure.
5859 */
5860
5861 static int s2io_ethtool_seeprom(struct net_device *dev,
5862 struct ethtool_eeprom *eeprom,
5863 u8 * data_buf)
5864 {
5865 int len = eeprom->len, cnt = 0;
5866 u64 valid = 0, data;
5867 struct s2io_nic *sp = netdev_priv(dev);
5868
5869 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5870 DBG_PRINT(ERR_DBG,
5871 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5872 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5873 eeprom->magic);
5874 return -EFAULT;
5875 }
5876
5877 while (len) {
5878 data = (u32) data_buf[cnt] & 0x000000FF;
5879 if (data) {
5880 valid = (u32) (data << 24);
5881 } else
5882 valid = data;
5883
5884 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5885 DBG_PRINT(ERR_DBG,
5886 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5887 DBG_PRINT(ERR_DBG,
5888 "write into the specified offset\n");
5889 return -EFAULT;
5890 }
5891 cnt++;
5892 len--;
5893 }
5894
5895 return 0;
5896 }
5897
5898 /**
5899 * s2io_register_test - reads and writes into all clock domains.
5900 * @sp : private member of the device structure, which is a pointer to the
5901 * s2io_nic structure.
5902 * @data : variable that returns the result of each of the test conducted b
5903 * by the driver.
5904 * Description:
5905 * Read and write into all clock domains. The NIC has 3 clock domains,
5906 * see that registers in all the three regions are accessible.
5907 * Return value:
5908 * 0 on success.
5909 */
5910
5911 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5912 {
5913 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5914 u64 val64 = 0, exp_val;
5915 int fail = 0;
5916
5917 val64 = readq(&bar0->pif_rd_swapper_fb);
5918 if (val64 != 0x123456789abcdefULL) {
5919 fail = 1;
5920 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5921 }
5922
5923 val64 = readq(&bar0->rmac_pause_cfg);
5924 if (val64 != 0xc000ffff00000000ULL) {
5925 fail = 1;
5926 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5927 }
5928
5929 val64 = readq(&bar0->rx_queue_cfg);
5930 if (sp->device_type == XFRAME_II_DEVICE)
5931 exp_val = 0x0404040404040404ULL;
5932 else
5933 exp_val = 0x0808080808080808ULL;
5934 if (val64 != exp_val) {
5935 fail = 1;
5936 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5937 }
5938
5939 val64 = readq(&bar0->xgxs_efifo_cfg);
5940 if (val64 != 0x000000001923141EULL) {
5941 fail = 1;
5942 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5943 }
5944
5945 val64 = 0x5A5A5A5A5A5A5A5AULL;
5946 writeq(val64, &bar0->xmsi_data);
5947 val64 = readq(&bar0->xmsi_data);
5948 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5949 fail = 1;
5950 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5951 }
5952
5953 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5954 writeq(val64, &bar0->xmsi_data);
5955 val64 = readq(&bar0->xmsi_data);
5956 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5957 fail = 1;
5958 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5959 }
5960
5961 *data = fail;
5962 return fail;
5963 }
5964
5965 /**
5966 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5967 * @sp : private member of the device structure, which is a pointer to the
5968 * s2io_nic structure.
5969 * @data:variable that returns the result of each of the test conducted by
5970 * the driver.
5971 * Description:
5972 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5973 * register.
5974 * Return value:
5975 * 0 on success.
5976 */
5977
5978 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5979 {
5980 int fail = 0;
5981 u64 ret_data, org_4F0, org_7F0;
5982 u8 saved_4F0 = 0, saved_7F0 = 0;
5983 struct net_device *dev = sp->dev;
5984
5985 /* Test Write Error at offset 0 */
5986 /* Note that SPI interface allows write access to all areas
5987 * of EEPROM. Hence doing all negative testing only for Xframe I.
5988 */
5989 if (sp->device_type == XFRAME_I_DEVICE)
5990 if (!write_eeprom(sp, 0, 0, 3))
5991 fail = 1;
5992
5993 /* Save current values at offsets 0x4F0 and 0x7F0 */
5994 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5995 saved_4F0 = 1;
5996 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5997 saved_7F0 = 1;
5998
5999 /* Test Write at offset 4f0 */
6000 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6001 fail = 1;
6002 if (read_eeprom(sp, 0x4F0, &ret_data))
6003 fail = 1;
6004
6005 if (ret_data != 0x012345) {
6006 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6007 "Data written %llx Data read %llx\n",
6008 dev->name, (unsigned long long)0x12345,
6009 (unsigned long long)ret_data);
6010 fail = 1;
6011 }
6012
6013 /* Reset the EEPROM data go FFFF */
6014 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6015
6016 /* Test Write Request Error at offset 0x7c */
6017 if (sp->device_type == XFRAME_I_DEVICE)
6018 if (!write_eeprom(sp, 0x07C, 0, 3))
6019 fail = 1;
6020
6021 /* Test Write Request at offset 0x7f0 */
6022 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6023 fail = 1;
6024 if (read_eeprom(sp, 0x7F0, &ret_data))
6025 fail = 1;
6026
6027 if (ret_data != 0x012345) {
6028 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6029 "Data written %llx Data read %llx\n",
6030 dev->name, (unsigned long long)0x12345,
6031 (unsigned long long)ret_data);
6032 fail = 1;
6033 }
6034
6035 /* Reset the EEPROM data go FFFF */
6036 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6037
6038 if (sp->device_type == XFRAME_I_DEVICE) {
6039 /* Test Write Error at offset 0x80 */
6040 if (!write_eeprom(sp, 0x080, 0, 3))
6041 fail = 1;
6042
6043 /* Test Write Error at offset 0xfc */
6044 if (!write_eeprom(sp, 0x0FC, 0, 3))
6045 fail = 1;
6046
6047 /* Test Write Error at offset 0x100 */
6048 if (!write_eeprom(sp, 0x100, 0, 3))
6049 fail = 1;
6050
6051 /* Test Write Error at offset 4ec */
6052 if (!write_eeprom(sp, 0x4EC, 0, 3))
6053 fail = 1;
6054 }
6055
6056 /* Restore values at offsets 0x4F0 and 0x7F0 */
6057 if (saved_4F0)
6058 write_eeprom(sp, 0x4F0, org_4F0, 3);
6059 if (saved_7F0)
6060 write_eeprom(sp, 0x7F0, org_7F0, 3);
6061
6062 *data = fail;
6063 return fail;
6064 }
6065
6066 /**
6067 * s2io_bist_test - invokes the MemBist test of the card .
6068 * @sp : private member of the device structure, which is a pointer to the
6069 * s2io_nic structure.
6070 * @data:variable that returns the result of each of the test conducted by
6071 * the driver.
6072 * Description:
6073 * This invokes the MemBist test of the card. We give around
6074 * 2 secs time for the Test to complete. If it's still not complete
6075 * within this peiod, we consider that the test failed.
6076 * Return value:
6077 * 0 on success and -1 on failure.
6078 */
6079
6080 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
6081 {
6082 u8 bist = 0;
6083 int cnt = 0, ret = -1;
6084
6085 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6086 bist |= PCI_BIST_START;
6087 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6088
6089 while (cnt < 20) {
6090 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6091 if (!(bist & PCI_BIST_START)) {
6092 *data = (bist & PCI_BIST_CODE_MASK);
6093 ret = 0;
6094 break;
6095 }
6096 msleep(100);
6097 cnt++;
6098 }
6099
6100 return ret;
6101 }
6102
6103 /**
6104 * s2io-link_test - verifies the link state of the nic
6105 * @sp ; private member of the device structure, which is a pointer to the
6106 * s2io_nic structure.
6107 * @data: variable that returns the result of each of the test conducted by
6108 * the driver.
6109 * Description:
6110 * The function verifies the link state of the NIC and updates the input
6111 * argument 'data' appropriately.
6112 * Return value:
6113 * 0 on success.
6114 */
6115
6116 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
6117 {
6118 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6119 u64 val64;
6120
6121 val64 = readq(&bar0->adapter_status);
6122 if(!(LINK_IS_UP(val64)))
6123 *data = 1;
6124 else
6125 *data = 0;
6126
6127 return *data;
6128 }
6129
6130 /**
6131 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6132 * @sp - private member of the device structure, which is a pointer to the
6133 * s2io_nic structure.
6134 * @data - variable that returns the result of each of the test
6135 * conducted by the driver.
6136 * Description:
6137 * This is one of the offline test that tests the read and write
6138 * access to the RldRam chip on the NIC.
6139 * Return value:
6140 * 0 on success.
6141 */
6142
6143 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
6144 {
6145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6146 u64 val64;
6147 int cnt, iteration = 0, test_fail = 0;
6148
6149 val64 = readq(&bar0->adapter_control);
6150 val64 &= ~ADAPTER_ECC_EN;
6151 writeq(val64, &bar0->adapter_control);
6152
6153 val64 = readq(&bar0->mc_rldram_test_ctrl);
6154 val64 |= MC_RLDRAM_TEST_MODE;
6155 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6156
6157 val64 = readq(&bar0->mc_rldram_mrs);
6158 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6159 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6160
6161 val64 |= MC_RLDRAM_MRS_ENABLE;
6162 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6163
6164 while (iteration < 2) {
6165 val64 = 0x55555555aaaa0000ULL;
6166 if (iteration == 1) {
6167 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6168 }
6169 writeq(val64, &bar0->mc_rldram_test_d0);
6170
6171 val64 = 0xaaaa5a5555550000ULL;
6172 if (iteration == 1) {
6173 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6174 }
6175 writeq(val64, &bar0->mc_rldram_test_d1);
6176
6177 val64 = 0x55aaaaaaaa5a0000ULL;
6178 if (iteration == 1) {
6179 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6180 }
6181 writeq(val64, &bar0->mc_rldram_test_d2);
6182
6183 val64 = (u64) (0x0000003ffffe0100ULL);
6184 writeq(val64, &bar0->mc_rldram_test_add);
6185
6186 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6187 MC_RLDRAM_TEST_GO;
6188 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6189
6190 for (cnt = 0; cnt < 5; cnt++) {
6191 val64 = readq(&bar0->mc_rldram_test_ctrl);
6192 if (val64 & MC_RLDRAM_TEST_DONE)
6193 break;
6194 msleep(200);
6195 }
6196
6197 if (cnt == 5)
6198 break;
6199
6200 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6201 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6202
6203 for (cnt = 0; cnt < 5; cnt++) {
6204 val64 = readq(&bar0->mc_rldram_test_ctrl);
6205 if (val64 & MC_RLDRAM_TEST_DONE)
6206 break;
6207 msleep(500);
6208 }
6209
6210 if (cnt == 5)
6211 break;
6212
6213 val64 = readq(&bar0->mc_rldram_test_ctrl);
6214 if (!(val64 & MC_RLDRAM_TEST_PASS))
6215 test_fail = 1;
6216
6217 iteration++;
6218 }
6219
6220 *data = test_fail;
6221
6222 /* Bring the adapter out of test mode */
6223 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6224
6225 return test_fail;
6226 }
6227
6228 /**
6229 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6230 * @sp : private member of the device structure, which is a pointer to the
6231 * s2io_nic structure.
6232 * @ethtest : pointer to a ethtool command specific structure that will be
6233 * returned to the user.
6234 * @data : variable that returns the result of each of the test
6235 * conducted by the driver.
6236 * Description:
6237 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6238 * the health of the card.
6239 * Return value:
6240 * void
6241 */
6242
6243 static void s2io_ethtool_test(struct net_device *dev,
6244 struct ethtool_test *ethtest,
6245 uint64_t * data)
6246 {
6247 struct s2io_nic *sp = netdev_priv(dev);
6248 int orig_state = netif_running(sp->dev);
6249
6250 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6251 /* Offline Tests. */
6252 if (orig_state)
6253 s2io_close(sp->dev);
6254
6255 if (s2io_register_test(sp, &data[0]))
6256 ethtest->flags |= ETH_TEST_FL_FAILED;
6257
6258 s2io_reset(sp);
6259
6260 if (s2io_rldram_test(sp, &data[3]))
6261 ethtest->flags |= ETH_TEST_FL_FAILED;
6262
6263 s2io_reset(sp);
6264
6265 if (s2io_eeprom_test(sp, &data[1]))
6266 ethtest->flags |= ETH_TEST_FL_FAILED;
6267
6268 if (s2io_bist_test(sp, &data[4]))
6269 ethtest->flags |= ETH_TEST_FL_FAILED;
6270
6271 if (orig_state)
6272 s2io_open(sp->dev);
6273
6274 data[2] = 0;
6275 } else {
6276 /* Online Tests. */
6277 if (!orig_state) {
6278 DBG_PRINT(ERR_DBG,
6279 "%s: is not up, cannot run test\n",
6280 dev->name);
6281 data[0] = -1;
6282 data[1] = -1;
6283 data[2] = -1;
6284 data[3] = -1;
6285 data[4] = -1;
6286 }
6287
6288 if (s2io_link_test(sp, &data[2]))
6289 ethtest->flags |= ETH_TEST_FL_FAILED;
6290
6291 data[0] = 0;
6292 data[1] = 0;
6293 data[3] = 0;
6294 data[4] = 0;
6295 }
6296 }
6297
6298 static void s2io_get_ethtool_stats(struct net_device *dev,
6299 struct ethtool_stats *estats,
6300 u64 * tmp_stats)
6301 {
6302 int i = 0, k;
6303 struct s2io_nic *sp = netdev_priv(dev);
6304 struct stat_block *stat_info = sp->mac_control.stats_info;
6305
6306 s2io_updt_stats(sp);
6307 tmp_stats[i++] =
6308 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6309 le32_to_cpu(stat_info->tmac_frms);
6310 tmp_stats[i++] =
6311 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6312 le32_to_cpu(stat_info->tmac_data_octets);
6313 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6314 tmp_stats[i++] =
6315 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6316 le32_to_cpu(stat_info->tmac_mcst_frms);
6317 tmp_stats[i++] =
6318 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6319 le32_to_cpu(stat_info->tmac_bcst_frms);
6320 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6321 tmp_stats[i++] =
6322 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6323 le32_to_cpu(stat_info->tmac_ttl_octets);
6324 tmp_stats[i++] =
6325 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6326 le32_to_cpu(stat_info->tmac_ucst_frms);
6327 tmp_stats[i++] =
6328 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6329 le32_to_cpu(stat_info->tmac_nucst_frms);
6330 tmp_stats[i++] =
6331 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6332 le32_to_cpu(stat_info->tmac_any_err_frms);
6333 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6334 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6335 tmp_stats[i++] =
6336 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6337 le32_to_cpu(stat_info->tmac_vld_ip);
6338 tmp_stats[i++] =
6339 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6340 le32_to_cpu(stat_info->tmac_drop_ip);
6341 tmp_stats[i++] =
6342 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6343 le32_to_cpu(stat_info->tmac_icmp);
6344 tmp_stats[i++] =
6345 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6346 le32_to_cpu(stat_info->tmac_rst_tcp);
6347 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6348 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6349 le32_to_cpu(stat_info->tmac_udp);
6350 tmp_stats[i++] =
6351 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6352 le32_to_cpu(stat_info->rmac_vld_frms);
6353 tmp_stats[i++] =
6354 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6355 le32_to_cpu(stat_info->rmac_data_octets);
6356 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6357 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6358 tmp_stats[i++] =
6359 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6360 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6361 tmp_stats[i++] =
6362 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6363 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6364 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6365 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6366 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6367 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6368 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6369 tmp_stats[i++] =
6370 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6371 le32_to_cpu(stat_info->rmac_ttl_octets);
6372 tmp_stats[i++] =
6373 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6374 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6375 tmp_stats[i++] =
6376 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6377 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6378 tmp_stats[i++] =
6379 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6380 le32_to_cpu(stat_info->rmac_discarded_frms);
6381 tmp_stats[i++] =
6382 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6383 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6384 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6386 tmp_stats[i++] =
6387 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6388 le32_to_cpu(stat_info->rmac_usized_frms);
6389 tmp_stats[i++] =
6390 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6391 le32_to_cpu(stat_info->rmac_osized_frms);
6392 tmp_stats[i++] =
6393 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6394 le32_to_cpu(stat_info->rmac_frag_frms);
6395 tmp_stats[i++] =
6396 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6397 le32_to_cpu(stat_info->rmac_jabber_frms);
6398 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6399 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6401 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6402 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6403 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6404 tmp_stats[i++] =
6405 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6406 le32_to_cpu(stat_info->rmac_ip);
6407 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6408 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6409 tmp_stats[i++] =
6410 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6411 le32_to_cpu(stat_info->rmac_drop_ip);
6412 tmp_stats[i++] =
6413 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6414 le32_to_cpu(stat_info->rmac_icmp);
6415 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6416 tmp_stats[i++] =
6417 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6418 le32_to_cpu(stat_info->rmac_udp);
6419 tmp_stats[i++] =
6420 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6421 le32_to_cpu(stat_info->rmac_err_drp_udp);
6422 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6423 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6424 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6425 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6429 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6430 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6431 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6432 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6433 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6434 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6435 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6436 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6437 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6438 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6439 tmp_stats[i++] =
6440 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6441 le32_to_cpu(stat_info->rmac_pause_cnt);
6442 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6443 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6444 tmp_stats[i++] =
6445 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6446 le32_to_cpu(stat_info->rmac_accepted_ip);
6447 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6448 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6453 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6454 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6455 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6457 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6458 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6459 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6460 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6461 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6462 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6466
6467 /* Enhanced statistics exist only for Hercules */
6468 if(sp->device_type == XFRAME_II_DEVICE) {
6469 tmp_stats[i++] =
6470 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6471 tmp_stats[i++] =
6472 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6473 tmp_stats[i++] =
6474 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6475 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6478 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6479 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6480 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6486 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6487 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6488 }
6489
6490 tmp_stats[i++] = 0;
6491 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6492 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6493 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6494 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6495 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6496 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6497 for (k = 0; k < MAX_RX_RINGS; k++)
6498 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6499 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6500 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6501 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6502 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6503 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6504 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6505 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6506 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6507 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6508 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6509 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6510 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6511 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6512 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6513 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6514 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6515 if (stat_info->sw_stat.num_aggregations) {
6516 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6517 int count = 0;
6518 /*
6519 * Since 64-bit divide does not work on all platforms,
6520 * do repeated subtraction.
6521 */
6522 while (tmp >= stat_info->sw_stat.num_aggregations) {
6523 tmp -= stat_info->sw_stat.num_aggregations;
6524 count++;
6525 }
6526 tmp_stats[i++] = count;
6527 }
6528 else
6529 tmp_stats[i++] = 0;
6530 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6531 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6532 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6533 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6534 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6535 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6536 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6537 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6538 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6539
6540 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6541 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6543 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6545
6546 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6547 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6549 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6550 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6551 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6553 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6556 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6557 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6558 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6559 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6561 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6564 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6566 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6570 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6571 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6572 }
6573
6574 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6575 {
6576 return (XENA_REG_SPACE);
6577 }
6578
6579
6580 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6581 {
6582 struct s2io_nic *sp = netdev_priv(dev);
6583
6584 return (sp->rx_csum);
6585 }
6586
6587 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6588 {
6589 struct s2io_nic *sp = netdev_priv(dev);
6590
6591 if (data)
6592 sp->rx_csum = 1;
6593 else
6594 sp->rx_csum = 0;
6595
6596 return 0;
6597 }
6598
6599 static int s2io_get_eeprom_len(struct net_device *dev)
6600 {
6601 return (XENA_EEPROM_SPACE);
6602 }
6603
6604 static int s2io_get_sset_count(struct net_device *dev, int sset)
6605 {
6606 struct s2io_nic *sp = netdev_priv(dev);
6607
6608 switch (sset) {
6609 case ETH_SS_TEST:
6610 return S2IO_TEST_LEN;
6611 case ETH_SS_STATS:
6612 switch(sp->device_type) {
6613 case XFRAME_I_DEVICE:
6614 return XFRAME_I_STAT_LEN;
6615 case XFRAME_II_DEVICE:
6616 return XFRAME_II_STAT_LEN;
6617 default:
6618 return 0;
6619 }
6620 default:
6621 return -EOPNOTSUPP;
6622 }
6623 }
6624
6625 static void s2io_ethtool_get_strings(struct net_device *dev,
6626 u32 stringset, u8 * data)
6627 {
6628 int stat_size = 0;
6629 struct s2io_nic *sp = netdev_priv(dev);
6630
6631 switch (stringset) {
6632 case ETH_SS_TEST:
6633 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6634 break;
6635 case ETH_SS_STATS:
6636 stat_size = sizeof(ethtool_xena_stats_keys);
6637 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6638 if(sp->device_type == XFRAME_II_DEVICE) {
6639 memcpy(data + stat_size,
6640 &ethtool_enhanced_stats_keys,
6641 sizeof(ethtool_enhanced_stats_keys));
6642 stat_size += sizeof(ethtool_enhanced_stats_keys);
6643 }
6644
6645 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6646 sizeof(ethtool_driver_stats_keys));
6647 }
6648 }
6649
6650 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6651 {
6652 if (data)
6653 dev->features |= NETIF_F_IP_CSUM;
6654 else
6655 dev->features &= ~NETIF_F_IP_CSUM;
6656
6657 return 0;
6658 }
6659
6660 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6661 {
6662 return (dev->features & NETIF_F_TSO) != 0;
6663 }
6664 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6665 {
6666 if (data)
6667 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6668 else
6669 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6670
6671 return 0;
6672 }
6673
6674 static const struct ethtool_ops netdev_ethtool_ops = {
6675 .get_settings = s2io_ethtool_gset,
6676 .set_settings = s2io_ethtool_sset,
6677 .get_drvinfo = s2io_ethtool_gdrvinfo,
6678 .get_regs_len = s2io_ethtool_get_regs_len,
6679 .get_regs = s2io_ethtool_gregs,
6680 .get_link = ethtool_op_get_link,
6681 .get_eeprom_len = s2io_get_eeprom_len,
6682 .get_eeprom = s2io_ethtool_geeprom,
6683 .set_eeprom = s2io_ethtool_seeprom,
6684 .get_ringparam = s2io_ethtool_gringparam,
6685 .get_pauseparam = s2io_ethtool_getpause_data,
6686 .set_pauseparam = s2io_ethtool_setpause_data,
6687 .get_rx_csum = s2io_ethtool_get_rx_csum,
6688 .set_rx_csum = s2io_ethtool_set_rx_csum,
6689 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6690 .set_sg = ethtool_op_set_sg,
6691 .get_tso = s2io_ethtool_op_get_tso,
6692 .set_tso = s2io_ethtool_op_set_tso,
6693 .set_ufo = ethtool_op_set_ufo,
6694 .self_test = s2io_ethtool_test,
6695 .get_strings = s2io_ethtool_get_strings,
6696 .phys_id = s2io_ethtool_idnic,
6697 .get_ethtool_stats = s2io_get_ethtool_stats,
6698 .get_sset_count = s2io_get_sset_count,
6699 };
6700
6701 /**
6702 * s2io_ioctl - Entry point for the Ioctl
6703 * @dev : Device pointer.
6704 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6705 * a proprietary structure used to pass information to the driver.
6706 * @cmd : This is used to distinguish between the different commands that
6707 * can be passed to the IOCTL functions.
6708 * Description:
6709 * Currently there are no special functionality supported in IOCTL, hence
6710 * function always return EOPNOTSUPPORTED
6711 */
6712
6713 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6714 {
6715 return -EOPNOTSUPP;
6716 }
6717
6718 /**
6719 * s2io_change_mtu - entry point to change MTU size for the device.
6720 * @dev : device pointer.
6721 * @new_mtu : the new MTU size for the device.
6722 * Description: A driver entry point to change MTU size for the device.
6723 * Before changing the MTU the device must be stopped.
6724 * Return value:
6725 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6726 * file on failure.
6727 */
6728
6729 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6730 {
6731 struct s2io_nic *sp = netdev_priv(dev);
6732 int ret = 0;
6733
6734 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6735 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6736 dev->name);
6737 return -EPERM;
6738 }
6739
6740 dev->mtu = new_mtu;
6741 if (netif_running(dev)) {
6742 s2io_stop_all_tx_queue(sp);
6743 s2io_card_down(sp);
6744 ret = s2io_card_up(sp);
6745 if (ret) {
6746 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6747 __func__);
6748 return ret;
6749 }
6750 s2io_wake_all_tx_queue(sp);
6751 } else { /* Device is down */
6752 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6753 u64 val64 = new_mtu;
6754
6755 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6756 }
6757
6758 return ret;
6759 }
6760
6761 /**
6762 * s2io_set_link - Set the LInk status
6763 * @data: long pointer to device private structue
6764 * Description: Sets the link status for the adapter
6765 */
6766
6767 static void s2io_set_link(struct work_struct *work)
6768 {
6769 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6770 struct net_device *dev = nic->dev;
6771 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6772 register u64 val64;
6773 u16 subid;
6774
6775 rtnl_lock();
6776
6777 if (!netif_running(dev))
6778 goto out_unlock;
6779
6780 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6781 /* The card is being reset, no point doing anything */
6782 goto out_unlock;
6783 }
6784
6785 subid = nic->pdev->subsystem_device;
6786 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6787 /*
6788 * Allow a small delay for the NICs self initiated
6789 * cleanup to complete.
6790 */
6791 msleep(100);
6792 }
6793
6794 val64 = readq(&bar0->adapter_status);
6795 if (LINK_IS_UP(val64)) {
6796 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6797 if (verify_xena_quiescence(nic)) {
6798 val64 = readq(&bar0->adapter_control);
6799 val64 |= ADAPTER_CNTL_EN;
6800 writeq(val64, &bar0->adapter_control);
6801 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6802 nic->device_type, subid)) {
6803 val64 = readq(&bar0->gpio_control);
6804 val64 |= GPIO_CTRL_GPIO_0;
6805 writeq(val64, &bar0->gpio_control);
6806 val64 = readq(&bar0->gpio_control);
6807 } else {
6808 val64 |= ADAPTER_LED_ON;
6809 writeq(val64, &bar0->adapter_control);
6810 }
6811 nic->device_enabled_once = TRUE;
6812 } else {
6813 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6814 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6815 s2io_stop_all_tx_queue(nic);
6816 }
6817 }
6818 val64 = readq(&bar0->adapter_control);
6819 val64 |= ADAPTER_LED_ON;
6820 writeq(val64, &bar0->adapter_control);
6821 s2io_link(nic, LINK_UP);
6822 } else {
6823 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6824 subid)) {
6825 val64 = readq(&bar0->gpio_control);
6826 val64 &= ~GPIO_CTRL_GPIO_0;
6827 writeq(val64, &bar0->gpio_control);
6828 val64 = readq(&bar0->gpio_control);
6829 }
6830 /* turn off LED */
6831 val64 = readq(&bar0->adapter_control);
6832 val64 = val64 &(~ADAPTER_LED_ON);
6833 writeq(val64, &bar0->adapter_control);
6834 s2io_link(nic, LINK_DOWN);
6835 }
6836 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6837
6838 out_unlock:
6839 rtnl_unlock();
6840 }
6841
6842 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6843 struct buffAdd *ba,
6844 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6845 u64 *temp2, int size)
6846 {
6847 struct net_device *dev = sp->dev;
6848 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6849
6850 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6851 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6852 /* allocate skb */
6853 if (*skb) {
6854 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6855 /*
6856 * As Rx frame are not going to be processed,
6857 * using same mapped address for the Rxd
6858 * buffer pointer
6859 */
6860 rxdp1->Buffer0_ptr = *temp0;
6861 } else {
6862 *skb = dev_alloc_skb(size);
6863 if (!(*skb)) {
6864 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6865 DBG_PRINT(INFO_DBG, "memory to allocate ");
6866 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6867 sp->mac_control.stats_info->sw_stat. \
6868 mem_alloc_fail_cnt++;
6869 return -ENOMEM ;
6870 }
6871 sp->mac_control.stats_info->sw_stat.mem_allocated
6872 += (*skb)->truesize;
6873 /* storing the mapped addr in a temp variable
6874 * such it will be used for next rxd whose
6875 * Host Control is NULL
6876 */
6877 rxdp1->Buffer0_ptr = *temp0 =
6878 pci_map_single( sp->pdev, (*skb)->data,
6879 size - NET_IP_ALIGN,
6880 PCI_DMA_FROMDEVICE);
6881 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6882 goto memalloc_failed;
6883 rxdp->Host_Control = (unsigned long) (*skb);
6884 }
6885 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6886 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6887 /* Two buffer Mode */
6888 if (*skb) {
6889 rxdp3->Buffer2_ptr = *temp2;
6890 rxdp3->Buffer0_ptr = *temp0;
6891 rxdp3->Buffer1_ptr = *temp1;
6892 } else {
6893 *skb = dev_alloc_skb(size);
6894 if (!(*skb)) {
6895 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6896 DBG_PRINT(INFO_DBG, "memory to allocate ");
6897 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6898 sp->mac_control.stats_info->sw_stat. \
6899 mem_alloc_fail_cnt++;
6900 return -ENOMEM;
6901 }
6902 sp->mac_control.stats_info->sw_stat.mem_allocated
6903 += (*skb)->truesize;
6904 rxdp3->Buffer2_ptr = *temp2 =
6905 pci_map_single(sp->pdev, (*skb)->data,
6906 dev->mtu + 4,
6907 PCI_DMA_FROMDEVICE);
6908 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6909 goto memalloc_failed;
6910 rxdp3->Buffer0_ptr = *temp0 =
6911 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6912 PCI_DMA_FROMDEVICE);
6913 if (pci_dma_mapping_error(sp->pdev,
6914 rxdp3->Buffer0_ptr)) {
6915 pci_unmap_single (sp->pdev,
6916 (dma_addr_t)rxdp3->Buffer2_ptr,
6917 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6918 goto memalloc_failed;
6919 }
6920 rxdp->Host_Control = (unsigned long) (*skb);
6921
6922 /* Buffer-1 will be dummy buffer not used */
6923 rxdp3->Buffer1_ptr = *temp1 =
6924 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6925 PCI_DMA_FROMDEVICE);
6926 if (pci_dma_mapping_error(sp->pdev,
6927 rxdp3->Buffer1_ptr)) {
6928 pci_unmap_single (sp->pdev,
6929 (dma_addr_t)rxdp3->Buffer0_ptr,
6930 BUF0_LEN, PCI_DMA_FROMDEVICE);
6931 pci_unmap_single (sp->pdev,
6932 (dma_addr_t)rxdp3->Buffer2_ptr,
6933 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6934 goto memalloc_failed;
6935 }
6936 }
6937 }
6938 return 0;
6939 memalloc_failed:
6940 stats->pci_map_fail_cnt++;
6941 stats->mem_freed += (*skb)->truesize;
6942 dev_kfree_skb(*skb);
6943 return -ENOMEM;
6944 }
6945
6946 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6947 int size)
6948 {
6949 struct net_device *dev = sp->dev;
6950 if (sp->rxd_mode == RXD_MODE_1) {
6951 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6952 } else if (sp->rxd_mode == RXD_MODE_3B) {
6953 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6954 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6955 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6956 }
6957 }
6958
6959 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6960 {
6961 int i, j, k, blk_cnt = 0, size;
6962 struct mac_info * mac_control = &sp->mac_control;
6963 struct config_param *config = &sp->config;
6964 struct net_device *dev = sp->dev;
6965 struct RxD_t *rxdp = NULL;
6966 struct sk_buff *skb = NULL;
6967 struct buffAdd *ba = NULL;
6968 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6969
6970 /* Calculate the size based on ring mode */
6971 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6972 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6973 if (sp->rxd_mode == RXD_MODE_1)
6974 size += NET_IP_ALIGN;
6975 else if (sp->rxd_mode == RXD_MODE_3B)
6976 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6977
6978 for (i = 0; i < config->rx_ring_num; i++) {
6979 blk_cnt = config->rx_cfg[i].num_rxd /
6980 (rxd_count[sp->rxd_mode] +1);
6981
6982 for (j = 0; j < blk_cnt; j++) {
6983 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6984 rxdp = mac_control->rings[i].
6985 rx_blocks[j].rxds[k].virt_addr;
6986 if(sp->rxd_mode == RXD_MODE_3B)
6987 ba = &mac_control->rings[i].ba[j][k];
6988 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6989 &skb,(u64 *)&temp0_64,
6990 (u64 *)&temp1_64,
6991 (u64 *)&temp2_64,
6992 size) == -ENOMEM) {
6993 return 0;
6994 }
6995
6996 set_rxd_buffer_size(sp, rxdp, size);
6997 wmb();
6998 /* flip the Ownership bit to Hardware */
6999 rxdp->Control_1 |= RXD_OWN_XENA;
7000 }
7001 }
7002 }
7003 return 0;
7004
7005 }
7006
7007 static int s2io_add_isr(struct s2io_nic * sp)
7008 {
7009 int ret = 0;
7010 struct net_device *dev = sp->dev;
7011 int err = 0;
7012
7013 if (sp->config.intr_type == MSI_X)
7014 ret = s2io_enable_msi_x(sp);
7015 if (ret) {
7016 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7017 sp->config.intr_type = INTA;
7018 }
7019
7020 /* Store the values of the MSIX table in the struct s2io_nic structure */
7021 store_xmsi_data(sp);
7022
7023 /* After proper initialization of H/W, register ISR */
7024 if (sp->config.intr_type == MSI_X) {
7025 int i, msix_rx_cnt = 0;
7026
7027 for (i = 0; i < sp->num_entries; i++) {
7028 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7029 if (sp->s2io_entries[i].type ==
7030 MSIX_RING_TYPE) {
7031 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7032 dev->name, i);
7033 err = request_irq(sp->entries[i].vector,
7034 s2io_msix_ring_handle, 0,
7035 sp->desc[i],
7036 sp->s2io_entries[i].arg);
7037 } else if (sp->s2io_entries[i].type ==
7038 MSIX_ALARM_TYPE) {
7039 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7040 dev->name, i);
7041 err = request_irq(sp->entries[i].vector,
7042 s2io_msix_fifo_handle, 0,
7043 sp->desc[i],
7044 sp->s2io_entries[i].arg);
7045
7046 }
7047 /* if either data or addr is zero print it. */
7048 if (!(sp->msix_info[i].addr &&
7049 sp->msix_info[i].data)) {
7050 DBG_PRINT(ERR_DBG,
7051 "%s @Addr:0x%llx Data:0x%llx\n",
7052 sp->desc[i],
7053 (unsigned long long)
7054 sp->msix_info[i].addr,
7055 (unsigned long long)
7056 ntohl(sp->msix_info[i].data));
7057 } else
7058 msix_rx_cnt++;
7059 if (err) {
7060 remove_msix_isr(sp);
7061
7062 DBG_PRINT(ERR_DBG,
7063 "%s:MSI-X-%d registration "
7064 "failed\n", dev->name, i);
7065
7066 DBG_PRINT(ERR_DBG,
7067 "%s: Defaulting to INTA\n",
7068 dev->name);
7069 sp->config.intr_type = INTA;
7070 break;
7071 }
7072 sp->s2io_entries[i].in_use =
7073 MSIX_REGISTERED_SUCCESS;
7074 }
7075 }
7076 if (!err) {
7077 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7078 --msix_rx_cnt);
7079 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7080 " through alarm vector\n");
7081 }
7082 }
7083 if (sp->config.intr_type == INTA) {
7084 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7085 sp->name, dev);
7086 if (err) {
7087 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7088 dev->name);
7089 return -1;
7090 }
7091 }
7092 return 0;
7093 }
7094 static void s2io_rem_isr(struct s2io_nic * sp)
7095 {
7096 if (sp->config.intr_type == MSI_X)
7097 remove_msix_isr(sp);
7098 else
7099 remove_inta_isr(sp);
7100 }
7101
7102 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
7103 {
7104 int cnt = 0;
7105 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7106 register u64 val64 = 0;
7107 struct config_param *config;
7108 config = &sp->config;
7109
7110 if (!is_s2io_card_up(sp))
7111 return;
7112
7113 del_timer_sync(&sp->alarm_timer);
7114 /* If s2io_set_link task is executing, wait till it completes. */
7115 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
7116 msleep(50);
7117 }
7118 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7119
7120 /* Disable napi */
7121 if (sp->config.napi) {
7122 int off = 0;
7123 if (config->intr_type == MSI_X) {
7124 for (; off < sp->config.rx_ring_num; off++)
7125 napi_disable(&sp->mac_control.rings[off].napi);
7126 }
7127 else
7128 napi_disable(&sp->napi);
7129 }
7130
7131 /* disable Tx and Rx traffic on the NIC */
7132 if (do_io)
7133 stop_nic(sp);
7134
7135 s2io_rem_isr(sp);
7136
7137 /* stop the tx queue, indicate link down */
7138 s2io_link(sp, LINK_DOWN);
7139
7140 /* Check if the device is Quiescent and then Reset the NIC */
7141 while(do_io) {
7142 /* As per the HW requirement we need to replenish the
7143 * receive buffer to avoid the ring bump. Since there is
7144 * no intention of processing the Rx frame at this pointwe are
7145 * just settting the ownership bit of rxd in Each Rx
7146 * ring to HW and set the appropriate buffer size
7147 * based on the ring mode
7148 */
7149 rxd_owner_bit_reset(sp);
7150
7151 val64 = readq(&bar0->adapter_status);
7152 if (verify_xena_quiescence(sp)) {
7153 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
7154 break;
7155 }
7156
7157 msleep(50);
7158 cnt++;
7159 if (cnt == 10) {
7160 DBG_PRINT(ERR_DBG,
7161 "s2io_close:Device not Quiescent ");
7162 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7163 (unsigned long long) val64);
7164 break;
7165 }
7166 }
7167 if (do_io)
7168 s2io_reset(sp);
7169
7170 /* Free all Tx buffers */
7171 free_tx_buffers(sp);
7172
7173 /* Free all Rx buffers */
7174 free_rx_buffers(sp);
7175
7176 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7177 }
7178
7179 static void s2io_card_down(struct s2io_nic * sp)
7180 {
7181 do_s2io_card_down(sp, 1);
7182 }
7183
7184 static int s2io_card_up(struct s2io_nic * sp)
7185 {
7186 int i, ret = 0;
7187 struct mac_info *mac_control;
7188 struct config_param *config;
7189 struct net_device *dev = (struct net_device *) sp->dev;
7190 u16 interruptible;
7191
7192 /* Initialize the H/W I/O registers */
7193 ret = init_nic(sp);
7194 if (ret != 0) {
7195 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7196 dev->name);
7197 if (ret != -EIO)
7198 s2io_reset(sp);
7199 return ret;
7200 }
7201
7202 /*
7203 * Initializing the Rx buffers. For now we are considering only 1
7204 * Rx ring and initializing buffers into 30 Rx blocks
7205 */
7206 mac_control = &sp->mac_control;
7207 config = &sp->config;
7208
7209 for (i = 0; i < config->rx_ring_num; i++) {
7210 mac_control->rings[i].mtu = dev->mtu;
7211 ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
7212 if (ret) {
7213 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7214 dev->name);
7215 s2io_reset(sp);
7216 free_rx_buffers(sp);
7217 return -ENOMEM;
7218 }
7219 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7220 mac_control->rings[i].rx_bufs_left);
7221 }
7222
7223 /* Initialise napi */
7224 if (config->napi) {
7225 int i;
7226 if (config->intr_type == MSI_X) {
7227 for (i = 0; i < sp->config.rx_ring_num; i++)
7228 napi_enable(&sp->mac_control.rings[i].napi);
7229 } else {
7230 napi_enable(&sp->napi);
7231 }
7232 }
7233
7234 /* Maintain the state prior to the open */
7235 if (sp->promisc_flg)
7236 sp->promisc_flg = 0;
7237 if (sp->m_cast_flg) {
7238 sp->m_cast_flg = 0;
7239 sp->all_multi_pos= 0;
7240 }
7241
7242 /* Setting its receive mode */
7243 s2io_set_multicast(dev);
7244
7245 if (sp->lro) {
7246 /* Initialize max aggregatable pkts per session based on MTU */
7247 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7248 /* Check if we can use(if specified) user provided value */
7249 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7250 sp->lro_max_aggr_per_sess = lro_max_pkts;
7251 }
7252
7253 /* Enable Rx Traffic and interrupts on the NIC */
7254 if (start_nic(sp)) {
7255 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7256 s2io_reset(sp);
7257 free_rx_buffers(sp);
7258 return -ENODEV;
7259 }
7260
7261 /* Add interrupt service routine */
7262 if (s2io_add_isr(sp) != 0) {
7263 if (sp->config.intr_type == MSI_X)
7264 s2io_rem_isr(sp);
7265 s2io_reset(sp);
7266 free_rx_buffers(sp);
7267 return -ENODEV;
7268 }
7269
7270 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7271
7272 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7273
7274 /* Enable select interrupts */
7275 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7276 if (sp->config.intr_type != INTA) {
7277 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7278 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7279 } else {
7280 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7281 interruptible |= TX_PIC_INTR;
7282 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7283 }
7284
7285 return 0;
7286 }
7287
7288 /**
7289 * s2io_restart_nic - Resets the NIC.
7290 * @data : long pointer to the device private structure
7291 * Description:
7292 * This function is scheduled to be run by the s2io_tx_watchdog
7293 * function after 0.5 secs to reset the NIC. The idea is to reduce
7294 * the run time of the watch dog routine which is run holding a
7295 * spin lock.
7296 */
7297
7298 static void s2io_restart_nic(struct work_struct *work)
7299 {
7300 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7301 struct net_device *dev = sp->dev;
7302
7303 rtnl_lock();
7304
7305 if (!netif_running(dev))
7306 goto out_unlock;
7307
7308 s2io_card_down(sp);
7309 if (s2io_card_up(sp)) {
7310 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7311 dev->name);
7312 }
7313 s2io_wake_all_tx_queue(sp);
7314 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7315 dev->name);
7316 out_unlock:
7317 rtnl_unlock();
7318 }
7319
7320 /**
7321 * s2io_tx_watchdog - Watchdog for transmit side.
7322 * @dev : Pointer to net device structure
7323 * Description:
7324 * This function is triggered if the Tx Queue is stopped
7325 * for a pre-defined amount of time when the Interface is still up.
7326 * If the Interface is jammed in such a situation, the hardware is
7327 * reset (by s2io_close) and restarted again (by s2io_open) to
7328 * overcome any problem that might have been caused in the hardware.
7329 * Return value:
7330 * void
7331 */
7332
7333 static void s2io_tx_watchdog(struct net_device *dev)
7334 {
7335 struct s2io_nic *sp = netdev_priv(dev);
7336
7337 if (netif_carrier_ok(dev)) {
7338 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7339 schedule_work(&sp->rst_timer_task);
7340 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7341 }
7342 }
7343
7344 /**
7345 * rx_osm_handler - To perform some OS related operations on SKB.
7346 * @sp: private member of the device structure,pointer to s2io_nic structure.
7347 * @skb : the socket buffer pointer.
7348 * @len : length of the packet
7349 * @cksum : FCS checksum of the frame.
7350 * @ring_no : the ring from which this RxD was extracted.
7351 * Description:
7352 * This function is called by the Rx interrupt serivce routine to perform
7353 * some OS related operations on the SKB before passing it to the upper
7354 * layers. It mainly checks if the checksum is OK, if so adds it to the
7355 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7356 * to the upper layer. If the checksum is wrong, it increments the Rx
7357 * packet error count, frees the SKB and returns error.
7358 * Return value:
7359 * SUCCESS on success and -1 on failure.
7360 */
7361 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7362 {
7363 struct s2io_nic *sp = ring_data->nic;
7364 struct net_device *dev = (struct net_device *) ring_data->dev;
7365 struct sk_buff *skb = (struct sk_buff *)
7366 ((unsigned long) rxdp->Host_Control);
7367 int ring_no = ring_data->ring_no;
7368 u16 l3_csum, l4_csum;
7369 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7370 struct lro *uninitialized_var(lro);
7371 u8 err_mask;
7372
7373 skb->dev = dev;
7374
7375 if (err) {
7376 /* Check for parity error */
7377 if (err & 0x1) {
7378 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7379 }
7380 err_mask = err >> 48;
7381 switch(err_mask) {
7382 case 1:
7383 sp->mac_control.stats_info->sw_stat.
7384 rx_parity_err_cnt++;
7385 break;
7386
7387 case 2:
7388 sp->mac_control.stats_info->sw_stat.
7389 rx_abort_cnt++;
7390 break;
7391
7392 case 3:
7393 sp->mac_control.stats_info->sw_stat.
7394 rx_parity_abort_cnt++;
7395 break;
7396
7397 case 4:
7398 sp->mac_control.stats_info->sw_stat.
7399 rx_rda_fail_cnt++;
7400 break;
7401
7402 case 5:
7403 sp->mac_control.stats_info->sw_stat.
7404 rx_unkn_prot_cnt++;
7405 break;
7406
7407 case 6:
7408 sp->mac_control.stats_info->sw_stat.
7409 rx_fcs_err_cnt++;
7410 break;
7411
7412 case 7:
7413 sp->mac_control.stats_info->sw_stat.
7414 rx_buf_size_err_cnt++;
7415 break;
7416
7417 case 8:
7418 sp->mac_control.stats_info->sw_stat.
7419 rx_rxd_corrupt_cnt++;
7420 break;
7421
7422 case 15:
7423 sp->mac_control.stats_info->sw_stat.
7424 rx_unkn_err_cnt++;
7425 break;
7426 }
7427 /*
7428 * Drop the packet if bad transfer code. Exception being
7429 * 0x5, which could be due to unsupported IPv6 extension header.
7430 * In this case, we let stack handle the packet.
7431 * Note that in this case, since checksum will be incorrect,
7432 * stack will validate the same.
7433 */
7434 if (err_mask != 0x5) {
7435 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7436 dev->name, err_mask);
7437 dev->stats.rx_crc_errors++;
7438 sp->mac_control.stats_info->sw_stat.mem_freed
7439 += skb->truesize;
7440 dev_kfree_skb(skb);
7441 ring_data->rx_bufs_left -= 1;
7442 rxdp->Host_Control = 0;
7443 return 0;
7444 }
7445 }
7446
7447 /* Updating statistics */
7448 ring_data->rx_packets++;
7449 rxdp->Host_Control = 0;
7450 if (sp->rxd_mode == RXD_MODE_1) {
7451 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7452
7453 ring_data->rx_bytes += len;
7454 skb_put(skb, len);
7455
7456 } else if (sp->rxd_mode == RXD_MODE_3B) {
7457 int get_block = ring_data->rx_curr_get_info.block_index;
7458 int get_off = ring_data->rx_curr_get_info.offset;
7459 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7460 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7461 unsigned char *buff = skb_push(skb, buf0_len);
7462
7463 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7464 ring_data->rx_bytes += buf0_len + buf2_len;
7465 memcpy(buff, ba->ba_0, buf0_len);
7466 skb_put(skb, buf2_len);
7467 }
7468
7469 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7470 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7471 (sp->rx_csum)) {
7472 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7473 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7474 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7475 /*
7476 * NIC verifies if the Checksum of the received
7477 * frame is Ok or not and accordingly returns
7478 * a flag in the RxD.
7479 */
7480 skb->ip_summed = CHECKSUM_UNNECESSARY;
7481 if (ring_data->lro) {
7482 u32 tcp_len;
7483 u8 *tcp;
7484 int ret = 0;
7485
7486 ret = s2io_club_tcp_session(ring_data,
7487 skb->data, &tcp, &tcp_len, &lro,
7488 rxdp, sp);
7489 switch (ret) {
7490 case 3: /* Begin anew */
7491 lro->parent = skb;
7492 goto aggregate;
7493 case 1: /* Aggregate */
7494 {
7495 lro_append_pkt(sp, lro,
7496 skb, tcp_len);
7497 goto aggregate;
7498 }
7499 case 4: /* Flush session */
7500 {
7501 lro_append_pkt(sp, lro,
7502 skb, tcp_len);
7503 queue_rx_frame(lro->parent,
7504 lro->vlan_tag);
7505 clear_lro_session(lro);
7506 sp->mac_control.stats_info->
7507 sw_stat.flush_max_pkts++;
7508 goto aggregate;
7509 }
7510 case 2: /* Flush both */
7511 lro->parent->data_len =
7512 lro->frags_len;
7513 sp->mac_control.stats_info->
7514 sw_stat.sending_both++;
7515 queue_rx_frame(lro->parent,
7516 lro->vlan_tag);
7517 clear_lro_session(lro);
7518 goto send_up;
7519 case 0: /* sessions exceeded */
7520 case -1: /* non-TCP or not
7521 * L2 aggregatable
7522 */
7523 case 5: /*
7524 * First pkt in session not
7525 * L3/L4 aggregatable
7526 */
7527 break;
7528 default:
7529 DBG_PRINT(ERR_DBG,
7530 "%s: Samadhana!!\n",
7531 __func__);
7532 BUG();
7533 }
7534 }
7535 } else {
7536 /*
7537 * Packet with erroneous checksum, let the
7538 * upper layers deal with it.
7539 */
7540 skb->ip_summed = CHECKSUM_NONE;
7541 }
7542 } else
7543 skb->ip_summed = CHECKSUM_NONE;
7544
7545 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7546 send_up:
7547 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7548 aggregate:
7549 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7550 return SUCCESS;
7551 }
7552
7553 /**
7554 * s2io_link - stops/starts the Tx queue.
7555 * @sp : private member of the device structure, which is a pointer to the
7556 * s2io_nic structure.
7557 * @link : inidicates whether link is UP/DOWN.
7558 * Description:
7559 * This function stops/starts the Tx queue depending on whether the link
7560 * status of the NIC is is down or up. This is called by the Alarm
7561 * interrupt handler whenever a link change interrupt comes up.
7562 * Return value:
7563 * void.
7564 */
7565
7566 static void s2io_link(struct s2io_nic * sp, int link)
7567 {
7568 struct net_device *dev = (struct net_device *) sp->dev;
7569
7570 if (link != sp->last_link_state) {
7571 init_tti(sp, link);
7572 if (link == LINK_DOWN) {
7573 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7574 s2io_stop_all_tx_queue(sp);
7575 netif_carrier_off(dev);
7576 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7577 sp->mac_control.stats_info->sw_stat.link_up_time =
7578 jiffies - sp->start_time;
7579 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7580 } else {
7581 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7582 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7583 sp->mac_control.stats_info->sw_stat.link_down_time =
7584 jiffies - sp->start_time;
7585 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7586 netif_carrier_on(dev);
7587 s2io_wake_all_tx_queue(sp);
7588 }
7589 }
7590 sp->last_link_state = link;
7591 sp->start_time = jiffies;
7592 }
7593
7594 /**
7595 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7596 * @sp : private member of the device structure, which is a pointer to the
7597 * s2io_nic structure.
7598 * Description:
7599 * This function initializes a few of the PCI and PCI-X configuration registers
7600 * with recommended values.
7601 * Return value:
7602 * void
7603 */
7604
7605 static void s2io_init_pci(struct s2io_nic * sp)
7606 {
7607 u16 pci_cmd = 0, pcix_cmd = 0;
7608
7609 /* Enable Data Parity Error Recovery in PCI-X command register. */
7610 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7611 &(pcix_cmd));
7612 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7613 (pcix_cmd | 1));
7614 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7615 &(pcix_cmd));
7616
7617 /* Set the PErr Response bit in PCI command register. */
7618 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7619 pci_write_config_word(sp->pdev, PCI_COMMAND,
7620 (pci_cmd | PCI_COMMAND_PARITY));
7621 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7622 }
7623
7624 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7625 u8 *dev_multiq)
7626 {
7627 if ((tx_fifo_num > MAX_TX_FIFOS) ||
7628 (tx_fifo_num < 1)) {
7629 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7630 "(%d) not supported\n", tx_fifo_num);
7631
7632 if (tx_fifo_num < 1)
7633 tx_fifo_num = 1;
7634 else
7635 tx_fifo_num = MAX_TX_FIFOS;
7636
7637 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7638 DBG_PRINT(ERR_DBG, "tx fifos\n");
7639 }
7640
7641 if (multiq)
7642 *dev_multiq = multiq;
7643
7644 if (tx_steering_type && (1 == tx_fifo_num)) {
7645 if (tx_steering_type != TX_DEFAULT_STEERING)
7646 DBG_PRINT(ERR_DBG,
7647 "s2io: Tx steering is not supported with "
7648 "one fifo. Disabling Tx steering.\n");
7649 tx_steering_type = NO_STEERING;
7650 }
7651
7652 if ((tx_steering_type < NO_STEERING) ||
7653 (tx_steering_type > TX_DEFAULT_STEERING)) {
7654 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7655 "supported\n");
7656 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7657 tx_steering_type = NO_STEERING;
7658 }
7659
7660 if (rx_ring_num > MAX_RX_RINGS) {
7661 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
7662 "supported\n");
7663 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7664 MAX_RX_RINGS);
7665 rx_ring_num = MAX_RX_RINGS;
7666 }
7667
7668 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7669 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7670 "Defaulting to INTA\n");
7671 *dev_intr_type = INTA;
7672 }
7673
7674 if ((*dev_intr_type == MSI_X) &&
7675 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7676 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7677 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7678 "Defaulting to INTA\n");
7679 *dev_intr_type = INTA;
7680 }
7681
7682 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7683 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7684 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7685 rx_ring_mode = 1;
7686 }
7687 return SUCCESS;
7688 }
7689
7690 /**
7691 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7692 * or Traffic class respectively.
7693 * @nic: device private variable
7694 * Description: The function configures the receive steering to
7695 * desired receive ring.
7696 * Return Value: SUCCESS on success and
7697 * '-1' on failure (endian settings incorrect).
7698 */
7699 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7700 {
7701 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7702 register u64 val64 = 0;
7703
7704 if (ds_codepoint > 63)
7705 return FAILURE;
7706
7707 val64 = RTS_DS_MEM_DATA(ring);
7708 writeq(val64, &bar0->rts_ds_mem_data);
7709
7710 val64 = RTS_DS_MEM_CTRL_WE |
7711 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7712 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7713
7714 writeq(val64, &bar0->rts_ds_mem_ctrl);
7715
7716 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7717 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7718 S2IO_BIT_RESET);
7719 }
7720
7721 static const struct net_device_ops s2io_netdev_ops = {
7722 .ndo_open = s2io_open,
7723 .ndo_stop = s2io_close,
7724 .ndo_get_stats = s2io_get_stats,
7725 .ndo_start_xmit = s2io_xmit,
7726 .ndo_validate_addr = eth_validate_addr,
7727 .ndo_set_multicast_list = s2io_set_multicast,
7728 .ndo_do_ioctl = s2io_ioctl,
7729 .ndo_set_mac_address = s2io_set_mac_addr,
7730 .ndo_change_mtu = s2io_change_mtu,
7731 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7732 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7733 .ndo_tx_timeout = s2io_tx_watchdog,
7734 #ifdef CONFIG_NET_POLL_CONTROLLER
7735 .ndo_poll_controller = s2io_netpoll,
7736 #endif
7737 };
7738
7739 /**
7740 * s2io_init_nic - Initialization of the adapter .
7741 * @pdev : structure containing the PCI related information of the device.
7742 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7743 * Description:
7744 * The function initializes an adapter identified by the pci_dec structure.
7745 * All OS related initialization including memory and device structure and
7746 * initlaization of the device private variable is done. Also the swapper
7747 * control register is initialized to enable read and write into the I/O
7748 * registers of the device.
7749 * Return value:
7750 * returns 0 on success and negative on failure.
7751 */
7752
7753 static int __devinit
7754 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7755 {
7756 struct s2io_nic *sp;
7757 struct net_device *dev;
7758 int i, j, ret;
7759 int dma_flag = FALSE;
7760 u32 mac_up, mac_down;
7761 u64 val64 = 0, tmp64 = 0;
7762 struct XENA_dev_config __iomem *bar0 = NULL;
7763 u16 subid;
7764 struct mac_info *mac_control;
7765 struct config_param *config;
7766 int mode;
7767 u8 dev_intr_type = intr_type;
7768 u8 dev_multiq = 0;
7769
7770 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7771 if (ret)
7772 return ret;
7773
7774 if ((ret = pci_enable_device(pdev))) {
7775 DBG_PRINT(ERR_DBG,
7776 "s2io_init_nic: pci_enable_device failed\n");
7777 return ret;
7778 }
7779
7780 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7781 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7782 dma_flag = TRUE;
7783 if (pci_set_consistent_dma_mask
7784 (pdev, DMA_64BIT_MASK)) {
7785 DBG_PRINT(ERR_DBG,
7786 "Unable to obtain 64bit DMA for \
7787 consistent allocations\n");
7788 pci_disable_device(pdev);
7789 return -ENOMEM;
7790 }
7791 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7792 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7793 } else {
7794 pci_disable_device(pdev);
7795 return -ENOMEM;
7796 }
7797 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7798 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __func__, ret);
7799 pci_disable_device(pdev);
7800 return -ENODEV;
7801 }
7802 if (dev_multiq)
7803 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7804 else
7805 dev = alloc_etherdev(sizeof(struct s2io_nic));
7806 if (dev == NULL) {
7807 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7808 pci_disable_device(pdev);
7809 pci_release_regions(pdev);
7810 return -ENODEV;
7811 }
7812
7813 pci_set_master(pdev);
7814 pci_set_drvdata(pdev, dev);
7815 SET_NETDEV_DEV(dev, &pdev->dev);
7816
7817 /* Private member variable initialized to s2io NIC structure */
7818 sp = netdev_priv(dev);
7819 memset(sp, 0, sizeof(struct s2io_nic));
7820 sp->dev = dev;
7821 sp->pdev = pdev;
7822 sp->high_dma_flag = dma_flag;
7823 sp->device_enabled_once = FALSE;
7824 if (rx_ring_mode == 1)
7825 sp->rxd_mode = RXD_MODE_1;
7826 if (rx_ring_mode == 2)
7827 sp->rxd_mode = RXD_MODE_3B;
7828
7829 sp->config.intr_type = dev_intr_type;
7830
7831 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7832 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7833 sp->device_type = XFRAME_II_DEVICE;
7834 else
7835 sp->device_type = XFRAME_I_DEVICE;
7836
7837 sp->lro = lro_enable;
7838
7839 /* Initialize some PCI/PCI-X fields of the NIC. */
7840 s2io_init_pci(sp);
7841
7842 /*
7843 * Setting the device configuration parameters.
7844 * Most of these parameters can be specified by the user during
7845 * module insertion as they are module loadable parameters. If
7846 * these parameters are not not specified during load time, they
7847 * are initialized with default values.
7848 */
7849 mac_control = &sp->mac_control;
7850 config = &sp->config;
7851
7852 config->napi = napi;
7853 config->tx_steering_type = tx_steering_type;
7854
7855 /* Tx side parameters. */
7856 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7857 config->tx_fifo_num = MAX_TX_FIFOS;
7858 else
7859 config->tx_fifo_num = tx_fifo_num;
7860
7861 /* Initialize the fifos used for tx steering */
7862 if (config->tx_fifo_num < 5) {
7863 if (config->tx_fifo_num == 1)
7864 sp->total_tcp_fifos = 1;
7865 else
7866 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7867 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7868 sp->total_udp_fifos = 1;
7869 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7870 } else {
7871 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7872 FIFO_OTHER_MAX_NUM);
7873 sp->udp_fifo_idx = sp->total_tcp_fifos;
7874 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7875 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7876 }
7877
7878 config->multiq = dev_multiq;
7879 for (i = 0; i < config->tx_fifo_num; i++) {
7880 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7881 config->tx_cfg[i].fifo_priority = i;
7882 }
7883
7884 /* mapping the QoS priority to the configured fifos */
7885 for (i = 0; i < MAX_TX_FIFOS; i++)
7886 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7887
7888 /* map the hashing selector table to the configured fifos */
7889 for (i = 0; i < config->tx_fifo_num; i++)
7890 sp->fifo_selector[i] = fifo_selector[i];
7891
7892
7893 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7894 for (i = 0; i < config->tx_fifo_num; i++) {
7895 config->tx_cfg[i].f_no_snoop =
7896 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7897 if (config->tx_cfg[i].fifo_len < 65) {
7898 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7899 break;
7900 }
7901 }
7902 /* + 2 because one Txd for skb->data and one Txd for UFO */
7903 config->max_txds = MAX_SKB_FRAGS + 2;
7904
7905 /* Rx side parameters. */
7906 config->rx_ring_num = rx_ring_num;
7907 for (i = 0; i < config->rx_ring_num; i++) {
7908 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7909 (rxd_count[sp->rxd_mode] + 1);
7910 config->rx_cfg[i].ring_priority = i;
7911 mac_control->rings[i].rx_bufs_left = 0;
7912 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7913 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7914 mac_control->rings[i].pdev = sp->pdev;
7915 mac_control->rings[i].dev = sp->dev;
7916 }
7917
7918 for (i = 0; i < rx_ring_num; i++) {
7919 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7920 config->rx_cfg[i].f_no_snoop =
7921 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7922 }
7923
7924 /* Setting Mac Control parameters */
7925 mac_control->rmac_pause_time = rmac_pause_time;
7926 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7927 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7928
7929
7930 /* initialize the shared memory used by the NIC and the host */
7931 if (init_shared_mem(sp)) {
7932 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7933 dev->name);
7934 ret = -ENOMEM;
7935 goto mem_alloc_failed;
7936 }
7937
7938 sp->bar0 = pci_ioremap_bar(pdev, 0);
7939 if (!sp->bar0) {
7940 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7941 dev->name);
7942 ret = -ENOMEM;
7943 goto bar0_remap_failed;
7944 }
7945
7946 sp->bar1 = pci_ioremap_bar(pdev, 2);
7947 if (!sp->bar1) {
7948 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7949 dev->name);
7950 ret = -ENOMEM;
7951 goto bar1_remap_failed;
7952 }
7953
7954 dev->irq = pdev->irq;
7955 dev->base_addr = (unsigned long) sp->bar0;
7956
7957 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7958 for (j = 0; j < MAX_TX_FIFOS; j++) {
7959 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7960 (sp->bar1 + (j * 0x00020000));
7961 }
7962
7963 /* Driver entry points */
7964 dev->netdev_ops = &s2io_netdev_ops;
7965 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7966 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7967
7968 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7969 if (sp->high_dma_flag == TRUE)
7970 dev->features |= NETIF_F_HIGHDMA;
7971 dev->features |= NETIF_F_TSO;
7972 dev->features |= NETIF_F_TSO6;
7973 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7974 dev->features |= NETIF_F_UFO;
7975 dev->features |= NETIF_F_HW_CSUM;
7976 }
7977 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7978 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7979 INIT_WORK(&sp->set_link_task, s2io_set_link);
7980
7981 pci_save_state(sp->pdev);
7982
7983 /* Setting swapper control on the NIC, for proper reset operation */
7984 if (s2io_set_swapper(sp)) {
7985 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7986 dev->name);
7987 ret = -EAGAIN;
7988 goto set_swap_failed;
7989 }
7990
7991 /* Verify if the Herc works on the slot its placed into */
7992 if (sp->device_type & XFRAME_II_DEVICE) {
7993 mode = s2io_verify_pci_mode(sp);
7994 if (mode < 0) {
7995 DBG_PRINT(ERR_DBG, "%s: ", __func__);
7996 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7997 ret = -EBADSLT;
7998 goto set_swap_failed;
7999 }
8000 }
8001
8002 if (sp->config.intr_type == MSI_X) {
8003 sp->num_entries = config->rx_ring_num + 1;
8004 ret = s2io_enable_msi_x(sp);
8005
8006 if (!ret) {
8007 ret = s2io_test_msi(sp);
8008 /* rollback MSI-X, will re-enable during add_isr() */
8009 remove_msix_isr(sp);
8010 }
8011 if (ret) {
8012
8013 DBG_PRINT(ERR_DBG,
8014 "%s: MSI-X requested but failed to enable\n",
8015 dev->name);
8016 sp->config.intr_type = INTA;
8017 }
8018 }
8019
8020 if (config->intr_type == MSI_X) {
8021 for (i = 0; i < config->rx_ring_num ; i++)
8022 netif_napi_add(dev, &mac_control->rings[i].napi,
8023 s2io_poll_msix, 64);
8024 } else {
8025 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8026 }
8027
8028 /* Not needed for Herc */
8029 if (sp->device_type & XFRAME_I_DEVICE) {
8030 /*
8031 * Fix for all "FFs" MAC address problems observed on
8032 * Alpha platforms
8033 */
8034 fix_mac_address(sp);
8035 s2io_reset(sp);
8036 }
8037
8038 /*
8039 * MAC address initialization.
8040 * For now only one mac address will be read and used.
8041 */
8042 bar0 = sp->bar0;
8043 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8044 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8045 writeq(val64, &bar0->rmac_addr_cmd_mem);
8046 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8047 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
8048 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8049 mac_down = (u32) tmp64;
8050 mac_up = (u32) (tmp64 >> 32);
8051
8052 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8053 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8054 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8055 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8056 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8057 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8058
8059 /* Set the factory defined MAC address initially */
8060 dev->addr_len = ETH_ALEN;
8061 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8062 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8063
8064 /* initialize number of multicast & unicast MAC entries variables */
8065 if (sp->device_type == XFRAME_I_DEVICE) {
8066 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8067 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8068 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8069 } else if (sp->device_type == XFRAME_II_DEVICE) {
8070 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8071 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8072 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8073 }
8074
8075 /* store mac addresses from CAM to s2io_nic structure */
8076 do_s2io_store_unicast_mc(sp);
8077
8078 /* Configure MSIX vector for number of rings configured plus one */
8079 if ((sp->device_type == XFRAME_II_DEVICE) &&
8080 (config->intr_type == MSI_X))
8081 sp->num_entries = config->rx_ring_num + 1;
8082
8083 /* Store the values of the MSIX table in the s2io_nic structure */
8084 store_xmsi_data(sp);
8085 /* reset Nic and bring it to known state */
8086 s2io_reset(sp);
8087
8088 /*
8089 * Initialize link state flags
8090 * and the card state parameter
8091 */
8092 sp->state = 0;
8093
8094 /* Initialize spinlocks */
8095 for (i = 0; i < sp->config.tx_fifo_num; i++)
8096 spin_lock_init(&mac_control->fifos[i].tx_lock);
8097
8098 /*
8099 * SXE-002: Configure link and activity LED to init state
8100 * on driver load.
8101 */
8102 subid = sp->pdev->subsystem_device;
8103 if ((subid & 0xFF) >= 0x07) {
8104 val64 = readq(&bar0->gpio_control);
8105 val64 |= 0x0000800000000000ULL;
8106 writeq(val64, &bar0->gpio_control);
8107 val64 = 0x0411040400000000ULL;
8108 writeq(val64, (void __iomem *) bar0 + 0x2700);
8109 val64 = readq(&bar0->gpio_control);
8110 }
8111
8112 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8113
8114 if (register_netdev(dev)) {
8115 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8116 ret = -ENODEV;
8117 goto register_failed;
8118 }
8119 s2io_vpd_read(sp);
8120 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8121 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
8122 sp->product_name, pdev->revision);
8123 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8124 s2io_driver_version);
8125 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
8126 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
8127 if (sp->device_type & XFRAME_II_DEVICE) {
8128 mode = s2io_print_pci_mode(sp);
8129 if (mode < 0) {
8130 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8131 ret = -EBADSLT;
8132 unregister_netdev(dev);
8133 goto set_swap_failed;
8134 }
8135 }
8136 switch(sp->rxd_mode) {
8137 case RXD_MODE_1:
8138 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8139 dev->name);
8140 break;
8141 case RXD_MODE_3B:
8142 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8143 dev->name);
8144 break;
8145 }
8146
8147 switch (sp->config.napi) {
8148 case 0:
8149 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8150 break;
8151 case 1:
8152 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8153 break;
8154 }
8155
8156 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8157 sp->config.tx_fifo_num);
8158
8159 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8160 sp->config.rx_ring_num);
8161
8162 switch(sp->config.intr_type) {
8163 case INTA:
8164 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8165 break;
8166 case MSI_X:
8167 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8168 break;
8169 }
8170 if (sp->config.multiq) {
8171 for (i = 0; i < sp->config.tx_fifo_num; i++)
8172 mac_control->fifos[i].multiq = config->multiq;
8173 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8174 dev->name);
8175 } else
8176 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8177 dev->name);
8178
8179 switch (sp->config.tx_steering_type) {
8180 case NO_STEERING:
8181 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8182 " transmit\n", dev->name);
8183 break;
8184 case TX_PRIORITY_STEERING:
8185 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8186 " transmit\n", dev->name);
8187 break;
8188 case TX_DEFAULT_STEERING:
8189 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8190 " transmit\n", dev->name);
8191 }
8192
8193 if (sp->lro)
8194 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8195 dev->name);
8196 if (ufo)
8197 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8198 " enabled\n", dev->name);
8199 /* Initialize device name */
8200 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8201
8202 if (vlan_tag_strip)
8203 sp->vlan_strip_flag = 1;
8204 else
8205 sp->vlan_strip_flag = 0;
8206
8207 /*
8208 * Make Link state as off at this point, when the Link change
8209 * interrupt comes the state will be automatically changed to
8210 * the right state.
8211 */
8212 netif_carrier_off(dev);
8213
8214 return 0;
8215
8216 register_failed:
8217 set_swap_failed:
8218 iounmap(sp->bar1);
8219 bar1_remap_failed:
8220 iounmap(sp->bar0);
8221 bar0_remap_failed:
8222 mem_alloc_failed:
8223 free_shared_mem(sp);
8224 pci_disable_device(pdev);
8225 pci_release_regions(pdev);
8226 pci_set_drvdata(pdev, NULL);
8227 free_netdev(dev);
8228
8229 return ret;
8230 }
8231
8232 /**
8233 * s2io_rem_nic - Free the PCI device
8234 * @pdev: structure containing the PCI related information of the device.
8235 * Description: This function is called by the Pci subsystem to release a
8236 * PCI device and free up all resource held up by the device. This could
8237 * be in response to a Hot plug event or when the driver is to be removed
8238 * from memory.
8239 */
8240
8241 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8242 {
8243 struct net_device *dev =
8244 (struct net_device *) pci_get_drvdata(pdev);
8245 struct s2io_nic *sp;
8246
8247 if (dev == NULL) {
8248 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8249 return;
8250 }
8251
8252 flush_scheduled_work();
8253
8254 sp = netdev_priv(dev);
8255 unregister_netdev(dev);
8256
8257 free_shared_mem(sp);
8258 iounmap(sp->bar0);
8259 iounmap(sp->bar1);
8260 pci_release_regions(pdev);
8261 pci_set_drvdata(pdev, NULL);
8262 free_netdev(dev);
8263 pci_disable_device(pdev);
8264 }
8265
8266 /**
8267 * s2io_starter - Entry point for the driver
8268 * Description: This function is the entry point for the driver. It verifies
8269 * the module loadable parameters and initializes PCI configuration space.
8270 */
8271
8272 static int __init s2io_starter(void)
8273 {
8274 return pci_register_driver(&s2io_driver);
8275 }
8276
8277 /**
8278 * s2io_closer - Cleanup routine for the driver
8279 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8280 */
8281
8282 static __exit void s2io_closer(void)
8283 {
8284 pci_unregister_driver(&s2io_driver);
8285 DBG_PRINT(INIT_DBG, "cleanup done\n");
8286 }
8287
8288 module_init(s2io_starter);
8289 module_exit(s2io_closer);
8290
8291 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8292 struct tcphdr **tcp, struct RxD_t *rxdp,
8293 struct s2io_nic *sp)
8294 {
8295 int ip_off;
8296 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8297
8298 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8299 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8300 __func__);
8301 return -1;
8302 }
8303
8304 /* Checking for DIX type or DIX type with VLAN */
8305 if ((l2_type == 0)
8306 || (l2_type == 4)) {
8307 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8308 /*
8309 * If vlan stripping is disabled and the frame is VLAN tagged,
8310 * shift the offset by the VLAN header size bytes.
8311 */
8312 if ((!sp->vlan_strip_flag) &&
8313 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8314 ip_off += HEADER_VLAN_SIZE;
8315 } else {
8316 /* LLC, SNAP etc are considered non-mergeable */
8317 return -1;
8318 }
8319
8320 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8321 ip_len = (u8)((*ip)->ihl);
8322 ip_len <<= 2;
8323 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8324
8325 return 0;
8326 }
8327
8328 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8329 struct tcphdr *tcp)
8330 {
8331 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8332 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8333 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8334 return -1;
8335 return 0;
8336 }
8337
8338 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8339 {
8340 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8341 }
8342
8343 static void initiate_new_session(struct lro *lro, u8 *l2h,
8344 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
8345 {
8346 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8347 lro->l2h = l2h;
8348 lro->iph = ip;
8349 lro->tcph = tcp;
8350 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8351 lro->tcp_ack = tcp->ack_seq;
8352 lro->sg_num = 1;
8353 lro->total_len = ntohs(ip->tot_len);
8354 lro->frags_len = 0;
8355 lro->vlan_tag = vlan_tag;
8356 /*
8357 * check if we saw TCP timestamp. Other consistency checks have
8358 * already been done.
8359 */
8360 if (tcp->doff == 8) {
8361 __be32 *ptr;
8362 ptr = (__be32 *)(tcp+1);
8363 lro->saw_ts = 1;
8364 lro->cur_tsval = ntohl(*(ptr+1));
8365 lro->cur_tsecr = *(ptr+2);
8366 }
8367 lro->in_use = 1;
8368 }
8369
8370 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8371 {
8372 struct iphdr *ip = lro->iph;
8373 struct tcphdr *tcp = lro->tcph;
8374 __sum16 nchk;
8375 struct stat_block *statinfo = sp->mac_control.stats_info;
8376 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8377
8378 /* Update L3 header */
8379 ip->tot_len = htons(lro->total_len);
8380 ip->check = 0;
8381 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8382 ip->check = nchk;
8383
8384 /* Update L4 header */
8385 tcp->ack_seq = lro->tcp_ack;
8386 tcp->window = lro->window;
8387
8388 /* Update tsecr field if this session has timestamps enabled */
8389 if (lro->saw_ts) {
8390 __be32 *ptr = (__be32 *)(tcp + 1);
8391 *(ptr+2) = lro->cur_tsecr;
8392 }
8393
8394 /* Update counters required for calculation of
8395 * average no. of packets aggregated.
8396 */
8397 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8398 statinfo->sw_stat.num_aggregations++;
8399 }
8400
8401 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8402 struct tcphdr *tcp, u32 l4_pyld)
8403 {
8404 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8405 lro->total_len += l4_pyld;
8406 lro->frags_len += l4_pyld;
8407 lro->tcp_next_seq += l4_pyld;
8408 lro->sg_num++;
8409
8410 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8411 lro->tcp_ack = tcp->ack_seq;
8412 lro->window = tcp->window;
8413
8414 if (lro->saw_ts) {
8415 __be32 *ptr;
8416 /* Update tsecr and tsval from this packet */
8417 ptr = (__be32 *)(tcp+1);
8418 lro->cur_tsval = ntohl(*(ptr+1));
8419 lro->cur_tsecr = *(ptr + 2);
8420 }
8421 }
8422
8423 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8424 struct tcphdr *tcp, u32 tcp_pyld_len)
8425 {
8426 u8 *ptr;
8427
8428 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8429
8430 if (!tcp_pyld_len) {
8431 /* Runt frame or a pure ack */
8432 return -1;
8433 }
8434
8435 if (ip->ihl != 5) /* IP has options */
8436 return -1;
8437
8438 /* If we see CE codepoint in IP header, packet is not mergeable */
8439 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8440 return -1;
8441
8442 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8443 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8444 tcp->ece || tcp->cwr || !tcp->ack) {
8445 /*
8446 * Currently recognize only the ack control word and
8447 * any other control field being set would result in
8448 * flushing the LRO session
8449 */
8450 return -1;
8451 }
8452
8453 /*
8454 * Allow only one TCP timestamp option. Don't aggregate if
8455 * any other options are detected.
8456 */
8457 if (tcp->doff != 5 && tcp->doff != 8)
8458 return -1;
8459
8460 if (tcp->doff == 8) {
8461 ptr = (u8 *)(tcp + 1);
8462 while (*ptr == TCPOPT_NOP)
8463 ptr++;
8464 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8465 return -1;
8466
8467 /* Ensure timestamp value increases monotonically */
8468 if (l_lro)
8469 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8470 return -1;
8471
8472 /* timestamp echo reply should be non-zero */
8473 if (*((__be32 *)(ptr+6)) == 0)
8474 return -1;
8475 }
8476
8477 return 0;
8478 }
8479
8480 static int
8481 s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8482 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8483 struct s2io_nic *sp)
8484 {
8485 struct iphdr *ip;
8486 struct tcphdr *tcph;
8487 int ret = 0, i;
8488 u16 vlan_tag = 0;
8489
8490 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8491 rxdp, sp))) {
8492 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8493 ip->saddr, ip->daddr);
8494 } else
8495 return ret;
8496
8497 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8498 tcph = (struct tcphdr *)*tcp;
8499 *tcp_len = get_l4_pyld_length(ip, tcph);
8500 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8501 struct lro *l_lro = &ring_data->lro0_n[i];
8502 if (l_lro->in_use) {
8503 if (check_for_socket_match(l_lro, ip, tcph))
8504 continue;
8505 /* Sock pair matched */
8506 *lro = l_lro;
8507
8508 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8509 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8510 "0x%x, actual 0x%x\n", __func__,
8511 (*lro)->tcp_next_seq,
8512 ntohl(tcph->seq));
8513
8514 sp->mac_control.stats_info->
8515 sw_stat.outof_sequence_pkts++;
8516 ret = 2;
8517 break;
8518 }
8519
8520 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8521 ret = 1; /* Aggregate */
8522 else
8523 ret = 2; /* Flush both */
8524 break;
8525 }
8526 }
8527
8528 if (ret == 0) {
8529 /* Before searching for available LRO objects,
8530 * check if the pkt is L3/L4 aggregatable. If not
8531 * don't create new LRO session. Just send this
8532 * packet up.
8533 */
8534 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8535 return 5;
8536 }
8537
8538 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8539 struct lro *l_lro = &ring_data->lro0_n[i];
8540 if (!(l_lro->in_use)) {
8541 *lro = l_lro;
8542 ret = 3; /* Begin anew */
8543 break;
8544 }
8545 }
8546 }
8547
8548 if (ret == 0) { /* sessions exceeded */
8549 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8550 __func__);
8551 *lro = NULL;
8552 return ret;
8553 }
8554
8555 switch (ret) {
8556 case 3:
8557 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8558 vlan_tag);
8559 break;
8560 case 2:
8561 update_L3L4_header(sp, *lro);
8562 break;
8563 case 1:
8564 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8565 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8566 update_L3L4_header(sp, *lro);
8567 ret = 4; /* Flush the LRO */
8568 }
8569 break;
8570 default:
8571 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8572 __func__);
8573 break;
8574 }
8575
8576 return ret;
8577 }
8578
8579 static void clear_lro_session(struct lro *lro)
8580 {
8581 static u16 lro_struct_size = sizeof(struct lro);
8582
8583 memset(lro, 0, lro_struct_size);
8584 }
8585
8586 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8587 {
8588 struct net_device *dev = skb->dev;
8589 struct s2io_nic *sp = netdev_priv(dev);
8590
8591 skb->protocol = eth_type_trans(skb, dev);
8592 if (sp->vlgrp && vlan_tag
8593 && (sp->vlan_strip_flag)) {
8594 /* Queueing the vlan frame to the upper layer */
8595 if (sp->config.napi)
8596 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8597 else
8598 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8599 } else {
8600 if (sp->config.napi)
8601 netif_receive_skb(skb);
8602 else
8603 netif_rx(skb);
8604 }
8605 }
8606
8607 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8608 struct sk_buff *skb,
8609 u32 tcp_len)
8610 {
8611 struct sk_buff *first = lro->parent;
8612
8613 first->len += tcp_len;
8614 first->data_len = lro->frags_len;
8615 skb_pull(skb, (skb->len - tcp_len));
8616 if (skb_shinfo(first)->frag_list)
8617 lro->last_frag->next = skb;
8618 else
8619 skb_shinfo(first)->frag_list = skb;
8620 first->truesize += skb->truesize;
8621 lro->last_frag = skb;
8622 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8623 return;
8624 }
8625
8626 /**
8627 * s2io_io_error_detected - called when PCI error is detected
8628 * @pdev: Pointer to PCI device
8629 * @state: The current pci connection state
8630 *
8631 * This function is called after a PCI bus error affecting
8632 * this device has been detected.
8633 */
8634 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8635 pci_channel_state_t state)
8636 {
8637 struct net_device *netdev = pci_get_drvdata(pdev);
8638 struct s2io_nic *sp = netdev_priv(netdev);
8639
8640 netif_device_detach(netdev);
8641
8642 if (netif_running(netdev)) {
8643 /* Bring down the card, while avoiding PCI I/O */
8644 do_s2io_card_down(sp, 0);
8645 }
8646 pci_disable_device(pdev);
8647
8648 return PCI_ERS_RESULT_NEED_RESET;
8649 }
8650
8651 /**
8652 * s2io_io_slot_reset - called after the pci bus has been reset.
8653 * @pdev: Pointer to PCI device
8654 *
8655 * Restart the card from scratch, as if from a cold-boot.
8656 * At this point, the card has exprienced a hard reset,
8657 * followed by fixups by BIOS, and has its config space
8658 * set up identically to what it was at cold boot.
8659 */
8660 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8661 {
8662 struct net_device *netdev = pci_get_drvdata(pdev);
8663 struct s2io_nic *sp = netdev_priv(netdev);
8664
8665 if (pci_enable_device(pdev)) {
8666 printk(KERN_ERR "s2io: "
8667 "Cannot re-enable PCI device after reset.\n");
8668 return PCI_ERS_RESULT_DISCONNECT;
8669 }
8670
8671 pci_set_master(pdev);
8672 s2io_reset(sp);
8673
8674 return PCI_ERS_RESULT_RECOVERED;
8675 }
8676
8677 /**
8678 * s2io_io_resume - called when traffic can start flowing again.
8679 * @pdev: Pointer to PCI device
8680 *
8681 * This callback is called when the error recovery driver tells
8682 * us that its OK to resume normal operation.
8683 */
8684 static void s2io_io_resume(struct pci_dev *pdev)
8685 {
8686 struct net_device *netdev = pci_get_drvdata(pdev);
8687 struct s2io_nic *sp = netdev_priv(netdev);
8688
8689 if (netif_running(netdev)) {
8690 if (s2io_card_up(sp)) {
8691 printk(KERN_ERR "s2io: "
8692 "Can't bring device back up after reset.\n");
8693 return;
8694 }
8695
8696 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8697 s2io_card_down(sp);
8698 printk(KERN_ERR "s2io: "
8699 "Can't resetore mac addr after reset.\n");
8700 return;
8701 }
8702 }
8703
8704 netif_device_attach(netdev);
8705 netif_tx_wake_all_queues(netdev);
8706 }
Linux kernel - Deliverables
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