2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
80 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
82 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
84 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
85 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
86 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
100 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
103 static struct ath5k_srev_name srev_names
[] = {
104 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
105 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
106 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
107 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
108 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
109 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
110 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
111 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
112 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
113 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
114 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
115 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
116 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
117 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
118 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
119 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
120 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
121 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
122 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
123 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
124 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
125 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
126 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
127 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
128 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
129 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
130 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
131 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
132 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
133 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
134 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
135 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
136 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
137 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
138 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
139 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 static struct ieee80211_rate ath5k_rates
[] = {
144 .hw_value
= ATH5K_RATE_CODE_1M
, },
146 .hw_value
= ATH5K_RATE_CODE_2M
,
147 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
148 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
150 .hw_value
= ATH5K_RATE_CODE_5_5M
,
151 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
152 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
154 .hw_value
= ATH5K_RATE_CODE_11M
,
155 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
156 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
158 .hw_value
= ATH5K_RATE_CODE_6M
,
161 .hw_value
= ATH5K_RATE_CODE_9M
,
164 .hw_value
= ATH5K_RATE_CODE_12M
,
167 .hw_value
= ATH5K_RATE_CODE_18M
,
170 .hw_value
= ATH5K_RATE_CODE_24M
,
173 .hw_value
= ATH5K_RATE_CODE_36M
,
176 .hw_value
= ATH5K_RATE_CODE_48M
,
179 .hw_value
= ATH5K_RATE_CODE_54M
,
185 * Prototypes - PCI stack related functions
187 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
188 const struct pci_device_id
*id
);
189 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
191 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
193 static int ath5k_pci_resume(struct pci_dev
*pdev
);
195 #define ath5k_pci_suspend NULL
196 #define ath5k_pci_resume NULL
197 #endif /* CONFIG_PM */
199 static struct pci_driver ath5k_pci_driver
= {
201 .id_table
= ath5k_pci_id_table
,
202 .probe
= ath5k_pci_probe
,
203 .remove
= __devexit_p(ath5k_pci_remove
),
204 .suspend
= ath5k_pci_suspend
,
205 .resume
= ath5k_pci_resume
,
211 * Prototypes - MAC 802.11 stack related functions
213 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
214 static int ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
);
215 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
216 static int ath5k_start(struct ieee80211_hw
*hw
);
217 static void ath5k_stop(struct ieee80211_hw
*hw
);
218 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
219 struct ieee80211_if_init_conf
*conf
);
220 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
221 struct ieee80211_if_init_conf
*conf
);
222 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
223 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
224 struct ieee80211_vif
*vif
,
225 struct ieee80211_if_conf
*conf
);
226 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
227 unsigned int changed_flags
,
228 unsigned int *new_flags
,
229 int mc_count
, struct dev_mc_list
*mclist
);
230 static int ath5k_set_key(struct ieee80211_hw
*hw
,
231 enum set_key_cmd cmd
,
232 const u8
*local_addr
, const u8
*addr
,
233 struct ieee80211_key_conf
*key
);
234 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
235 struct ieee80211_low_level_stats
*stats
);
236 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
237 struct ieee80211_tx_queue_stats
*stats
);
238 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
239 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
240 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
241 struct sk_buff
*skb
);
243 static struct ieee80211_ops ath5k_hw_ops
= {
245 .start
= ath5k_start
,
247 .add_interface
= ath5k_add_interface
,
248 .remove_interface
= ath5k_remove_interface
,
249 .config
= ath5k_config
,
250 .config_interface
= ath5k_config_interface
,
251 .configure_filter
= ath5k_configure_filter
,
252 .set_key
= ath5k_set_key
,
253 .get_stats
= ath5k_get_stats
,
255 .get_tx_stats
= ath5k_get_tx_stats
,
256 .get_tsf
= ath5k_get_tsf
,
257 .reset_tsf
= ath5k_reset_tsf
,
261 * Prototypes - Internal functions
264 static int ath5k_attach(struct pci_dev
*pdev
,
265 struct ieee80211_hw
*hw
);
266 static void ath5k_detach(struct pci_dev
*pdev
,
267 struct ieee80211_hw
*hw
);
268 /* Channel/mode setup */
269 static inline short ath5k_ieee2mhz(short chan
);
270 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
271 struct ieee80211_channel
*channels
,
274 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
275 static int ath5k_chan_set(struct ath5k_softc
*sc
,
276 struct ieee80211_channel
*chan
);
277 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
279 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
281 /* Descriptor setup */
282 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
283 struct pci_dev
*pdev
);
284 static void ath5k_desc_free(struct ath5k_softc
*sc
,
285 struct pci_dev
*pdev
);
287 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
288 struct ath5k_buf
*bf
);
289 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
290 struct ath5k_buf
*bf
);
291 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
292 struct ath5k_buf
*bf
)
297 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
299 dev_kfree_skb_any(bf
->skb
);
304 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
305 int qtype
, int subtype
);
306 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
307 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
308 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
309 struct ath5k_txq
*txq
);
310 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
311 static void ath5k_txq_release(struct ath5k_softc
*sc
);
313 static int ath5k_rx_start(struct ath5k_softc
*sc
);
314 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
315 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
316 struct ath5k_desc
*ds
,
318 struct ath5k_rx_status
*rs
);
319 static void ath5k_tasklet_rx(unsigned long data
);
321 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
322 struct ath5k_txq
*txq
);
323 static void ath5k_tasklet_tx(unsigned long data
);
324 /* Beacon handling */
325 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
326 struct ath5k_buf
*bf
);
327 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
328 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
329 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
331 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
333 u64 tsf
= ath5k_hw_get_tsf64(ah
);
335 if ((tsf
& 0x7fff) < rstamp
)
338 return (tsf
& ~0x7fff) | rstamp
;
341 /* Interrupt handling */
342 static int ath5k_init(struct ath5k_softc
*sc
, bool is_resume
);
343 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
344 static int ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
);
345 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
346 static void ath5k_tasklet_reset(unsigned long data
);
348 static void ath5k_calibrate(unsigned long data
);
350 static int ath5k_init_leds(struct ath5k_softc
*sc
);
351 static void ath5k_led_enable(struct ath5k_softc
*sc
);
352 static void ath5k_led_off(struct ath5k_softc
*sc
);
353 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
356 * Module init/exit functions
365 ret
= pci_register_driver(&ath5k_pci_driver
);
367 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
377 pci_unregister_driver(&ath5k_pci_driver
);
379 ath5k_debug_finish();
382 module_init(init_ath5k_pci
);
383 module_exit(exit_ath5k_pci
);
386 /********************\
387 * PCI Initialization *
388 \********************/
391 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
393 const char *name
= "xxxxx";
396 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
397 if (srev_names
[i
].sr_type
!= type
)
400 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
401 name
= srev_names
[i
].sr_name
;
403 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
404 name
= srev_names
[i
].sr_name
;
413 ath5k_pci_probe(struct pci_dev
*pdev
,
414 const struct pci_device_id
*id
)
417 struct ath5k_softc
*sc
;
418 struct ieee80211_hw
*hw
;
422 ret
= pci_enable_device(pdev
);
424 dev_err(&pdev
->dev
, "can't enable device\n");
428 /* XXX 32-bit addressing only */
429 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
431 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
436 * Cache line size is used to size and align various
437 * structures used to communicate with the hardware.
439 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
442 * Linux 2.4.18 (at least) writes the cache line size
443 * register as a 16-bit wide register which is wrong.
444 * We must have this setup properly for rx buffer
445 * DMA to work so force a reasonable value here if it
448 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
449 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
452 * The default setting of latency timer yields poor results,
453 * set it to the value used by other systems. It may be worth
454 * tweaking this setting more.
456 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
458 /* Enable bus mastering */
459 pci_set_master(pdev
);
462 * Disable the RETRY_TIMEOUT register (0x41) to keep
463 * PCI Tx retries from interfering with C3 CPU state.
465 pci_write_config_byte(pdev
, 0x41, 0);
467 ret
= pci_request_region(pdev
, 0, "ath5k");
469 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
473 mem
= pci_iomap(pdev
, 0, 0);
475 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
481 * Allocate hw (mac80211 main struct)
482 * and hw->priv (driver private data)
484 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
486 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
491 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
493 /* Initialize driver private data */
494 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
495 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
496 IEEE80211_HW_SIGNAL_DBM
|
497 IEEE80211_HW_NOISE_DBM
;
499 hw
->wiphy
->interface_modes
=
500 BIT(NL80211_IFTYPE_STATION
) |
501 BIT(NL80211_IFTYPE_ADHOC
) |
502 BIT(NL80211_IFTYPE_MESH_POINT
);
504 hw
->extra_tx_headroom
= 2;
505 hw
->channel_change_time
= 5000;
510 ath5k_debug_init_device(sc
);
513 * Mark the device as detached to avoid processing
514 * interrupts until setup is complete.
516 __set_bit(ATH_STAT_INVALID
, sc
->status
);
518 sc
->iobase
= mem
; /* So we can unmap it on detach */
519 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
520 sc
->opmode
= NL80211_IFTYPE_STATION
;
521 mutex_init(&sc
->lock
);
522 spin_lock_init(&sc
->rxbuflock
);
523 spin_lock_init(&sc
->txbuflock
);
524 spin_lock_init(&sc
->block
);
526 /* Set private data */
527 pci_set_drvdata(pdev
, hw
);
529 /* Setup interrupt handler */
530 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
532 ATH5K_ERR(sc
, "request_irq failed\n");
536 /* Initialize device */
537 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
538 if (IS_ERR(sc
->ah
)) {
539 ret
= PTR_ERR(sc
->ah
);
543 /* set up multi-rate retry capabilities */
544 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
545 hw
->max_altrates
= 3;
546 hw
->max_altrate_tries
= 11;
549 /* Finish private driver data initialization */
550 ret
= ath5k_attach(pdev
, hw
);
554 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
555 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
557 sc
->ah
->ah_phy_revision
);
559 if (!sc
->ah
->ah_single_chip
) {
560 /* Single chip radio (!RF5111) */
561 if (sc
->ah
->ah_radio_5ghz_revision
&&
562 !sc
->ah
->ah_radio_2ghz_revision
) {
563 /* No 5GHz support -> report 2GHz radio */
564 if (!test_bit(AR5K_MODE_11A
,
565 sc
->ah
->ah_capabilities
.cap_mode
)) {
566 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
567 ath5k_chip_name(AR5K_VERSION_RAD
,
568 sc
->ah
->ah_radio_5ghz_revision
),
569 sc
->ah
->ah_radio_5ghz_revision
);
570 /* No 2GHz support (5110 and some
571 * 5Ghz only cards) -> report 5Ghz radio */
572 } else if (!test_bit(AR5K_MODE_11B
,
573 sc
->ah
->ah_capabilities
.cap_mode
)) {
574 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
575 ath5k_chip_name(AR5K_VERSION_RAD
,
576 sc
->ah
->ah_radio_5ghz_revision
),
577 sc
->ah
->ah_radio_5ghz_revision
);
578 /* Multiband radio */
580 ATH5K_INFO(sc
, "RF%s multiband radio found"
582 ath5k_chip_name(AR5K_VERSION_RAD
,
583 sc
->ah
->ah_radio_5ghz_revision
),
584 sc
->ah
->ah_radio_5ghz_revision
);
587 /* Multi chip radio (RF5111 - RF2111) ->
588 * report both 2GHz/5GHz radios */
589 else if (sc
->ah
->ah_radio_5ghz_revision
&&
590 sc
->ah
->ah_radio_2ghz_revision
){
591 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
592 ath5k_chip_name(AR5K_VERSION_RAD
,
593 sc
->ah
->ah_radio_5ghz_revision
),
594 sc
->ah
->ah_radio_5ghz_revision
);
595 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD
,
597 sc
->ah
->ah_radio_2ghz_revision
),
598 sc
->ah
->ah_radio_2ghz_revision
);
603 /* ready to process interrupts */
604 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
608 ath5k_hw_detach(sc
->ah
);
610 free_irq(pdev
->irq
, sc
);
612 ieee80211_free_hw(hw
);
614 pci_iounmap(pdev
, mem
);
616 pci_release_region(pdev
, 0);
618 pci_disable_device(pdev
);
623 static void __devexit
624 ath5k_pci_remove(struct pci_dev
*pdev
)
626 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
627 struct ath5k_softc
*sc
= hw
->priv
;
629 ath5k_debug_finish_device(sc
);
630 ath5k_detach(pdev
, hw
);
631 ath5k_hw_detach(sc
->ah
);
632 free_irq(pdev
->irq
, sc
);
633 pci_iounmap(pdev
, sc
->iobase
);
634 pci_release_region(pdev
, 0);
635 pci_disable_device(pdev
);
636 ieee80211_free_hw(hw
);
641 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
643 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
644 struct ath5k_softc
*sc
= hw
->priv
;
648 ath5k_stop_hw(sc
, true);
650 free_irq(pdev
->irq
, sc
);
651 pci_save_state(pdev
);
652 pci_disable_device(pdev
);
653 pci_set_power_state(pdev
, PCI_D3hot
);
659 ath5k_pci_resume(struct pci_dev
*pdev
)
661 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
662 struct ath5k_softc
*sc
= hw
->priv
;
665 pci_restore_state(pdev
);
667 err
= pci_enable_device(pdev
);
672 * Suspend/Resume resets the PCI configuration space, so we have to
673 * re-disable the RETRY_TIMEOUT register (0x41) to keep
674 * PCI Tx retries from interfering with C3 CPU state
676 pci_write_config_byte(pdev
, 0x41, 0);
678 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
680 ATH5K_ERR(sc
, "request_irq failed\n");
684 err
= ath5k_init(sc
, true);
687 ath5k_led_enable(sc
);
691 free_irq(pdev
->irq
, sc
);
693 pci_disable_device(pdev
);
696 #endif /* CONFIG_PM */
699 /***********************\
700 * Driver Initialization *
701 \***********************/
704 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
706 struct ath5k_softc
*sc
= hw
->priv
;
707 struct ath5k_hw
*ah
= sc
->ah
;
711 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
714 * Check if the MAC has multi-rate retry support.
715 * We do this by trying to setup a fake extended
716 * descriptor. MAC's that don't have support will
717 * return false w/o doing anything. MAC's that do
718 * support it will return true w/o doing anything.
720 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
724 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
727 * Collect the channel list. The 802.11 layer
728 * is resposible for filtering this list based
729 * on settings like the phy mode and regulatory
730 * domain restrictions.
732 ret
= ath5k_setup_bands(hw
);
734 ATH5K_ERR(sc
, "can't get channels\n");
738 /* NB: setup here so ath5k_rate_update is happy */
739 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
740 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
742 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
745 * Allocate tx+rx descriptors and populate the lists.
747 ret
= ath5k_desc_alloc(sc
, pdev
);
749 ATH5K_ERR(sc
, "can't allocate descriptors\n");
754 * Allocate hardware transmit queues: one queue for
755 * beacon frames and one data queue for each QoS
756 * priority. Note that hw functions handle reseting
757 * these queues at the needed time.
759 ret
= ath5k_beaconq_setup(ah
);
761 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
766 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
767 if (IS_ERR(sc
->txq
)) {
768 ATH5K_ERR(sc
, "can't setup xmit queue\n");
769 ret
= PTR_ERR(sc
->txq
);
773 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
774 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
775 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
776 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
778 ath5k_hw_get_lladdr(ah
, mac
);
779 SET_IEEE80211_PERM_ADDR(hw
, mac
);
780 /* All MAC address bits matter for ACKs */
781 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
782 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
784 ret
= ieee80211_register_hw(hw
);
786 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
794 ath5k_txq_release(sc
);
796 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
798 ath5k_desc_free(sc
, pdev
);
804 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
806 struct ath5k_softc
*sc
= hw
->priv
;
809 * NB: the order of these is important:
810 * o call the 802.11 layer before detaching ath5k_hw to
811 * insure callbacks into the driver to delete global
812 * key cache entries can be handled
813 * o reclaim the tx queue data structures after calling
814 * the 802.11 layer as we'll get called back to reclaim
815 * node state and potentially want to use them
816 * o to cleanup the tx queues the hal is called, so detach
818 * XXX: ??? detach ath5k_hw ???
819 * Other than that, it's straightforward...
821 ieee80211_unregister_hw(hw
);
822 ath5k_desc_free(sc
, pdev
);
823 ath5k_txq_release(sc
);
824 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
825 ath5k_unregister_leds(sc
);
828 * NB: can't reclaim these until after ieee80211_ifdetach
829 * returns because we'll get called back to reclaim node
830 * state and potentially want to use them.
837 /********************\
838 * Channel/mode setup *
839 \********************/
842 * Convert IEEE channel number to MHz frequency.
845 ath5k_ieee2mhz(short chan
)
847 if (chan
<= 14 || chan
>= 27)
848 return ieee80211chan2mhz(chan
);
850 return 2212 + chan
* 20;
854 ath5k_copy_channels(struct ath5k_hw
*ah
,
855 struct ieee80211_channel
*channels
,
859 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
861 if (!test_bit(mode
, ah
->ah_modes
))
866 case AR5K_MODE_11A_TURBO
:
867 /* 1..220, but 2GHz frequencies are filtered by check_channel */
869 chfreq
= CHANNEL_5GHZ
;
873 case AR5K_MODE_11G_TURBO
:
875 chfreq
= CHANNEL_2GHZ
;
878 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
882 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
884 freq
= ath5k_ieee2mhz(ch
);
886 /* Check if channel is supported by the chipset */
887 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
890 /* Write channel info and increment counter */
891 channels
[count
].center_freq
= freq
;
892 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
893 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
897 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
899 case AR5K_MODE_11A_TURBO
:
900 case AR5K_MODE_11G_TURBO
:
901 channels
[count
].hw_value
= chfreq
|
902 CHANNEL_OFDM
| CHANNEL_TURBO
;
905 channels
[count
].hw_value
= CHANNEL_B
;
916 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
920 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
921 sc
->rate_idx
[b
->band
][i
] = -1;
923 for (i
= 0; i
< b
->n_bitrates
; i
++) {
924 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
925 if (b
->bitrates
[i
].hw_value_short
)
926 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
931 ath5k_setup_bands(struct ieee80211_hw
*hw
)
933 struct ath5k_softc
*sc
= hw
->priv
;
934 struct ath5k_hw
*ah
= sc
->ah
;
935 struct ieee80211_supported_band
*sband
;
936 int max_c
, count_c
= 0;
939 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
940 max_c
= ARRAY_SIZE(sc
->channels
);
943 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
944 sband
->band
= IEEE80211_BAND_2GHZ
;
945 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
947 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
949 memcpy(sband
->bitrates
, &ath5k_rates
[0],
950 sizeof(struct ieee80211_rate
) * 12);
951 sband
->n_bitrates
= 12;
953 sband
->channels
= sc
->channels
;
954 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
955 AR5K_MODE_11G
, max_c
);
957 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
958 count_c
= sband
->n_channels
;
960 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
962 memcpy(sband
->bitrates
, &ath5k_rates
[0],
963 sizeof(struct ieee80211_rate
) * 4);
964 sband
->n_bitrates
= 4;
966 /* 5211 only supports B rates and uses 4bit rate codes
967 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
970 if (ah
->ah_version
== AR5K_AR5211
) {
971 for (i
= 0; i
< 4; i
++) {
972 sband
->bitrates
[i
].hw_value
=
973 sband
->bitrates
[i
].hw_value
& 0xF;
974 sband
->bitrates
[i
].hw_value_short
=
975 sband
->bitrates
[i
].hw_value_short
& 0xF;
979 sband
->channels
= sc
->channels
;
980 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
981 AR5K_MODE_11B
, max_c
);
983 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
984 count_c
= sband
->n_channels
;
987 ath5k_setup_rate_idx(sc
, sband
);
989 /* 5GHz band, A mode */
990 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
991 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
992 sband
->band
= IEEE80211_BAND_5GHZ
;
993 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
995 memcpy(sband
->bitrates
, &ath5k_rates
[4],
996 sizeof(struct ieee80211_rate
) * 8);
997 sband
->n_bitrates
= 8;
999 sband
->channels
= &sc
->channels
[count_c
];
1000 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1001 AR5K_MODE_11A
, max_c
);
1003 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1005 ath5k_setup_rate_idx(sc
, sband
);
1007 ath5k_debug_dump_bands(sc
);
1013 * Set/change channels. If the channel is really being changed,
1014 * it's done by reseting the chip. To accomplish this we must
1015 * first cleanup any pending DMA, then restart stuff after a la
1019 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1021 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1022 sc
->curchan
->center_freq
, chan
->center_freq
);
1024 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1025 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1028 sc
->curband
= &sc
->sbands
[chan
->band
];
1031 * To switch channels clear any pending DMA operations;
1032 * wait long enough for the RX fifo to drain, reset the
1033 * hardware at the new frequency, and then re-enable
1034 * the relevant bits of the h/w.
1036 return ath5k_reset(sc
, true, true);
1043 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1047 if (mode
== AR5K_MODE_11A
) {
1048 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1050 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1055 ath5k_mode_setup(struct ath5k_softc
*sc
)
1057 struct ath5k_hw
*ah
= sc
->ah
;
1060 /* configure rx filter */
1061 rfilt
= sc
->filter_flags
;
1062 ath5k_hw_set_rx_filter(ah
, rfilt
);
1064 if (ath5k_hw_hasbssidmask(ah
))
1065 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1067 /* configure operational mode */
1068 ath5k_hw_set_opmode(ah
);
1070 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1071 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1075 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1077 WARN_ON(hw_rix
< 0 || hw_rix
> AR5K_MAX_RATES
);
1078 return sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1086 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1088 struct ath5k_hw
*ah
= sc
->ah
;
1089 struct sk_buff
*skb
= bf
->skb
;
1090 struct ath5k_desc
*ds
;
1092 if (likely(skb
== NULL
)) {
1096 * Allocate buffer with headroom_needed space for the
1097 * fake physical layer header at the start.
1099 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1100 if (unlikely(skb
== NULL
)) {
1101 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1102 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1106 * Cache-line-align. This is important (for the
1107 * 5210 at least) as not doing so causes bogus data
1110 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1112 skb_reserve(skb
, sc
->cachelsz
- off
);
1115 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1116 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1117 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
))) {
1118 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1126 * Setup descriptors. For receive we always terminate
1127 * the descriptor list with a self-linked entry so we'll
1128 * not get overrun under high load (as can happen with a
1129 * 5212 when ANI processing enables PHY error frames).
1131 * To insure the last descriptor is self-linked we create
1132 * each descriptor as self-linked and add it to the end. As
1133 * each additional descriptor is added the previous self-linked
1134 * entry is ``fixed'' naturally. This should be safe even
1135 * if DMA is happening. When processing RX interrupts we
1136 * never remove/process the last, self-linked, entry on the
1137 * descriptor list. This insures the hardware always has
1138 * someplace to write a new frame.
1141 ds
->ds_link
= bf
->daddr
; /* link to self */
1142 ds
->ds_data
= bf
->skbaddr
;
1143 ah
->ah_setup_rx_desc(ah
, ds
,
1144 skb_tailroom(skb
), /* buffer size */
1147 if (sc
->rxlink
!= NULL
)
1148 *sc
->rxlink
= bf
->daddr
;
1149 sc
->rxlink
= &ds
->ds_link
;
1154 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1156 struct ath5k_hw
*ah
= sc
->ah
;
1157 struct ath5k_txq
*txq
= sc
->txq
;
1158 struct ath5k_desc
*ds
= bf
->desc
;
1159 struct sk_buff
*skb
= bf
->skb
;
1160 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1161 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1162 struct ieee80211_rate
*rate
;
1163 unsigned int mrr_rate
[3], mrr_tries
[3];
1166 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1168 /* XXX endianness */
1169 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1172 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1173 flags
|= AR5K_TXDESC_NOACK
;
1177 if (info
->control
.hw_key
) {
1178 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1179 pktlen
+= info
->control
.hw_key
->icv_len
;
1181 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1182 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1183 (sc
->power_level
* 2),
1184 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1185 info
->control
.retry_limit
, keyidx
, 0, flags
, 0, 0);
1189 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1190 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1191 for (i
= 0; i
< 3; i
++) {
1192 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1196 mrr_rate
[i
] = rate
->hw_value
;
1197 mrr_tries
[i
] = info
->control
.retries
[i
].limit
;
1200 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1201 mrr_rate
[0], mrr_tries
[0],
1202 mrr_rate
[1], mrr_tries
[1],
1203 mrr_rate
[2], mrr_tries
[2]);
1206 ds
->ds_data
= bf
->skbaddr
;
1208 spin_lock_bh(&txq
->lock
);
1209 list_add_tail(&bf
->list
, &txq
->q
);
1210 sc
->tx_stats
[txq
->qnum
].len
++;
1211 if (txq
->link
== NULL
) /* is this first packet? */
1212 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1213 else /* no, so only link it */
1214 *txq
->link
= bf
->daddr
;
1216 txq
->link
= &ds
->ds_link
;
1217 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1219 spin_unlock_bh(&txq
->lock
);
1223 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1227 /*******************\
1228 * Descriptors setup *
1229 \*******************/
1232 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1234 struct ath5k_desc
*ds
;
1235 struct ath5k_buf
*bf
;
1240 /* allocate descriptors */
1241 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1242 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1243 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1244 if (sc
->desc
== NULL
) {
1245 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1250 da
= sc
->desc_daddr
;
1251 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1252 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1254 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1255 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1257 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1263 INIT_LIST_HEAD(&sc
->rxbuf
);
1264 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1267 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1270 INIT_LIST_HEAD(&sc
->txbuf
);
1271 sc
->txbuf_len
= ATH_TXBUF
;
1272 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1273 da
+= sizeof(*ds
)) {
1276 list_add_tail(&bf
->list
, &sc
->txbuf
);
1286 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1293 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1295 struct ath5k_buf
*bf
;
1297 ath5k_txbuf_free(sc
, sc
->bbuf
);
1298 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1299 ath5k_txbuf_free(sc
, bf
);
1300 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1301 ath5k_txbuf_free(sc
, bf
);
1303 /* Free memory associated with all descriptors */
1304 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1318 static struct ath5k_txq
*
1319 ath5k_txq_setup(struct ath5k_softc
*sc
,
1320 int qtype
, int subtype
)
1322 struct ath5k_hw
*ah
= sc
->ah
;
1323 struct ath5k_txq
*txq
;
1324 struct ath5k_txq_info qi
= {
1325 .tqi_subtype
= subtype
,
1326 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1327 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1328 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1333 * Enable interrupts only for EOL and DESC conditions.
1334 * We mark tx descriptors to receive a DESC interrupt
1335 * when a tx queue gets deep; otherwise waiting for the
1336 * EOL to reap descriptors. Note that this is done to
1337 * reduce interrupt load and this only defers reaping
1338 * descriptors, never transmitting frames. Aside from
1339 * reducing interrupts this also permits more concurrency.
1340 * The only potential downside is if the tx queue backs
1341 * up in which case the top half of the kernel may backup
1342 * due to a lack of tx descriptors.
1344 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1345 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1346 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1349 * NB: don't print a message, this happens
1350 * normally on parts with too few tx queues
1352 return ERR_PTR(qnum
);
1354 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1355 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1356 qnum
, ARRAY_SIZE(sc
->txqs
));
1357 ath5k_hw_release_tx_queue(ah
, qnum
);
1358 return ERR_PTR(-EINVAL
);
1360 txq
= &sc
->txqs
[qnum
];
1364 INIT_LIST_HEAD(&txq
->q
);
1365 spin_lock_init(&txq
->lock
);
1368 return &sc
->txqs
[qnum
];
1372 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1374 struct ath5k_txq_info qi
= {
1375 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1376 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1377 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1378 /* NB: for dynamic turbo, don't enable any other interrupts */
1379 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1382 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1386 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1388 struct ath5k_hw
*ah
= sc
->ah
;
1389 struct ath5k_txq_info qi
;
1392 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1395 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1396 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1398 * Always burst out beacon and CAB traffic
1399 * (aifs = cwmin = cwmax = 0)
1404 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1406 * Adhoc mode; backoff between 0 and (2 * cw_min).
1410 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1413 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1414 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1415 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1417 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1419 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1420 "hardware queue!\n", __func__
);
1424 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1428 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1430 struct ath5k_buf
*bf
, *bf0
;
1433 * NB: this assumes output has been stopped and
1434 * we do not need to block ath5k_tx_tasklet
1436 spin_lock_bh(&txq
->lock
);
1437 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1438 ath5k_debug_printtxbuf(sc
, bf
);
1440 ath5k_txbuf_free(sc
, bf
);
1442 spin_lock_bh(&sc
->txbuflock
);
1443 sc
->tx_stats
[txq
->qnum
].len
--;
1444 list_move_tail(&bf
->list
, &sc
->txbuf
);
1446 spin_unlock_bh(&sc
->txbuflock
);
1449 spin_unlock_bh(&txq
->lock
);
1453 * Drain the transmit queues and reclaim resources.
1456 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1458 struct ath5k_hw
*ah
= sc
->ah
;
1461 /* XXX return value */
1462 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1463 /* don't touch the hardware if marked invalid */
1464 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1465 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1466 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1467 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1468 if (sc
->txqs
[i
].setup
) {
1469 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1470 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1473 ath5k_hw_get_txdp(ah
,
1478 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1480 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1481 if (sc
->txqs
[i
].setup
)
1482 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1486 ath5k_txq_release(struct ath5k_softc
*sc
)
1488 struct ath5k_txq
*txq
= sc
->txqs
;
1491 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1493 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1506 * Enable the receive h/w following a reset.
1509 ath5k_rx_start(struct ath5k_softc
*sc
)
1511 struct ath5k_hw
*ah
= sc
->ah
;
1512 struct ath5k_buf
*bf
;
1515 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1517 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1518 sc
->cachelsz
, sc
->rxbufsize
);
1522 spin_lock_bh(&sc
->rxbuflock
);
1523 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1524 ret
= ath5k_rxbuf_setup(sc
, bf
);
1526 spin_unlock_bh(&sc
->rxbuflock
);
1530 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1531 spin_unlock_bh(&sc
->rxbuflock
);
1533 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1534 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1535 ath5k_mode_setup(sc
); /* set filters, etc. */
1536 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1544 * Disable the receive h/w in preparation for a reset.
1547 ath5k_rx_stop(struct ath5k_softc
*sc
)
1549 struct ath5k_hw
*ah
= sc
->ah
;
1551 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1552 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1553 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1555 ath5k_debug_printrxbuffs(sc
, ah
);
1557 sc
->rxlink
= NULL
; /* just in case */
1561 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1562 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1564 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1565 unsigned int keyix
, hlen
;
1567 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1568 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1569 return RX_FLAG_DECRYPTED
;
1571 /* Apparently when a default key is used to decrypt the packet
1572 the hw does not set the index used to decrypt. In such cases
1573 get the index from the packet. */
1574 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1575 if (ieee80211_has_protected(hdr
->frame_control
) &&
1576 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1577 skb
->len
>= hlen
+ 4) {
1578 keyix
= skb
->data
[hlen
+ 3] >> 6;
1580 if (test_bit(keyix
, sc
->keymap
))
1581 return RX_FLAG_DECRYPTED
;
1589 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1590 struct ieee80211_rx_status
*rxs
)
1594 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1596 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1597 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1598 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1600 * Received an IBSS beacon with the same BSSID. Hardware *must*
1601 * have updated the local TSF. We have to work around various
1602 * hardware bugs, though...
1604 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1605 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1606 hw_tu
= TSF_TO_TU(tsf
);
1608 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1609 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1610 (unsigned long long)bc_tstamp
,
1611 (unsigned long long)rxs
->mactime
,
1612 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1613 (unsigned long long)tsf
);
1616 * Sometimes the HW will give us a wrong tstamp in the rx
1617 * status, causing the timestamp extension to go wrong.
1618 * (This seems to happen especially with beacon frames bigger
1619 * than 78 byte (incl. FCS))
1620 * But we know that the receive timestamp must be later than the
1621 * timestamp of the beacon since HW must have synced to that.
1623 * NOTE: here we assume mactime to be after the frame was
1624 * received, not like mac80211 which defines it at the start.
1626 if (bc_tstamp
> rxs
->mactime
) {
1627 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1628 "fixing mactime from %llx to %llx\n",
1629 (unsigned long long)rxs
->mactime
,
1630 (unsigned long long)tsf
);
1635 * Local TSF might have moved higher than our beacon timers,
1636 * in that case we have to update them to continue sending
1637 * beacons. This also takes care of synchronizing beacon sending
1638 * times with other stations.
1640 if (hw_tu
>= sc
->nexttbtt
)
1641 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1647 ath5k_tasklet_rx(unsigned long data
)
1649 struct ieee80211_rx_status rxs
= {};
1650 struct ath5k_rx_status rs
= {};
1651 struct sk_buff
*skb
;
1652 struct ath5k_softc
*sc
= (void *)data
;
1653 struct ath5k_buf
*bf
, *bf_last
;
1654 struct ath5k_desc
*ds
;
1659 spin_lock(&sc
->rxbuflock
);
1660 if (list_empty(&sc
->rxbuf
)) {
1661 ATH5K_WARN(sc
, "empty rx buf pool\n");
1664 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1668 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1669 BUG_ON(bf
->skb
== NULL
);
1674 * last buffer must not be freed to ensure proper hardware
1675 * function. When the hardware finishes also a packet next to
1676 * it, we are sure, it doesn't use it anymore and we can go on.
1681 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1682 struct ath5k_buf
, list
);
1683 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1688 /* skip the overwritten one (even status is martian) */
1692 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1693 if (unlikely(ret
== -EINPROGRESS
))
1695 else if (unlikely(ret
)) {
1696 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1697 spin_unlock(&sc
->rxbuflock
);
1701 if (unlikely(rs
.rs_more
)) {
1702 ATH5K_WARN(sc
, "unsupported jumbo\n");
1706 if (unlikely(rs
.rs_status
)) {
1707 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1709 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1711 * Decrypt error. If the error occurred
1712 * because there was no hardware key, then
1713 * let the frame through so the upper layers
1714 * can process it. This is necessary for 5210
1715 * parts which have no way to setup a ``clear''
1718 * XXX do key cache faulting
1720 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1721 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1724 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1725 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1729 /* let crypto-error packets fall through in MNTR */
1731 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1732 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1736 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1737 PCI_DMA_FROMDEVICE
);
1740 skb_put(skb
, rs
.rs_datalen
);
1743 * the hardware adds a padding to 4 byte boundaries between
1744 * the header and the payload data if the header length is
1745 * not multiples of 4 - remove it
1747 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1750 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1755 * always extend the mac timestamp, since this information is
1756 * also needed for proper IBSS merging.
1758 * XXX: it might be too late to do it here, since rs_tstamp is
1759 * 15bit only. that means TSF extension has to be done within
1760 * 32768usec (about 32ms). it might be necessary to move this to
1761 * the interrupt handler, like it is done in madwifi.
1763 * Unfortunately we don't know when the hardware takes the rx
1764 * timestamp (beginning of phy frame, data frame, end of rx?).
1765 * The only thing we know is that it is hardware specific...
1766 * On AR5213 it seems the rx timestamp is at the end of the
1767 * frame, but i'm not sure.
1769 * NOTE: mac80211 defines mactime at the beginning of the first
1770 * data symbol. Since we don't have any time references it's
1771 * impossible to comply to that. This affects IBSS merge only
1772 * right now, so it's not too bad...
1774 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1775 rxs
.flag
|= RX_FLAG_TSFT
;
1777 rxs
.freq
= sc
->curchan
->center_freq
;
1778 rxs
.band
= sc
->curband
->band
;
1780 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1781 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1782 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1784 rxs
.antenna
= rs
.rs_antenna
;
1785 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1786 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1788 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1789 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1790 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1792 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1794 /* check beacons in IBSS mode */
1795 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1796 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1798 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1800 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1801 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1803 spin_unlock(&sc
->rxbuflock
);
1814 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1816 struct ath5k_tx_status ts
= {};
1817 struct ath5k_buf
*bf
, *bf0
;
1818 struct ath5k_desc
*ds
;
1819 struct sk_buff
*skb
;
1820 struct ieee80211_tx_info
*info
;
1823 spin_lock(&txq
->lock
);
1824 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1827 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1828 if (unlikely(ret
== -EINPROGRESS
))
1830 else if (unlikely(ret
)) {
1831 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1837 info
= IEEE80211_SKB_CB(skb
);
1840 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1843 memset(&info
->status
, 0, sizeof(info
->status
));
1844 info
->tx_rate_idx
= ath5k_hw_to_driver_rix(sc
,
1845 ts
.ts_rate
[ts
.ts_final_idx
]);
1846 info
->status
.retry_count
= ts
.ts_longretry
;
1848 for (i
= 0; i
< 4; i
++) {
1849 struct ieee80211_tx_altrate
*r
=
1850 &info
->status
.retries
[i
];
1852 if (ts
.ts_rate
[i
]) {
1853 r
->rate_idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1854 r
->limit
= ts
.ts_retry
[i
];
1861 info
->status
.excessive_retries
= 0;
1862 if (unlikely(ts
.ts_status
)) {
1863 sc
->ll_stats
.dot11ACKFailureCount
++;
1864 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1865 info
->status
.excessive_retries
= 1;
1866 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1867 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1869 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1870 info
->status
.ack_signal
= ts
.ts_rssi
;
1873 ieee80211_tx_status(sc
->hw
, skb
);
1874 sc
->tx_stats
[txq
->qnum
].count
++;
1876 spin_lock(&sc
->txbuflock
);
1877 sc
->tx_stats
[txq
->qnum
].len
--;
1878 list_move_tail(&bf
->list
, &sc
->txbuf
);
1880 spin_unlock(&sc
->txbuflock
);
1882 if (likely(list_empty(&txq
->q
)))
1884 spin_unlock(&txq
->lock
);
1885 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1886 ieee80211_wake_queues(sc
->hw
);
1890 ath5k_tasklet_tx(unsigned long data
)
1892 struct ath5k_softc
*sc
= (void *)data
;
1894 ath5k_tx_processq(sc
, sc
->txq
);
1903 * Setup the beacon frame for transmit.
1906 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1908 struct sk_buff
*skb
= bf
->skb
;
1909 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1910 struct ath5k_hw
*ah
= sc
->ah
;
1911 struct ath5k_desc
*ds
;
1912 int ret
, antenna
= 0;
1915 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1917 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1918 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1919 (unsigned long long)bf
->skbaddr
);
1920 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1921 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1927 flags
= AR5K_TXDESC_NOACK
;
1928 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1929 ds
->ds_link
= bf
->daddr
; /* self-linked */
1930 flags
|= AR5K_TXDESC_VEOL
;
1932 * Let hardware handle antenna switching if txantenna is not set
1937 * Switch antenna every 4 beacons if txantenna is not set
1938 * XXX assumes two antennas
1941 antenna
= sc
->bsent
& 4 ? 2 : 1;
1944 ds
->ds_data
= bf
->skbaddr
;
1945 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1946 ieee80211_get_hdrlen_from_skb(skb
),
1947 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1948 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1949 1, AR5K_TXKEYIX_INVALID
,
1950 antenna
, flags
, 0, 0);
1956 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1961 * Transmit a beacon frame at SWBA. Dynamic updates to the
1962 * frame contents are done as needed and the slot time is
1963 * also adjusted based on current state.
1965 * this is usually called from interrupt context (ath5k_intr())
1966 * but also from ath5k_beacon_config() in IBSS mode which in turn
1967 * can be called from a tasklet and user context
1970 ath5k_beacon_send(struct ath5k_softc
*sc
)
1972 struct ath5k_buf
*bf
= sc
->bbuf
;
1973 struct ath5k_hw
*ah
= sc
->ah
;
1975 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1977 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1978 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1979 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1983 * Check if the previous beacon has gone out. If
1984 * not don't don't try to post another, skip this
1985 * period and wait for the next. Missed beacons
1986 * indicate a problem and should not occur. If we
1987 * miss too many consecutive beacons reset the device.
1989 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1991 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1992 "missed %u consecutive beacons\n", sc
->bmisscount
);
1993 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
1994 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1995 "stuck beacon time (%u missed)\n",
1997 tasklet_schedule(&sc
->restq
);
2001 if (unlikely(sc
->bmisscount
!= 0)) {
2002 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2003 "resume beacon xmit after %u misses\n",
2009 * Stop any current dma and put the new frame on the queue.
2010 * This should never fail since we check above that no frames
2011 * are still pending on the queue.
2013 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2014 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2015 /* NB: hw still stops DMA, so proceed */
2018 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2019 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2020 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2021 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2028 * ath5k_beacon_update_timers - update beacon timers
2030 * @sc: struct ath5k_softc pointer we are operating on
2031 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2032 * beacon timer update based on the current HW TSF.
2034 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2035 * of a received beacon or the current local hardware TSF and write it to the
2036 * beacon timer registers.
2038 * This is called in a variety of situations, e.g. when a beacon is received,
2039 * when a TSF update has been detected, but also when an new IBSS is created or
2040 * when we otherwise know we have to update the timers, but we keep it in this
2041 * function to have it all together in one place.
2044 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2046 struct ath5k_hw
*ah
= sc
->ah
;
2047 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2050 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2051 if (WARN_ON(!intval
))
2054 /* beacon TSF converted to TU */
2055 bc_tu
= TSF_TO_TU(bc_tsf
);
2057 /* current TSF converted to TU */
2058 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2059 hw_tu
= TSF_TO_TU(hw_tsf
);
2062 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2065 * no beacons received, called internally.
2066 * just need to refresh timers based on HW TSF.
2068 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2069 } else if (bc_tsf
== 0) {
2071 * no beacon received, probably called by ath5k_reset_tsf().
2072 * reset TSF to start with 0.
2075 intval
|= AR5K_BEACON_RESET_TSF
;
2076 } else if (bc_tsf
> hw_tsf
) {
2078 * beacon received, SW merge happend but HW TSF not yet updated.
2079 * not possible to reconfigure timers yet, but next time we
2080 * receive a beacon with the same BSSID, the hardware will
2081 * automatically update the TSF and then we need to reconfigure
2084 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2085 "need to wait for HW TSF sync\n");
2089 * most important case for beacon synchronization between STA.
2091 * beacon received and HW TSF has been already updated by HW.
2092 * update next TBTT based on the TSF of the beacon, but make
2093 * sure it is ahead of our local TSF timer.
2095 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2099 sc
->nexttbtt
= nexttbtt
;
2101 intval
|= AR5K_BEACON_ENA
;
2102 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2105 * debugging output last in order to preserve the time critical aspect
2109 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2110 "reconfigured timers based on HW TSF\n");
2111 else if (bc_tsf
== 0)
2112 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2113 "reset HW TSF and timers\n");
2115 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2116 "updated timers based on beacon TSF\n");
2118 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2119 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2120 (unsigned long long) bc_tsf
,
2121 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2122 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2123 intval
& AR5K_BEACON_PERIOD
,
2124 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2125 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2130 * ath5k_beacon_config - Configure the beacon queues and interrupts
2132 * @sc: struct ath5k_softc pointer we are operating on
2134 * When operating in station mode we want to receive a BMISS interrupt when we
2135 * stop seeing beacons from the AP we've associated with so we can look for
2136 * another AP to associate with.
2138 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2139 * interrupts to detect TSF updates only.
2141 * AP mode is missing.
2144 ath5k_beacon_config(struct ath5k_softc
*sc
)
2146 struct ath5k_hw
*ah
= sc
->ah
;
2148 ath5k_hw_set_imr(ah
, 0);
2150 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2152 if (sc
->opmode
== NL80211_IFTYPE_STATION
) {
2153 sc
->imask
|= AR5K_INT_BMISS
;
2154 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2156 * In IBSS mode we use a self-linked tx descriptor and let the
2157 * hardware send the beacons automatically. We have to load it
2159 * We use the SWBA interrupt only to keep track of the beacon
2160 * timers in order to detect automatic TSF updates.
2162 ath5k_beaconq_config(sc
);
2164 sc
->imask
|= AR5K_INT_SWBA
;
2166 if (ath5k_hw_hasveol(ah
)) {
2167 spin_lock(&sc
->block
);
2168 ath5k_beacon_send(sc
);
2169 spin_unlock(&sc
->block
);
2174 ath5k_hw_set_imr(ah
, sc
->imask
);
2178 /********************\
2179 * Interrupt handling *
2180 \********************/
2183 ath5k_init(struct ath5k_softc
*sc
, bool is_resume
)
2185 struct ath5k_hw
*ah
= sc
->ah
;
2188 mutex_lock(&sc
->lock
);
2190 if (is_resume
&& !test_bit(ATH_STAT_STARTED
, sc
->status
))
2193 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2195 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2198 * Stop anything previously setup. This is safe
2199 * no matter this is the first time through or not.
2201 ath5k_stop_locked(sc
);
2204 * The basic interface to setting the hardware in a good
2205 * state is ``reset''. On return the hardware is known to
2206 * be powered up and with interrupts disabled. This must
2207 * be followed by initialization of the appropriate bits
2208 * and then setup of the interrupt mask.
2210 sc
->curchan
= sc
->hw
->conf
.channel
;
2211 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2212 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2213 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2215 ret
= ath5k_reset(sc
, false, false);
2220 * Reset the key cache since some parts do not reset the
2221 * contents on initial power up or resume from suspend.
2223 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2224 ath5k_hw_reset_key(ah
, i
);
2226 __set_bit(ATH_STAT_STARTED
, sc
->status
);
2228 /* Set ack to be sent at low bit-rates */
2229 ath5k_hw_set_ack_bitrate_high(ah
, false);
2231 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2232 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2238 mutex_unlock(&sc
->lock
);
2243 ath5k_stop_locked(struct ath5k_softc
*sc
)
2245 struct ath5k_hw
*ah
= sc
->ah
;
2247 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2248 test_bit(ATH_STAT_INVALID
, sc
->status
));
2251 * Shutdown the hardware and driver:
2252 * stop output from above
2253 * disable interrupts
2255 * turn off the radio
2256 * clear transmit machinery
2257 * clear receive machinery
2258 * drain and release tx queues
2259 * reclaim beacon resources
2260 * power down hardware
2262 * Note that some of this work is not possible if the
2263 * hardware is gone (invalid).
2265 ieee80211_stop_queues(sc
->hw
);
2267 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2269 ath5k_hw_set_imr(ah
, 0);
2270 synchronize_irq(sc
->pdev
->irq
);
2272 ath5k_txq_cleanup(sc
);
2273 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2275 ath5k_hw_phy_disable(ah
);
2283 * Stop the device, grabbing the top-level lock to protect
2284 * against concurrent entry through ath5k_init (which can happen
2285 * if another thread does a system call and the thread doing the
2286 * stop is preempted).
2289 ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
)
2293 mutex_lock(&sc
->lock
);
2294 ret
= ath5k_stop_locked(sc
);
2295 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2297 * Set the chip in full sleep mode. Note that we are
2298 * careful to do this only when bringing the interface
2299 * completely to a stop. When the chip is in this state
2300 * it must be carefully woken up or references to
2301 * registers in the PCI clock domain may freeze the bus
2302 * (and system). This varies by chip and is mostly an
2303 * issue with newer parts that go to sleep more quickly.
2305 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2308 * don't put newer MAC revisions > 7.8 to sleep because
2309 * of the above mentioned problems
2311 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2312 "not putting device to sleep\n");
2314 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2315 "putting device to full sleep\n");
2316 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2319 ath5k_txbuf_free(sc
, sc
->bbuf
);
2321 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2324 mutex_unlock(&sc
->lock
);
2326 del_timer_sync(&sc
->calib_tim
);
2327 tasklet_kill(&sc
->rxtq
);
2328 tasklet_kill(&sc
->txtq
);
2329 tasklet_kill(&sc
->restq
);
2335 ath5k_intr(int irq
, void *dev_id
)
2337 struct ath5k_softc
*sc
= dev_id
;
2338 struct ath5k_hw
*ah
= sc
->ah
;
2339 enum ath5k_int status
;
2340 unsigned int counter
= 1000;
2342 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2343 !ath5k_hw_is_intr_pending(ah
)))
2348 * Figure out the reason(s) for the interrupt. Note
2349 * that get_isr returns a pseudo-ISR that may include
2350 * bits we haven't explicitly enabled so we mask the
2351 * value to insure we only process bits we requested.
2353 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2354 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2356 status
&= sc
->imask
; /* discard unasked for bits */
2357 if (unlikely(status
& AR5K_INT_FATAL
)) {
2359 * Fatal errors are unrecoverable.
2360 * Typically these are caused by DMA errors.
2362 tasklet_schedule(&sc
->restq
);
2363 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2364 tasklet_schedule(&sc
->restq
);
2366 if (status
& AR5K_INT_SWBA
) {
2368 * Software beacon alert--time to send a beacon.
2369 * Handle beacon transmission directly; deferring
2370 * this is too slow to meet timing constraints
2373 * In IBSS mode we use this interrupt just to
2374 * keep track of the next TBTT (target beacon
2375 * transmission time) in order to detect wether
2376 * automatic TSF updates happened.
2378 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2379 /* XXX: only if VEOL suppported */
2380 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2381 sc
->nexttbtt
+= sc
->bintval
;
2382 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2383 "SWBA nexttbtt: %x hw_tu: %x "
2387 (unsigned long long) tsf
);
2389 spin_lock(&sc
->block
);
2390 ath5k_beacon_send(sc
);
2391 spin_unlock(&sc
->block
);
2394 if (status
& AR5K_INT_RXEOL
) {
2396 * NB: the hardware should re-read the link when
2397 * RXE bit is written, but it doesn't work at
2398 * least on older hardware revs.
2402 if (status
& AR5K_INT_TXURN
) {
2403 /* bump tx trigger level */
2404 ath5k_hw_update_tx_triglevel(ah
, true);
2406 if (status
& AR5K_INT_RX
)
2407 tasklet_schedule(&sc
->rxtq
);
2408 if (status
& AR5K_INT_TX
)
2409 tasklet_schedule(&sc
->txtq
);
2410 if (status
& AR5K_INT_BMISS
) {
2412 if (status
& AR5K_INT_MIB
) {
2414 * These stats are also used for ANI i think
2415 * so how about updating them more often ?
2417 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2420 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2422 if (unlikely(!counter
))
2423 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2429 ath5k_tasklet_reset(unsigned long data
)
2431 struct ath5k_softc
*sc
= (void *)data
;
2433 ath5k_reset_wake(sc
);
2437 * Periodically recalibrate the PHY to account
2438 * for temperature/environment changes.
2441 ath5k_calibrate(unsigned long data
)
2443 struct ath5k_softc
*sc
= (void *)data
;
2444 struct ath5k_hw
*ah
= sc
->ah
;
2446 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2447 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2448 sc
->curchan
->hw_value
);
2450 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2452 * Rfgain is out of bounds, reset the chip
2453 * to load new gain values.
2455 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2456 ath5k_reset_wake(sc
);
2458 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2459 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2460 ieee80211_frequency_to_channel(
2461 sc
->curchan
->center_freq
));
2463 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2464 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2474 ath5k_led_enable(struct ath5k_softc
*sc
)
2476 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2477 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2483 ath5k_led_on(struct ath5k_softc
*sc
)
2485 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2487 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2491 ath5k_led_off(struct ath5k_softc
*sc
)
2493 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2495 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2499 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2500 enum led_brightness brightness
)
2502 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2505 if (brightness
== LED_OFF
)
2506 ath5k_led_off(led
->sc
);
2508 ath5k_led_on(led
->sc
);
2512 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2513 const char *name
, char *trigger
)
2518 strncpy(led
->name
, name
, sizeof(led
->name
));
2519 led
->led_dev
.name
= led
->name
;
2520 led
->led_dev
.default_trigger
= trigger
;
2521 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2523 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2526 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2533 ath5k_unregister_led(struct ath5k_led
*led
)
2537 led_classdev_unregister(&led
->led_dev
);
2538 ath5k_led_off(led
->sc
);
2543 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2545 ath5k_unregister_led(&sc
->rx_led
);
2546 ath5k_unregister_led(&sc
->tx_led
);
2551 ath5k_init_leds(struct ath5k_softc
*sc
)
2554 struct ieee80211_hw
*hw
= sc
->hw
;
2555 struct pci_dev
*pdev
= sc
->pdev
;
2556 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2559 * Auto-enable soft led processing for IBM cards and for
2560 * 5211 minipci cards.
2562 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2563 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2564 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2566 sc
->led_on
= 0; /* active low */
2568 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2569 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2570 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2572 sc
->led_on
= 1; /* active high */
2574 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2577 ath5k_led_enable(sc
);
2579 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2580 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2581 ieee80211_get_rx_led_name(hw
));
2585 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2586 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2587 ieee80211_get_tx_led_name(hw
));
2593 /********************\
2594 * Mac80211 functions *
2595 \********************/
2598 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2600 struct ath5k_softc
*sc
= hw
->priv
;
2601 struct ath5k_buf
*bf
;
2602 unsigned long flags
;
2606 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2608 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2609 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2612 * the hardware expects the header padded to 4 byte boundaries
2613 * if this is not the case we add the padding after the header
2615 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2618 if (skb_headroom(skb
) < pad
) {
2619 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2620 " headroom to pad %d\n", hdrlen
, pad
);
2624 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2627 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2628 if (list_empty(&sc
->txbuf
)) {
2629 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2630 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2631 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2634 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2635 list_del(&bf
->list
);
2637 if (list_empty(&sc
->txbuf
))
2638 ieee80211_stop_queues(hw
);
2639 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2643 if (ath5k_txbuf_setup(sc
, bf
)) {
2645 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2646 list_add_tail(&bf
->list
, &sc
->txbuf
);
2648 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2649 dev_kfree_skb_any(skb
);
2657 ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
)
2659 struct ath5k_hw
*ah
= sc
->ah
;
2662 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2665 ath5k_hw_set_imr(ah
, 0);
2666 ath5k_txq_cleanup(sc
);
2669 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2671 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2676 * This is needed only to setup initial state
2677 * but it's best done after a reset.
2679 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2681 ret
= ath5k_rx_start(sc
);
2683 ATH5K_ERR(sc
, "can't start recv logic\n");
2688 * Change channels and update the h/w rate map if we're switching;
2689 * e.g. 11a to 11b/g.
2691 * We may be doing a reset in response to an ioctl that changes the
2692 * channel so update any state that might change as a result.
2696 /* ath5k_chan_change(sc, c); */
2698 ath5k_beacon_config(sc
);
2699 /* intrs are enabled by ath5k_beacon_config */
2707 ath5k_reset_wake(struct ath5k_softc
*sc
)
2711 ret
= ath5k_reset(sc
, true, true);
2713 ieee80211_wake_queues(sc
->hw
);
2718 static int ath5k_start(struct ieee80211_hw
*hw
)
2720 return ath5k_init(hw
->priv
, false);
2723 static void ath5k_stop(struct ieee80211_hw
*hw
)
2725 ath5k_stop_hw(hw
->priv
, false);
2728 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2729 struct ieee80211_if_init_conf
*conf
)
2731 struct ath5k_softc
*sc
= hw
->priv
;
2734 mutex_lock(&sc
->lock
);
2740 sc
->vif
= conf
->vif
;
2742 switch (conf
->type
) {
2743 case NL80211_IFTYPE_STATION
:
2744 case NL80211_IFTYPE_ADHOC
:
2745 case NL80211_IFTYPE_MONITOR
:
2746 sc
->opmode
= conf
->type
;
2753 /* Set to a reasonable value. Note that this will
2754 * be set to mac80211's value at ath5k_config(). */
2759 mutex_unlock(&sc
->lock
);
2764 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2765 struct ieee80211_if_init_conf
*conf
)
2767 struct ath5k_softc
*sc
= hw
->priv
;
2769 mutex_lock(&sc
->lock
);
2770 if (sc
->vif
!= conf
->vif
)
2775 mutex_unlock(&sc
->lock
);
2779 * TODO: Phy disable/diversity etc
2782 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2784 struct ath5k_softc
*sc
= hw
->priv
;
2785 struct ieee80211_conf
*conf
= &hw
->conf
;
2787 sc
->bintval
= conf
->beacon_int
;
2788 sc
->power_level
= conf
->power_level
;
2790 return ath5k_chan_set(sc
, conf
->channel
);
2794 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2795 struct ieee80211_if_conf
*conf
)
2797 struct ath5k_softc
*sc
= hw
->priv
;
2798 struct ath5k_hw
*ah
= sc
->ah
;
2801 mutex_lock(&sc
->lock
);
2802 if (sc
->vif
!= vif
) {
2807 /* Cache for later use during resets */
2808 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2809 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2810 * a clean way of letting us retrieve this yet. */
2811 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2815 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2816 vif
->type
== NL80211_IFTYPE_ADHOC
) {
2817 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2822 /* call old handler for now */
2823 ath5k_beacon_update(hw
, beacon
);
2826 mutex_unlock(&sc
->lock
);
2828 return ath5k_reset_wake(sc
);
2830 mutex_unlock(&sc
->lock
);
2834 #define SUPPORTED_FIF_FLAGS \
2835 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2836 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC
2839 * o always accept unicast, broadcast, and multicast traffic
2840 * o multicast traffic for all BSSIDs will be enabled if mac80211
2842 * o maintain current state of phy ofdm or phy cck error reception.
2843 * If the hardware detects any of these type of errors then
2844 * ath5k_hw_get_rx_filter() will pass to us the respective
2845 * hardware filters to be able to receive these type of frames.
2846 * o probe request frames are accepted only when operating in
2847 * hostap, adhoc, or monitor modes
2848 * o enable promiscuous mode according to the interface state
2850 * - when operating in adhoc mode so the 802.11 layer creates
2851 * node table entries for peers,
2852 * - when operating in station mode for collecting rssi data when
2853 * the station is otherwise quiet, or
2856 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2857 unsigned int changed_flags
,
2858 unsigned int *new_flags
,
2859 int mc_count
, struct dev_mc_list
*mclist
)
2861 struct ath5k_softc
*sc
= hw
->priv
;
2862 struct ath5k_hw
*ah
= sc
->ah
;
2863 u32 mfilt
[2], val
, rfilt
;
2870 /* Only deal with supported flags */
2871 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2872 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2874 /* If HW detects any phy or radar errors, leave those filters on.
2875 * Also, always enable Unicast, Broadcasts and Multicast
2876 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2877 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2878 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2879 AR5K_RX_FILTER_MCAST
);
2881 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2882 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2883 rfilt
|= AR5K_RX_FILTER_PROM
;
2884 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2887 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2890 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2891 if (*new_flags
& FIF_ALLMULTI
) {
2895 for (i
= 0; i
< mc_count
; i
++) {
2898 /* calculate XOR of eight 6-bit values */
2899 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2900 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2901 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2902 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2904 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2905 /* XXX: we might be able to just do this instead,
2906 * but not sure, needs testing, if we do use this we'd
2907 * neet to inform below to not reset the mcast */
2908 /* ath5k_hw_set_mcast_filterindex(ah,
2909 * mclist->dmi_addr[5]); */
2910 mclist
= mclist
->next
;
2914 /* This is the best we can do */
2915 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2916 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2918 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2919 * and probes for any BSSID, this needs testing */
2920 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2921 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2923 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2924 * set we should only pass on control frames for this
2925 * station. This needs testing. I believe right now this
2926 * enables *all* control frames, which is OK.. but
2927 * but we should see if we can improve on granularity */
2928 if (*new_flags
& FIF_CONTROL
)
2929 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2931 /* Additional settings per mode -- this is per ath5k */
2933 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2935 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2936 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2937 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2938 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2939 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2940 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2941 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2942 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2943 rfilt
|= AR5K_RX_FILTER_PROM
;
2944 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
2945 rfilt
|= AR5K_RX_FILTER_BEACON
;
2948 ath5k_hw_set_rx_filter(ah
,rfilt
);
2950 /* Set multicast bits */
2951 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2952 /* Set the cached hw filter flags, this will alter actually
2954 sc
->filter_flags
= rfilt
;
2958 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2959 const u8
*local_addr
, const u8
*addr
,
2960 struct ieee80211_key_conf
*key
)
2962 struct ath5k_softc
*sc
= hw
->priv
;
2967 /* XXX: fix hardware encryption, its not working. For now
2968 * allow software encryption */
2978 mutex_lock(&sc
->lock
);
2982 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2984 ATH5K_ERR(sc
, "can't set the key\n");
2987 __set_bit(key
->keyidx
, sc
->keymap
);
2988 key
->hw_key_idx
= key
->keyidx
;
2991 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2992 __clear_bit(key
->keyidx
, sc
->keymap
);
3001 mutex_unlock(&sc
->lock
);
3006 ath5k_get_stats(struct ieee80211_hw
*hw
,
3007 struct ieee80211_low_level_stats
*stats
)
3009 struct ath5k_softc
*sc
= hw
->priv
;
3010 struct ath5k_hw
*ah
= sc
->ah
;
3013 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3015 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3021 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3022 struct ieee80211_tx_queue_stats
*stats
)
3024 struct ath5k_softc
*sc
= hw
->priv
;
3026 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3032 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3034 struct ath5k_softc
*sc
= hw
->priv
;
3036 return ath5k_hw_get_tsf64(sc
->ah
);
3040 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3042 struct ath5k_softc
*sc
= hw
->priv
;
3045 * in IBSS mode we need to update the beacon timers too.
3046 * this will also reset the TSF if we call it with 0
3048 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3049 ath5k_beacon_update_timers(sc
, 0);
3051 ath5k_hw_reset_tsf(sc
->ah
);
3055 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3057 struct ath5k_softc
*sc
= hw
->priv
;
3058 unsigned long flags
;
3061 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3063 if (sc
->opmode
!= NL80211_IFTYPE_ADHOC
) {
3068 spin_lock_irqsave(&sc
->block
, flags
);
3069 ath5k_txbuf_free(sc
, sc
->bbuf
);
3070 sc
->bbuf
->skb
= skb
;
3071 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3073 sc
->bbuf
->skb
= NULL
;
3074 spin_unlock_irqrestore(&sc
->block
, flags
);
3076 ath5k_beacon_config(sc
);