drivers/net/wireless/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <net/mac80211.h>
  23 #include <linux/leds.h>
  24 #include <linux/rfkill.h>
  25
  26 #include "hw.h"
  27 #include "rc.h"
  28 #include "debug.h"
  29
  30 struct ath_node;
  31
  32 /* Macro to expand scalars to 64-bit objects */
  33
  34 #define ito64(x) (sizeof(x) == 8) ?                     \
  35         (((unsigned long long int)(x)) & (0xff)) :      \
  36         (sizeof(x) == 16) ?                             \
  37         (((unsigned long long int)(x)) & 0xffff) :      \
  38         ((sizeof(x) == 32) ?                            \
  39          (((unsigned long long int)(x)) & 0xffffffff) : \
  40          (unsigned long long int)(x))
  41
  42 /* increment with wrap-around */
  43 #define INCR(_l, _sz)   do {                    \
  44                 (_l)++;                         \
  45                 (_l) &= ((_sz) - 1);            \
  46         } while (0)
  47
  48 /* decrement with wrap-around */
  49 #define DECR(_l,  _sz)  do {                    \
  50                 (_l)--;                         \
  51                 (_l) &= ((_sz) - 1);            \
  52         } while (0)
  53
  54 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  55
  56 #define ASSERT(exp) do {                        \
  57                 if (unlikely(!(exp))) {         \
  58                         BUG();                  \
  59                 }                               \
  60         } while (0)
  61
  62 #define TSF_TO_TU(_h,_l) \
  63         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  64
  65 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  66
  67 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  68
  69 struct ath_config {
  70         u32 ath_aggr_prot;
  71         u16 txpowlimit;
  72         u8 cabqReadytime;
  73         u8 swBeaconProcess;
  74 };
  75
  76 /*************************/
  77 /* Descriptor Management */
  78 /*************************/
  79
  80 #define ATH_TXBUF_RESET(_bf) do {                               \
  81                 (_bf)->bf_status = 0;                           \
  82                 (_bf)->bf_lastbf = NULL;                        \
  83                 (_bf)->bf_next = NULL;                          \
  84                 memset(&((_bf)->bf_state), 0,                   \
  85                        sizeof(struct ath_buf_state));           \
  86         } while (0)
  87
  88 /**
  89  * enum buffer_type - Buffer type flags
  90  *
  91  * @BUF_HT: Send this buffer using HT capabilities
  92  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  93  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  94  *      (used in aggregation scheduling)
  95  * @BUF_RETRY: Indicates whether the buffer is retried
  96  * @BUF_XRETRY: To denote excessive retries of the buffer
  97  */
  98 enum buffer_type {
  99         BUF_HT                  = BIT(1),
 100         BUF_AMPDU               = BIT(2),
 101         BUF_AGGR                = BIT(3),
 102         BUF_RETRY               = BIT(4),
 103         BUF_XRETRY              = BIT(5),
 104 };
 105
 106 struct ath_buf_state {
 107         int bfs_nframes;
 108         u16 bfs_al;
 109         u16 bfs_frmlen;
 110         int bfs_seqno;
 111         int bfs_tidno;
 112         int bfs_retries;
 113         u32 bf_type;
 114         u32 bfs_keyix;
 115         enum ath9k_key_type bfs_keytype;
 116 };
 117
 118 #define bf_nframes              bf_state.bfs_nframes
 119 #define bf_al                   bf_state.bfs_al
 120 #define bf_frmlen               bf_state.bfs_frmlen
 121 #define bf_retries              bf_state.bfs_retries
 122 #define bf_seqno                bf_state.bfs_seqno
 123 #define bf_tidno                bf_state.bfs_tidno
 124 #define bf_keyix                bf_state.bfs_keyix
 125 #define bf_keytype              bf_state.bfs_keytype
 126 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 127 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 128 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 129 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 130 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 131
 132 struct ath_buf {
 133         struct list_head list;
 134         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 135                                            an aggregate) */
 136         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 137         void *bf_mpdu;                  /* enclosing frame structure */
 138         struct ath_desc *bf_desc;       /* virtual addr of desc */
 139         dma_addr_t bf_daddr;            /* physical addr of desc */
 140         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 141         u32 bf_status;
 142         u16 bf_flags;
 143         struct ath_buf_state bf_state;
 144         dma_addr_t bf_dmacontext;
 145 };
 146
 147 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 148 #define ATH_BUFSTATUS_STALE     0x00000002
 149
 150 struct ath_descdma {
 151         const char *dd_name;
 152         struct ath_desc *dd_desc;
 153         dma_addr_t dd_desc_paddr;
 154         u32 dd_desc_len;
 155         struct ath_buf *dd_bufptr;
 156         dma_addr_t dd_dmacontext;
 157 };
 158
 159 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 160                       struct list_head *head, const char *name,
 161                       int nbuf, int ndesc);
 162 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 163                          struct list_head *head);
 164
 165 /***********/
 166 /* RX / TX */
 167 /***********/
 168
 169 #define ATH_MAX_ANTENNA         3
 170 #define ATH_RXBUF               512
 171 #define WME_NUM_TID             16
 172 #define ATH_TXBUF               512
 173 #define ATH_TXMAXTRY            13
 174 #define ATH_11N_TXMAXTRY        10
 175 #define ATH_MGT_TXMAXTRY        4
 176 #define WME_BA_BMP_SIZE         64
 177 #define WME_MAX_BA              WME_BA_BMP_SIZE
 178 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 179
 180 #define TID_TO_WME_AC(_tid)                             \
 181         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 182          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 183          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 184          WME_AC_VO)
 185
 186 #define WME_AC_BE   0
 187 #define WME_AC_BK   1
 188 #define WME_AC_VI   2
 189 #define WME_AC_VO   3
 190 #define WME_NUM_AC  4
 191
 192 #define ADDBA_EXCHANGE_ATTEMPTS    10
 193 #define ATH_AGGR_DELIM_SZ          4
 194 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 195 /* number of delimiters for encryption padding */
 196 #define ATH_AGGR_ENCRYPTDELIM      10
 197 /* minimum h/w qdepth to be sustained to maximize aggregation */
 198 #define ATH_AGGR_MIN_QDEPTH        2
 199 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 200 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 201 #define ATH_AMPDU_LIMIT_DEFAULT    ATH_AMPDU_LIMIT_MAX
 202
 203 #define IEEE80211_SEQ_SEQ_SHIFT    4
 204 #define IEEE80211_SEQ_MAX          4096
 205 #define IEEE80211_MIN_AMPDU_BUF    0x8
 206 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 207 #define IEEE80211_WEP_IVLEN        3
 208 #define IEEE80211_WEP_KIDLEN       1
 209 #define IEEE80211_WEP_CRCLEN       4
 210 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 211                                     (IEEE80211_WEP_IVLEN +      \
 212                                      IEEE80211_WEP_KIDLEN +     \
 213                                      IEEE80211_WEP_CRCLEN))
 214
 215 /* return whether a bit at index _n in bitmap _bm is set
 216  * _sz is the size of the bitmap  */
 217 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 218                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 219
 220 /* return block-ack bitmap index given sequence and starting sequence */
 221 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 222
 223 /* returns delimiter padding required given the packet length */
 224 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 225         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 226           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 227
 228 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 229         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 230
 231 #define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
 232 #define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
 233 #define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 234 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 235
 236 enum ATH_AGGR_STATUS {
 237         ATH_AGGR_DONE,
 238         ATH_AGGR_BAW_CLOSED,
 239         ATH_AGGR_LIMITED,
 240 };
 241
 242 struct ath_txq {
 243         u32 axq_qnum;
 244         u32 *axq_link;
 245         struct list_head axq_q;
 246         spinlock_t axq_lock;
 247         u32 axq_depth;
 248         u8 axq_aggr_depth;
 249         u32 axq_totalqueued;
 250         bool stopped;
 251         struct ath_buf *axq_linkbuf;
 252
 253         /* first desc of the last descriptor that contains CTS */
 254         struct ath_desc *axq_lastdsWithCTS;
 255
 256         /* final desc of the gating desc that determines whether
 257            lastdsWithCTS has been DMA'ed or not */
 258         struct ath_desc *axq_gatingds;
 259
 260         struct list_head axq_acq;
 261 };
 262
 263 #define AGGR_CLEANUP         BIT(1)
 264 #define AGGR_ADDBA_COMPLETE  BIT(2)
 265 #define AGGR_ADDBA_PROGRESS  BIT(3)
 266
 267 struct ath_atx_tid {
 268         struct list_head list;
 269         struct list_head buf_q;
 270         struct ath_node *an;
 271         struct ath_atx_ac *ac;
 272         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
 273         u16 seq_start;
 274         u16 seq_next;
 275         u16 baw_size;
 276         int tidno;
 277         int baw_head;   /* first un-acked tx buffer */
 278         int baw_tail;   /* next unused tx buffer slot */
 279         int sched;
 280         int paused;
 281         u8 state;
 282         int addba_exchangeattempts;
 283 };
 284
 285 struct ath_atx_ac {
 286         int sched;
 287         int qnum;
 288         struct list_head list;
 289         struct list_head tid_q;
 290 };
 291
 292 struct ath_tx_control {
 293         struct ath_txq *txq;
 294         int if_id;
 295 };
 296
 297 struct ath_xmit_status {
 298         int retries;
 299         int flags;
 300 #define ATH_TX_ERROR        0x01
 301 #define ATH_TX_XRETRY       0x02
 302 #define ATH_TX_BAR          0x04
 303 };
 304
 305 /* All RSSI values are noise floor adjusted */
 306 struct ath_tx_stat {
 307         int rssi;
 308         int rssictl[ATH_MAX_ANTENNA];
 309         int rssiextn[ATH_MAX_ANTENNA];
 310         int rateieee;
 311         int rateKbps;
 312         int ratecode;
 313         int flags;
 314         u32 airtime;    /* time on air per final tx rate */
 315 };
 316
 317 struct aggr_rifs_param {
 318         int param_max_frames;
 319         int param_max_len;
 320         int param_rl;
 321         int param_al;
 322         struct ath_rc_series *param_rcs;
 323 };
 324
 325 struct ath_node {
 326         struct ath_softc *an_sc;
 327         struct ath_atx_tid tid[WME_NUM_TID];
 328         struct ath_atx_ac ac[WME_NUM_AC];
 329         u16 maxampdu;
 330         u8 mpdudensity;
 331 };
 332
 333 struct ath_tx {
 334         u16 seq_no;
 335         u32 txqsetup;
 336         int hwq_map[ATH9K_WME_AC_VO+1];
 337         spinlock_t txbuflock;
 338         struct list_head txbuf;
 339         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 340         struct ath_descdma txdma;
 341 };
 342
 343 struct ath_rx {
 344         u8 defant;
 345         u8 rxotherant;
 346         u32 *rxlink;
 347         int bufsize;
 348         unsigned int rxfilter;
 349         spinlock_t rxflushlock;
 350         spinlock_t rxbuflock;
 351         struct list_head rxbuf;
 352         struct ath_descdma rxdma;
 353 };
 354
 355 int ath_startrecv(struct ath_softc *sc);
 356 bool ath_stoprecv(struct ath_softc *sc);
 357 void ath_flushrecv(struct ath_softc *sc);
 358 u32 ath_calcrxfilter(struct ath_softc *sc);
 359 int ath_rx_init(struct ath_softc *sc, int nbufs);
 360 void ath_rx_cleanup(struct ath_softc *sc);
 361 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 362 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 363 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 364 int ath_tx_setup(struct ath_softc *sc, int haltype);
 365 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 366 void ath_draintxq(struct ath_softc *sc,
 367                      struct ath_txq *txq, bool retry_tx);
 368 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 369 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 370 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 371 int ath_tx_init(struct ath_softc *sc, int nbufs);
 372 int ath_tx_cleanup(struct ath_softc *sc);
 373 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 374 int ath_txq_update(struct ath_softc *sc, int qnum,
 375                    struct ath9k_tx_queue_info *q);
 376 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
 377                  struct ath_tx_control *txctl);
 378 void ath_tx_tasklet(struct ath_softc *sc);
 379 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
 380 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 381 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 382                       u16 tid, u16 *ssn);
 383 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 384 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 385
 386 /********/
 387 /* VIFs */
 388 /********/
 389
 390 /*
 391  * Define the scheme that we select MAC address for multiple
 392  * BSS on the same radio. The very first VIF will just use the MAC
 393  * address from the EEPROM. For the next 3 VIFs, we set the
 394  * U/L bit (bit 1) in MAC address, and use the next two bits as the
 395  * index of the VIF.
 396  */
 397
 398 #define ATH_SET_VIF_BSSID_MASK(bssid_mask) \
 399         ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
 400
 401 struct ath_vif {
 402         int av_bslot;
 403         enum nl80211_iftype av_opmode;
 404         struct ath_buf *av_bcbuf;
 405         struct ath_tx_control av_btxctl;
 406 };
 407
 408 /*******************/
 409 /* Beacon Handling */
 410 /*******************/
 411
 412 /*
 413  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 414  * number of BSSIDs) if a given beacon does not go out even after waiting this
 415  * number of beacon intervals, the game's up.
 416  */
 417 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 418 #define ATH_BCBUF                       1
 419 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 420 #define ATH_DEFAULT_BMISS_LIMIT         10
 421 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 422
 423 struct ath_beacon_config {
 424         u16 beacon_interval;
 425         u16 listen_interval;
 426         u16 dtim_period;
 427         u16 bmiss_timeout;
 428         u8 dtim_count;
 429         u8 tim_offset;
 430         union {
 431                 u64 last_tsf;
 432                 u8 last_tstamp[8];
 433         } u; /* last received beacon/probe response timestamp of this BSS. */
 434 };
 435
 436 struct ath_beacon {
 437         enum {
 438                 OK,             /* no change needed */
 439                 UPDATE,         /* update pending */
 440                 COMMIT          /* beacon sent, commit change */
 441         } updateslot;           /* slot time update fsm */
 442
 443         u32 beaconq;
 444         u32 bmisscnt;
 445         u32 ast_be_xmit;
 446         u64 bc_tstamp;
 447         int bslot[ATH_BCBUF];
 448         int slottime;
 449         int slotupdate;
 450         struct ath9k_tx_queue_info beacon_qi;
 451         struct ath_descdma bdma;
 452         struct ath_txq *cabq;
 453         struct list_head bbuf;
 454 };
 455
 456 void ath9k_beacon_tasklet(unsigned long data);
 457 void ath_beacon_config(struct ath_softc *sc, int if_id);
 458 int ath_beaconq_setup(struct ath_hw *ah);
 459 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
 460 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 461 void ath_beacon_sync(struct ath_softc *sc, int if_id);
 462
 463 /*******/
 464 /* ANI */
 465 /*******/
 466
 467 /* ANI values for STA only.
 468    FIXME: Add appropriate values for AP later */
 469
 470 #define ATH_ANI_POLLINTERVAL    100     /* 100 milliseconds between ANI poll */
 471 #define ATH_SHORT_CALINTERVAL   1000    /* 1 second between calibrations */
 472 #define ATH_LONG_CALINTERVAL    30000   /* 30 seconds between calibrations */
 473 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
 474
 475 struct ath_ani {
 476         bool caldone;
 477         int16_t noise_floor;
 478         unsigned int longcal_timer;
 479         unsigned int shortcal_timer;
 480         unsigned int resetcal_timer;
 481         unsigned int checkani_timer;
 482         struct timer_list timer;
 483 };
 484
 485 /********************/
 486 /*   LED Control    */
 487 /********************/
 488
 489 #define ATH_LED_PIN     1
 490 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 491 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 492
 493 enum ath_led_type {
 494         ATH_LED_RADIO,
 495         ATH_LED_ASSOC,
 496         ATH_LED_TX,
 497         ATH_LED_RX
 498 };
 499
 500 struct ath_led {
 501         struct ath_softc *sc;
 502         struct led_classdev led_cdev;
 503         enum ath_led_type led_type;
 504         char name[32];
 505         bool registered;
 506 };
 507
 508 /* Rfkill */
 509 #define ATH_RFKILL_POLL_INTERVAL        2000 /* msecs */
 510
 511 struct ath_rfkill {
 512         struct rfkill *rfkill;
 513         struct delayed_work rfkill_poll;
 514         char rfkill_name[32];
 515 };
 516
 517 /********************/
 518 /* Main driver core */
 519 /********************/
 520
 521 /*
 522  * Default cache line size, in bytes.
 523  * Used when PCI device not fully initialized by bootrom/BIOS
 524 */
 525 #define DEFAULT_CACHELINE       32
 526 #define ATH_DEFAULT_NOISE_FLOOR -95
 527 #define ATH_REGCLASSIDS_MAX     10
 528 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 529 #define ATH_MAX_SW_RETRIES      10
 530 #define ATH_CHAN_MAX            255
 531 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 532
 533 /*
 534  * The key cache is used for h/w cipher state and also for
 535  * tracking station state such as the current tx antenna.
 536  * We also setup a mapping table between key cache slot indices
 537  * and station state to short-circuit node lookups on rx.
 538  * Different parts have different size key caches.  We handle
 539  * up to ATH_KEYMAX entries (could dynamically allocate state).
 540  */
 541 #define ATH_KEYMAX              128     /* max key cache size we handle */
 542
 543 #define ATH_IF_ID_ANY           0xff
 544 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 545 #define ATH_RSSI_DUMMY_MARKER   0x127
 546 #define ATH_RATE_DUMMY_MARKER   0
 547
 548 #define SC_OP_INVALID           BIT(0)
 549 #define SC_OP_BEACONS           BIT(1)
 550 #define SC_OP_RXAGGR            BIT(2)
 551 #define SC_OP_TXAGGR            BIT(3)
 552 #define SC_OP_CHAINMASK_UPDATE  BIT(4)
 553 #define SC_OP_FULL_RESET        BIT(5)
 554 #define SC_OP_NO_RESET          BIT(6)
 555 #define SC_OP_PREAMBLE_SHORT    BIT(7)
 556 #define SC_OP_PROTECT_ENABLE    BIT(8)
 557 #define SC_OP_RXFLUSH           BIT(9)
 558 #define SC_OP_LED_ASSOCIATED    BIT(10)
 559 #define SC_OP_RFKILL_REGISTERED BIT(11)
 560 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
 561 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
 562 #define SC_OP_WAIT_FOR_BEACON   BIT(14)
 563 #define SC_OP_LED_ON            BIT(15)
 564
 565 struct ath_bus_ops {
 566         void            (*read_cachesize)(struct ath_softc *sc, int *csz);
 567         void            (*cleanup)(struct ath_softc *sc);
 568         bool            (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
 569 };
 570
 571 struct ath_softc {
 572         struct ieee80211_hw *hw;
 573         struct device *dev;
 574         struct tasklet_struct intr_tq;
 575         struct tasklet_struct bcon_tasklet;
 576         struct ath_hw *sc_ah;
 577         void __iomem *mem;
 578         int irq;
 579         spinlock_t sc_resetlock;
 580         struct mutex mutex;
 581
 582         u8 curbssid[ETH_ALEN];
 583         u8 bssidmask[ETH_ALEN];
 584         u32 intrstatus;
 585         u32 sc_flags; /* SC_OP_* */
 586         u16 curtxpow;
 587         u16 curaid;
 588         u16 cachelsz;
 589         u8 nbcnvifs;
 590         u16 nvifs;
 591         u8 tx_chainmask;
 592         u8 rx_chainmask;
 593         u32 keymax;
 594         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 595         u8 splitmic;
 596         atomic_t ps_usecount;
 597         enum ath9k_int imask;
 598         enum ath9k_ht_extprotspacing ht_extprotspacing;
 599         enum ath9k_ht_macmode tx_chan_width;
 600
 601         struct ath_config config;
 602         struct ath_rx rx;
 603         struct ath_tx tx;
 604         struct ath_beacon beacon;
 605         struct ieee80211_vif *vifs[ATH_BCBUF];
 606         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 607         struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
 608         struct ath_rate_table *cur_rate_table;
 609         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 610
 611         struct ath_led radio_led;
 612         struct ath_led assoc_led;
 613         struct ath_led tx_led;
 614         struct ath_led rx_led;
 615         struct delayed_work ath_led_blink_work;
 616         int led_on_duration;
 617         int led_off_duration;
 618         int led_on_cnt;
 619         int led_off_cnt;
 620
 621         struct ath_rfkill rf_kill;
 622         struct ath_ani ani;
 623         struct ath9k_node_stats nodestats;
 624 #ifdef CONFIG_ATH9K_DEBUG
 625         struct ath9k_debug debug;
 626 #endif
 627         struct ath_bus_ops *bus_ops;
 628 };
 629
 630 int ath_reset(struct ath_softc *sc, bool retry_tx);
 631 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 632 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 633 int ath_cabq_update(struct ath_softc *);
 634
 635 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
 636 {
 637         sc->bus_ops->read_cachesize(sc, csz);
 638 }
 639
 640 static inline void ath_bus_cleanup(struct ath_softc *sc)
 641 {
 642         sc->bus_ops->cleanup(sc);
 643 }
 644
 645 extern struct ieee80211_ops ath9k_ops;
 646
 647 irqreturn_t ath_isr(int irq, void *dev);
 648 void ath_cleanup(struct ath_softc *sc);
 649 int ath_attach(u16 devid, struct ath_softc *sc);
 650 void ath_detach(struct ath_softc *sc);
 651 const char *ath_mac_bb_name(u32 mac_bb_version);
 652 const char *ath_rf_name(u16 rf_version);
 653
 654 #ifdef CONFIG_PCI
 655 int ath_pci_init(void);
 656 void ath_pci_exit(void);
 657 #else
 658 static inline int ath_pci_init(void) { return 0; };
 659 static inline void ath_pci_exit(void) {};
 660 #endif
 661
 662 #ifdef CONFIG_ATHEROS_AR71XX
 663 int ath_ahb_init(void);
 664 void ath_ahb_exit(void);
 665 #else
 666 static inline int ath_ahb_init(void) { return 0; };
 667 static inline void ath_ahb_exit(void) {};
 668 #endif
 669
 670 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
 671 {
 672         if (atomic_inc_return(&sc->ps_usecount) == 1)
 673                 if (sc->sc_ah->ah_power_mode !=  ATH9K_PM_AWAKE) {
 674                         sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
 675                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 676                 }
 677 }
 678
 679 static inline void ath9k_ps_restore(struct ath_softc *sc)
 680 {
 681         if (atomic_dec_and_test(&sc->ps_usecount))
 682                 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
 683                         ath9k_hw_setpower(sc->sc_ah,
 684                                           sc->sc_ah->ah_restore_mode);
 685 }
 686 #endif /* ATH9K_H */