2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define AH_USE_EEPROM 0x1
23 #define AR5416_EEPROM_MAGIC 0x5aa5
25 #define AR5416_EEPROM_MAGIC 0xa55a
28 #define CTRY_DEBUG 0x1ff
29 #define CTRY_DEFAULT 0
31 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
32 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
33 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
34 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
35 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
36 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
37 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
38 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
39 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
41 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
42 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
43 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
44 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
46 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
51 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
52 #define AR5416_EEPROM_S 2
53 #define AR5416_EEPROM_OFFSET 0x2000
54 #define AR5416_EEPROM_MAX 0xae0
56 #define AR5416_EEPROM_START_ADDR \
57 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
59 #define SD_NO_CTL 0xE0
70 #define EXT_ADDITIVE (0x8000)
71 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
72 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
73 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
75 #define SUB_NUM_CTL_MODES_AT_5G_40 2
76 #define SUB_NUM_CTL_MODES_AT_2G_40 3
78 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
79 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
81 #define AR_EEPROM_MAC(i) (0x1d+(i))
82 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
83 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
84 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
86 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
87 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
88 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
89 #define AR_EEPROM_RFSILENT_POLARITY_S 1
91 #define EEP_RFSILENT_ENABLED 0x0001
92 #define EEP_RFSILENT_ENABLED_S 0
93 #define EEP_RFSILENT_POLARITY 0x0002
94 #define EEP_RFSILENT_POLARITY_S 1
95 #define EEP_RFSILENT_GPIO_SEL 0x001c
96 #define EEP_RFSILENT_GPIO_SEL_S 2
98 #define AR5416_OPFLAGS_11A 0x01
99 #define AR5416_OPFLAGS_11G 0x02
100 #define AR5416_OPFLAGS_N_5G_HT40 0x04
101 #define AR5416_OPFLAGS_N_2G_HT40 0x08
102 #define AR5416_OPFLAGS_N_5G_HT20 0x10
103 #define AR5416_OPFLAGS_N_2G_HT20 0x20
105 #define AR5416_EEP_NO_BACK_VER 0x1
106 #define AR5416_EEP_VER 0xE
107 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
108 #define AR5416_EEP_MINOR_VER_2 0x2
109 #define AR5416_EEP_MINOR_VER_3 0x3
110 #define AR5416_EEP_MINOR_VER_7 0x7
111 #define AR5416_EEP_MINOR_VER_9 0x9
112 #define AR5416_EEP_MINOR_VER_16 0x10
113 #define AR5416_EEP_MINOR_VER_17 0x11
114 #define AR5416_EEP_MINOR_VER_19 0x13
115 #define AR5416_EEP_MINOR_VER_20 0x14
117 #define AR5416_NUM_5G_CAL_PIERS 8
118 #define AR5416_NUM_2G_CAL_PIERS 4
119 #define AR5416_NUM_5G_20_TARGET_POWERS 8
120 #define AR5416_NUM_5G_40_TARGET_POWERS 8
121 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
122 #define AR5416_NUM_2G_20_TARGET_POWERS 4
123 #define AR5416_NUM_2G_40_TARGET_POWERS 4
124 #define AR5416_NUM_CTLS 24
125 #define AR5416_NUM_BAND_EDGES 8
126 #define AR5416_NUM_PD_GAINS 4
127 #define AR5416_PD_GAINS_IN_MASK 4
128 #define AR5416_PD_GAIN_ICEPTS 5
129 #define AR5416_EEPROM_MODAL_SPURS 5
130 #define AR5416_MAX_RATE_POWER 63
131 #define AR5416_NUM_PDADC_VALUES 128
132 #define AR5416_BCHAN_UNUSED 0xFF
133 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
134 #define AR5416_MAX_CHAINS 3
135 #define AR5416_PWR_TABLE_OFFSET -5
137 /* Rx gain type values */
138 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
139 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
140 #define AR5416_EEP_RXGAIN_ORIG 2
142 /* Tx gain type values */
143 #define AR5416_EEP_TXGAIN_ORIGINAL 0
144 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
146 #define AR5416_EEP4K_START_LOC 64
147 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
148 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
149 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
150 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
151 #define AR5416_EEP4K_NUM_CTLS 12
152 #define AR5416_EEP4K_NUM_BAND_EDGES 4
153 #define AR5416_EEP4K_NUM_PD_GAINS 2
154 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
155 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
156 #define AR5416_EEP4K_MAX_CHAINS 1
182 rate6mb
, rate9mb
, rate12mb
, rate18mb
,
183 rate24mb
, rate36mb
, rate48mb
, rate54mb
,
184 rate1l
, rate2l
, rate2s
, rate5_5l
,
185 rate5_5s
, rate11l
, rate11s
, rateXr
,
186 rateHt20_0
, rateHt20_1
, rateHt20_2
, rateHt20_3
,
187 rateHt20_4
, rateHt20_5
, rateHt20_6
, rateHt20_7
,
188 rateHt40_0
, rateHt40_1
, rateHt40_2
, rateHt40_3
,
189 rateHt40_4
, rateHt40_5
, rateHt40_6
, rateHt40_7
,
190 rateDupCck
, rateDupOfdm
, rateExtCck
, rateExtOfdm
,
194 enum ath9k_hal_freq_band
{
195 ATH9K_HAL_FREQ_BAND_5GHZ
= 0,
196 ATH9K_HAL_FREQ_BAND_2GHZ
= 1
199 struct base_eep_header
{
210 u16 blueToothOptions
;
226 struct base_eep_header_4k
{
237 u16 blueToothOptions
;
251 struct modal_eep_header
{
252 u32 antCtrlChain
[AR5416_MAX_CHAINS
];
254 u8 antennaGainCh
[AR5416_MAX_CHAINS
];
256 u8 txRxAttenCh
[AR5416_MAX_CHAINS
];
257 u8 rxTxMarginCh
[AR5416_MAX_CHAINS
];
260 u8 xlnaGainCh
[AR5416_MAX_CHAINS
];
265 u8 noiseFloorThreshCh
[AR5416_MAX_CHAINS
];
268 u8 iqCalICh
[AR5416_MAX_CHAINS
];
269 u8 iqCalQCh
[AR5416_MAX_CHAINS
];
274 u8 pwrDecreaseFor2Chain
;
275 u8 pwrDecreaseFor3Chain
;
276 u8 txFrameToDataStart
;
278 u8 ht40PowerIncForPdadc
;
279 u8 bswAtten
[AR5416_MAX_CHAINS
];
280 u8 bswMargin
[AR5416_MAX_CHAINS
];
282 u8 xatten2Db
[AR5416_MAX_CHAINS
];
283 u8 xatten2Margin
[AR5416_MAX_CHAINS
];
289 femBandSelectUsed
:1, xlnabufin
:1, xlnaisel
:2, xlnabufmode
:1;
291 u16 xpaBiasLvlFreq
[3];
294 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
297 struct modal_eep_4k_header
{
298 u32 antCtrlChain
[AR5416_EEP4K_MAX_CHAINS
];
300 u8 antennaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
302 u8 txRxAttenCh
[AR5416_EEP4K_MAX_CHAINS
];
303 u8 rxTxMarginCh
[AR5416_EEP4K_MAX_CHAINS
];
306 u8 xlnaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
311 u8 noiseFloorThreshCh
[AR5416_EEP4K_MAX_CHAINS
];
314 u8 iqCalICh
[AR5416_EEP4K_MAX_CHAINS
];
315 u8 iqCalQCh
[AR5416_EEP4K_MAX_CHAINS
];
320 u8 txFrameToDataStart
;
322 u8 ht40PowerIncForPdadc
;
323 u8 bswAtten
[AR5416_EEP4K_MAX_CHAINS
];
324 u8 bswMargin
[AR5416_EEP4K_MAX_CHAINS
];
326 u8 xatten2Db
[AR5416_EEP4K_MAX_CHAINS
];
327 u8 xatten2Margin
[AR5416_EEP4K_MAX_CHAINS
];
335 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
339 struct cal_data_per_freq
{
340 u8 pwrPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
341 u8 vpdPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
344 struct cal_data_per_freq_4k
{
345 u8 pwrPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
346 u8 vpdPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
349 struct cal_target_power_leg
{
354 struct cal_target_power_ht
{
360 #ifdef __BIG_ENDIAN_BITFIELD
361 struct cal_ctl_edges
{
366 struct cal_ctl_edges
{
372 struct cal_ctl_data
{
374 ctlEdges
[AR5416_MAX_CHAINS
][AR5416_NUM_BAND_EDGES
];
377 struct cal_ctl_data_4k
{
379 ctlEdges
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_BAND_EDGES
];
382 struct ar5416_eeprom_def
{
383 struct base_eep_header baseEepHeader
;
385 struct modal_eep_header modalHeader
[2];
386 u8 calFreqPier5G
[AR5416_NUM_5G_CAL_PIERS
];
387 u8 calFreqPier2G
[AR5416_NUM_2G_CAL_PIERS
];
388 struct cal_data_per_freq
389 calPierData5G
[AR5416_MAX_CHAINS
][AR5416_NUM_5G_CAL_PIERS
];
390 struct cal_data_per_freq
391 calPierData2G
[AR5416_MAX_CHAINS
][AR5416_NUM_2G_CAL_PIERS
];
392 struct cal_target_power_leg
393 calTargetPower5G
[AR5416_NUM_5G_20_TARGET_POWERS
];
394 struct cal_target_power_ht
395 calTargetPower5GHT20
[AR5416_NUM_5G_20_TARGET_POWERS
];
396 struct cal_target_power_ht
397 calTargetPower5GHT40
[AR5416_NUM_5G_40_TARGET_POWERS
];
398 struct cal_target_power_leg
399 calTargetPowerCck
[AR5416_NUM_2G_CCK_TARGET_POWERS
];
400 struct cal_target_power_leg
401 calTargetPower2G
[AR5416_NUM_2G_20_TARGET_POWERS
];
402 struct cal_target_power_ht
403 calTargetPower2GHT20
[AR5416_NUM_2G_20_TARGET_POWERS
];
404 struct cal_target_power_ht
405 calTargetPower2GHT40
[AR5416_NUM_2G_40_TARGET_POWERS
];
406 u8 ctlIndex
[AR5416_NUM_CTLS
];
407 struct cal_ctl_data ctlData
[AR5416_NUM_CTLS
];
411 struct ar5416_eeprom_4k
{
412 struct base_eep_header_4k baseEepHeader
;
414 struct modal_eep_4k_header modalHeader
;
415 u8 calFreqPier2G
[AR5416_EEP4K_NUM_2G_CAL_PIERS
];
416 struct cal_data_per_freq_4k
417 calPierData2G
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_2G_CAL_PIERS
];
418 struct cal_target_power_leg
419 calTargetPowerCck
[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
];
420 struct cal_target_power_leg
421 calTargetPower2G
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
422 struct cal_target_power_ht
423 calTargetPower2GHT20
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
424 struct cal_target_power_ht
425 calTargetPower2GHT40
[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
];
426 u8 ctlIndex
[AR5416_EEP4K_NUM_CTLS
];
427 struct cal_ctl_data_4k ctlData
[AR5416_EEP4K_NUM_CTLS
];
431 enum reg_ext_bitmap
{
432 REG_EXT_JAPAN_MIDBAND
= 1,
433 REG_EXT_FCC_DFS_HT40
= 2,
434 REG_EXT_JAPAN_NONDFS_HT40
= 3,
435 REG_EXT_JAPAN_DFS_HT40
= 4
438 struct ath9k_country_entry
{
448 EEP_MAP_DEFAULT
= 0x0,
454 int (*check_eeprom
)(struct ath_hw
*hw
);
455 u32 (*get_eeprom
)(struct ath_hw
*hw
, enum eeprom_param param
);
456 bool (*fill_eeprom
)(struct ath_hw
*hw
);
457 int (*get_eeprom_ver
)(struct ath_hw
*hw
);
458 int (*get_eeprom_rev
)(struct ath_hw
*hw
);
459 u8 (*get_num_ant_config
)(struct ath_hw
*hw
, enum ieee80211_band band
);
460 u16 (*get_eeprom_antenna_cfg
)(struct ath_hw
*hw
,
461 struct ath9k_channel
*chan
);
462 bool (*set_board_values
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
);
463 void (*set_addac
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
);
464 int (*set_txpower
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
,
465 u16 cfgCtl
, u8 twiceAntennaReduction
,
466 u8 twiceMaxRegulatoryPower
, u8 powerLimit
);
467 u16 (*get_spur_channel
)(struct ath_hw
*ah
, u16 i
, bool is2GHz
);
470 #define ar5416_get_ntxchains(_txchainmask) \
471 (((_txchainmask >> 2) & 1) + \
472 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
474 int ath9k_hw_eeprom_attach(struct ath_hw
*ah
);
476 #endif /* EEPROM_H */