drivers/net/wireless/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/pci.h>
  19 #include "ath9k.h"
  20
  21 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  22         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  23         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  24         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  25         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  26         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  27         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  28         { 0 }
  29 };
  30
  31 /* return bus cachesize in 4B word units */
  32 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
  33 {
  34         u8 u8tmp;
  35
  36         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
  37                              (u8 *)&u8tmp);
  38         *csz = (int)u8tmp;
  39
  40         /*
  41          * This check was put in to avoid "unplesant" consequences if
  42          * the bootrom has not fully initialized all PCI devices.
  43          * Sometimes the cache line size register is not set
  44          */
  45
  46         if (*csz == 0)
  47                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  48 }
  49
  50 static void ath_pci_cleanup(struct ath_softc *sc)
  51 {
  52         struct pci_dev *pdev = to_pci_dev(sc->dev);
  53
  54         pci_iounmap(pdev, sc->mem);
  55         pci_release_region(pdev, 0);
  56         pci_disable_device(pdev);
  57 }
  58
  59 static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
  60 {
  61         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  62
  63         if (!ath9k_hw_wait(ah,
  64                            AR_EEPROM_STATUS_DATA,
  65                            AR_EEPROM_STATUS_DATA_BUSY |
  66                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
  67                 return false;
  68         }
  69
  70         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  71                    AR_EEPROM_STATUS_DATA_VAL);
  72
  73         return true;
  74 }
  75
  76 static struct ath_bus_ops ath_pci_bus_ops = {
  77         .read_cachesize = ath_pci_read_cachesize,
  78         .cleanup = ath_pci_cleanup,
  79         .eeprom_read = ath_pci_eeprom_read,
  80 };
  81
  82 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  83 {
  84         void __iomem *mem;
  85         struct ath_softc *sc;
  86         struct ieee80211_hw *hw;
  87         u8 csz;
  88         u32 val;
  89         int ret = 0;
  90         struct ath_hw *ah;
  91
  92         if (pci_enable_device(pdev))
  93                 return -EIO;
  94
  95         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  96
  97         if (ret) {
  98                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
  99                 goto bad;
 100         }
 101
 102         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 103
 104         if (ret) {
 105                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 106                         "DMA enable failed\n");
 107                 goto bad;
 108         }
 109
 110         /*
 111          * Cache line size is used to size and align various
 112          * structures used to communicate with the hardware.
 113          */
 114         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 115         if (csz == 0) {
 116                 /*
 117                  * Linux 2.4.18 (at least) writes the cache line size
 118                  * register as a 16-bit wide register which is wrong.
 119                  * We must have this setup properly for rx buffer
 120                  * DMA to work so force a reasonable value here if it
 121                  * comes up zero.
 122                  */
 123                 csz = L1_CACHE_BYTES / sizeof(u32);
 124                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 125         }
 126         /*
 127          * The default setting of latency timer yields poor results,
 128          * set it to the value used by other systems. It may be worth
 129          * tweaking this setting more.
 130          */
 131         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 132
 133         pci_set_master(pdev);
 134
 135         /*
 136          * Disable the RETRY_TIMEOUT register (0x41) to keep
 137          * PCI Tx retries from interfering with C3 CPU state.
 138          */
 139         pci_read_config_dword(pdev, 0x40, &val);
 140         if ((val & 0x0000ff00) != 0)
 141                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 142
 143         ret = pci_request_region(pdev, 0, "ath9k");
 144         if (ret) {
 145                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 146                 ret = -ENODEV;
 147                 goto bad;
 148         }
 149
 150         mem = pci_iomap(pdev, 0, 0);
 151         if (!mem) {
 152                 printk(KERN_ERR "PCI memory map error\n") ;
 153                 ret = -EIO;
 154                 goto bad1;
 155         }
 156
 157         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 158         if (hw == NULL) {
 159                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
 160                 goto bad2;
 161         }
 162
 163         SET_IEEE80211_DEV(hw, &pdev->dev);
 164         pci_set_drvdata(pdev, hw);
 165
 166         sc = hw->priv;
 167         sc->hw = hw;
 168         sc->dev = &pdev->dev;
 169         sc->mem = mem;
 170         sc->bus_ops = &ath_pci_bus_ops;
 171
 172         if (ath_attach(id->device, sc) != 0) {
 173                 ret = -ENODEV;
 174                 goto bad3;
 175         }
 176
 177         /* setup interrupt service routine */
 178
 179         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
 180                 printk(KERN_ERR "%s: request_irq failed\n",
 181                         wiphy_name(hw->wiphy));
 182                 ret = -EIO;
 183                 goto bad4;
 184         }
 185
 186         sc->irq = pdev->irq;
 187
 188         ah = sc->sc_ah;
 189         printk(KERN_INFO
 190                "%s: Atheros AR%s MAC/BB Rev:%x "
 191                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
 192                wiphy_name(hw->wiphy),
 193                ath_mac_bb_name(ah->hw_version.macVersion),
 194                ah->hw_version.macRev,
 195                ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
 196                ah->hw_version.phyRev,
 197                (unsigned long)mem, pdev->irq);
 198
 199         return 0;
 200 bad4:
 201         ath_detach(sc);
 202 bad3:
 203         ieee80211_free_hw(hw);
 204 bad2:
 205         pci_iounmap(pdev, mem);
 206 bad1:
 207         pci_release_region(pdev, 0);
 208 bad:
 209         pci_disable_device(pdev);
 210         return ret;
 211 }
 212
 213 static void ath_pci_remove(struct pci_dev *pdev)
 214 {
 215         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 216         struct ath_softc *sc = hw->priv;
 217
 218         ath_cleanup(sc);
 219 }
 220
 221 #ifdef CONFIG_PM
 222
 223 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 224 {
 225         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 226         struct ath_softc *sc = hw->priv;
 227
 228         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 229
 230 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 231         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 232                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
 233 #endif
 234
 235         pci_save_state(pdev);
 236         pci_disable_device(pdev);
 237         pci_set_power_state(pdev, PCI_D3hot);
 238
 239         return 0;
 240 }
 241
 242 static int ath_pci_resume(struct pci_dev *pdev)
 243 {
 244         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 245         struct ath_softc *sc = hw->priv;
 246         u32 val;
 247         int err;
 248
 249         err = pci_enable_device(pdev);
 250         if (err)
 251                 return err;
 252         pci_restore_state(pdev);
 253         /*
 254          * Suspend/Resume resets the PCI configuration space, so we have to
 255          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 256          * PCI Tx retries from interfering with C3 CPU state
 257          */
 258         pci_read_config_dword(pdev, 0x40, &val);
 259         if ((val & 0x0000ff00) != 0)
 260                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 261
 262         /* Enable LED */
 263         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 264                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 265         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 266
 267 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 268         /*
 269          * check the h/w rfkill state on resume
 270          * and start the rfkill poll timer
 271          */
 272         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 273                 queue_delayed_work(sc->hw->workqueue,
 274                                    &sc->rf_kill.rfkill_poll, 0);
 275 #endif
 276
 277         return 0;
 278 }
 279
 280 #endif /* CONFIG_PM */
 281
 282 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 283
 284 static struct pci_driver ath_pci_driver = {
 285         .name       = "ath9k",
 286         .id_table   = ath_pci_id_table,
 287         .probe      = ath_pci_probe,
 288         .remove     = ath_pci_remove,
 289 #ifdef CONFIG_PM
 290         .suspend    = ath_pci_suspend,
 291         .resume     = ath_pci_resume,
 292 #endif /* CONFIG_PM */
 293 };
 294
 295 int __init ath_pci_init(void)
 296 {
 297         return pci_register_driver(&ath_pci_driver);
 298 }
 299
 300 void ath_pci_exit(void)
 301 {
 302         pci_unregister_driver(&ath_pci_driver);
 303 }