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iwlwifi: enable RF kill interrupt in start_hw
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-eeprom.h"
76 #include "iwl-agn-hw.h"
77
78 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
79
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
83
84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
85 {
86 struct iwl_trans_pcie *trans_pcie =
87 IWL_TRANS_GET_PCIE_TRANS(trans);
88 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
89 struct device *dev = trans->dev;
90
91 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
92
93 spin_lock_init(&rxq->lock);
94
95 if (WARN_ON(rxq->bd || rxq->rb_stts))
96 return -EINVAL;
97
98 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
99 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
100 &rxq->bd_dma, GFP_KERNEL);
101 if (!rxq->bd)
102 goto err_bd;
103
104 /*Allocate the driver's pointer to receive buffer status */
105 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
106 &rxq->rb_stts_dma, GFP_KERNEL);
107 if (!rxq->rb_stts)
108 goto err_rb_stts;
109
110 return 0;
111
112 err_rb_stts:
113 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
114 rxq->bd, rxq->bd_dma);
115 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
116 rxq->bd = NULL;
117 err_bd:
118 return -ENOMEM;
119 }
120
121 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
122 {
123 struct iwl_trans_pcie *trans_pcie =
124 IWL_TRANS_GET_PCIE_TRANS(trans);
125 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
126 int i;
127
128 /* Fill the rx_used queue with _all_ of the Rx buffers */
129 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
130 /* In the reset function, these buffers may have been allocated
131 * to an SKB, so we need to unmap and free potential storage */
132 if (rxq->pool[i].page != NULL) {
133 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
134 PAGE_SIZE << trans_pcie->rx_page_order,
135 DMA_FROM_DEVICE);
136 __free_pages(rxq->pool[i].page,
137 trans_pcie->rx_page_order);
138 rxq->pool[i].page = NULL;
139 }
140 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
141 }
142 }
143
144 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
145 struct iwl_rx_queue *rxq)
146 {
147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
148 u32 rb_size;
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
151
152 if (trans_pcie->rx_buf_size_8k)
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
154 else
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156
157 /* Stop Rx DMA */
158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
159
160 /* Reset driver's Rx queue write index */
161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
162
163 /* Tell device where to find RBD circular buffer in DRAM */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
165 (u32)(rxq->bd_dma >> 8));
166
167 /* Tell device where in DRAM to update its Rx status */
168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
169 rxq->rb_stts_dma >> 4);
170
171 /* Enable Rx DMA
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
176 * RB timeout 0x10
177 * 256 RBDs
178 */
179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
183 rb_size|
184 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
185 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
186
187 /* Set interrupt coalescing timer to default (2048 usecs) */
188 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
189 }
190
191 static int iwl_rx_init(struct iwl_trans *trans)
192 {
193 struct iwl_trans_pcie *trans_pcie =
194 IWL_TRANS_GET_PCIE_TRANS(trans);
195 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
196
197 int i, err;
198 unsigned long flags;
199
200 if (!rxq->bd) {
201 err = iwl_trans_rx_alloc(trans);
202 if (err)
203 return err;
204 }
205
206 spin_lock_irqsave(&rxq->lock, flags);
207 INIT_LIST_HEAD(&rxq->rx_free);
208 INIT_LIST_HEAD(&rxq->rx_used);
209
210 iwl_trans_rxq_free_rx_bufs(trans);
211
212 for (i = 0; i < RX_QUEUE_SIZE; i++)
213 rxq->queue[i] = NULL;
214
215 /* Set us so that we have processed and used all buffers, but have
216 * not restocked the Rx queue with fresh buffers */
217 rxq->read = rxq->write = 0;
218 rxq->write_actual = 0;
219 rxq->free_count = 0;
220 spin_unlock_irqrestore(&rxq->lock, flags);
221
222 iwlagn_rx_replenish(trans);
223
224 iwl_trans_rx_hw_init(trans, rxq);
225
226 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
227 rxq->need_update = 1;
228 iwl_rx_queue_update_write_ptr(trans, rxq);
229 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
230
231 return 0;
232 }
233
234 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
235 {
236 struct iwl_trans_pcie *trans_pcie =
237 IWL_TRANS_GET_PCIE_TRANS(trans);
238 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
239
240 unsigned long flags;
241
242 /*if rxq->bd is NULL, it means that nothing has been allocated,
243 * exit now */
244 if (!rxq->bd) {
245 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
246 return;
247 }
248
249 spin_lock_irqsave(&rxq->lock, flags);
250 iwl_trans_rxq_free_rx_bufs(trans);
251 spin_unlock_irqrestore(&rxq->lock, flags);
252
253 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
254 rxq->bd, rxq->bd_dma);
255 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
256 rxq->bd = NULL;
257
258 if (rxq->rb_stts)
259 dma_free_coherent(trans->dev,
260 sizeof(struct iwl_rb_status),
261 rxq->rb_stts, rxq->rb_stts_dma);
262 else
263 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
264 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
265 rxq->rb_stts = NULL;
266 }
267
268 static int iwl_trans_rx_stop(struct iwl_trans *trans)
269 {
270
271 /* stop Rx DMA */
272 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
273 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
274 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
275 }
276
277 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
278 struct iwl_dma_ptr *ptr, size_t size)
279 {
280 if (WARN_ON(ptr->addr))
281 return -EINVAL;
282
283 ptr->addr = dma_alloc_coherent(trans->dev, size,
284 &ptr->dma, GFP_KERNEL);
285 if (!ptr->addr)
286 return -ENOMEM;
287 ptr->size = size;
288 return 0;
289 }
290
291 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
292 struct iwl_dma_ptr *ptr)
293 {
294 if (unlikely(!ptr->addr))
295 return;
296
297 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
298 memset(ptr, 0, sizeof(*ptr));
299 }
300
301 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
302 {
303 struct iwl_tx_queue *txq = (void *)data;
304 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
305 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
306
307 spin_lock(&txq->lock);
308 /* check if triggered erroneously */
309 if (txq->q.read_ptr == txq->q.write_ptr) {
310 spin_unlock(&txq->lock);
311 return;
312 }
313 spin_unlock(&txq->lock);
314
315
316 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
317 jiffies_to_msecs(trans_pcie->wd_timeout));
318 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
319 txq->q.read_ptr, txq->q.write_ptr);
320 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
321 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
322 & (TFD_QUEUE_SIZE_MAX - 1),
323 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
324
325 iwl_op_mode_nic_error(trans->op_mode);
326 }
327
328 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
329 struct iwl_tx_queue *txq, int slots_num,
330 u32 txq_id)
331 {
332 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
333 int i;
334 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
335
336 if (WARN_ON(txq->entries || txq->tfds))
337 return -EINVAL;
338
339 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
340 (unsigned long)txq);
341 txq->trans_pcie = trans_pcie;
342
343 txq->q.n_window = slots_num;
344
345 txq->entries = kcalloc(slots_num,
346 sizeof(struct iwl_pcie_tx_queue_entry),
347 GFP_KERNEL);
348
349 if (!txq->entries)
350 goto error;
351
352 if (txq_id == trans_pcie->cmd_queue)
353 for (i = 0; i < slots_num; i++) {
354 txq->entries[i].cmd =
355 kmalloc(sizeof(struct iwl_device_cmd),
356 GFP_KERNEL);
357 if (!txq->entries[i].cmd)
358 goto error;
359 }
360
361 /* Circular buffer of transmit frame descriptors (TFDs),
362 * shared with device */
363 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
364 &txq->q.dma_addr, GFP_KERNEL);
365 if (!txq->tfds) {
366 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
367 goto error;
368 }
369 txq->q.id = txq_id;
370
371 return 0;
372 error:
373 if (txq->entries && txq_id == trans_pcie->cmd_queue)
374 for (i = 0; i < slots_num; i++)
375 kfree(txq->entries[i].cmd);
376 kfree(txq->entries);
377 txq->entries = NULL;
378
379 return -ENOMEM;
380
381 }
382
383 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
384 int slots_num, u32 txq_id)
385 {
386 int ret;
387
388 txq->need_update = 0;
389
390 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
391 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
392 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
393
394 /* Initialize queue's high/low-water marks, and head/tail indexes */
395 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
396 txq_id);
397 if (ret)
398 return ret;
399
400 spin_lock_init(&txq->lock);
401
402 /*
403 * Tell nic where to find circular buffer of Tx Frame Descriptors for
404 * given Tx queue, and enable the DMA channel used for that queue.
405 * Circular buffer (TFD queue in DRAM) physical base address */
406 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
407 txq->q.dma_addr >> 8);
408
409 return 0;
410 }
411
412 /**
413 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
414 */
415 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
416 {
417 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
418 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
419 struct iwl_queue *q = &txq->q;
420 enum dma_data_direction dma_dir;
421
422 if (!q->n_bd)
423 return;
424
425 /* In the command queue, all the TBs are mapped as BIDI
426 * so unmap them as such.
427 */
428 if (txq_id == trans_pcie->cmd_queue)
429 dma_dir = DMA_BIDIRECTIONAL;
430 else
431 dma_dir = DMA_TO_DEVICE;
432
433 spin_lock_bh(&txq->lock);
434 while (q->write_ptr != q->read_ptr) {
435 /* The read_ptr needs to bound by q->n_window */
436 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
437 dma_dir);
438 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
439 }
440 spin_unlock_bh(&txq->lock);
441 }
442
443 /**
444 * iwl_tx_queue_free - Deallocate DMA queue.
445 * @txq: Transmit queue to deallocate.
446 *
447 * Empty queue by removing and destroying all BD's.
448 * Free all buffers.
449 * 0-fill, but do not free "txq" descriptor structure.
450 */
451 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
452 {
453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
454 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
455 struct device *dev = trans->dev;
456 int i;
457 if (WARN_ON(!txq))
458 return;
459
460 iwl_tx_queue_unmap(trans, txq_id);
461
462 /* De-alloc array of command/tx buffers */
463
464 if (txq_id == trans_pcie->cmd_queue)
465 for (i = 0; i < txq->q.n_window; i++)
466 kfree(txq->entries[i].cmd);
467
468 /* De-alloc circular buffer of TFDs */
469 if (txq->q.n_bd) {
470 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
471 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
472 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
473 }
474
475 kfree(txq->entries);
476 txq->entries = NULL;
477
478 del_timer_sync(&txq->stuck_timer);
479
480 /* 0-fill queue descriptor structure */
481 memset(txq, 0, sizeof(*txq));
482 }
483
484 /**
485 * iwl_trans_tx_free - Free TXQ Context
486 *
487 * Destroy all TX DMA queues and structures
488 */
489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
490 {
491 int txq_id;
492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
493
494 /* Tx queues */
495 if (trans_pcie->txq) {
496 for (txq_id = 0;
497 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
498 iwl_tx_queue_free(trans, txq_id);
499 }
500
501 kfree(trans_pcie->txq);
502 trans_pcie->txq = NULL;
503
504 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
505
506 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
507 }
508
509 /**
510 * iwl_trans_tx_alloc - allocate TX context
511 * Allocate all Tx DMA structures and initialize them
512 *
513 * @param priv
514 * @return error code
515 */
516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
517 {
518 int ret;
519 int txq_id, slots_num;
520 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
521
522 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
523 sizeof(struct iwlagn_scd_bc_tbl);
524
525 /*It is not allowed to alloc twice, so warn when this happens.
526 * We cannot rely on the previous allocation, so free and fail */
527 if (WARN_ON(trans_pcie->txq)) {
528 ret = -EINVAL;
529 goto error;
530 }
531
532 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
533 scd_bc_tbls_size);
534 if (ret) {
535 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
536 goto error;
537 }
538
539 /* Alloc keep-warm buffer */
540 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
541 if (ret) {
542 IWL_ERR(trans, "Keep Warm allocation failed\n");
543 goto error;
544 }
545
546 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
547 sizeof(struct iwl_tx_queue), GFP_KERNEL);
548 if (!trans_pcie->txq) {
549 IWL_ERR(trans, "Not enough memory for txq\n");
550 ret = ENOMEM;
551 goto error;
552 }
553
554 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
555 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
556 txq_id++) {
557 slots_num = (txq_id == trans_pcie->cmd_queue) ?
558 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
559 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
560 slots_num, txq_id);
561 if (ret) {
562 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
563 goto error;
564 }
565 }
566
567 return 0;
568
569 error:
570 iwl_trans_pcie_tx_free(trans);
571
572 return ret;
573 }
574 static int iwl_tx_init(struct iwl_trans *trans)
575 {
576 int ret;
577 int txq_id, slots_num;
578 unsigned long flags;
579 bool alloc = false;
580 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
581
582 if (!trans_pcie->txq) {
583 ret = iwl_trans_tx_alloc(trans);
584 if (ret)
585 goto error;
586 alloc = true;
587 }
588
589 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
590
591 /* Turn off all Tx DMA fifos */
592 iwl_write_prph(trans, SCD_TXFACT, 0);
593
594 /* Tell NIC where to find the "keep warm" buffer */
595 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
596 trans_pcie->kw.dma >> 4);
597
598 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
599
600 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
601 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
602 txq_id++) {
603 slots_num = (txq_id == trans_pcie->cmd_queue) ?
604 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
605 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
606 slots_num, txq_id);
607 if (ret) {
608 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
609 goto error;
610 }
611 }
612
613 return 0;
614 error:
615 /*Upon error, free only if we allocated something */
616 if (alloc)
617 iwl_trans_pcie_tx_free(trans);
618 return ret;
619 }
620
621 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
622 {
623 /*
624 * (for documentation purposes)
625 * to set power to V_AUX, do:
626
627 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
628 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
629 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
630 ~APMG_PS_CTRL_MSK_PWR_SRC);
631 */
632
633 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
634 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
635 ~APMG_PS_CTRL_MSK_PWR_SRC);
636 }
637
638 /* PCI registers */
639 #define PCI_CFG_RETRY_TIMEOUT 0x041
640 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
641 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
642
643 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
644 {
645 int pos;
646 u16 pci_lnk_ctl;
647 struct iwl_trans_pcie *trans_pcie =
648 IWL_TRANS_GET_PCIE_TRANS(trans);
649
650 struct pci_dev *pci_dev = trans_pcie->pci_dev;
651
652 pos = pci_pcie_cap(pci_dev);
653 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
654 return pci_lnk_ctl;
655 }
656
657 static void iwl_apm_config(struct iwl_trans *trans)
658 {
659 /*
660 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
661 * Check if BIOS (or OS) enabled L1-ASPM on this device.
662 * If so (likely), disable L0S, so device moves directly L0->L1;
663 * costs negligible amount of power savings.
664 * If not (unlikely), enable L0S, so there is at least some
665 * power savings, even without L1.
666 */
667 u16 lctl = iwl_pciexp_link_ctrl(trans);
668
669 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
670 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
671 /* L1-ASPM enabled; disable(!) L0S */
672 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
673 dev_printk(KERN_INFO, trans->dev,
674 "L1 Enabled; Disabling L0S\n");
675 } else {
676 /* L1-ASPM disabled; enable(!) L0S */
677 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
678 dev_printk(KERN_INFO, trans->dev,
679 "L1 Disabled; Enabling L0S\n");
680 }
681 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
682 }
683
684 /*
685 * Start up NIC's basic functionality after it has been reset
686 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
687 * NOTE: This does not load uCode nor start the embedded processor
688 */
689 static int iwl_apm_init(struct iwl_trans *trans)
690 {
691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
692 int ret = 0;
693 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
694
695 /*
696 * Use "set_bit" below rather than "write", to preserve any hardware
697 * bits already set by default after reset.
698 */
699
700 /* Disable L0S exit timer (platform NMI Work/Around) */
701 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
702 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
703
704 /*
705 * Disable L0s without affecting L1;
706 * don't wait for ICH L0s (ICH bug W/A)
707 */
708 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
709 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
710
711 /* Set FH wait threshold to maximum (HW error during stress W/A) */
712 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
713
714 /*
715 * Enable HAP INTA (interrupt from management bus) to
716 * wake device's PCI Express link L1a -> L0s
717 */
718 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
719 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
720
721 iwl_apm_config(trans);
722
723 /* Configure analog phase-lock-loop before activating to D0A */
724 if (trans->cfg->base_params->pll_cfg_val)
725 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
726 trans->cfg->base_params->pll_cfg_val);
727
728 /*
729 * Set "initialization complete" bit to move adapter from
730 * D0U* --> D0A* (powered-up active) state.
731 */
732 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
733
734 /*
735 * Wait for clock stabilization; once stabilized, access to
736 * device-internal resources is supported, e.g. iwl_write_prph()
737 * and accesses to uCode SRAM.
738 */
739 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
740 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
741 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
742 if (ret < 0) {
743 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
744 goto out;
745 }
746
747 /*
748 * Enable DMA clock and wait for it to stabilize.
749 *
750 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
751 * do not disable clocks. This preserves any hardware bits already
752 * set by default in "CLK_CTRL_REG" after reset.
753 */
754 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
755 udelay(20);
756
757 /* Disable L1-Active */
758 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
759 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
760
761 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
762
763 out:
764 return ret;
765 }
766
767 static int iwl_apm_stop_master(struct iwl_trans *trans)
768 {
769 int ret = 0;
770
771 /* stop device's busmaster DMA activity */
772 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
773
774 ret = iwl_poll_bit(trans, CSR_RESET,
775 CSR_RESET_REG_FLAG_MASTER_DISABLED,
776 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
777 if (ret)
778 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
779
780 IWL_DEBUG_INFO(trans, "stop master\n");
781
782 return ret;
783 }
784
785 static void iwl_apm_stop(struct iwl_trans *trans)
786 {
787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
788 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
789
790 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
791
792 /* Stop device's DMA activity */
793 iwl_apm_stop_master(trans);
794
795 /* Reset the entire device */
796 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
797
798 udelay(10);
799
800 /*
801 * Clear "initialization complete" bit to move adapter from
802 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
803 */
804 iwl_clear_bit(trans, CSR_GP_CNTRL,
805 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
806 }
807
808 static int iwl_nic_init(struct iwl_trans *trans)
809 {
810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811 unsigned long flags;
812
813 /* nic_init */
814 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
815 iwl_apm_init(trans);
816
817 /* Set interrupt coalescing calibration timer to default (512 usecs) */
818 iwl_write8(trans, CSR_INT_COALESCING,
819 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
820
821 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
822
823 iwl_set_pwr_vmain(trans);
824
825 iwl_op_mode_nic_config(trans->op_mode);
826
827 #ifndef CONFIG_IWLWIFI_IDI
828 /* Allocate the RX queue, or reset if it is already allocated */
829 iwl_rx_init(trans);
830 #endif
831
832 /* Allocate or reset and init all Tx and Command queues */
833 if (iwl_tx_init(trans))
834 return -ENOMEM;
835
836 if (trans->cfg->base_params->shadow_reg_enable) {
837 /* enable shadow regs in HW */
838 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
839 0x800FFFFF);
840 }
841
842 return 0;
843 }
844
845 #define HW_READY_TIMEOUT (50)
846
847 /* Note: returns poll_bit return value, which is >= 0 if success */
848 static int iwl_set_hw_ready(struct iwl_trans *trans)
849 {
850 int ret;
851
852 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
853 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
854
855 /* See if we got it */
856 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
857 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
858 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
859 HW_READY_TIMEOUT);
860
861 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
862 return ret;
863 }
864
865 /* Note: returns standard 0/-ERROR code */
866 static int iwl_prepare_card_hw(struct iwl_trans *trans)
867 {
868 int ret;
869
870 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
871
872 ret = iwl_set_hw_ready(trans);
873 /* If the card is ready, exit 0 */
874 if (ret >= 0)
875 return 0;
876
877 /* If HW is not ready, prepare the conditions to check again */
878 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
879 CSR_HW_IF_CONFIG_REG_PREPARE);
880
881 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
882 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
883 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
884
885 if (ret < 0)
886 return ret;
887
888 /* HW should be ready by now, check again. */
889 ret = iwl_set_hw_ready(trans);
890 if (ret >= 0)
891 return 0;
892 return ret;
893 }
894
895 /*
896 * ucode
897 */
898 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
899 const struct fw_desc *section)
900 {
901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
902 dma_addr_t phy_addr = section->p_addr;
903 u32 byte_cnt = section->len;
904 u32 dst_addr = section->offset;
905 int ret;
906
907 trans_pcie->ucode_write_complete = false;
908
909 iwl_write_direct32(trans,
910 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
911 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
912
913 iwl_write_direct32(trans,
914 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
915
916 iwl_write_direct32(trans,
917 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
918 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
919
920 iwl_write_direct32(trans,
921 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
922 (iwl_get_dma_hi_addr(phy_addr)
923 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
924
925 iwl_write_direct32(trans,
926 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
927 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
928 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
929 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
930
931 iwl_write_direct32(trans,
932 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
933 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
934 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
935 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
936
937 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
938 section_num);
939 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
940 trans_pcie->ucode_write_complete, 5 * HZ);
941 if (!ret) {
942 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
943 section_num);
944 return -ETIMEDOUT;
945 }
946
947 return 0;
948 }
949
950 static int iwl_load_given_ucode(struct iwl_trans *trans,
951 const struct fw_img *image)
952 {
953 int ret = 0;
954 int i;
955
956 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
957 if (!image->sec[i].p_addr)
958 break;
959
960 ret = iwl_load_section(trans, i, &image->sec[i]);
961 if (ret)
962 return ret;
963 }
964
965 /* Remove all resets to allow NIC to operate */
966 iwl_write32(trans, CSR_RESET, 0);
967
968 return 0;
969 }
970
971 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
972 const struct fw_img *fw)
973 {
974 int ret;
975 bool hw_rfkill;
976
977 /* This may fail if AMT took ownership of the device */
978 if (iwl_prepare_card_hw(trans)) {
979 IWL_WARN(trans, "Exit HW not ready\n");
980 return -EIO;
981 }
982
983 iwl_enable_rfkill_int(trans);
984
985 /* If platform's RF_KILL switch is NOT set to KILL */
986 hw_rfkill = iwl_is_rfkill_set(trans);
987 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
988 if (hw_rfkill)
989 return -ERFKILL;
990
991 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
992
993 ret = iwl_nic_init(trans);
994 if (ret) {
995 IWL_ERR(trans, "Unable to init nic\n");
996 return ret;
997 }
998
999 /* make sure rfkill handshake bits are cleared */
1000 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1001 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1002 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1003
1004 /* clear (again), then enable host interrupts */
1005 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1006 iwl_enable_interrupts(trans);
1007
1008 /* really make sure rfkill handshake bits are cleared */
1009 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1010 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1011
1012 /* Load the given image to the HW */
1013 return iwl_load_given_ucode(trans, fw);
1014 }
1015
1016 /*
1017 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1018 * must be called under the irq lock and with MAC access
1019 */
1020 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1021 {
1022 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1023 IWL_TRANS_GET_PCIE_TRANS(trans);
1024
1025 lockdep_assert_held(&trans_pcie->irq_lock);
1026
1027 iwl_write_prph(trans, SCD_TXFACT, mask);
1028 }
1029
1030 static void iwl_tx_start(struct iwl_trans *trans)
1031 {
1032 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1033 u32 a;
1034 unsigned long flags;
1035 int i, chan;
1036 u32 reg_val;
1037
1038 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1039
1040 trans_pcie->scd_base_addr =
1041 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1042 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1043 /* reset conext data memory */
1044 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1045 a += 4)
1046 iwl_write_targ_mem(trans, a, 0);
1047 /* reset tx status memory */
1048 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1049 a += 4)
1050 iwl_write_targ_mem(trans, a, 0);
1051 for (; a < trans_pcie->scd_base_addr +
1052 SCD_TRANS_TBL_OFFSET_QUEUE(
1053 trans->cfg->base_params->num_of_queues);
1054 a += 4)
1055 iwl_write_targ_mem(trans, a, 0);
1056
1057 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1058 trans_pcie->scd_bc_tbls.dma >> 10);
1059
1060 /* Enable DMA channel */
1061 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1062 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1063 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1064 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1065
1066 /* Update FH chicken bits */
1067 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1068 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1069 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1070
1071 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1072 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1073 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1074
1075 /* initiate the queues */
1076 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1077 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1078 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1079 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1080 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1081 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1082 SCD_CONTEXT_QUEUE_OFFSET(i) +
1083 sizeof(u32),
1084 ((SCD_WIN_SIZE <<
1085 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1086 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1087 ((SCD_FRAME_LIMIT <<
1088 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1089 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1090 }
1091
1092 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1093 IWL_MASK(0, trans->cfg->base_params->num_of_queues));
1094
1095 /* Activate all Tx DMA/FIFO channels */
1096 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1097
1098 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1099
1100 /* make sure all queue are not stopped/used */
1101 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1102 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1103
1104 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1105 int fifo = trans_pcie->setup_q_to_fifo[i];
1106
1107 set_bit(i, trans_pcie->queue_used);
1108
1109 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1110 fifo, true);
1111 }
1112
1113 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1114
1115 /* Enable L1-Active */
1116 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1117 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1118 }
1119
1120 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1121 {
1122 iwl_reset_ict(trans);
1123 iwl_tx_start(trans);
1124 }
1125
1126 /**
1127 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1128 */
1129 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1130 {
1131 int ch, txq_id, ret;
1132 unsigned long flags;
1133 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1134
1135 /* Turn off all Tx DMA fifos */
1136 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1137
1138 iwl_trans_txq_set_sched(trans, 0);
1139
1140 /* Stop each Tx DMA channel, and wait for it to be idle */
1141 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1142 iwl_write_direct32(trans,
1143 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1144 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1145 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1146 1000);
1147 if (ret < 0)
1148 IWL_ERR(trans, "Failing on timeout while stopping"
1149 " DMA channel %d [0x%08x]", ch,
1150 iwl_read_direct32(trans,
1151 FH_TSSR_TX_STATUS_REG));
1152 }
1153 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1154
1155 if (!trans_pcie->txq) {
1156 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1157 return 0;
1158 }
1159
1160 /* Unmap DMA from host system and free skb's */
1161 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1162 txq_id++)
1163 iwl_tx_queue_unmap(trans, txq_id);
1164
1165 return 0;
1166 }
1167
1168 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1169 {
1170 unsigned long flags;
1171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1172
1173 /* tell the device to stop sending interrupts */
1174 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1175 iwl_disable_interrupts(trans);
1176 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1177
1178 /* device going down, Stop using ICT table */
1179 iwl_disable_ict(trans);
1180
1181 /*
1182 * If a HW restart happens during firmware loading,
1183 * then the firmware loading might call this function
1184 * and later it might be called again due to the
1185 * restart. So don't process again if the device is
1186 * already dead.
1187 */
1188 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1189 iwl_trans_tx_stop(trans);
1190 #ifndef CONFIG_IWLWIFI_IDI
1191 iwl_trans_rx_stop(trans);
1192 #endif
1193 /* Power-down device's busmaster DMA clocks */
1194 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1195 APMG_CLK_VAL_DMA_CLK_RQT);
1196 udelay(5);
1197 }
1198
1199 /* Make sure (redundant) we've released our request to stay awake */
1200 iwl_clear_bit(trans, CSR_GP_CNTRL,
1201 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1202
1203 /* Stop the device, and put it in low power state */
1204 iwl_apm_stop(trans);
1205
1206 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1207 * Clean again the interrupt here
1208 */
1209 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1210 iwl_disable_interrupts(trans);
1211 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1212
1213 /* wait to make sure we flush pending tasklet*/
1214 synchronize_irq(trans_pcie->irq);
1215 tasklet_kill(&trans_pcie->irq_tasklet);
1216
1217 cancel_work_sync(&trans_pcie->rx_replenish);
1218
1219 /* stop and reset the on-board processor */
1220 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1221
1222 /* clear all status bits */
1223 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1224 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1225 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1226 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1227 }
1228
1229 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1230 {
1231 /* let the ucode operate on its own */
1232 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1233 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1234
1235 iwl_disable_interrupts(trans);
1236 iwl_clear_bit(trans, CSR_GP_CNTRL,
1237 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1238 }
1239
1240 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1241 struct iwl_device_cmd *dev_cmd, int txq_id)
1242 {
1243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1244 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1245 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1246 struct iwl_cmd_meta *out_meta;
1247 struct iwl_tx_queue *txq;
1248 struct iwl_queue *q;
1249 dma_addr_t phys_addr = 0;
1250 dma_addr_t txcmd_phys;
1251 dma_addr_t scratch_phys;
1252 u16 len, firstlen, secondlen;
1253 u8 wait_write_ptr = 0;
1254 __le16 fc = hdr->frame_control;
1255 u8 hdr_len = ieee80211_hdrlen(fc);
1256 u16 __maybe_unused wifi_seq;
1257
1258 txq = &trans_pcie->txq[txq_id];
1259 q = &txq->q;
1260
1261 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1262 WARN_ON_ONCE(1);
1263 return -EINVAL;
1264 }
1265
1266 spin_lock(&txq->lock);
1267
1268 /* Set up driver data for this TFD */
1269 txq->entries[q->write_ptr].skb = skb;
1270 txq->entries[q->write_ptr].cmd = dev_cmd;
1271
1272 dev_cmd->hdr.cmd = REPLY_TX;
1273 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1274 INDEX_TO_SEQ(q->write_ptr)));
1275
1276 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1277 out_meta = &txq->entries[q->write_ptr].meta;
1278
1279 /*
1280 * Use the first empty entry in this queue's command buffer array
1281 * to contain the Tx command and MAC header concatenated together
1282 * (payload data will be in another buffer).
1283 * Size of this varies, due to varying MAC header length.
1284 * If end is not dword aligned, we'll have 2 extra bytes at the end
1285 * of the MAC header (device reads on dword boundaries).
1286 * We'll tell device about this padding later.
1287 */
1288 len = sizeof(struct iwl_tx_cmd) +
1289 sizeof(struct iwl_cmd_header) + hdr_len;
1290 firstlen = (len + 3) & ~3;
1291
1292 /* Tell NIC about any 2-byte padding after MAC header */
1293 if (firstlen != len)
1294 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1295
1296 /* Physical address of this Tx command's header (not MAC header!),
1297 * within command buffer array. */
1298 txcmd_phys = dma_map_single(trans->dev,
1299 &dev_cmd->hdr, firstlen,
1300 DMA_BIDIRECTIONAL);
1301 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1302 goto out_err;
1303 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1304 dma_unmap_len_set(out_meta, len, firstlen);
1305
1306 if (!ieee80211_has_morefrags(fc)) {
1307 txq->need_update = 1;
1308 } else {
1309 wait_write_ptr = 1;
1310 txq->need_update = 0;
1311 }
1312
1313 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1314 * if any (802.11 null frames have no payload). */
1315 secondlen = skb->len - hdr_len;
1316 if (secondlen > 0) {
1317 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1318 secondlen, DMA_TO_DEVICE);
1319 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1320 dma_unmap_single(trans->dev,
1321 dma_unmap_addr(out_meta, mapping),
1322 dma_unmap_len(out_meta, len),
1323 DMA_BIDIRECTIONAL);
1324 goto out_err;
1325 }
1326 }
1327
1328 /* Attach buffers to TFD */
1329 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1330 if (secondlen > 0)
1331 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1332 secondlen, 0);
1333
1334 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1335 offsetof(struct iwl_tx_cmd, scratch);
1336
1337 /* take back ownership of DMA buffer to enable update */
1338 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1339 DMA_BIDIRECTIONAL);
1340 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1341 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1342
1343 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1344 le16_to_cpu(dev_cmd->hdr.sequence));
1345 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1346
1347 /* Set up entry for this TFD in Tx byte-count array */
1348 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1349
1350 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1351 DMA_BIDIRECTIONAL);
1352
1353 trace_iwlwifi_dev_tx(trans->dev,
1354 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1355 sizeof(struct iwl_tfd),
1356 &dev_cmd->hdr, firstlen,
1357 skb->data + hdr_len, secondlen);
1358
1359 /* start timer if queue currently empty */
1360 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1361 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1362
1363 /* Tell device the write index *just past* this latest filled TFD */
1364 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1365 iwl_txq_update_write_ptr(trans, txq);
1366
1367 /*
1368 * At this point the frame is "transmitted" successfully
1369 * and we will get a TX status notification eventually,
1370 * regardless of the value of ret. "ret" only indicates
1371 * whether or not we should update the write pointer.
1372 */
1373 if (iwl_queue_space(q) < q->high_mark) {
1374 if (wait_write_ptr) {
1375 txq->need_update = 1;
1376 iwl_txq_update_write_ptr(trans, txq);
1377 } else {
1378 iwl_stop_queue(trans, txq);
1379 }
1380 }
1381 spin_unlock(&txq->lock);
1382 return 0;
1383 out_err:
1384 spin_unlock(&txq->lock);
1385 return -1;
1386 }
1387
1388 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1389 {
1390 struct iwl_trans_pcie *trans_pcie =
1391 IWL_TRANS_GET_PCIE_TRANS(trans);
1392 int err;
1393 bool hw_rfkill;
1394
1395 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1396
1397 if (!trans_pcie->irq_requested) {
1398 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1399 iwl_irq_tasklet, (unsigned long)trans);
1400
1401 iwl_alloc_isr_ict(trans);
1402
1403 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1404 DRV_NAME, trans);
1405 if (err) {
1406 IWL_ERR(trans, "Error allocating IRQ %d\n",
1407 trans_pcie->irq);
1408 goto error;
1409 }
1410
1411 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1412 trans_pcie->irq_requested = true;
1413 }
1414
1415 err = iwl_prepare_card_hw(trans);
1416 if (err) {
1417 IWL_ERR(trans, "Error while preparing HW: %d", err);
1418 goto err_free_irq;
1419 }
1420
1421 iwl_apm_init(trans);
1422
1423 /* From now on, the op_mode will be kept updated about RF kill state */
1424 iwl_enable_rfkill_int(trans);
1425
1426 hw_rfkill = iwl_is_rfkill_set(trans);
1427 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1428
1429 return err;
1430
1431 err_free_irq:
1432 free_irq(trans_pcie->irq, trans);
1433 error:
1434 iwl_free_isr_ict(trans);
1435 tasklet_kill(&trans_pcie->irq_tasklet);
1436 return err;
1437 }
1438
1439 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1440 {
1441 iwl_apm_stop(trans);
1442
1443 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1444
1445 /* Even if we stop the HW, we still want the RF kill interrupt */
1446 iwl_enable_rfkill_int(trans);
1447 }
1448
1449 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1450 struct sk_buff_head *skbs)
1451 {
1452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1453 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1454 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1455 int tfd_num = ssn & (txq->q.n_bd - 1);
1456 int freed = 0;
1457
1458 spin_lock(&txq->lock);
1459
1460 if (txq->q.read_ptr != tfd_num) {
1461 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1462 txq_id, txq->q.read_ptr, tfd_num, ssn);
1463 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1464 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1465 iwl_wake_queue(trans, txq);
1466 }
1467
1468 spin_unlock(&txq->lock);
1469 }
1470
1471 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1472 {
1473 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1474 }
1475
1476 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1477 {
1478 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1479 }
1480
1481 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1482 {
1483 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1484 }
1485
1486 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1487 const struct iwl_trans_config *trans_cfg)
1488 {
1489 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1490
1491 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1492 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1493 trans_pcie->n_no_reclaim_cmds = 0;
1494 else
1495 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1496 if (trans_pcie->n_no_reclaim_cmds)
1497 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1498 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1499
1500 trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1501
1502 if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1503 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1504
1505 /* at least the command queue must be mapped */
1506 WARN_ON(!trans_pcie->n_q_to_fifo);
1507
1508 memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1509 trans_pcie->n_q_to_fifo * sizeof(u8));
1510
1511 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1512 if (trans_pcie->rx_buf_size_8k)
1513 trans_pcie->rx_page_order = get_order(8 * 1024);
1514 else
1515 trans_pcie->rx_page_order = get_order(4 * 1024);
1516
1517 trans_pcie->wd_timeout =
1518 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1519
1520 trans_pcie->command_names = trans_cfg->command_names;
1521 }
1522
1523 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1524 {
1525 struct iwl_trans_pcie *trans_pcie =
1526 IWL_TRANS_GET_PCIE_TRANS(trans);
1527
1528 iwl_trans_pcie_tx_free(trans);
1529 #ifndef CONFIG_IWLWIFI_IDI
1530 iwl_trans_pcie_rx_free(trans);
1531 #endif
1532 if (trans_pcie->irq_requested == true) {
1533 free_irq(trans_pcie->irq, trans);
1534 iwl_free_isr_ict(trans);
1535 }
1536
1537 pci_disable_msi(trans_pcie->pci_dev);
1538 iounmap(trans_pcie->hw_base);
1539 pci_release_regions(trans_pcie->pci_dev);
1540 pci_disable_device(trans_pcie->pci_dev);
1541
1542 kfree(trans);
1543 }
1544
1545 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1546 {
1547 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1548
1549 if (state)
1550 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1551 else
1552 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1553 }
1554
1555 #ifdef CONFIG_PM_SLEEP
1556 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1557 {
1558 return 0;
1559 }
1560
1561 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1562 {
1563 bool hw_rfkill;
1564
1565 iwl_enable_rfkill_int(trans);
1566
1567 hw_rfkill = iwl_is_rfkill_set(trans);
1568 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1569
1570 if (!hw_rfkill)
1571 iwl_enable_interrupts(trans);
1572
1573 return 0;
1574 }
1575 #endif /* CONFIG_PM_SLEEP */
1576
1577 #define IWL_FLUSH_WAIT_MS 2000
1578
1579 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1580 {
1581 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1582 struct iwl_tx_queue *txq;
1583 struct iwl_queue *q;
1584 int cnt;
1585 unsigned long now = jiffies;
1586 int ret = 0;
1587
1588 /* waiting for all the tx frames complete might take a while */
1589 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1590 if (cnt == trans_pcie->cmd_queue)
1591 continue;
1592 txq = &trans_pcie->txq[cnt];
1593 q = &txq->q;
1594 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1595 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1596 msleep(1);
1597
1598 if (q->read_ptr != q->write_ptr) {
1599 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1600 ret = -ETIMEDOUT;
1601 break;
1602 }
1603 }
1604 return ret;
1605 }
1606
1607 static const char *get_fh_string(int cmd)
1608 {
1609 #define IWL_CMD(x) case x: return #x
1610 switch (cmd) {
1611 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1612 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1613 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1614 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1615 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1616 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1617 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1618 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1619 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1620 default:
1621 return "UNKNOWN";
1622 }
1623 #undef IWL_CMD
1624 }
1625
1626 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1627 {
1628 int i;
1629 #ifdef CONFIG_IWLWIFI_DEBUG
1630 int pos = 0;
1631 size_t bufsz = 0;
1632 #endif
1633 static const u32 fh_tbl[] = {
1634 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1635 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1636 FH_RSCSR_CHNL0_WPTR,
1637 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1638 FH_MEM_RSSR_SHARED_CTRL_REG,
1639 FH_MEM_RSSR_RX_STATUS_REG,
1640 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1641 FH_TSSR_TX_STATUS_REG,
1642 FH_TSSR_TX_ERROR_REG
1643 };
1644 #ifdef CONFIG_IWLWIFI_DEBUG
1645 if (display) {
1646 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1647 *buf = kmalloc(bufsz, GFP_KERNEL);
1648 if (!*buf)
1649 return -ENOMEM;
1650 pos += scnprintf(*buf + pos, bufsz - pos,
1651 "FH register values:\n");
1652 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1653 pos += scnprintf(*buf + pos, bufsz - pos,
1654 " %34s: 0X%08x\n",
1655 get_fh_string(fh_tbl[i]),
1656 iwl_read_direct32(trans, fh_tbl[i]));
1657 }
1658 return pos;
1659 }
1660 #endif
1661 IWL_ERR(trans, "FH register values:\n");
1662 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1663 IWL_ERR(trans, " %34s: 0X%08x\n",
1664 get_fh_string(fh_tbl[i]),
1665 iwl_read_direct32(trans, fh_tbl[i]));
1666 }
1667 return 0;
1668 }
1669
1670 static const char *get_csr_string(int cmd)
1671 {
1672 #define IWL_CMD(x) case x: return #x
1673 switch (cmd) {
1674 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1675 IWL_CMD(CSR_INT_COALESCING);
1676 IWL_CMD(CSR_INT);
1677 IWL_CMD(CSR_INT_MASK);
1678 IWL_CMD(CSR_FH_INT_STATUS);
1679 IWL_CMD(CSR_GPIO_IN);
1680 IWL_CMD(CSR_RESET);
1681 IWL_CMD(CSR_GP_CNTRL);
1682 IWL_CMD(CSR_HW_REV);
1683 IWL_CMD(CSR_EEPROM_REG);
1684 IWL_CMD(CSR_EEPROM_GP);
1685 IWL_CMD(CSR_OTP_GP_REG);
1686 IWL_CMD(CSR_GIO_REG);
1687 IWL_CMD(CSR_GP_UCODE_REG);
1688 IWL_CMD(CSR_GP_DRIVER_REG);
1689 IWL_CMD(CSR_UCODE_DRV_GP1);
1690 IWL_CMD(CSR_UCODE_DRV_GP2);
1691 IWL_CMD(CSR_LED_REG);
1692 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1693 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1694 IWL_CMD(CSR_ANA_PLL_CFG);
1695 IWL_CMD(CSR_HW_REV_WA_REG);
1696 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1697 default:
1698 return "UNKNOWN";
1699 }
1700 #undef IWL_CMD
1701 }
1702
1703 void iwl_dump_csr(struct iwl_trans *trans)
1704 {
1705 int i;
1706 static const u32 csr_tbl[] = {
1707 CSR_HW_IF_CONFIG_REG,
1708 CSR_INT_COALESCING,
1709 CSR_INT,
1710 CSR_INT_MASK,
1711 CSR_FH_INT_STATUS,
1712 CSR_GPIO_IN,
1713 CSR_RESET,
1714 CSR_GP_CNTRL,
1715 CSR_HW_REV,
1716 CSR_EEPROM_REG,
1717 CSR_EEPROM_GP,
1718 CSR_OTP_GP_REG,
1719 CSR_GIO_REG,
1720 CSR_GP_UCODE_REG,
1721 CSR_GP_DRIVER_REG,
1722 CSR_UCODE_DRV_GP1,
1723 CSR_UCODE_DRV_GP2,
1724 CSR_LED_REG,
1725 CSR_DRAM_INT_TBL_REG,
1726 CSR_GIO_CHICKEN_BITS,
1727 CSR_ANA_PLL_CFG,
1728 CSR_HW_REV_WA_REG,
1729 CSR_DBG_HPET_MEM_REG
1730 };
1731 IWL_ERR(trans, "CSR values:\n");
1732 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1733 "CSR_INT_PERIODIC_REG)\n");
1734 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1735 IWL_ERR(trans, " %25s: 0X%08x\n",
1736 get_csr_string(csr_tbl[i]),
1737 iwl_read32(trans, csr_tbl[i]));
1738 }
1739 }
1740
1741 #ifdef CONFIG_IWLWIFI_DEBUGFS
1742 /* create and remove of files */
1743 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1744 if (!debugfs_create_file(#name, mode, parent, trans, \
1745 &iwl_dbgfs_##name##_ops)) \
1746 return -ENOMEM; \
1747 } while (0)
1748
1749 /* file operation */
1750 #define DEBUGFS_READ_FUNC(name) \
1751 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1752 char __user *user_buf, \
1753 size_t count, loff_t *ppos);
1754
1755 #define DEBUGFS_WRITE_FUNC(name) \
1756 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1757 const char __user *user_buf, \
1758 size_t count, loff_t *ppos);
1759
1760
1761 #define DEBUGFS_READ_FILE_OPS(name) \
1762 DEBUGFS_READ_FUNC(name); \
1763 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1764 .read = iwl_dbgfs_##name##_read, \
1765 .open = simple_open, \
1766 .llseek = generic_file_llseek, \
1767 };
1768
1769 #define DEBUGFS_WRITE_FILE_OPS(name) \
1770 DEBUGFS_WRITE_FUNC(name); \
1771 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1772 .write = iwl_dbgfs_##name##_write, \
1773 .open = simple_open, \
1774 .llseek = generic_file_llseek, \
1775 };
1776
1777 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1778 DEBUGFS_READ_FUNC(name); \
1779 DEBUGFS_WRITE_FUNC(name); \
1780 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1781 .write = iwl_dbgfs_##name##_write, \
1782 .read = iwl_dbgfs_##name##_read, \
1783 .open = simple_open, \
1784 .llseek = generic_file_llseek, \
1785 };
1786
1787 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1788 char __user *user_buf,
1789 size_t count, loff_t *ppos)
1790 {
1791 struct iwl_trans *trans = file->private_data;
1792 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1793 struct iwl_tx_queue *txq;
1794 struct iwl_queue *q;
1795 char *buf;
1796 int pos = 0;
1797 int cnt;
1798 int ret;
1799 size_t bufsz;
1800
1801 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1802
1803 if (!trans_pcie->txq) {
1804 IWL_ERR(trans, "txq not ready\n");
1805 return -EAGAIN;
1806 }
1807 buf = kzalloc(bufsz, GFP_KERNEL);
1808 if (!buf)
1809 return -ENOMEM;
1810
1811 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1812 txq = &trans_pcie->txq[cnt];
1813 q = &txq->q;
1814 pos += scnprintf(buf + pos, bufsz - pos,
1815 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1816 cnt, q->read_ptr, q->write_ptr,
1817 !!test_bit(cnt, trans_pcie->queue_used),
1818 !!test_bit(cnt, trans_pcie->queue_stopped));
1819 }
1820 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1821 kfree(buf);
1822 return ret;
1823 }
1824
1825 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1826 char __user *user_buf,
1827 size_t count, loff_t *ppos) {
1828 struct iwl_trans *trans = file->private_data;
1829 struct iwl_trans_pcie *trans_pcie =
1830 IWL_TRANS_GET_PCIE_TRANS(trans);
1831 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1832 char buf[256];
1833 int pos = 0;
1834 const size_t bufsz = sizeof(buf);
1835
1836 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1837 rxq->read);
1838 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1839 rxq->write);
1840 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1841 rxq->free_count);
1842 if (rxq->rb_stts) {
1843 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1844 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1845 } else {
1846 pos += scnprintf(buf + pos, bufsz - pos,
1847 "closed_rb_num: Not Allocated\n");
1848 }
1849 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1850 }
1851
1852 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1853 char __user *user_buf,
1854 size_t count, loff_t *ppos) {
1855
1856 struct iwl_trans *trans = file->private_data;
1857 struct iwl_trans_pcie *trans_pcie =
1858 IWL_TRANS_GET_PCIE_TRANS(trans);
1859 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1860
1861 int pos = 0;
1862 char *buf;
1863 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1864 ssize_t ret;
1865
1866 buf = kzalloc(bufsz, GFP_KERNEL);
1867 if (!buf) {
1868 IWL_ERR(trans, "Can not allocate Buffer\n");
1869 return -ENOMEM;
1870 }
1871
1872 pos += scnprintf(buf + pos, bufsz - pos,
1873 "Interrupt Statistics Report:\n");
1874
1875 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1876 isr_stats->hw);
1877 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1878 isr_stats->sw);
1879 if (isr_stats->sw || isr_stats->hw) {
1880 pos += scnprintf(buf + pos, bufsz - pos,
1881 "\tLast Restarting Code: 0x%X\n",
1882 isr_stats->err_code);
1883 }
1884 #ifdef CONFIG_IWLWIFI_DEBUG
1885 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1886 isr_stats->sch);
1887 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1888 isr_stats->alive);
1889 #endif
1890 pos += scnprintf(buf + pos, bufsz - pos,
1891 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1892
1893 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1894 isr_stats->ctkill);
1895
1896 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1897 isr_stats->wakeup);
1898
1899 pos += scnprintf(buf + pos, bufsz - pos,
1900 "Rx command responses:\t\t %u\n", isr_stats->rx);
1901
1902 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1903 isr_stats->tx);
1904
1905 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1906 isr_stats->unhandled);
1907
1908 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1909 kfree(buf);
1910 return ret;
1911 }
1912
1913 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1914 const char __user *user_buf,
1915 size_t count, loff_t *ppos)
1916 {
1917 struct iwl_trans *trans = file->private_data;
1918 struct iwl_trans_pcie *trans_pcie =
1919 IWL_TRANS_GET_PCIE_TRANS(trans);
1920 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1921
1922 char buf[8];
1923 int buf_size;
1924 u32 reset_flag;
1925
1926 memset(buf, 0, sizeof(buf));
1927 buf_size = min(count, sizeof(buf) - 1);
1928 if (copy_from_user(buf, user_buf, buf_size))
1929 return -EFAULT;
1930 if (sscanf(buf, "%x", &reset_flag) != 1)
1931 return -EFAULT;
1932 if (reset_flag == 0)
1933 memset(isr_stats, 0, sizeof(*isr_stats));
1934
1935 return count;
1936 }
1937
1938 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1939 const char __user *user_buf,
1940 size_t count, loff_t *ppos)
1941 {
1942 struct iwl_trans *trans = file->private_data;
1943 char buf[8];
1944 int buf_size;
1945 int csr;
1946
1947 memset(buf, 0, sizeof(buf));
1948 buf_size = min(count, sizeof(buf) - 1);
1949 if (copy_from_user(buf, user_buf, buf_size))
1950 return -EFAULT;
1951 if (sscanf(buf, "%d", &csr) != 1)
1952 return -EFAULT;
1953
1954 iwl_dump_csr(trans);
1955
1956 return count;
1957 }
1958
1959 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1960 char __user *user_buf,
1961 size_t count, loff_t *ppos)
1962 {
1963 struct iwl_trans *trans = file->private_data;
1964 char *buf;
1965 int pos = 0;
1966 ssize_t ret = -EFAULT;
1967
1968 ret = pos = iwl_dump_fh(trans, &buf, true);
1969 if (buf) {
1970 ret = simple_read_from_buffer(user_buf,
1971 count, ppos, buf, pos);
1972 kfree(buf);
1973 }
1974
1975 return ret;
1976 }
1977
1978 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1979 const char __user *user_buf,
1980 size_t count, loff_t *ppos)
1981 {
1982 struct iwl_trans *trans = file->private_data;
1983
1984 if (!trans->op_mode)
1985 return -EAGAIN;
1986
1987 iwl_op_mode_nic_error(trans->op_mode);
1988
1989 return count;
1990 }
1991
1992 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1993 DEBUGFS_READ_FILE_OPS(fh_reg);
1994 DEBUGFS_READ_FILE_OPS(rx_queue);
1995 DEBUGFS_READ_FILE_OPS(tx_queue);
1996 DEBUGFS_WRITE_FILE_OPS(csr);
1997 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1998
1999 /*
2000 * Create the debugfs files and directories
2001 *
2002 */
2003 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2004 struct dentry *dir)
2005 {
2006 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2007 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2008 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2009 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2010 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2011 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2012 return 0;
2013 }
2014 #else
2015 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2016 struct dentry *dir)
2017 { return 0; }
2018
2019 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2020
2021 const struct iwl_trans_ops trans_ops_pcie = {
2022 .start_hw = iwl_trans_pcie_start_hw,
2023 .stop_hw = iwl_trans_pcie_stop_hw,
2024 .fw_alive = iwl_trans_pcie_fw_alive,
2025 .start_fw = iwl_trans_pcie_start_fw,
2026 .stop_device = iwl_trans_pcie_stop_device,
2027
2028 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2029
2030 .send_cmd = iwl_trans_pcie_send_cmd,
2031
2032 .tx = iwl_trans_pcie_tx,
2033 .reclaim = iwl_trans_pcie_reclaim,
2034
2035 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2036 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2037
2038 .free = iwl_trans_pcie_free,
2039
2040 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2041
2042 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2043
2044 #ifdef CONFIG_PM_SLEEP
2045 .suspend = iwl_trans_pcie_suspend,
2046 .resume = iwl_trans_pcie_resume,
2047 #endif
2048 .write8 = iwl_trans_pcie_write8,
2049 .write32 = iwl_trans_pcie_write32,
2050 .read32 = iwl_trans_pcie_read32,
2051 .configure = iwl_trans_pcie_configure,
2052 .set_pmi = iwl_trans_pcie_set_pmi,
2053 };
2054
2055 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2056 const struct pci_device_id *ent,
2057 const struct iwl_cfg *cfg)
2058 {
2059 struct iwl_trans_pcie *trans_pcie;
2060 struct iwl_trans *trans;
2061 u16 pci_cmd;
2062 int err;
2063
2064 trans = kzalloc(sizeof(struct iwl_trans) +
2065 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2066
2067 if (WARN_ON(!trans))
2068 return NULL;
2069
2070 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2071
2072 trans->ops = &trans_ops_pcie;
2073 trans->cfg = cfg;
2074 trans_pcie->trans = trans;
2075 spin_lock_init(&trans_pcie->irq_lock);
2076 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2077
2078 /* W/A - seems to solve weird behavior. We need to remove this if we
2079 * don't want to stay in L1 all the time. This wastes a lot of power */
2080 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2081 PCIE_LINK_STATE_CLKPM);
2082
2083 if (pci_enable_device(pdev)) {
2084 err = -ENODEV;
2085 goto out_no_pci;
2086 }
2087
2088 pci_set_master(pdev);
2089
2090 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2091 if (!err)
2092 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2093 if (err) {
2094 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2095 if (!err)
2096 err = pci_set_consistent_dma_mask(pdev,
2097 DMA_BIT_MASK(32));
2098 /* both attempts failed: */
2099 if (err) {
2100 dev_printk(KERN_ERR, &pdev->dev,
2101 "No suitable DMA available.\n");
2102 goto out_pci_disable_device;
2103 }
2104 }
2105
2106 err = pci_request_regions(pdev, DRV_NAME);
2107 if (err) {
2108 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2109 goto out_pci_disable_device;
2110 }
2111
2112 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2113 if (!trans_pcie->hw_base) {
2114 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2115 err = -ENODEV;
2116 goto out_pci_release_regions;
2117 }
2118
2119 dev_printk(KERN_INFO, &pdev->dev,
2120 "pci_resource_len = 0x%08llx\n",
2121 (unsigned long long) pci_resource_len(pdev, 0));
2122 dev_printk(KERN_INFO, &pdev->dev,
2123 "pci_resource_base = %p\n", trans_pcie->hw_base);
2124
2125 dev_printk(KERN_INFO, &pdev->dev,
2126 "HW Revision ID = 0x%X\n", pdev->revision);
2127
2128 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2129 * PCI Tx retries from interfering with C3 CPU state */
2130 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2131
2132 err = pci_enable_msi(pdev);
2133 if (err)
2134 dev_printk(KERN_ERR, &pdev->dev,
2135 "pci_enable_msi failed(0X%x)", err);
2136
2137 trans->dev = &pdev->dev;
2138 trans_pcie->irq = pdev->irq;
2139 trans_pcie->pci_dev = pdev;
2140 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2141 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2142 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2143 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2144
2145 /* TODO: Move this away, not needed if not MSI */
2146 /* enable rfkill interrupt: hw bug w/a */
2147 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2148 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2149 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2150 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2151 }
2152
2153 /* Initialize the wait queue for commands */
2154 init_waitqueue_head(&trans->wait_command_queue);
2155
2156 return trans;
2157
2158 out_pci_release_regions:
2159 pci_release_regions(pdev);
2160 out_pci_disable_device:
2161 pci_disable_device(pdev);
2162 out_no_pci:
2163 kfree(trans);
2164 return NULL;
2165 }
2166
Linux kernel - Deliverables
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