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rtl8xxxu: rtl8723au: Introduce a pointer to efuse
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
1 /*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42
43 #define DRIVER_NAME "rtl8xxxu"
44
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91 };
92
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122 };
123
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129 };
130
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154 };
155
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185 };
186
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283 };
284
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384 };
385
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482 };
483
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581 };
582
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665 };
666
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749 };
750
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820 };
821
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895 };
896
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964 };
965
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397 write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442 }
1443
1444 /*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1475 {
1476 struct device *dev = &priv->udev->dev;
1477 int mbox_nr, retry, retval = 0;
1478 int mbox_reg, mbox_ext_reg;
1479 u8 val8;
1480
1481 mutex_lock(&priv->h2c_mutex);
1482
1483 mbox_nr = priv->next_mbox;
1484 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1485 mbox_ext_reg = priv->fops->mbox_ext_reg +
1486 (mbox_nr * priv->fops->mbox_ext_width);
1487
1488 /*
1489 * MBOX ready?
1490 */
1491 retry = 100;
1492 do {
1493 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1494 if (!(val8 & BIT(mbox_nr)))
1495 break;
1496 } while (retry--);
1497
1498 if (!retry) {
1499 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1500 retval = -EBUSY;
1501 goto error;
1502 }
1503
1504 /*
1505 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1506 */
1507 if (h2c->cmd.cmd & H2C_EXT) {
1508 if (priv->fops->mbox_ext_width == 4) {
1509 rtl8xxxu_write32(priv, mbox_ext_reg,
1510 le32_to_cpu(h2c->raw_wide.ext));
1511 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1512 dev_info(dev, "H2C_EXT %08x\n",
1513 le32_to_cpu(h2c->raw_wide.ext));
1514 } else {
1515 rtl8xxxu_write16(priv, mbox_ext_reg,
1516 le16_to_cpu(h2c->raw.ext));
1517 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1518 dev_info(dev, "H2C_EXT %04x\n",
1519 le16_to_cpu(h2c->raw.ext));
1520 }
1521 }
1522 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1523 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1524 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1525
1526 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1527
1528 error:
1529 mutex_unlock(&priv->h2c_mutex);
1530 return retval;
1531 }
1532
1533 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1534 {
1535 u8 val8;
1536 u32 val32;
1537
1538 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1539 val8 |= BIT(0) | BIT(3);
1540 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1541
1542 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1543 val32 &= ~(BIT(4) | BIT(5));
1544 val32 |= BIT(3);
1545 if (priv->rf_paths == 2) {
1546 val32 &= ~(BIT(20) | BIT(21));
1547 val32 |= BIT(19);
1548 }
1549 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1550
1551 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1552 val32 &= ~OFDM_RF_PATH_TX_MASK;
1553 if (priv->tx_paths == 2)
1554 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1555 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1556 val32 |= OFDM_RF_PATH_TX_B;
1557 else
1558 val32 |= OFDM_RF_PATH_TX_A;
1559 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1560
1561 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1562 val32 &= ~FPGA_RF_MODE_JAPAN;
1563 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1564
1565 if (priv->rf_paths == 2)
1566 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1567 else
1568 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1569
1570 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1571 if (priv->rf_paths == 2)
1572 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1573
1574 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1575 }
1576
1577 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1578 {
1579 u8 sps0;
1580 u32 val32;
1581
1582 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1583
1584 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1585
1586 /* RF RX code for preamble power saving */
1587 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1588 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1589 if (priv->rf_paths == 2)
1590 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1591 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1592
1593 /* Disable TX for four paths */
1594 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1595 val32 &= ~OFDM_RF_PATH_TX_MASK;
1596 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1597
1598 /* Enable power saving */
1599 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1600 val32 |= FPGA_RF_MODE_JAPAN;
1601 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1602
1603 /* AFE control register to power down bits [30:22] */
1604 if (priv->rf_paths == 2)
1605 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1606 else
1607 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1608
1609 /* Power down RF module */
1610 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1611 if (priv->rf_paths == 2)
1612 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1613
1614 sps0 &= ~(BIT(0) | BIT(3));
1615 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1616 }
1617
1618
1619 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1620 {
1621 u8 val8;
1622
1623 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1624 val8 &= ~BIT(6);
1625 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1626
1627 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1628 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1629 val8 &= ~BIT(0);
1630 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1631 }
1632
1633
1634 /*
1635 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1636 * supports the 2.4GHz band, so channels 1 - 14:
1637 * group 0: channels 1 - 3
1638 * group 1: channels 4 - 9
1639 * group 2: channels 10 - 14
1640 *
1641 * Note: We index from 0 in the code
1642 */
1643 static int rtl8723a_channel_to_group(int channel)
1644 {
1645 int group;
1646
1647 if (channel < 4)
1648 group = 0;
1649 else if (channel < 10)
1650 group = 1;
1651 else
1652 group = 2;
1653
1654 return group;
1655 }
1656
1657 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1658 {
1659 struct rtl8xxxu_priv *priv = hw->priv;
1660 u32 val32, rsr;
1661 u8 val8, opmode;
1662 bool ht = true;
1663 int sec_ch_above, channel;
1664 int i;
1665
1666 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1667 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1668 channel = hw->conf.chandef.chan->hw_value;
1669
1670 switch (hw->conf.chandef.width) {
1671 case NL80211_CHAN_WIDTH_20_NOHT:
1672 ht = false;
1673 case NL80211_CHAN_WIDTH_20:
1674 opmode |= BW_OPMODE_20MHZ;
1675 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1676
1677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1678 val32 &= ~FPGA_RF_MODE;
1679 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1680
1681 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1682 val32 &= ~FPGA_RF_MODE;
1683 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1684
1685 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1686 val32 |= FPGA0_ANALOG2_20MHZ;
1687 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1688 break;
1689 case NL80211_CHAN_WIDTH_40:
1690 if (hw->conf.chandef.center_freq1 >
1691 hw->conf.chandef.chan->center_freq) {
1692 sec_ch_above = 1;
1693 channel += 2;
1694 } else {
1695 sec_ch_above = 0;
1696 channel -= 2;
1697 }
1698
1699 opmode &= ~BW_OPMODE_20MHZ;
1700 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1701 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1702 if (sec_ch_above)
1703 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1704 else
1705 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1706 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1707
1708 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1709 val32 |= FPGA_RF_MODE;
1710 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1711
1712 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1713 val32 |= FPGA_RF_MODE;
1714 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1715
1716 /*
1717 * Set Control channel to upper or lower. These settings
1718 * are required only for 40MHz
1719 */
1720 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1721 val32 &= ~CCK0_SIDEBAND;
1722 if (!sec_ch_above)
1723 val32 |= CCK0_SIDEBAND;
1724 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1725
1726 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1727 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1728 if (sec_ch_above)
1729 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1730 else
1731 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1732 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1733
1734 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1735 val32 &= ~FPGA0_ANALOG2_20MHZ;
1736 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1737
1738 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1739 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1740 if (sec_ch_above)
1741 val32 |= FPGA0_PS_UPPER_CHANNEL;
1742 else
1743 val32 |= FPGA0_PS_LOWER_CHANNEL;
1744 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1745 break;
1746
1747 default:
1748 break;
1749 }
1750
1751 for (i = RF_A; i < priv->rf_paths; i++) {
1752 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1753 val32 &= ~MODE_AG_CHANNEL_MASK;
1754 val32 |= channel;
1755 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1756 }
1757
1758 if (ht)
1759 val8 = 0x0e;
1760 else
1761 val8 = 0x0a;
1762
1763 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1764 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1765
1766 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1767 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1768
1769 for (i = RF_A; i < priv->rf_paths; i++) {
1770 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1771 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1772 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1773 else
1774 val32 |= MODE_AG_CHANNEL_20MHZ;
1775 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1776 }
1777 }
1778
1779 static void
1780 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1781 {
1782 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1783 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1784 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1785 u8 val8;
1786 int group, i;
1787
1788 group = rtl8723a_channel_to_group(channel);
1789
1790 cck[0] = priv->cck_tx_power_index_A[group];
1791 cck[1] = priv->cck_tx_power_index_B[group];
1792
1793 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1794 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1795
1796 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1797 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1798
1799 mcsbase[0] = ofdm[0];
1800 mcsbase[1] = ofdm[1];
1801 if (!ht40) {
1802 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1803 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1804 }
1805
1806 if (priv->tx_paths > 1) {
1807 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1808 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1809 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1810 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1811 }
1812
1813 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1814 dev_info(&priv->udev->dev,
1815 "%s: Setting TX power CCK A: %02x, "
1816 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1817 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1818
1819 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1820 if (cck[i] > RF6052_MAX_TX_PWR)
1821 cck[i] = RF6052_MAX_TX_PWR;
1822 if (ofdm[i] > RF6052_MAX_TX_PWR)
1823 ofdm[i] = RF6052_MAX_TX_PWR;
1824 }
1825
1826 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1827 val32 &= 0xffff00ff;
1828 val32 |= (cck[0] << 8);
1829 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1830
1831 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1832 val32 &= 0xff;
1833 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1834 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1835
1836 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1837 val32 &= 0xffffff00;
1838 val32 |= cck[1];
1839 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1840
1841 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1842 val32 &= 0xff;
1843 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1844 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1845
1846 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1847 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1848 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1849 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1850 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1851 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1852
1853 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1854 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1855
1856 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1857 mcsbase[0] << 16 | mcsbase[0] << 24;
1858 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1859 mcsbase[1] << 16 | mcsbase[1] << 24;
1860
1861 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1862 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1863
1864 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1865 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1866
1867 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1868 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1869
1870 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1871 for (i = 0; i < 3; i++) {
1872 if (i != 2)
1873 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1874 else
1875 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1876 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1877 }
1878 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1879 for (i = 0; i < 3; i++) {
1880 if (i != 2)
1881 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1882 else
1883 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1884 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1885 }
1886 }
1887
1888 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1889 enum nl80211_iftype linktype)
1890 {
1891 u8 val8;
1892
1893 val8 = rtl8xxxu_read8(priv, REG_MSR);
1894 val8 &= ~MSR_LINKTYPE_MASK;
1895
1896 switch (linktype) {
1897 case NL80211_IFTYPE_UNSPECIFIED:
1898 val8 |= MSR_LINKTYPE_NONE;
1899 break;
1900 case NL80211_IFTYPE_ADHOC:
1901 val8 |= MSR_LINKTYPE_ADHOC;
1902 break;
1903 case NL80211_IFTYPE_STATION:
1904 val8 |= MSR_LINKTYPE_STATION;
1905 break;
1906 case NL80211_IFTYPE_AP:
1907 val8 |= MSR_LINKTYPE_AP;
1908 break;
1909 default:
1910 goto out;
1911 }
1912
1913 rtl8xxxu_write8(priv, REG_MSR, val8);
1914 out:
1915 return;
1916 }
1917
1918 static void
1919 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1920 {
1921 u16 val16;
1922
1923 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1924 RETRY_LIMIT_SHORT_MASK) |
1925 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1926 RETRY_LIMIT_LONG_MASK);
1927
1928 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1929 }
1930
1931 static void
1932 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1933 {
1934 u16 val16;
1935
1936 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1937 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1938
1939 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1940 }
1941
1942 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1943 {
1944 struct device *dev = &priv->udev->dev;
1945 char *cut;
1946
1947 switch (priv->chip_cut) {
1948 case 0:
1949 cut = "A";
1950 break;
1951 case 1:
1952 cut = "B";
1953 break;
1954 case 2:
1955 cut = "C";
1956 break;
1957 case 3:
1958 cut = "D";
1959 break;
1960 case 4:
1961 cut = "E";
1962 break;
1963 default:
1964 cut = "unknown";
1965 }
1966
1967 dev_info(dev,
1968 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1969 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1970 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1971 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1972
1973 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1974 }
1975
1976 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1977 {
1978 struct device *dev = &priv->udev->dev;
1979 u32 val32, bonding;
1980 u16 val16;
1981
1982 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1983 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1984 SYS_CFG_CHIP_VERSION_SHIFT;
1985 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1986 dev_info(dev, "Unsupported test chip\n");
1987 return -ENOTSUPP;
1988 }
1989
1990 if (val32 & SYS_CFG_BT_FUNC) {
1991 if (priv->chip_cut >= 3) {
1992 sprintf(priv->chip_name, "8723BU");
1993 priv->rtlchip = 0x8723b;
1994 } else {
1995 sprintf(priv->chip_name, "8723AU");
1996 priv->usb_interrupts = 1;
1997 priv->rtlchip = 0x8723a;
1998 }
1999
2000 priv->rf_paths = 1;
2001 priv->rx_paths = 1;
2002 priv->tx_paths = 1;
2003
2004 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2005 if (val32 & MULTI_WIFI_FUNC_EN)
2006 priv->has_wifi = 1;
2007 if (val32 & MULTI_BT_FUNC_EN)
2008 priv->has_bluetooth = 1;
2009 if (val32 & MULTI_GPS_FUNC_EN)
2010 priv->has_gps = 1;
2011 priv->is_multi_func = 1;
2012 } else if (val32 & SYS_CFG_TYPE_ID) {
2013 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2014 bonding &= HPON_FSM_BONDING_MASK;
2015 if (priv->chip_cut >= 3) {
2016 if (bonding == HPON_FSM_BONDING_1T2R) {
2017 sprintf(priv->chip_name, "8191EU");
2018 priv->rf_paths = 2;
2019 priv->rx_paths = 2;
2020 priv->tx_paths = 1;
2021 priv->rtlchip = 0x8191e;
2022 } else {
2023 sprintf(priv->chip_name, "8192EU");
2024 priv->rf_paths = 2;
2025 priv->rx_paths = 2;
2026 priv->tx_paths = 2;
2027 priv->rtlchip = 0x8192e;
2028 }
2029 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2030 sprintf(priv->chip_name, "8191CU");
2031 priv->rf_paths = 2;
2032 priv->rx_paths = 2;
2033 priv->tx_paths = 1;
2034 priv->usb_interrupts = 1;
2035 priv->rtlchip = 0x8191c;
2036 } else {
2037 sprintf(priv->chip_name, "8192CU");
2038 priv->rf_paths = 2;
2039 priv->rx_paths = 2;
2040 priv->tx_paths = 2;
2041 priv->usb_interrupts = 1;
2042 priv->rtlchip = 0x8192c;
2043 }
2044 priv->has_wifi = 1;
2045 } else {
2046 sprintf(priv->chip_name, "8188CU");
2047 priv->rf_paths = 1;
2048 priv->rx_paths = 1;
2049 priv->tx_paths = 1;
2050 priv->rtlchip = 0x8188c;
2051 priv->usb_interrupts = 1;
2052 priv->has_wifi = 1;
2053 }
2054
2055 switch (priv->rtlchip) {
2056 case 0x8188e:
2057 case 0x8192e:
2058 case 0x8723b:
2059 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2060 case SYS_CFG_VENDOR_ID_TSMC:
2061 sprintf(priv->chip_vendor, "TSMC");
2062 break;
2063 case SYS_CFG_VENDOR_ID_SMIC:
2064 sprintf(priv->chip_vendor, "SMIC");
2065 priv->vendor_smic = 1;
2066 break;
2067 case SYS_CFG_VENDOR_ID_UMC:
2068 sprintf(priv->chip_vendor, "UMC");
2069 priv->vendor_umc = 1;
2070 break;
2071 default:
2072 sprintf(priv->chip_vendor, "unknown");
2073 }
2074 break;
2075 default:
2076 if (val32 & SYS_CFG_VENDOR_ID) {
2077 sprintf(priv->chip_vendor, "UMC");
2078 priv->vendor_umc = 1;
2079 } else {
2080 sprintf(priv->chip_vendor, "TSMC");
2081 }
2082 }
2083
2084 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2085 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2086
2087 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2088 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2089 priv->ep_tx_high_queue = 1;
2090 priv->ep_tx_count++;
2091 }
2092
2093 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2094 priv->ep_tx_normal_queue = 1;
2095 priv->ep_tx_count++;
2096 }
2097
2098 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2099 priv->ep_tx_low_queue = 1;
2100 priv->ep_tx_count++;
2101 }
2102
2103 /*
2104 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2105 */
2106 if (!priv->ep_tx_count) {
2107 switch (priv->nr_out_eps) {
2108 case 4:
2109 case 3:
2110 priv->ep_tx_low_queue = 1;
2111 priv->ep_tx_count++;
2112 case 2:
2113 priv->ep_tx_normal_queue = 1;
2114 priv->ep_tx_count++;
2115 case 1:
2116 priv->ep_tx_high_queue = 1;
2117 priv->ep_tx_count++;
2118 break;
2119 default:
2120 dev_info(dev, "Unsupported USB TX end-points\n");
2121 return -ENOTSUPP;
2122 }
2123 }
2124
2125 return 0;
2126 }
2127
2128 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2129 {
2130 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2131
2132 if (efuse->rtl_id != cpu_to_le16(0x8129))
2133 return -EINVAL;
2134
2135 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2136
2137 memcpy(priv->cck_tx_power_index_A,
2138 efuse->cck_tx_power_index_A,
2139 sizeof(priv->cck_tx_power_index_A));
2140 memcpy(priv->cck_tx_power_index_B,
2141 efuse->cck_tx_power_index_B,
2142 sizeof(priv->cck_tx_power_index_B));
2143
2144 memcpy(priv->ht40_1s_tx_power_index_A,
2145 efuse->ht40_1s_tx_power_index_A,
2146 sizeof(priv->ht40_1s_tx_power_index_A));
2147 memcpy(priv->ht40_1s_tx_power_index_B,
2148 efuse->ht40_1s_tx_power_index_B,
2149 sizeof(priv->ht40_1s_tx_power_index_B));
2150
2151 memcpy(priv->ht20_tx_power_index_diff,
2152 efuse->ht20_tx_power_index_diff,
2153 sizeof(priv->ht20_tx_power_index_diff));
2154 memcpy(priv->ofdm_tx_power_index_diff,
2155 efuse->ofdm_tx_power_index_diff,
2156 sizeof(priv->ofdm_tx_power_index_diff));
2157
2158 memcpy(priv->ht40_max_power_offset,
2159 efuse->ht40_max_power_offset,
2160 sizeof(priv->ht40_max_power_offset));
2161 memcpy(priv->ht20_max_power_offset,
2162 efuse->ht20_max_power_offset,
2163 sizeof(priv->ht20_max_power_offset));
2164
2165 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2166 efuse->vendor_name);
2167 dev_info(&priv->udev->dev, "Product: %.41s\n",
2168 efuse->device_name);
2169 return 0;
2170 }
2171
2172 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2173 {
2174 if (priv->efuse_wifi.efuse8723bu.rtl_id != cpu_to_le16(0x8129))
2175 return -EINVAL;
2176
2177 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723bu.mac_addr);
2178
2179 memcpy(priv->cck_tx_power_index_A,
2180 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_A,
2181 sizeof(priv->cck_tx_power_index_A));
2182 memcpy(priv->cck_tx_power_index_B,
2183 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_B,
2184 sizeof(priv->cck_tx_power_index_B));
2185
2186 memcpy(priv->ht40_1s_tx_power_index_A,
2187 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_A,
2188 sizeof(priv->ht40_1s_tx_power_index_A));
2189 memcpy(priv->ht40_1s_tx_power_index_B,
2190 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_B,
2191 sizeof(priv->ht40_1s_tx_power_index_B));
2192
2193 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2194 priv->efuse_wifi.efuse8723bu.vendor_name);
2195 dev_info(&priv->udev->dev, "Product: %.41s\n",
2196 priv->efuse_wifi.efuse8723bu.device_name);
2197
2198 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2199 int i;
2200 unsigned char *raw = priv->efuse_wifi.raw;
2201
2202 dev_info(&priv->udev->dev,
2203 "%s: dumping efuse (0x%02zx bytes):\n",
2204 __func__, sizeof(struct rtl8723bu_efuse));
2205 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2206 dev_info(&priv->udev->dev, "%02x: "
2207 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2208 raw[i], raw[i + 1], raw[i + 2],
2209 raw[i + 3], raw[i + 4], raw[i + 5],
2210 raw[i + 6], raw[i + 7]);
2211 }
2212 }
2213
2214 return 0;
2215 }
2216
2217 #ifdef CONFIG_RTL8XXXU_UNTESTED
2218
2219 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2220 {
2221 int i;
2222
2223 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
2224 return -EINVAL;
2225
2226 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
2227
2228 memcpy(priv->cck_tx_power_index_A,
2229 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
2230 sizeof(priv->cck_tx_power_index_A));
2231 memcpy(priv->cck_tx_power_index_B,
2232 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
2233 sizeof(priv->cck_tx_power_index_B));
2234
2235 memcpy(priv->ht40_1s_tx_power_index_A,
2236 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
2237 sizeof(priv->ht40_1s_tx_power_index_A));
2238 memcpy(priv->ht40_1s_tx_power_index_B,
2239 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
2240 sizeof(priv->ht40_1s_tx_power_index_B));
2241 memcpy(priv->ht40_2s_tx_power_index_diff,
2242 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
2243 sizeof(priv->ht40_2s_tx_power_index_diff));
2244
2245 memcpy(priv->ht20_tx_power_index_diff,
2246 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
2247 sizeof(priv->ht20_tx_power_index_diff));
2248 memcpy(priv->ofdm_tx_power_index_diff,
2249 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
2250 sizeof(priv->ofdm_tx_power_index_diff));
2251
2252 memcpy(priv->ht40_max_power_offset,
2253 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
2254 sizeof(priv->ht40_max_power_offset));
2255 memcpy(priv->ht20_max_power_offset,
2256 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
2257 sizeof(priv->ht20_max_power_offset));
2258
2259 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2260 priv->efuse_wifi.efuse8192.vendor_name);
2261 dev_info(&priv->udev->dev, "Product: %.20s\n",
2262 priv->efuse_wifi.efuse8192.device_name);
2263
2264 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
2265 sprintf(priv->chip_name, "8188RU");
2266 priv->hi_pa = 1;
2267 }
2268
2269 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2270 unsigned char *raw = priv->efuse_wifi.raw;
2271
2272 dev_info(&priv->udev->dev,
2273 "%s: dumping efuse (0x%02zx bytes):\n",
2274 __func__, sizeof(struct rtl8192cu_efuse));
2275 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2276 dev_info(&priv->udev->dev, "%02x: "
2277 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2278 raw[i], raw[i + 1], raw[i + 2],
2279 raw[i + 3], raw[i + 4], raw[i + 5],
2280 raw[i + 6], raw[i + 7]);
2281 }
2282 }
2283 return 0;
2284 }
2285
2286 #endif
2287
2288 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2289 {
2290 int i;
2291
2292 if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
2293 return -EINVAL;
2294
2295 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
2296
2297 memcpy(priv->cck_tx_power_index_A,
2298 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
2299 sizeof(priv->cck_tx_power_index_A));
2300 memcpy(priv->cck_tx_power_index_B,
2301 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
2302 sizeof(priv->cck_tx_power_index_B));
2303
2304 memcpy(priv->ht40_1s_tx_power_index_A,
2305 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
2306 sizeof(priv->ht40_1s_tx_power_index_A));
2307 memcpy(priv->ht40_1s_tx_power_index_B,
2308 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
2309 sizeof(priv->ht40_1s_tx_power_index_B));
2310
2311 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2312 priv->efuse_wifi.efuse8192eu.vendor_name);
2313 dev_info(&priv->udev->dev, "Product: %.11s\n",
2314 priv->efuse_wifi.efuse8192eu.device_name);
2315 dev_info(&priv->udev->dev, "Serial: %.11s\n",
2316 priv->efuse_wifi.efuse8192eu.serial);
2317
2318 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2319 unsigned char *raw = priv->efuse_wifi.raw;
2320
2321 dev_info(&priv->udev->dev,
2322 "%s: dumping efuse (0x%02zx bytes):\n",
2323 __func__, sizeof(struct rtl8192eu_efuse));
2324 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2325 dev_info(&priv->udev->dev, "%02x: "
2326 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2327 raw[i], raw[i + 1], raw[i + 2],
2328 raw[i + 3], raw[i + 4], raw[i + 5],
2329 raw[i + 6], raw[i + 7]);
2330 }
2331 }
2332 return 0;
2333 }
2334
2335 static int
2336 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2337 {
2338 int i;
2339 u8 val8;
2340 u32 val32;
2341
2342 /* Write Address */
2343 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2344 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2345 val8 &= 0xfc;
2346 val8 |= (offset >> 8) & 0x03;
2347 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2348
2349 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2350 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2351
2352 /* Poll for data read */
2353 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2354 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2355 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2356 if (val32 & BIT(31))
2357 break;
2358 }
2359
2360 if (i == RTL8XXXU_MAX_REG_POLL)
2361 return -EIO;
2362
2363 udelay(50);
2364 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2365
2366 *data = val32 & 0xff;
2367 return 0;
2368 }
2369
2370 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2371 {
2372 struct device *dev = &priv->udev->dev;
2373 int i, ret = 0;
2374 u8 val8, word_mask, header, extheader;
2375 u16 val16, efuse_addr, offset;
2376 u32 val32;
2377
2378 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2379 if (val16 & EEPROM_ENABLE)
2380 priv->has_eeprom = 1;
2381 if (val16 & EEPROM_BOOT)
2382 priv->boot_eeprom = 1;
2383
2384 if (priv->is_multi_func) {
2385 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2386 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2387 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2388 }
2389
2390 dev_dbg(dev, "Booting from %s\n",
2391 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2392
2393 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2394
2395 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2396 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2397 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2398 val16 |= SYS_ISO_PWC_EV12V;
2399 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2400 }
2401 /* Reset: 0x0000[28], default valid */
2402 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2403 if (!(val16 & SYS_FUNC_ELDR)) {
2404 val16 |= SYS_FUNC_ELDR;
2405 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2406 }
2407
2408 /*
2409 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2410 */
2411 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2412 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2413 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2414 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2415 }
2416
2417 /* Default value is 0xff */
2418 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2419
2420 efuse_addr = 0;
2421 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2422 u16 map_addr;
2423
2424 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2425 if (ret || header == 0xff)
2426 goto exit;
2427
2428 if ((header & 0x1f) == 0x0f) { /* extended header */
2429 offset = (header & 0xe0) >> 5;
2430
2431 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2432 &extheader);
2433 if (ret)
2434 goto exit;
2435 /* All words disabled */
2436 if ((extheader & 0x0f) == 0x0f)
2437 continue;
2438
2439 offset |= ((extheader & 0xf0) >> 1);
2440 word_mask = extheader & 0x0f;
2441 } else {
2442 offset = (header >> 4) & 0x0f;
2443 word_mask = header & 0x0f;
2444 }
2445
2446 /* Get word enable value from PG header */
2447
2448 /* We have 8 bits to indicate validity */
2449 map_addr = offset * 8;
2450 if (map_addr >= EFUSE_MAP_LEN) {
2451 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2452 "efuse corrupt!\n",
2453 __func__, map_addr);
2454 ret = -EINVAL;
2455 goto exit;
2456 }
2457 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2458 /* Check word enable condition in the section */
2459 if (word_mask & BIT(i)) {
2460 map_addr += 2;
2461 continue;
2462 }
2463
2464 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2465 if (ret)
2466 goto exit;
2467 priv->efuse_wifi.raw[map_addr++] = val8;
2468
2469 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2470 if (ret)
2471 goto exit;
2472 priv->efuse_wifi.raw[map_addr++] = val8;
2473 }
2474 }
2475
2476 exit:
2477 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2478
2479 return ret;
2480 }
2481
2482 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2483 {
2484 u8 val8;
2485 u16 sys_func;
2486
2487 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2488 val8 &= ~BIT(0);
2489 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2490 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2491 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2492 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2493 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2494 val8 |= BIT(0);
2495 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2496 sys_func |= SYS_FUNC_CPU_ENABLE;
2497 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2498 }
2499
2500 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2501 {
2502 struct device *dev = &priv->udev->dev;
2503 int ret = 0, i;
2504 u32 val32;
2505
2506 /* Poll checksum report */
2507 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2508 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2509 if (val32 & MCU_FW_DL_CSUM_REPORT)
2510 break;
2511 }
2512
2513 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2514 dev_warn(dev, "Firmware checksum poll timed out\n");
2515 ret = -EAGAIN;
2516 goto exit;
2517 }
2518
2519 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2520 val32 |= MCU_FW_DL_READY;
2521 val32 &= ~MCU_WINT_INIT_READY;
2522 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2523
2524 /*
2525 * Reset the 8051 in order for the firmware to start running,
2526 * otherwise it won't come up on the 8192eu
2527 */
2528 rtl8xxxu_reset_8051(priv);
2529
2530 /* Wait for firmware to become ready */
2531 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2532 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2533 if (val32 & MCU_WINT_INIT_READY)
2534 break;
2535
2536 udelay(100);
2537 }
2538
2539 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2540 dev_warn(dev, "Firmware failed to start\n");
2541 ret = -EAGAIN;
2542 goto exit;
2543 }
2544
2545 exit:
2546 return ret;
2547 }
2548
2549 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2550 {
2551 int pages, remainder, i, ret;
2552 u8 val8;
2553 u16 val16;
2554 u32 val32;
2555 u8 *fwptr;
2556
2557 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2558 val8 |= 4;
2559 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2560
2561 /* 8051 enable */
2562 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2563 val16 |= SYS_FUNC_CPU_ENABLE;
2564 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2565
2566 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2567 if (val8 & MCU_FW_RAM_SEL) {
2568 pr_info("do the RAM reset\n");
2569 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2570 rtl8xxxu_reset_8051(priv);
2571 }
2572
2573 /* MCU firmware download enable */
2574 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2575 val8 |= MCU_FW_DL_ENABLE;
2576 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2577
2578 /* 8051 reset */
2579 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2580 val32 &= ~BIT(19);
2581 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2582
2583 /* Reset firmware download checksum */
2584 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2585 val8 |= MCU_FW_DL_CSUM_REPORT;
2586 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2587
2588 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2589 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2590
2591 fwptr = priv->fw_data->data;
2592
2593 for (i = 0; i < pages; i++) {
2594 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2595 val8 |= i;
2596 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2597
2598 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2599 fwptr, RTL_FW_PAGE_SIZE);
2600 if (ret != RTL_FW_PAGE_SIZE) {
2601 ret = -EAGAIN;
2602 goto fw_abort;
2603 }
2604
2605 fwptr += RTL_FW_PAGE_SIZE;
2606 }
2607
2608 if (remainder) {
2609 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2610 val8 |= i;
2611 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2612 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2613 fwptr, remainder);
2614 if (ret != remainder) {
2615 ret = -EAGAIN;
2616 goto fw_abort;
2617 }
2618 }
2619
2620 ret = 0;
2621 fw_abort:
2622 /* MCU firmware download disable */
2623 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2624 val16 &= ~MCU_FW_DL_ENABLE;
2625 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2626
2627 return ret;
2628 }
2629
2630 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2631 {
2632 struct device *dev = &priv->udev->dev;
2633 const struct firmware *fw;
2634 int ret = 0;
2635 u16 signature;
2636
2637 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2638 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2639 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2640 ret = -EAGAIN;
2641 goto exit;
2642 }
2643 if (!fw) {
2644 dev_warn(dev, "Firmware data not available\n");
2645 ret = -EINVAL;
2646 goto exit;
2647 }
2648
2649 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2650 if (!priv->fw_data) {
2651 ret = -ENOMEM;
2652 goto exit;
2653 }
2654 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2655
2656 signature = le16_to_cpu(priv->fw_data->signature);
2657 switch (signature & 0xfff0) {
2658 case 0x92e0:
2659 case 0x92c0:
2660 case 0x88c0:
2661 case 0x5300:
2662 case 0x2300:
2663 break;
2664 default:
2665 ret = -EINVAL;
2666 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2667 __func__, signature);
2668 }
2669
2670 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2671 le16_to_cpu(priv->fw_data->major_version),
2672 priv->fw_data->minor_version, signature);
2673
2674 exit:
2675 release_firmware(fw);
2676 return ret;
2677 }
2678
2679 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2680 {
2681 char *fw_name;
2682 int ret;
2683
2684 switch (priv->chip_cut) {
2685 case 0:
2686 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2687 break;
2688 case 1:
2689 if (priv->enable_bluetooth)
2690 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2691 else
2692 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2693
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
2699 ret = rtl8xxxu_load_firmware(priv, fw_name);
2700 return ret;
2701 }
2702
2703 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2704 {
2705 char *fw_name;
2706 int ret;
2707
2708 if (priv->enable_bluetooth)
2709 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2710 else
2711 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2712
2713 ret = rtl8xxxu_load_firmware(priv, fw_name);
2714 return ret;
2715 }
2716
2717 #ifdef CONFIG_RTL8XXXU_UNTESTED
2718
2719 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2720 {
2721 char *fw_name;
2722 int ret;
2723
2724 if (!priv->vendor_umc)
2725 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2726 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2727 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2728 else
2729 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2730
2731 ret = rtl8xxxu_load_firmware(priv, fw_name);
2732
2733 return ret;
2734 }
2735
2736 #endif
2737
2738 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2739 {
2740 char *fw_name;
2741 int ret;
2742
2743 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2744
2745 ret = rtl8xxxu_load_firmware(priv, fw_name);
2746
2747 return ret;
2748 }
2749
2750 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2751 {
2752 u16 val16;
2753 int i = 100;
2754
2755 /* Inform 8051 to perform reset */
2756 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2757
2758 for (i = 100; i > 0; i--) {
2759 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2760
2761 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2762 dev_dbg(&priv->udev->dev,
2763 "%s: Firmware self reset success!\n", __func__);
2764 break;
2765 }
2766 udelay(50);
2767 }
2768
2769 if (!i) {
2770 /* Force firmware reset */
2771 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2772 val16 &= ~SYS_FUNC_CPU_ENABLE;
2773 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2774 }
2775 }
2776
2777 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2778 {
2779 u32 val32;
2780
2781 val32 = rtl8xxxu_read32(priv, 0x64);
2782 val32 &= ~(BIT(20) | BIT(24));
2783 rtl8xxxu_write32(priv, 0x64, val32);
2784
2785 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2786 val32 &= ~BIT(4);
2787 val32 |= BIT(3);
2788 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2789
2790 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2791 val32 &= ~BIT(23);
2792 val32 |= BIT(24);
2793 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2794
2795 val32 = rtl8xxxu_read32(priv, 0x0944);
2796 val32 |= (BIT(0) | BIT(1));
2797 rtl8xxxu_write32(priv, 0x0944, val32);
2798
2799 val32 = rtl8xxxu_read32(priv, 0x0930);
2800 val32 &= 0xffffff00;
2801 val32 |= 0x77;
2802 rtl8xxxu_write32(priv, 0x0930, val32);
2803
2804 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2805 val32 |= BIT(11);
2806 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2807 }
2808
2809 static int
2810 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2811 {
2812 int i, ret;
2813 u16 reg;
2814 u8 val;
2815
2816 for (i = 0; ; i++) {
2817 reg = array[i].reg;
2818 val = array[i].val;
2819
2820 if (reg == 0xffff && val == 0xff)
2821 break;
2822
2823 ret = rtl8xxxu_write8(priv, reg, val);
2824 if (ret != 1) {
2825 dev_warn(&priv->udev->dev,
2826 "Failed to initialize MAC\n");
2827 return -EAGAIN;
2828 }
2829 }
2830
2831 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2832
2833 return 0;
2834 }
2835
2836 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2837 struct rtl8xxxu_reg32val *array)
2838 {
2839 int i, ret;
2840 u16 reg;
2841 u32 val;
2842
2843 for (i = 0; ; i++) {
2844 reg = array[i].reg;
2845 val = array[i].val;
2846
2847 if (reg == 0xffff && val == 0xffffffff)
2848 break;
2849
2850 ret = rtl8xxxu_write32(priv, reg, val);
2851 if (ret != sizeof(val)) {
2852 dev_warn(&priv->udev->dev,
2853 "Failed to initialize PHY\n");
2854 return -EAGAIN;
2855 }
2856 udelay(1);
2857 }
2858
2859 return 0;
2860 }
2861
2862 /*
2863 * Most of this is black magic retrieved from the old rtl8723au driver
2864 */
2865 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2866 {
2867 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2868 u32 val32;
2869
2870 /*
2871 * Todo: The vendor driver maintains a table of PHY register
2872 * addresses, which is initialized here. Do we need this?
2873 */
2874
2875 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2876 udelay(2);
2877 val8 |= AFE_PLL_320_ENABLE;
2878 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2879 udelay(2);
2880
2881 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2882 udelay(2);
2883
2884 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2885 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2886 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2887
2888 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2889 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2890 val32 &= ~AFE_XTAL_RF_GATE;
2891 if (priv->has_bluetooth)
2892 val32 &= ~AFE_XTAL_BT_GATE;
2893 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2894
2895 /* 6. 0x1f[7:0] = 0x07 */
2896 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2897 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2898
2899 if (priv->hi_pa)
2900 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2901 else if (priv->tx_paths == 2)
2902 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2903 else if (priv->rtlchip == 0x8723b)
2904 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
2905 else
2906 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2907
2908
2909 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2910 priv->vendor_umc && priv->chip_cut == 1)
2911 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2912
2913 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2914 /*
2915 * For 1T2R boards, patch the registers.
2916 *
2917 * It looks like 8191/2 1T2R boards use path B for TX
2918 */
2919 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2920 val32 &= ~(BIT(0) | BIT(1));
2921 val32 |= BIT(1);
2922 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2923
2924 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2925 val32 &= ~0x300033;
2926 val32 |= 0x200022;
2927 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2928
2929 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2930 val32 &= 0xff000000;
2931 val32 |= 0x45000000;
2932 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2933
2934 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2935 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2936 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2937 OFDM_RF_PATH_TX_B);
2938 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2939
2940 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2941 val32 &= ~(BIT(4) | BIT(5));
2942 val32 |= BIT(4);
2943 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2944
2945 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2946 val32 &= ~(BIT(27) | BIT(26));
2947 val32 |= BIT(27);
2948 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2949
2950 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2951 val32 &= ~(BIT(27) | BIT(26));
2952 val32 |= BIT(27);
2953 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2954
2955 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2956 val32 &= ~(BIT(27) | BIT(26));
2957 val32 |= BIT(27);
2958 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2959
2960 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2961 val32 &= ~(BIT(27) | BIT(26));
2962 val32 |= BIT(27);
2963 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2964
2965 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2966 val32 &= ~(BIT(27) | BIT(26));
2967 val32 |= BIT(27);
2968 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2969 }
2970
2971 if (priv->rtlchip == 0x8723b)
2972 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
2973 else if (priv->hi_pa)
2974 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2975 else
2976 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2977
2978 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
2979 priv->efuse_wifi.efuse8723.version >= 0x01) {
2980 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2981
2982 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2983 val32 &= 0xff000fff;
2984 val32 |= ((val8 | (val8 << 6)) << 12);
2985
2986 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2987 }
2988
2989 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2990 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2991 ldohci12 = 0x57;
2992 lpldo = 1;
2993 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2994
2995 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2996
2997 return 0;
2998 }
2999
3000 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3001 struct rtl8xxxu_rfregval *array,
3002 enum rtl8xxxu_rfpath path)
3003 {
3004 int i, ret;
3005 u8 reg;
3006 u32 val;
3007
3008 for (i = 0; ; i++) {
3009 reg = array[i].reg;
3010 val = array[i].val;
3011
3012 if (reg == 0xff && val == 0xffffffff)
3013 break;
3014
3015 switch (reg) {
3016 case 0xfe:
3017 msleep(50);
3018 continue;
3019 case 0xfd:
3020 mdelay(5);
3021 continue;
3022 case 0xfc:
3023 mdelay(1);
3024 continue;
3025 case 0xfb:
3026 udelay(50);
3027 continue;
3028 case 0xfa:
3029 udelay(5);
3030 continue;
3031 case 0xf9:
3032 udelay(1);
3033 continue;
3034 }
3035
3036 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3037 if (ret) {
3038 dev_warn(&priv->udev->dev,
3039 "Failed to initialize RF\n");
3040 return -EAGAIN;
3041 }
3042 udelay(1);
3043 }
3044
3045 return 0;
3046 }
3047
3048 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3049 struct rtl8xxxu_rfregval *table,
3050 enum rtl8xxxu_rfpath path)
3051 {
3052 u32 val32;
3053 u16 val16, rfsi_rfenv;
3054 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3055
3056 switch (path) {
3057 case RF_A:
3058 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3059 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3060 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3061 break;
3062 case RF_B:
3063 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3064 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3065 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3066 break;
3067 default:
3068 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3069 __func__, path + 'A');
3070 return -EINVAL;
3071 }
3072 /* For path B, use XB */
3073 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3074 rfsi_rfenv &= FPGA0_RF_RFENV;
3075
3076 /*
3077 * These two we might be able to optimize into one
3078 */
3079 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3080 val32 |= BIT(20); /* 0x10 << 16 */
3081 rtl8xxxu_write32(priv, reg_int_oe, val32);
3082 udelay(1);
3083
3084 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3085 val32 |= BIT(4);
3086 rtl8xxxu_write32(priv, reg_int_oe, val32);
3087 udelay(1);
3088
3089 /*
3090 * These two we might be able to optimize into one
3091 */
3092 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3093 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3094 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3095 udelay(1);
3096
3097 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3098 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3099 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3100 udelay(1);
3101
3102 rtl8xxxu_init_rf_regs(priv, table, path);
3103
3104 /* For path B, use XB */
3105 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3106 val16 &= ~FPGA0_RF_RFENV;
3107 val16 |= rfsi_rfenv;
3108 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3109
3110 return 0;
3111 }
3112
3113 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3114 {
3115 int ret = -EBUSY;
3116 int count = 0;
3117 u32 value;
3118
3119 value = LLT_OP_WRITE | address << 8 | data;
3120
3121 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3122
3123 do {
3124 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3125 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3126 ret = 0;
3127 break;
3128 }
3129 } while (count++ < 20);
3130
3131 return ret;
3132 }
3133
3134 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3135 {
3136 int ret;
3137 int i;
3138
3139 for (i = 0; i < last_tx_page; i++) {
3140 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3141 if (ret)
3142 goto exit;
3143 }
3144
3145 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3146 if (ret)
3147 goto exit;
3148
3149 /* Mark remaining pages as a ring buffer */
3150 for (i = last_tx_page + 1; i < 0xff; i++) {
3151 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3152 if (ret)
3153 goto exit;
3154 }
3155
3156 /* Let last entry point to the start entry of ring buffer */
3157 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3158 if (ret)
3159 goto exit;
3160
3161 exit:
3162 return ret;
3163 }
3164
3165 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3166 {
3167 u32 val32;
3168 int ret = 0;
3169 int i;
3170
3171 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3172 val32 |= AUTO_LLT_INIT_LLT;
3173 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3174
3175 for (i = 500; i; i--) {
3176 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3177 if (!(val32 & AUTO_LLT_INIT_LLT))
3178 break;
3179 usleep_range(2, 4);
3180 }
3181
3182 if (!i) {
3183 ret = -EBUSY;
3184 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3185 }
3186
3187 return ret;
3188 }
3189
3190 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3191 {
3192 u16 val16, hi, lo;
3193 u16 hiq, mgq, bkq, beq, viq, voq;
3194 int hip, mgp, bkp, bep, vip, vop;
3195 int ret = 0;
3196
3197 switch (priv->ep_tx_count) {
3198 case 1:
3199 if (priv->ep_tx_high_queue) {
3200 hi = TRXDMA_QUEUE_HIGH;
3201 } else if (priv->ep_tx_low_queue) {
3202 hi = TRXDMA_QUEUE_LOW;
3203 } else if (priv->ep_tx_normal_queue) {
3204 hi = TRXDMA_QUEUE_NORMAL;
3205 } else {
3206 hi = 0;
3207 ret = -EINVAL;
3208 }
3209
3210 hiq = hi;
3211 mgq = hi;
3212 bkq = hi;
3213 beq = hi;
3214 viq = hi;
3215 voq = hi;
3216
3217 hip = 0;
3218 mgp = 0;
3219 bkp = 0;
3220 bep = 0;
3221 vip = 0;
3222 vop = 0;
3223 break;
3224 case 2:
3225 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3226 hi = TRXDMA_QUEUE_HIGH;
3227 lo = TRXDMA_QUEUE_LOW;
3228 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3229 hi = TRXDMA_QUEUE_NORMAL;
3230 lo = TRXDMA_QUEUE_LOW;
3231 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3232 hi = TRXDMA_QUEUE_HIGH;
3233 lo = TRXDMA_QUEUE_NORMAL;
3234 } else {
3235 ret = -EINVAL;
3236 hi = 0;
3237 lo = 0;
3238 }
3239
3240 hiq = hi;
3241 mgq = hi;
3242 bkq = lo;
3243 beq = lo;
3244 viq = hi;
3245 voq = hi;
3246
3247 hip = 0;
3248 mgp = 0;
3249 bkp = 1;
3250 bep = 1;
3251 vip = 0;
3252 vop = 0;
3253 break;
3254 case 3:
3255 beq = TRXDMA_QUEUE_LOW;
3256 bkq = TRXDMA_QUEUE_LOW;
3257 viq = TRXDMA_QUEUE_NORMAL;
3258 voq = TRXDMA_QUEUE_HIGH;
3259 mgq = TRXDMA_QUEUE_HIGH;
3260 hiq = TRXDMA_QUEUE_HIGH;
3261
3262 hip = hiq ^ 3;
3263 mgp = mgq ^ 3;
3264 bkp = bkq ^ 3;
3265 bep = beq ^ 3;
3266 vip = viq ^ 3;
3267 vop = viq ^ 3;
3268 break;
3269 default:
3270 ret = -EINVAL;
3271 }
3272
3273 /*
3274 * None of the vendor drivers are configuring the beacon
3275 * queue here .... why?
3276 */
3277 if (!ret) {
3278 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3279 val16 &= 0x7;
3280 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3281 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3282 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3283 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3284 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3285 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3286 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3287
3288 priv->pipe_out[TXDESC_QUEUE_VO] =
3289 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3290 priv->pipe_out[TXDESC_QUEUE_VI] =
3291 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3292 priv->pipe_out[TXDESC_QUEUE_BE] =
3293 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3294 priv->pipe_out[TXDESC_QUEUE_BK] =
3295 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3296 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3297 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3298 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3299 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3300 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3301 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3302 priv->pipe_out[TXDESC_QUEUE_CMD] =
3303 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3304 }
3305
3306 return ret;
3307 }
3308
3309 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3310 bool iqk_ok, int result[][8],
3311 int candidate, bool tx_only)
3312 {
3313 u32 oldval, x, tx0_a, reg;
3314 int y, tx0_c;
3315 u32 val32;
3316
3317 if (!iqk_ok)
3318 return;
3319
3320 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3321 oldval = val32 >> 22;
3322
3323 x = result[candidate][0];
3324 if ((x & 0x00000200) != 0)
3325 x = x | 0xfffffc00;
3326 tx0_a = (x * oldval) >> 8;
3327
3328 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3329 val32 &= ~0x3ff;
3330 val32 |= tx0_a;
3331 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3332
3333 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3334 val32 &= ~BIT(31);
3335 if ((x * oldval >> 7) & 0x1)
3336 val32 |= BIT(31);
3337 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3338
3339 y = result[candidate][1];
3340 if ((y & 0x00000200) != 0)
3341 y = y | 0xfffffc00;
3342 tx0_c = (y * oldval) >> 8;
3343
3344 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3345 val32 &= ~0xf0000000;
3346 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3347 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3348
3349 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3350 val32 &= ~0x003f0000;
3351 val32 |= ((tx0_c & 0x3f) << 16);
3352 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3353
3354 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3355 val32 &= ~BIT(29);
3356 if ((y * oldval >> 7) & 0x1)
3357 val32 |= BIT(29);
3358 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3359
3360 if (tx_only) {
3361 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3362 return;
3363 }
3364
3365 reg = result[candidate][2];
3366
3367 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3368 val32 &= ~0x3ff;
3369 val32 |= (reg & 0x3ff);
3370 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3371
3372 reg = result[candidate][3] & 0x3F;
3373
3374 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3375 val32 &= ~0xfc00;
3376 val32 |= ((reg << 10) & 0xfc00);
3377 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3378
3379 reg = (result[candidate][3] >> 6) & 0xF;
3380
3381 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3382 val32 &= ~0xf0000000;
3383 val32 |= (reg << 28);
3384 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3385 }
3386
3387 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3388 bool iqk_ok, int result[][8],
3389 int candidate, bool tx_only)
3390 {
3391 u32 oldval, x, tx1_a, reg;
3392 int y, tx1_c;
3393 u32 val32;
3394
3395 if (!iqk_ok)
3396 return;
3397
3398 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3399 oldval = val32 >> 22;
3400
3401 x = result[candidate][4];
3402 if ((x & 0x00000200) != 0)
3403 x = x | 0xfffffc00;
3404 tx1_a = (x * oldval) >> 8;
3405
3406 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3407 val32 &= ~0x3ff;
3408 val32 |= tx1_a;
3409 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3410
3411 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3412 val32 &= ~BIT(27);
3413 if ((x * oldval >> 7) & 0x1)
3414 val32 |= BIT(27);
3415 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3416
3417 y = result[candidate][5];
3418 if ((y & 0x00000200) != 0)
3419 y = y | 0xfffffc00;
3420 tx1_c = (y * oldval) >> 8;
3421
3422 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3423 val32 &= ~0xf0000000;
3424 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3425 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3426
3427 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3428 val32 &= ~0x003f0000;
3429 val32 |= ((tx1_c & 0x3f) << 16);
3430 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3431
3432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3433 val32 &= ~BIT(25);
3434 if ((y * oldval >> 7) & 0x1)
3435 val32 |= BIT(25);
3436 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3437
3438 if (tx_only) {
3439 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3440 return;
3441 }
3442
3443 reg = result[candidate][6];
3444
3445 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3446 val32 &= ~0x3ff;
3447 val32 |= (reg & 0x3ff);
3448 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3449
3450 reg = result[candidate][7] & 0x3f;
3451
3452 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3453 val32 &= ~0xfc00;
3454 val32 |= ((reg << 10) & 0xfc00);
3455 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3456
3457 reg = (result[candidate][7] >> 6) & 0xf;
3458
3459 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3460 val32 &= ~0x0000f000;
3461 val32 |= (reg << 12);
3462 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3463 }
3464
3465 #define MAX_TOLERANCE 5
3466
3467 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3468 int result[][8], int c1, int c2)
3469 {
3470 u32 i, j, diff, simubitmap, bound = 0;
3471 int candidate[2] = {-1, -1}; /* for path A and path B */
3472 bool retval = true;
3473
3474 if (priv->tx_paths > 1)
3475 bound = 8;
3476 else
3477 bound = 4;
3478
3479 simubitmap = 0;
3480
3481 for (i = 0; i < bound; i++) {
3482 diff = (result[c1][i] > result[c2][i]) ?
3483 (result[c1][i] - result[c2][i]) :
3484 (result[c2][i] - result[c1][i]);
3485 if (diff > MAX_TOLERANCE) {
3486 if ((i == 2 || i == 6) && !simubitmap) {
3487 if (result[c1][i] + result[c1][i + 1] == 0)
3488 candidate[(i / 4)] = c2;
3489 else if (result[c2][i] + result[c2][i + 1] == 0)
3490 candidate[(i / 4)] = c1;
3491 else
3492 simubitmap = simubitmap | (1 << i);
3493 } else {
3494 simubitmap = simubitmap | (1 << i);
3495 }
3496 }
3497 }
3498
3499 if (simubitmap == 0) {
3500 for (i = 0; i < (bound / 4); i++) {
3501 if (candidate[i] >= 0) {
3502 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3503 result[3][j] = result[candidate[i]][j];
3504 retval = false;
3505 }
3506 }
3507 return retval;
3508 } else if (!(simubitmap & 0x0f)) {
3509 /* path A OK */
3510 for (i = 0; i < 4; i++)
3511 result[3][i] = result[c1][i];
3512 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3513 /* path B OK */
3514 for (i = 4; i < 8; i++)
3515 result[3][i] = result[c1][i];
3516 }
3517
3518 return false;
3519 }
3520
3521 static void
3522 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3523 {
3524 int i;
3525
3526 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3527 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3528
3529 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3530 }
3531
3532 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3533 const u32 *reg, u32 *backup)
3534 {
3535 int i;
3536
3537 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3538 rtl8xxxu_write8(priv, reg[i], backup[i]);
3539
3540 rtl8xxxu_write32(priv, reg[i], backup[i]);
3541 }
3542
3543 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3544 u32 *backup, int count)
3545 {
3546 int i;
3547
3548 for (i = 0; i < count; i++)
3549 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3550 }
3551
3552 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3553 u32 *backup, int count)
3554 {
3555 int i;
3556
3557 for (i = 0; i < count; i++)
3558 rtl8xxxu_write32(priv, regs[i], backup[i]);
3559 }
3560
3561
3562 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3563 bool path_a_on)
3564 {
3565 u32 path_on;
3566 int i;
3567
3568 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3569 if (priv->tx_paths == 1) {
3570 path_on = 0x0bdb25a0;
3571 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3572 } else {
3573 rtl8xxxu_write32(priv, regs[0], path_on);
3574 }
3575
3576 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3577 rtl8xxxu_write32(priv, regs[i], path_on);
3578 }
3579
3580 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3581 const u32 *regs, u32 *backup)
3582 {
3583 int i = 0;
3584
3585 rtl8xxxu_write8(priv, regs[i], 0x3f);
3586
3587 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3588 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3589
3590 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3591 }
3592
3593 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3594 {
3595 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3596 int result = 0;
3597
3598 /* path-A IQK setting */
3599 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3600 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3601 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3602
3603 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3604 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3605 0x28160502;
3606 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3607
3608 /* path-B IQK setting */
3609 if (priv->rf_paths > 1) {
3610 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3611 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3612 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3613 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3614 }
3615
3616 /* LO calibration setting */
3617 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3618
3619 /* One shot, path A LOK & IQK */
3620 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3621 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3622
3623 mdelay(1);
3624
3625 /* Check failed */
3626 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3627 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3628 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3629 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3630
3631 if (!(reg_eac & BIT(28)) &&
3632 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3633 ((reg_e9c & 0x03ff0000) != 0x00420000))
3634 result |= 0x01;
3635 else /* If TX not OK, ignore RX */
3636 goto out;
3637
3638 /* If TX is OK, check whether RX is OK */
3639 if (!(reg_eac & BIT(27)) &&
3640 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3641 ((reg_eac & 0x03ff0000) != 0x00360000))
3642 result |= 0x02;
3643 else
3644 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3645 __func__);
3646 out:
3647 return result;
3648 }
3649
3650 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3651 {
3652 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3653 int result = 0;
3654
3655 /* One shot, path B LOK & IQK */
3656 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3657 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3658
3659 mdelay(1);
3660
3661 /* Check failed */
3662 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3663 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3664 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3665 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3666 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3667
3668 if (!(reg_eac & BIT(31)) &&
3669 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3670 ((reg_ebc & 0x03ff0000) != 0x00420000))
3671 result |= 0x01;
3672 else
3673 goto out;
3674
3675 if (!(reg_eac & BIT(30)) &&
3676 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3677 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3678 result |= 0x02;
3679 else
3680 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3681 __func__);
3682 out:
3683 return result;
3684 }
3685
3686 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3687 int result[][8], int t)
3688 {
3689 struct device *dev = &priv->udev->dev;
3690 u32 i, val32;
3691 int path_a_ok, path_b_ok;
3692 int retry = 2;
3693 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3694 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3695 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3696 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3697 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3698 REG_TX_TO_TX, REG_RX_CCK,
3699 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3700 REG_RX_TO_RX, REG_STANDBY,
3701 REG_SLEEP, REG_PMPD_ANAEN
3702 };
3703 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3704 REG_TXPAUSE, REG_BEACON_CTRL,
3705 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3706 };
3707 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3708 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3709 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3710 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3711 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3712 };
3713
3714 /*
3715 * Note: IQ calibration must be performed after loading
3716 * PHY_REG.txt , and radio_a, radio_b.txt
3717 */
3718
3719 if (t == 0) {
3720 /* Save ADDA parameters, turn Path A ADDA on */
3721 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3722 RTL8XXXU_ADDA_REGS);
3723 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3724 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3725 priv->bb_backup, RTL8XXXU_BB_REGS);
3726 }
3727
3728 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3729
3730 if (t == 0) {
3731 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3732 if (val32 & FPGA0_HSSI_PARM1_PI)
3733 priv->pi_enabled = 1;
3734 }
3735
3736 if (!priv->pi_enabled) {
3737 /* Switch BB to PI mode to do IQ Calibration. */
3738 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3739 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3740 }
3741
3742 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3743 val32 &= ~FPGA_RF_MODE_CCK;
3744 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3745
3746 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3747 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3748 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3749
3750 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3751 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3752 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3753
3754 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3755 val32 &= ~BIT(10);
3756 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3757 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3758 val32 &= ~BIT(10);
3759 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3760
3761 if (priv->tx_paths > 1) {
3762 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3763 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3764 }
3765
3766 /* MAC settings */
3767 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3768
3769 /* Page B init */
3770 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3771
3772 if (priv->tx_paths > 1)
3773 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3774
3775 /* IQ calibration setting */
3776 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3777 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3778 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3779
3780 for (i = 0; i < retry; i++) {
3781 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3782 if (path_a_ok == 0x03) {
3783 val32 = rtl8xxxu_read32(priv,
3784 REG_TX_POWER_BEFORE_IQK_A);
3785 result[t][0] = (val32 >> 16) & 0x3ff;
3786 val32 = rtl8xxxu_read32(priv,
3787 REG_TX_POWER_AFTER_IQK_A);
3788 result[t][1] = (val32 >> 16) & 0x3ff;
3789 val32 = rtl8xxxu_read32(priv,
3790 REG_RX_POWER_BEFORE_IQK_A_2);
3791 result[t][2] = (val32 >> 16) & 0x3ff;
3792 val32 = rtl8xxxu_read32(priv,
3793 REG_RX_POWER_AFTER_IQK_A_2);
3794 result[t][3] = (val32 >> 16) & 0x3ff;
3795 break;
3796 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3797 /* TX IQK OK */
3798 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3799 __func__);
3800
3801 val32 = rtl8xxxu_read32(priv,
3802 REG_TX_POWER_BEFORE_IQK_A);
3803 result[t][0] = (val32 >> 16) & 0x3ff;
3804 val32 = rtl8xxxu_read32(priv,
3805 REG_TX_POWER_AFTER_IQK_A);
3806 result[t][1] = (val32 >> 16) & 0x3ff;
3807 }
3808 }
3809
3810 if (!path_a_ok)
3811 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3812
3813 if (priv->tx_paths > 1) {
3814 /*
3815 * Path A into standby
3816 */
3817 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3818 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3819 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3820
3821 /* Turn Path B ADDA on */
3822 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3823
3824 for (i = 0; i < retry; i++) {
3825 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3826 if (path_b_ok == 0x03) {
3827 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3828 result[t][4] = (val32 >> 16) & 0x3ff;
3829 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3830 result[t][5] = (val32 >> 16) & 0x3ff;
3831 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3832 result[t][6] = (val32 >> 16) & 0x3ff;
3833 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3834 result[t][7] = (val32 >> 16) & 0x3ff;
3835 break;
3836 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3837 /* TX IQK OK */
3838 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3839 result[t][4] = (val32 >> 16) & 0x3ff;
3840 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3841 result[t][5] = (val32 >> 16) & 0x3ff;
3842 }
3843 }
3844
3845 if (!path_b_ok)
3846 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3847 }
3848
3849 /* Back to BB mode, load original value */
3850 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3851
3852 if (t) {
3853 if (!priv->pi_enabled) {
3854 /*
3855 * Switch back BB to SI mode after finishing
3856 * IQ Calibration
3857 */
3858 val32 = 0x01000000;
3859 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3860 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3861 }
3862
3863 /* Reload ADDA power saving parameters */
3864 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3865 RTL8XXXU_ADDA_REGS);
3866
3867 /* Reload MAC parameters */
3868 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3869
3870 /* Reload BB parameters */
3871 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3872 priv->bb_backup, RTL8XXXU_BB_REGS);
3873
3874 /* Restore RX initial gain */
3875 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3876
3877 if (priv->tx_paths > 1) {
3878 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3879 0x00032ed3);
3880 }
3881
3882 /* Load 0xe30 IQC default value */
3883 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3884 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3885 }
3886 }
3887
3888 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3889 {
3890 struct device *dev = &priv->udev->dev;
3891 int result[4][8]; /* last is final result */
3892 int i, candidate;
3893 bool path_a_ok, path_b_ok;
3894 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3895 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3896 s32 reg_tmp = 0;
3897 bool simu;
3898
3899 memset(result, 0, sizeof(result));
3900 candidate = -1;
3901
3902 path_a_ok = false;
3903 path_b_ok = false;
3904
3905 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3906
3907 for (i = 0; i < 3; i++) {
3908 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3909
3910 if (i == 1) {
3911 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3912 if (simu) {
3913 candidate = 0;
3914 break;
3915 }
3916 }
3917
3918 if (i == 2) {
3919 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3920 if (simu) {
3921 candidate = 0;
3922 break;
3923 }
3924
3925 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3926 if (simu) {
3927 candidate = 1;
3928 } else {
3929 for (i = 0; i < 8; i++)
3930 reg_tmp += result[3][i];
3931
3932 if (reg_tmp)
3933 candidate = 3;
3934 else
3935 candidate = -1;
3936 }
3937 }
3938 }
3939
3940 for (i = 0; i < 4; i++) {
3941 reg_e94 = result[i][0];
3942 reg_e9c = result[i][1];
3943 reg_ea4 = result[i][2];
3944 reg_eac = result[i][3];
3945 reg_eb4 = result[i][4];
3946 reg_ebc = result[i][5];
3947 reg_ec4 = result[i][6];
3948 reg_ecc = result[i][7];
3949 }
3950
3951 if (candidate >= 0) {
3952 reg_e94 = result[candidate][0];
3953 priv->rege94 = reg_e94;
3954 reg_e9c = result[candidate][1];
3955 priv->rege9c = reg_e9c;
3956 reg_ea4 = result[candidate][2];
3957 reg_eac = result[candidate][3];
3958 reg_eb4 = result[candidate][4];
3959 priv->regeb4 = reg_eb4;
3960 reg_ebc = result[candidate][5];
3961 priv->regebc = reg_ebc;
3962 reg_ec4 = result[candidate][6];
3963 reg_ecc = result[candidate][7];
3964 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3965 dev_dbg(dev,
3966 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3967 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3968 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3969 path_a_ok = true;
3970 path_b_ok = true;
3971 } else {
3972 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3973 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3974 }
3975
3976 if (reg_e94 && candidate >= 0)
3977 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3978 candidate, (reg_ea4 == 0));
3979
3980 if (priv->tx_paths > 1 && reg_eb4)
3981 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3982 candidate, (reg_ec4 == 0));
3983
3984 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3985 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3986 }
3987
3988 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3989 {
3990 u32 val32;
3991 u32 rf_amode, rf_bmode = 0, lstf;
3992
3993 /* Check continuous TX and Packet TX */
3994 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3995
3996 if (lstf & OFDM_LSTF_MASK) {
3997 /* Disable all continuous TX */
3998 val32 = lstf & ~OFDM_LSTF_MASK;
3999 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4000
4001 /* Read original RF mode Path A */
4002 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
4003
4004 /* Set RF mode to standby Path A */
4005 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
4006 (rf_amode & 0x8ffff) | 0x10000);
4007
4008 /* Path-B */
4009 if (priv->tx_paths > 1) {
4010 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4011 RF6052_REG_AC);
4012
4013 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4014 (rf_bmode & 0x8ffff) | 0x10000);
4015 }
4016 } else {
4017 /* Deal with Packet TX case */
4018 /* block all queues */
4019 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4020 }
4021
4022 /* Start LC calibration */
4023 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4024 val32 |= 0x08000;
4025 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4026
4027 msleep(100);
4028
4029 /* Restore original parameters */
4030 if (lstf & OFDM_LSTF_MASK) {
4031 /* Path-A */
4032 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4033 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4034
4035 /* Path-B */
4036 if (priv->tx_paths > 1)
4037 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4038 rf_bmode);
4039 } else /* Deal with Packet TX case */
4040 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
4041 }
4042
4043 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
4044 {
4045 int i;
4046 u16 reg;
4047
4048 reg = REG_MACID;
4049
4050 for (i = 0; i < ETH_ALEN; i++)
4051 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
4052
4053 return 0;
4054 }
4055
4056 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
4057 {
4058 int i;
4059 u16 reg;
4060
4061 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
4062
4063 reg = REG_BSSID;
4064
4065 for (i = 0; i < ETH_ALEN; i++)
4066 rtl8xxxu_write8(priv, reg + i, bssid[i]);
4067
4068 return 0;
4069 }
4070
4071 static void
4072 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
4073 {
4074 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
4075 u8 max_agg = 0xf;
4076 int i;
4077
4078 ampdu_factor = 1 << (ampdu_factor + 2);
4079 if (ampdu_factor > max_agg)
4080 ampdu_factor = max_agg;
4081
4082 for (i = 0; i < 4; i++) {
4083 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
4084 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
4085
4086 if ((vals[i] & 0x0f) > ampdu_factor)
4087 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
4088
4089 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
4090 }
4091 }
4092
4093 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
4094 {
4095 u8 val8;
4096
4097 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
4098 val8 &= 0xf8;
4099 val8 |= density;
4100 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
4101 }
4102
4103 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
4104 {
4105 u8 val8;
4106 int count, ret;
4107
4108 /* Start of rtl8723AU_card_enable_flow */
4109 /* Act to Cardemu sequence*/
4110 /* Turn off RF */
4111 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
4112
4113 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
4114 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4115 val8 &= ~LEDCFG2_DPDT_SELECT;
4116 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4117
4118 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
4119 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4120 val8 |= BIT(1);
4121 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4122
4123 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4124 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4125 if ((val8 & BIT(1)) == 0)
4126 break;
4127 udelay(10);
4128 }
4129
4130 if (!count) {
4131 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
4132 __func__);
4133 ret = -EBUSY;
4134 goto exit;
4135 }
4136
4137 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
4138 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4139 val8 |= SYS_ISO_ANALOG_IPS;
4140 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4141
4142 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
4143 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4144 val8 &= ~LDOA15_ENABLE;
4145 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4146
4147 exit:
4148 return ret;
4149 }
4150
4151 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
4152 {
4153 u8 val8;
4154 u8 val32;
4155 int count, ret;
4156
4157 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4158
4159 /*
4160 * Poll - wait for RX packet to complete
4161 */
4162 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4163 val32 = rtl8xxxu_read32(priv, 0x5f8);
4164 if (!val32)
4165 break;
4166 udelay(10);
4167 }
4168
4169 if (!count) {
4170 dev_warn(&priv->udev->dev,
4171 "%s: RX poll timed out (0x05f8)\n", __func__);
4172 ret = -EBUSY;
4173 goto exit;
4174 }
4175
4176 /* Disable CCK and OFDM, clock gated */
4177 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4178 val8 &= ~SYS_FUNC_BBRSTB;
4179 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4180
4181 udelay(2);
4182
4183 /* Reset baseband */
4184 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4185 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
4186 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4187
4188 /* Reset MAC TRX */
4189 val8 = rtl8xxxu_read8(priv, REG_CR);
4190 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
4191 rtl8xxxu_write8(priv, REG_CR, val8);
4192
4193 /* Reset MAC TRX */
4194 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
4195 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
4196 rtl8xxxu_write8(priv, REG_CR + 1, val8);
4197
4198 /* Respond TX OK to scheduler */
4199 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
4200 val8 |= DUAL_TSF_TX_OK;
4201 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
4202
4203 exit:
4204 return ret;
4205 }
4206
4207 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
4208 {
4209 u8 val8;
4210
4211 /* Clear suspend enable and power down enable*/
4212 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4213 val8 &= ~(BIT(3) | BIT(7));
4214 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4215
4216 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
4217 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4218 val8 &= ~BIT(0);
4219 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4220
4221 /* 0x04[12:11] = 11 enable WL suspend*/
4222 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4223 val8 &= ~(BIT(3) | BIT(4));
4224 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4225 }
4226
4227 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
4228 {
4229 u8 val8;
4230
4231 /* Clear suspend enable and power down enable*/
4232 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4233 val8 &= ~(BIT(3) | BIT(4));
4234 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4235 }
4236
4237 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
4238 {
4239 u8 val8;
4240 u32 val32;
4241 int count, ret = 0;
4242
4243 /* disable HWPDN 0x04[15]=0*/
4244 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4245 val8 &= ~BIT(7);
4246 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4247
4248 /* disable SW LPS 0x04[10]= 0 */
4249 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4250 val8 &= ~BIT(2);
4251 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4252
4253 /* disable WL suspend*/
4254 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4255 val8 &= ~(BIT(3) | BIT(4));
4256 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4257
4258 /* wait till 0x04[17] = 1 power ready*/
4259 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4260 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4261 if (val32 & BIT(17))
4262 break;
4263
4264 udelay(10);
4265 }
4266
4267 if (!count) {
4268 ret = -EBUSY;
4269 goto exit;
4270 }
4271
4272 /* We should be able to optimize the following three entries into one */
4273
4274 /* release WLON reset 0x04[16]= 1*/
4275 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4276 val8 |= BIT(0);
4277 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4278
4279 /* set, then poll until 0 */
4280 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4281 val32 |= APS_FSMCO_MAC_ENABLE;
4282 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4283
4284 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4285 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4286 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4287 ret = 0;
4288 break;
4289 }
4290 udelay(10);
4291 }
4292
4293 if (!count) {
4294 ret = -EBUSY;
4295 goto exit;
4296 }
4297
4298 exit:
4299 return ret;
4300 }
4301
4302 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
4303 {
4304 u8 val8;
4305 u32 val32;
4306 int count, ret = 0;
4307
4308 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
4309 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4310 val8 |= LDOA15_ENABLE;
4311 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4312
4313 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
4314 val8 = rtl8xxxu_read8(priv, 0x0067);
4315 val8 &= ~BIT(4);
4316 rtl8xxxu_write8(priv, 0x0067, val8);
4317
4318 mdelay(1);
4319
4320 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4321 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4322 val8 &= ~SYS_ISO_ANALOG_IPS;
4323 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4324
4325 /* disable SW LPS 0x04[10]= 0 */
4326 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4327 val8 &= ~BIT(2);
4328 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4329
4330 /* wait till 0x04[17] = 1 power ready*/
4331 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4332 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4333 if (val32 & BIT(17))
4334 break;
4335
4336 udelay(10);
4337 }
4338
4339 if (!count) {
4340 ret = -EBUSY;
4341 goto exit;
4342 }
4343
4344 /* We should be able to optimize the following three entries into one */
4345
4346 /* release WLON reset 0x04[16]= 1*/
4347 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4348 val8 |= BIT(0);
4349 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4350
4351 /* disable HWPDN 0x04[15]= 0*/
4352 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4353 val8 &= ~BIT(7);
4354 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4355
4356 /* disable WL suspend*/
4357 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4358 val8 &= ~(BIT(3) | BIT(4));
4359 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4360
4361 /* set, then poll until 0 */
4362 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4363 val32 |= APS_FSMCO_MAC_ENABLE;
4364 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4365
4366 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4367 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4368 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4369 ret = 0;
4370 break;
4371 }
4372 udelay(10);
4373 }
4374
4375 if (!count) {
4376 ret = -EBUSY;
4377 goto exit;
4378 }
4379
4380 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4381 /*
4382 * Note: Vendor driver actually clears this bit, despite the
4383 * documentation claims it's being set!
4384 */
4385 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4386 val8 |= LEDCFG2_DPDT_SELECT;
4387 val8 &= ~LEDCFG2_DPDT_SELECT;
4388 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4389
4390 exit:
4391 return ret;
4392 }
4393
4394 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4395 {
4396 u8 val8;
4397
4398 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4399 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4400
4401 /* 0x04[12:11] = 01 enable WL suspend */
4402 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4403 val8 &= ~BIT(4);
4404 val8 |= BIT(3);
4405 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4406
4407 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4408 val8 |= BIT(7);
4409 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4410
4411 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4412 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4413 val8 |= BIT(0);
4414 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4415
4416 return 0;
4417 }
4418
4419 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4420 {
4421 u8 val8;
4422 u16 val16;
4423 u32 val32;
4424 int ret;
4425
4426 /*
4427 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4428 */
4429 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4430
4431 rtl8723a_disabled_to_emu(priv);
4432
4433 ret = rtl8723a_emu_to_active(priv);
4434 if (ret)
4435 goto exit;
4436
4437 /*
4438 * 0x0004[19] = 1, reset 8051
4439 */
4440 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4441 val8 |= BIT(3);
4442 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4443
4444 /*
4445 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4446 * Set CR bit10 to enable 32k calibration.
4447 */
4448 val16 = rtl8xxxu_read16(priv, REG_CR);
4449 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4450 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4451 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4452 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4453 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4454 rtl8xxxu_write16(priv, REG_CR, val16);
4455
4456 /* For EFuse PG */
4457 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4458 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4459 val32 |= (0x06 << 28);
4460 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4461 exit:
4462 return ret;
4463 }
4464
4465 #ifdef CONFIG_RTL8XXXU_UNTESTED
4466
4467 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4468 {
4469 u8 val8;
4470 u16 val16;
4471 u32 val32;
4472 int i;
4473
4474 for (i = 100; i; i--) {
4475 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4476 if (val8 & APS_FSMCO_PFM_ALDN)
4477 break;
4478 }
4479
4480 if (!i) {
4481 pr_info("%s: Poll failed\n", __func__);
4482 return -ENODEV;
4483 }
4484
4485 /*
4486 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4487 */
4488 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4489 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4490 udelay(100);
4491
4492 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4493 if (!(val8 & LDOV12D_ENABLE)) {
4494 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4495 val8 |= LDOV12D_ENABLE;
4496 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4497
4498 udelay(100);
4499
4500 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4501 val8 &= ~SYS_ISO_MD2PP;
4502 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4503 }
4504
4505 /*
4506 * Auto enable WLAN
4507 */
4508 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4509 val16 |= APS_FSMCO_MAC_ENABLE;
4510 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4511
4512 for (i = 1000; i; i--) {
4513 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4514 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4515 break;
4516 }
4517 if (!i) {
4518 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4519 return -EBUSY;
4520 }
4521
4522 /*
4523 * Enable radio, GPIO, LED
4524 */
4525 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4526 APS_FSMCO_PFM_ALDN;
4527 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4528
4529 /*
4530 * Release RF digital isolation
4531 */
4532 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4533 val16 &= ~SYS_ISO_DIOR;
4534 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4535
4536 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4537 val8 &= ~APSD_CTRL_OFF;
4538 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4539 for (i = 200; i; i--) {
4540 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4541 if (!(val8 & APSD_CTRL_OFF_STATUS))
4542 break;
4543 }
4544
4545 if (!i) {
4546 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4547 return -EBUSY;
4548 }
4549
4550 /*
4551 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4552 */
4553 val16 = rtl8xxxu_read16(priv, REG_CR);
4554 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4555 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4556 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4557 rtl8xxxu_write16(priv, REG_CR, val16);
4558
4559 /*
4560 * Workaround for 8188RU LNA power leakage problem.
4561 */
4562 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4563 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4564 val32 &= ~BIT(1);
4565 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4566 }
4567 return 0;
4568 }
4569
4570 #endif
4571
4572 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4573 {
4574 u16 val16;
4575 u32 val32;
4576 int ret;
4577
4578 ret = 0;
4579
4580 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4581 if (val32 & SYS_CFG_SPS_LDO_SEL) {
4582 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4583 } else {
4584 /*
4585 * Raise 1.2V voltage
4586 */
4587 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4588 val32 &= 0xff0fffff;
4589 val32 |= 0x00500000;
4590 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4591 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4592 }
4593
4594 rtl8192e_disabled_to_emu(priv);
4595
4596 ret = rtl8192e_emu_to_active(priv);
4597 if (ret)
4598 goto exit;
4599
4600 rtl8xxxu_write16(priv, REG_CR, 0x0000);
4601
4602 /*
4603 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4604 * Set CR bit10 to enable 32k calibration.
4605 */
4606 val16 = rtl8xxxu_read16(priv, REG_CR);
4607 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4608 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4609 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4610 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4611 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4612 rtl8xxxu_write16(priv, REG_CR, val16);
4613
4614 exit:
4615 return ret;
4616 }
4617
4618 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4619 {
4620 u8 val8;
4621 u16 val16;
4622 u32 val32;
4623
4624 /*
4625 * Workaround for 8188RU LNA power leakage problem.
4626 */
4627 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4628 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4629 val32 |= BIT(1);
4630 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4631 }
4632
4633 rtl8xxxu_active_to_lps(priv);
4634
4635 /* Turn off RF */
4636 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4637
4638 /* Reset Firmware if running in RAM */
4639 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4640 rtl8xxxu_firmware_self_reset(priv);
4641
4642 /* Reset MCU */
4643 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4644 val16 &= ~SYS_FUNC_CPU_ENABLE;
4645 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4646
4647 /* Reset MCU ready status */
4648 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4649
4650 rtl8xxxu_active_to_emu(priv);
4651 rtl8xxxu_emu_to_disabled(priv);
4652
4653 /* Reset MCU IO Wrapper */
4654 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4655 val8 &= ~BIT(0);
4656 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4657
4658 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4659 val8 |= BIT(0);
4660 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4661
4662 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4663 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4664 }
4665
4666 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4667 {
4668 if (!priv->has_bluetooth)
4669 return;
4670 }
4671
4672 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4673 {
4674 struct rtl8xxxu_priv *priv = hw->priv;
4675 struct device *dev = &priv->udev->dev;
4676 struct rtl8xxxu_rfregval *rftable;
4677 bool macpower;
4678 int ret;
4679 u8 val8;
4680 u16 val16;
4681 u32 val32;
4682
4683 /* Check if MAC is already powered on */
4684 val8 = rtl8xxxu_read8(priv, REG_CR);
4685
4686 /*
4687 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4688 * initialized. First MAC returns 0xea, second MAC returns 0x00
4689 */
4690 if (val8 == 0xea)
4691 macpower = false;
4692 else
4693 macpower = true;
4694
4695 ret = priv->fops->power_on(priv);
4696 if (ret < 0) {
4697 dev_warn(dev, "%s: Failed power on\n", __func__);
4698 goto exit;
4699 }
4700
4701 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4702 if (!macpower) {
4703 if (priv->ep_tx_normal_queue)
4704 val8 = TX_PAGE_NUM_NORM_PQ;
4705 else
4706 val8 = 0;
4707
4708 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4709
4710 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4711
4712 if (priv->ep_tx_high_queue)
4713 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4714 if (priv->ep_tx_low_queue)
4715 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4716
4717 rtl8xxxu_write32(priv, REG_RQPN, val32);
4718
4719 /*
4720 * Set TX buffer boundary
4721 */
4722 val8 = TX_TOTAL_PAGE_NUM + 1;
4723 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4724 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4725 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4726 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4727 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4728 }
4729
4730 ret = rtl8xxxu_download_firmware(priv);
4731 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4732 if (ret)
4733 goto exit;
4734 ret = rtl8xxxu_start_firmware(priv);
4735 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4736 if (ret)
4737 goto exit;
4738
4739 ret = rtl8xxxu_init_queue_priority(priv);
4740 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4741 if (ret)
4742 goto exit;
4743
4744 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4745 if (!macpower) {
4746 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
4747 if (ret) {
4748 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4749 goto exit;
4750 }
4751 }
4752
4753 /* Fix USB interface interference issue */
4754 if (priv->rtlchip == 0x8723a) {
4755 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4756 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4757 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4758 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4759 } else {
4760 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4761 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4762 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
4763 }
4764
4765 /* Solve too many protocol error on USB bus */
4766 /* Can't do this for 8188/8192 UMC A cut parts */
4767 if (priv->rtlchip == 0x8723a ||
4768 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
4769 priv->rtlchip == 0x8188c) &&
4770 (priv->chip_cut || !priv->vendor_umc))) {
4771 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4772 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4773 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4774
4775 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4776 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4777 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4778
4779 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4780 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4781 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4782
4783 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4784 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4785 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4786 }
4787
4788 if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
4789 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4790 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4791 }
4792
4793 if (priv->fops->phy_init_antenna_selection)
4794 priv->fops->phy_init_antenna_selection(priv);
4795
4796 if (priv->rtlchip == 0x8723b)
4797 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
4798 else
4799 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4800
4801 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4802 if (ret)
4803 goto exit;
4804
4805 ret = rtl8xxxu_init_phy_bb(priv);
4806 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4807 if (ret)
4808 goto exit;
4809
4810 switch(priv->rtlchip) {
4811 case 0x8723a:
4812 rftable = rtl8723au_radioa_1t_init_table;
4813 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4814 break;
4815 case 0x8723b:
4816 rftable = rtl8723bu_radioa_1t_init_table;
4817 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4818 break;
4819 case 0x8188c:
4820 if (priv->hi_pa)
4821 rftable = rtl8188ru_radioa_1t_highpa_table;
4822 else
4823 rftable = rtl8192cu_radioa_1t_init_table;
4824 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4825 break;
4826 case 0x8191c:
4827 rftable = rtl8192cu_radioa_1t_init_table;
4828 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4829 break;
4830 case 0x8192c:
4831 rftable = rtl8192cu_radioa_2t_init_table;
4832 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4833 if (ret)
4834 break;
4835 rftable = rtl8192cu_radiob_2t_init_table;
4836 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4837 break;
4838 default:
4839 ret = -EINVAL;
4840 }
4841
4842 if (ret)
4843 goto exit;
4844
4845 /* Reduce 80M spur */
4846 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4847 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4848 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4849 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4850
4851 /* RFSW Control - clear bit 14 ?? */
4852 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4853 /* 0x07000760 */
4854 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4855 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4856 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4857 FPGA0_RF_BD_CTRL_SHIFT);
4858 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4859 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4860 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4861
4862 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4863 RF6052_REG_MODE_AG);
4864
4865 /*
4866 * Set RX page boundary
4867 */
4868 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4869 /*
4870 * Transfer page size is always 128
4871 */
4872 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4873 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4874 rtl8xxxu_write8(priv, REG_PBP, val8);
4875
4876 /*
4877 * Unit in 8 bytes, not obvious what it is used for
4878 */
4879 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4880
4881 /*
4882 * Enable all interrupts - not obvious USB needs to do this
4883 */
4884 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4885 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4886
4887 rtl8xxxu_set_mac(priv);
4888 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4889
4890 /*
4891 * Configure initial WMAC settings
4892 */
4893 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4894 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4895 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4896 rtl8xxxu_write32(priv, REG_RCR, val32);
4897
4898 /*
4899 * Accept all multicast
4900 */
4901 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4902 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4903
4904 /*
4905 * Init adaptive controls
4906 */
4907 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4908 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4909 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4910 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4911
4912 /* CCK = 0x0a, OFDM = 0x10 */
4913 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4914 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4915 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4916
4917 /*
4918 * Init EDCA
4919 */
4920 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4921
4922 /* Set CCK SIFS */
4923 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4924
4925 /* Set OFDM SIFS */
4926 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4927
4928 /* TXOP */
4929 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4930 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4931 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4932 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4933
4934 /* Set data auto rate fallback retry count */
4935 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4936 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4937 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4938 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4939
4940 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4941 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4942 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4943
4944 /* Set ACK timeout */
4945 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4946
4947 /*
4948 * Initialize beacon parameters
4949 */
4950 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4951 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4952 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4953 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4954 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4955 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4956
4957 /*
4958 * Enable CCK and OFDM block
4959 */
4960 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4961 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4962 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4963
4964 /*
4965 * Invalidate all CAM entries - bit 30 is undocumented
4966 */
4967 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4968
4969 /*
4970 * Start out with default power levels for channel 6, 20MHz
4971 */
4972 rtl8723a_set_tx_power(priv, 1, false);
4973
4974 /* Let the 8051 take control of antenna setting */
4975 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4976 val8 |= LEDCFG2_DPDT_SELECT;
4977 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4978
4979 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4980
4981 /* Disable BAR - not sure if this has any effect on USB */
4982 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4983
4984 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4985
4986 rtl8723a_phy_iq_calibrate(priv);
4987
4988 /*
4989 * This should enable thermal meter
4990 */
4991 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4992
4993 rtl8723a_phy_lc_calibrate(priv);
4994
4995 /* Init BT hw config. */
4996 rtl8xxxu_init_bt(priv);
4997
4998 /*
4999 * Not sure if we really need to save these parameters, but the
5000 * vendor driver does
5001 */
5002 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
5003 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
5004 priv->path_a_hi_power = 1;
5005
5006 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
5007 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
5008
5009 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5010 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
5011
5012 /* Set NAV_UPPER to 30000us */
5013 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
5014 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
5015
5016 if (priv->rtlchip == 0x8723a) {
5017 /*
5018 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
5019 * but we need to find root cause.
5020 * This is 8723au only.
5021 */
5022 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5023 if ((val32 & 0xff000000) != 0x83000000) {
5024 val32 |= FPGA_RF_MODE_CCK;
5025 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5026 }
5027 }
5028
5029 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
5030 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
5031 /* ack for xmit mgmt frames. */
5032 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
5033
5034 exit:
5035 return ret;
5036 }
5037
5038 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
5039 {
5040 struct rtl8xxxu_priv *priv = hw->priv;
5041
5042 rtl8xxxu_power_off(priv);
5043 }
5044
5045 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
5046 struct ieee80211_key_conf *key, const u8 *mac)
5047 {
5048 u32 cmd, val32, addr, ctrl;
5049 int j, i, tmp_debug;
5050
5051 tmp_debug = rtl8xxxu_debug;
5052 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
5053 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
5054
5055 /*
5056 * This is a bit of a hack - the lower bits of the cipher
5057 * suite selector happens to match the cipher index in the CAM
5058 */
5059 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
5060 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
5061
5062 for (j = 5; j >= 0; j--) {
5063 switch (j) {
5064 case 0:
5065 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
5066 break;
5067 case 1:
5068 val32 = mac[2] | (mac[3] << 8) |
5069 (mac[4] << 16) | (mac[5] << 24);
5070 break;
5071 default:
5072 i = (j - 2) << 2;
5073 val32 = key->key[i] | (key->key[i + 1] << 8) |
5074 key->key[i + 2] << 16 | key->key[i + 3] << 24;
5075 break;
5076 }
5077
5078 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
5079 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
5080 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
5081 udelay(100);
5082 }
5083
5084 rtl8xxxu_debug = tmp_debug;
5085 }
5086
5087 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
5088 struct ieee80211_vif *vif, const u8 *mac)
5089 {
5090 struct rtl8xxxu_priv *priv = hw->priv;
5091 u8 val8;
5092
5093 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5094 val8 |= BEACON_DISABLE_TSF_UPDATE;
5095 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5096 }
5097
5098 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
5099 struct ieee80211_vif *vif)
5100 {
5101 struct rtl8xxxu_priv *priv = hw->priv;
5102 u8 val8;
5103
5104 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5105 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
5106 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5107 }
5108
5109 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
5110 u32 ramask, int sgi)
5111 {
5112 struct h2c_cmd h2c;
5113
5114 h2c.ramask.cmd = H2C_SET_RATE_MASK;
5115 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
5116 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
5117
5118 h2c.ramask.arg = 0x80;
5119 if (sgi)
5120 h2c.ramask.arg |= 0x20;
5121
5122 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
5123 ramask, h2c.ramask.arg);
5124 rtl8723a_h2c_cmd(priv, &h2c);
5125 }
5126
5127 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
5128 {
5129 u32 val32;
5130 u8 rate_idx = 0;
5131
5132 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
5133
5134 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5135 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5136 val32 |= rate_cfg;
5137 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5138
5139 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
5140
5141 while (rate_cfg) {
5142 rate_cfg = (rate_cfg >> 1);
5143 rate_idx++;
5144 }
5145 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
5146 }
5147
5148 static void
5149 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5150 struct ieee80211_bss_conf *bss_conf, u32 changed)
5151 {
5152 struct rtl8xxxu_priv *priv = hw->priv;
5153 struct device *dev = &priv->udev->dev;
5154 struct ieee80211_sta *sta;
5155 u32 val32;
5156 u8 val8;
5157
5158 if (changed & BSS_CHANGED_ASSOC) {
5159 struct h2c_cmd h2c;
5160
5161 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
5162
5163 memset(&h2c, 0, sizeof(struct h2c_cmd));
5164 rtl8xxxu_set_linktype(priv, vif->type);
5165
5166 if (bss_conf->assoc) {
5167 u32 ramask;
5168 int sgi = 0;
5169
5170 rcu_read_lock();
5171 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5172 if (!sta) {
5173 dev_info(dev, "%s: ASSOC no sta found\n",
5174 __func__);
5175 rcu_read_unlock();
5176 goto error;
5177 }
5178
5179 if (sta->ht_cap.ht_supported)
5180 dev_info(dev, "%s: HT supported\n", __func__);
5181 if (sta->vht_cap.vht_supported)
5182 dev_info(dev, "%s: VHT supported\n", __func__);
5183
5184 /* TODO: Set bits 28-31 for rate adaptive id */
5185 ramask = (sta->supp_rates[0] & 0xfff) |
5186 sta->ht_cap.mcs.rx_mask[0] << 12 |
5187 sta->ht_cap.mcs.rx_mask[1] << 20;
5188 if (sta->ht_cap.cap &
5189 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5190 sgi = 1;
5191 rcu_read_unlock();
5192
5193 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
5194
5195 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5196
5197 rtl8723a_stop_tx_beacon(priv);
5198
5199 /* joinbss sequence */
5200 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5201 0xc000 | bss_conf->aid);
5202
5203 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
5204 } else {
5205 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5206 val8 |= BEACON_DISABLE_TSF_UPDATE;
5207 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5208
5209 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
5210 }
5211 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
5212 rtl8723a_h2c_cmd(priv, &h2c);
5213 }
5214
5215 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5216 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5217 bss_conf->use_short_preamble);
5218 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5219 if (bss_conf->use_short_preamble)
5220 val32 |= RSR_ACK_SHORT_PREAMBLE;
5221 else
5222 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5223 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5224 }
5225
5226 if (changed & BSS_CHANGED_ERP_SLOT) {
5227 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5228 bss_conf->use_short_slot);
5229
5230 if (bss_conf->use_short_slot)
5231 val8 = 9;
5232 else
5233 val8 = 20;
5234 rtl8xxxu_write8(priv, REG_SLOT, val8);
5235 }
5236
5237 if (changed & BSS_CHANGED_BSSID) {
5238 dev_dbg(dev, "Changed BSSID!\n");
5239 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5240 }
5241
5242 if (changed & BSS_CHANGED_BASIC_RATES) {
5243 dev_dbg(dev, "Changed BASIC_RATES!\n");
5244 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5245 }
5246 error:
5247 return;
5248 }
5249
5250 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5251 {
5252 u32 rtlqueue;
5253
5254 switch (queue) {
5255 case IEEE80211_AC_VO:
5256 rtlqueue = TXDESC_QUEUE_VO;
5257 break;
5258 case IEEE80211_AC_VI:
5259 rtlqueue = TXDESC_QUEUE_VI;
5260 break;
5261 case IEEE80211_AC_BE:
5262 rtlqueue = TXDESC_QUEUE_BE;
5263 break;
5264 case IEEE80211_AC_BK:
5265 rtlqueue = TXDESC_QUEUE_BK;
5266 break;
5267 default:
5268 rtlqueue = TXDESC_QUEUE_BE;
5269 }
5270
5271 return rtlqueue;
5272 }
5273
5274 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
5275 {
5276 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5277 u32 queue;
5278
5279 if (ieee80211_is_mgmt(hdr->frame_control))
5280 queue = TXDESC_QUEUE_MGNT;
5281 else
5282 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5283
5284 return queue;
5285 }
5286
5287 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
5288 {
5289 __le16 *ptr = (__le16 *)tx_desc;
5290 u16 csum = 0;
5291 int i;
5292
5293 /*
5294 * Clear csum field before calculation, as the csum field is
5295 * in the middle of the struct.
5296 */
5297 tx_desc->csum = cpu_to_le16(0);
5298
5299 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
5300 csum = csum ^ le16_to_cpu(ptr[i]);
5301
5302 tx_desc->csum |= cpu_to_le16(csum);
5303 }
5304
5305 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5306 {
5307 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5308 unsigned long flags;
5309
5310 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5311 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5312 list_del(&tx_urb->list);
5313 priv->tx_urb_free_count--;
5314 usb_free_urb(&tx_urb->urb);
5315 }
5316 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5317 }
5318
5319 static struct rtl8xxxu_tx_urb *
5320 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5321 {
5322 struct rtl8xxxu_tx_urb *tx_urb;
5323 unsigned long flags;
5324
5325 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5326 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5327 struct rtl8xxxu_tx_urb, list);
5328 if (tx_urb) {
5329 list_del(&tx_urb->list);
5330 priv->tx_urb_free_count--;
5331 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5332 !priv->tx_stopped) {
5333 priv->tx_stopped = true;
5334 ieee80211_stop_queues(priv->hw);
5335 }
5336 }
5337
5338 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5339
5340 return tx_urb;
5341 }
5342
5343 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5344 struct rtl8xxxu_tx_urb *tx_urb)
5345 {
5346 unsigned long flags;
5347
5348 INIT_LIST_HEAD(&tx_urb->list);
5349
5350 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5351
5352 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5353 priv->tx_urb_free_count++;
5354 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5355 priv->tx_stopped) {
5356 priv->tx_stopped = false;
5357 ieee80211_wake_queues(priv->hw);
5358 }
5359
5360 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5361 }
5362
5363 static void rtl8xxxu_tx_complete(struct urb *urb)
5364 {
5365 struct sk_buff *skb = (struct sk_buff *)urb->context;
5366 struct ieee80211_tx_info *tx_info;
5367 struct ieee80211_hw *hw;
5368 struct rtl8xxxu_tx_urb *tx_urb =
5369 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5370
5371 tx_info = IEEE80211_SKB_CB(skb);
5372 hw = tx_info->rate_driver_data[0];
5373
5374 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5375
5376 ieee80211_tx_info_clear_status(tx_info);
5377 tx_info->status.rates[0].idx = -1;
5378 tx_info->status.rates[0].count = 0;
5379
5380 if (!urb->status)
5381 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5382
5383 ieee80211_tx_status_irqsafe(hw, skb);
5384
5385 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5386 }
5387
5388 static void rtl8xxxu_dump_action(struct device *dev,
5389 struct ieee80211_hdr *hdr)
5390 {
5391 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5392 u16 cap, timeout;
5393
5394 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5395 return;
5396
5397 switch (mgmt->u.action.u.addba_resp.action_code) {
5398 case WLAN_ACTION_ADDBA_RESP:
5399 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5400 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5401 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5402 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5403 "status %02x\n",
5404 timeout,
5405 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5406 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5407 (cap >> 1) & 0x1,
5408 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5409 break;
5410 case WLAN_ACTION_ADDBA_REQ:
5411 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5412 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5413 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5414 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5415 timeout,
5416 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5417 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5418 (cap >> 1) & 0x1);
5419 break;
5420 default:
5421 dev_info(dev, "action frame %02x\n",
5422 mgmt->u.action.u.addba_resp.action_code);
5423 break;
5424 }
5425 }
5426
5427 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5428 struct ieee80211_tx_control *control,
5429 struct sk_buff *skb)
5430 {
5431 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5432 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5433 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5434 struct rtl8xxxu_priv *priv = hw->priv;
5435 struct rtl8xxxu_tx_desc *tx_desc;
5436 struct rtl8xxxu_tx_urb *tx_urb;
5437 struct ieee80211_sta *sta = NULL;
5438 struct ieee80211_vif *vif = tx_info->control.vif;
5439 struct device *dev = &priv->udev->dev;
5440 u32 queue, rate;
5441 u16 pktlen = skb->len;
5442 u16 seq_number;
5443 u16 rate_flag = tx_info->control.rates[0].flags;
5444 int ret;
5445
5446 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5447 dev_warn(dev,
5448 "%s: Not enough headroom (%i) for tx descriptor\n",
5449 __func__, skb_headroom(skb));
5450 goto error;
5451 }
5452
5453 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5454 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5455 __func__, skb->len);
5456 goto error;
5457 }
5458
5459 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5460 if (!tx_urb) {
5461 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5462 goto error;
5463 }
5464
5465 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5466 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5467 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5468
5469 if (ieee80211_is_action(hdr->frame_control))
5470 rtl8xxxu_dump_action(dev, hdr);
5471
5472 tx_info->rate_driver_data[0] = hw;
5473
5474 if (control && control->sta)
5475 sta = control->sta;
5476
5477 tx_desc = (struct rtl8xxxu_tx_desc *)
5478 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5479
5480 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5481 tx_desc->pkt_size = cpu_to_le16(pktlen);
5482 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5483
5484 tx_desc->txdw0 =
5485 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5486 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5487 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5488 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5489
5490 queue = rtl8xxxu_queue_select(hw, skb);
5491 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5492
5493 if (tx_info->control.hw_key) {
5494 switch (tx_info->control.hw_key->cipher) {
5495 case WLAN_CIPHER_SUITE_WEP40:
5496 case WLAN_CIPHER_SUITE_WEP104:
5497 case WLAN_CIPHER_SUITE_TKIP:
5498 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5499 break;
5500 case WLAN_CIPHER_SUITE_CCMP:
5501 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5502 break;
5503 default:
5504 break;
5505 }
5506 }
5507
5508 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5509 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5510
5511 if (rate_flag & IEEE80211_TX_RC_MCS)
5512 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5513 else
5514 rate = tx_rate->hw_value;
5515 tx_desc->txdw5 = cpu_to_le32(rate);
5516
5517 if (ieee80211_is_data(hdr->frame_control))
5518 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5519
5520 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5521 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5522 if (sta->ht_cap.ht_supported) {
5523 u32 ampdu, val32;
5524
5525 ampdu = (u32)sta->ht_cap.ampdu_density;
5526 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5527 tx_desc->txdw2 |= cpu_to_le32(val32);
5528 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5529 } else
5530 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5531 } else
5532 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5533
5534 if (ieee80211_is_data_qos(hdr->frame_control))
5535 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5536 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5537 (sta && vif && vif->bss_conf.use_short_preamble))
5538 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5539 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5540 (ieee80211_is_data_qos(hdr->frame_control) &&
5541 sta && sta->ht_cap.cap &
5542 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5543 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5544 }
5545 if (ieee80211_is_mgmt(hdr->frame_control)) {
5546 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5547 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5548 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5549 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5550 }
5551
5552 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5553 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5554 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5555 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5556 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5557 }
5558
5559 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5560
5561 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5562 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5563
5564 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5565 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5566 if (ret) {
5567 usb_unanchor_urb(&tx_urb->urb);
5568 rtl8xxxu_free_tx_urb(priv, tx_urb);
5569 goto error;
5570 }
5571 return;
5572 error:
5573 dev_kfree_skb(skb);
5574 }
5575
5576 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5577 struct ieee80211_rx_status *rx_status,
5578 struct rtl8xxxu_rx_desc *rx_desc,
5579 struct rtl8723au_phy_stats *phy_stats)
5580 {
5581 if (phy_stats->sgi_en)
5582 rx_status->flag |= RX_FLAG_SHORT_GI;
5583
5584 if (rx_desc->rxmcs < DESC_RATE_6M) {
5585 /*
5586 * Handle PHY stats for CCK rates
5587 */
5588 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5589
5590 switch (cck_agc_rpt & 0xc0) {
5591 case 0xc0:
5592 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5593 break;
5594 case 0x80:
5595 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5596 break;
5597 case 0x40:
5598 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5599 break;
5600 case 0x00:
5601 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5602 break;
5603 }
5604 } else {
5605 rx_status->signal =
5606 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5607 }
5608 }
5609
5610 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5611 {
5612 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5613 unsigned long flags;
5614
5615 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5616
5617 list_for_each_entry_safe(rx_urb, tmp,
5618 &priv->rx_urb_pending_list, list) {
5619 list_del(&rx_urb->list);
5620 priv->rx_urb_pending_count--;
5621 usb_free_urb(&rx_urb->urb);
5622 }
5623
5624 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5625 }
5626
5627 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5628 struct rtl8xxxu_rx_urb *rx_urb)
5629 {
5630 struct sk_buff *skb;
5631 unsigned long flags;
5632 int pending = 0;
5633
5634 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5635
5636 if (!priv->shutdown) {
5637 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5638 priv->rx_urb_pending_count++;
5639 pending = priv->rx_urb_pending_count;
5640 } else {
5641 skb = (struct sk_buff *)rx_urb->urb.context;
5642 dev_kfree_skb(skb);
5643 usb_free_urb(&rx_urb->urb);
5644 }
5645
5646 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5647
5648 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5649 schedule_work(&priv->rx_urb_wq);
5650 }
5651
5652 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5653 {
5654 struct rtl8xxxu_priv *priv;
5655 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5656 struct list_head local;
5657 struct sk_buff *skb;
5658 unsigned long flags;
5659 int ret;
5660
5661 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5662 INIT_LIST_HEAD(&local);
5663
5664 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5665
5666 list_splice_init(&priv->rx_urb_pending_list, &local);
5667 priv->rx_urb_pending_count = 0;
5668
5669 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5670
5671 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5672 list_del_init(&rx_urb->list);
5673 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5674 /*
5675 * If out of memory or temporary error, put it back on the
5676 * queue and try again. Otherwise the device is dead/gone
5677 * and we should drop it.
5678 */
5679 switch (ret) {
5680 case 0:
5681 break;
5682 case -ENOMEM:
5683 case -EAGAIN:
5684 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5685 break;
5686 default:
5687 pr_info("failed to requeue urb %i\n", ret);
5688 skb = (struct sk_buff *)rx_urb->urb.context;
5689 dev_kfree_skb(skb);
5690 usb_free_urb(&rx_urb->urb);
5691 }
5692 }
5693 }
5694
5695 static void rtl8xxxu_rx_complete(struct urb *urb)
5696 {
5697 struct rtl8xxxu_rx_urb *rx_urb =
5698 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5699 struct ieee80211_hw *hw = rx_urb->hw;
5700 struct rtl8xxxu_priv *priv = hw->priv;
5701 struct sk_buff *skb = (struct sk_buff *)urb->context;
5702 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5703 struct rtl8723au_phy_stats *phy_stats;
5704 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5705 struct device *dev = &priv->udev->dev;
5706 __le32 *_rx_desc_le = (__le32 *)skb->data;
5707 u32 *_rx_desc = (u32 *)skb->data;
5708 int drvinfo_sz, desc_shift, i;
5709
5710 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5711 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5712
5713 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5714 desc_shift = rx_desc->shift;
5715 skb_put(skb, urb->actual_length);
5716
5717 if (urb->status == 0) {
5718 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5719 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5720
5721 skb_pull(skb, drvinfo_sz + desc_shift);
5722
5723 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5724
5725 if (rx_desc->phy_stats)
5726 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5727 rx_desc, phy_stats);
5728
5729 rx_status->freq = hw->conf.chandef.chan->center_freq;
5730 rx_status->band = hw->conf.chandef.chan->band;
5731
5732 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5733 rx_status->flag |= RX_FLAG_MACTIME_START;
5734
5735 if (!rx_desc->swdec)
5736 rx_status->flag |= RX_FLAG_DECRYPTED;
5737 if (rx_desc->crc32)
5738 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5739 if (rx_desc->bw)
5740 rx_status->flag |= RX_FLAG_40MHZ;
5741
5742 if (rx_desc->rxht) {
5743 rx_status->flag |= RX_FLAG_HT;
5744 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5745 } else {
5746 rx_status->rate_idx = rx_desc->rxmcs;
5747 }
5748
5749 ieee80211_rx_irqsafe(hw, skb);
5750 skb = NULL;
5751 rx_urb->urb.context = NULL;
5752 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5753 } else {
5754 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5755 goto cleanup;
5756 }
5757 return;
5758
5759 cleanup:
5760 usb_free_urb(urb);
5761 dev_kfree_skb(skb);
5762 return;
5763 }
5764
5765 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5766 struct rtl8xxxu_rx_urb *rx_urb)
5767 {
5768 struct sk_buff *skb;
5769 int skb_size;
5770 int ret;
5771
5772 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5773 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5774 if (!skb)
5775 return -ENOMEM;
5776
5777 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5778 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5779 skb_size, rtl8xxxu_rx_complete, skb);
5780 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5781 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5782 if (ret)
5783 usb_unanchor_urb(&rx_urb->urb);
5784 return ret;
5785 }
5786
5787 static void rtl8xxxu_int_complete(struct urb *urb)
5788 {
5789 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5790 struct device *dev = &priv->udev->dev;
5791 int ret;
5792
5793 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5794 if (urb->status == 0) {
5795 usb_anchor_urb(urb, &priv->int_anchor);
5796 ret = usb_submit_urb(urb, GFP_ATOMIC);
5797 if (ret)
5798 usb_unanchor_urb(urb);
5799 } else {
5800 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5801 }
5802 }
5803
5804
5805 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5806 {
5807 struct rtl8xxxu_priv *priv = hw->priv;
5808 struct urb *urb;
5809 u32 val32;
5810 int ret;
5811
5812 urb = usb_alloc_urb(0, GFP_KERNEL);
5813 if (!urb)
5814 return -ENOMEM;
5815
5816 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5817 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5818 rtl8xxxu_int_complete, priv, 1);
5819 usb_anchor_urb(urb, &priv->int_anchor);
5820 ret = usb_submit_urb(urb, GFP_KERNEL);
5821 if (ret) {
5822 usb_unanchor_urb(urb);
5823 goto error;
5824 }
5825
5826 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5827 val32 |= USB_HIMR_CPWM;
5828 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5829
5830 error:
5831 return ret;
5832 }
5833
5834 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5835 struct ieee80211_vif *vif)
5836 {
5837 struct rtl8xxxu_priv *priv = hw->priv;
5838 int ret;
5839 u8 val8;
5840
5841 switch (vif->type) {
5842 case NL80211_IFTYPE_STATION:
5843 rtl8723a_stop_tx_beacon(priv);
5844
5845 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5846 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5847 BEACON_DISABLE_TSF_UPDATE;
5848 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5849 ret = 0;
5850 break;
5851 default:
5852 ret = -EOPNOTSUPP;
5853 }
5854
5855 rtl8xxxu_set_linktype(priv, vif->type);
5856
5857 return ret;
5858 }
5859
5860 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5861 struct ieee80211_vif *vif)
5862 {
5863 struct rtl8xxxu_priv *priv = hw->priv;
5864
5865 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5866 }
5867
5868 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5869 {
5870 struct rtl8xxxu_priv *priv = hw->priv;
5871 struct device *dev = &priv->udev->dev;
5872 u16 val16;
5873 int ret = 0, channel;
5874 bool ht40;
5875
5876 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5877 dev_info(dev,
5878 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5879 __func__, hw->conf.chandef.chan->hw_value,
5880 changed, hw->conf.chandef.width);
5881
5882 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5883 val16 = ((hw->conf.long_frame_max_tx_count <<
5884 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5885 ((hw->conf.short_frame_max_tx_count <<
5886 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5887 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5888 }
5889
5890 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5891 switch (hw->conf.chandef.width) {
5892 case NL80211_CHAN_WIDTH_20_NOHT:
5893 case NL80211_CHAN_WIDTH_20:
5894 ht40 = false;
5895 break;
5896 case NL80211_CHAN_WIDTH_40:
5897 ht40 = true;
5898 break;
5899 default:
5900 ret = -ENOTSUPP;
5901 goto exit;
5902 }
5903
5904 channel = hw->conf.chandef.chan->hw_value;
5905
5906 rtl8723a_set_tx_power(priv, channel, ht40);
5907
5908 rtl8723au_config_channel(hw);
5909 }
5910
5911 exit:
5912 return ret;
5913 }
5914
5915 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5916 struct ieee80211_vif *vif, u16 queue,
5917 const struct ieee80211_tx_queue_params *param)
5918 {
5919 struct rtl8xxxu_priv *priv = hw->priv;
5920 struct device *dev = &priv->udev->dev;
5921 u32 val32;
5922 u8 aifs, acm_ctrl, acm_bit;
5923
5924 aifs = param->aifs;
5925
5926 val32 = aifs |
5927 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5928 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5929 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5930
5931 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5932 dev_dbg(dev,
5933 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5934 __func__, queue, val32, param->acm, acm_ctrl);
5935
5936 switch (queue) {
5937 case IEEE80211_AC_VO:
5938 acm_bit = ACM_HW_CTRL_VO;
5939 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5940 break;
5941 case IEEE80211_AC_VI:
5942 acm_bit = ACM_HW_CTRL_VI;
5943 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5944 break;
5945 case IEEE80211_AC_BE:
5946 acm_bit = ACM_HW_CTRL_BE;
5947 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5948 break;
5949 case IEEE80211_AC_BK:
5950 acm_bit = ACM_HW_CTRL_BK;
5951 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5952 break;
5953 default:
5954 acm_bit = 0;
5955 break;
5956 }
5957
5958 if (param->acm)
5959 acm_ctrl |= acm_bit;
5960 else
5961 acm_ctrl &= ~acm_bit;
5962 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5963
5964 return 0;
5965 }
5966
5967 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5968 unsigned int changed_flags,
5969 unsigned int *total_flags, u64 multicast)
5970 {
5971 struct rtl8xxxu_priv *priv = hw->priv;
5972 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5973
5974 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5975 __func__, changed_flags, *total_flags);
5976
5977 /*
5978 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5979 */
5980
5981 if (*total_flags & FIF_FCSFAIL)
5982 rcr |= RCR_ACCEPT_CRC32;
5983 else
5984 rcr &= ~RCR_ACCEPT_CRC32;
5985
5986 /*
5987 * FIF_PLCPFAIL not supported?
5988 */
5989
5990 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5991 rcr &= ~RCR_CHECK_BSSID_BEACON;
5992 else
5993 rcr |= RCR_CHECK_BSSID_BEACON;
5994
5995 if (*total_flags & FIF_CONTROL)
5996 rcr |= RCR_ACCEPT_CTRL_FRAME;
5997 else
5998 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5999
6000 if (*total_flags & FIF_OTHER_BSS) {
6001 rcr |= RCR_ACCEPT_AP;
6002 rcr &= ~RCR_CHECK_BSSID_MATCH;
6003 } else {
6004 rcr &= ~RCR_ACCEPT_AP;
6005 rcr |= RCR_CHECK_BSSID_MATCH;
6006 }
6007
6008 if (*total_flags & FIF_PSPOLL)
6009 rcr |= RCR_ACCEPT_PM;
6010 else
6011 rcr &= ~RCR_ACCEPT_PM;
6012
6013 /*
6014 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6015 */
6016
6017 rtl8xxxu_write32(priv, REG_RCR, rcr);
6018
6019 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6020 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6021 FIF_PROBE_REQ);
6022 }
6023
6024 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6025 {
6026 if (rts > 2347)
6027 return -EINVAL;
6028
6029 return 0;
6030 }
6031
6032 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6033 struct ieee80211_vif *vif,
6034 struct ieee80211_sta *sta,
6035 struct ieee80211_key_conf *key)
6036 {
6037 struct rtl8xxxu_priv *priv = hw->priv;
6038 struct device *dev = &priv->udev->dev;
6039 u8 mac_addr[ETH_ALEN];
6040 u8 val8;
6041 u16 val16;
6042 u32 val32;
6043 int retval = -EOPNOTSUPP;
6044
6045 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6046 __func__, cmd, key->cipher, key->keyidx);
6047
6048 if (vif->type != NL80211_IFTYPE_STATION)
6049 return -EOPNOTSUPP;
6050
6051 if (key->keyidx > 3)
6052 return -EOPNOTSUPP;
6053
6054 switch (key->cipher) {
6055 case WLAN_CIPHER_SUITE_WEP40:
6056 case WLAN_CIPHER_SUITE_WEP104:
6057
6058 break;
6059 case WLAN_CIPHER_SUITE_CCMP:
6060 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6061 break;
6062 case WLAN_CIPHER_SUITE_TKIP:
6063 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6064 default:
6065 return -EOPNOTSUPP;
6066 }
6067
6068 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6069 dev_dbg(dev, "%s: pairwise key\n", __func__);
6070 ether_addr_copy(mac_addr, sta->addr);
6071 } else {
6072 dev_dbg(dev, "%s: group key\n", __func__);
6073 eth_broadcast_addr(mac_addr);
6074 }
6075
6076 val16 = rtl8xxxu_read16(priv, REG_CR);
6077 val16 |= CR_SECURITY_ENABLE;
6078 rtl8xxxu_write16(priv, REG_CR, val16);
6079
6080 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6081 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6082 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6083 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6084
6085 switch (cmd) {
6086 case SET_KEY:
6087 key->hw_key_idx = key->keyidx;
6088 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6089 rtl8xxxu_cam_write(priv, key, mac_addr);
6090 retval = 0;
6091 break;
6092 case DISABLE_KEY:
6093 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6094 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6095 key->keyidx << CAM_CMD_KEY_SHIFT;
6096 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6097 retval = 0;
6098 break;
6099 default:
6100 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6101 }
6102
6103 return retval;
6104 }
6105
6106 static int
6107 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6108 struct ieee80211_ampdu_params *params)
6109 {
6110 struct rtl8xxxu_priv *priv = hw->priv;
6111 struct device *dev = &priv->udev->dev;
6112 u8 ampdu_factor, ampdu_density;
6113 struct ieee80211_sta *sta = params->sta;
6114 enum ieee80211_ampdu_mlme_action action = params->action;
6115
6116 switch (action) {
6117 case IEEE80211_AMPDU_TX_START:
6118 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6119 ampdu_factor = sta->ht_cap.ampdu_factor;
6120 ampdu_density = sta->ht_cap.ampdu_density;
6121 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6122 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6123 dev_dbg(dev,
6124 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6125 ampdu_factor, ampdu_density);
6126 break;
6127 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6128 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
6129 rtl8xxxu_set_ampdu_factor(priv, 0);
6130 rtl8xxxu_set_ampdu_min_space(priv, 0);
6131 break;
6132 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6133 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
6134 __func__);
6135 rtl8xxxu_set_ampdu_factor(priv, 0);
6136 rtl8xxxu_set_ampdu_min_space(priv, 0);
6137 break;
6138 case IEEE80211_AMPDU_RX_START:
6139 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6140 break;
6141 case IEEE80211_AMPDU_RX_STOP:
6142 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6143 break;
6144 default:
6145 break;
6146 }
6147 return 0;
6148 }
6149
6150 static int rtl8xxxu_start(struct ieee80211_hw *hw)
6151 {
6152 struct rtl8xxxu_priv *priv = hw->priv;
6153 struct rtl8xxxu_rx_urb *rx_urb;
6154 struct rtl8xxxu_tx_urb *tx_urb;
6155 unsigned long flags;
6156 int ret, i;
6157
6158 ret = 0;
6159
6160 init_usb_anchor(&priv->rx_anchor);
6161 init_usb_anchor(&priv->tx_anchor);
6162 init_usb_anchor(&priv->int_anchor);
6163
6164 rtl8723a_enable_rf(priv);
6165 if (priv->usb_interrupts) {
6166 ret = rtl8xxxu_submit_int_urb(hw);
6167 if (ret)
6168 goto exit;
6169 }
6170
6171 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6172 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6173 if (!tx_urb) {
6174 if (!i)
6175 ret = -ENOMEM;
6176
6177 goto error_out;
6178 }
6179 usb_init_urb(&tx_urb->urb);
6180 INIT_LIST_HEAD(&tx_urb->list);
6181 tx_urb->hw = hw;
6182 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6183 priv->tx_urb_free_count++;
6184 }
6185
6186 priv->tx_stopped = false;
6187
6188 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6189 priv->shutdown = false;
6190 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6191
6192 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
6193 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
6194 if (!rx_urb) {
6195 if (!i)
6196 ret = -ENOMEM;
6197
6198 goto error_out;
6199 }
6200 usb_init_urb(&rx_urb->urb);
6201 INIT_LIST_HEAD(&rx_urb->list);
6202 rx_urb->hw = hw;
6203
6204 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6205 }
6206 exit:
6207 /*
6208 * Accept all data and mgmt frames
6209 */
6210 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
6211 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
6212
6213 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
6214
6215 return ret;
6216
6217 error_out:
6218 rtl8xxxu_free_tx_resources(priv);
6219 /*
6220 * Disable all data and mgmt frames
6221 */
6222 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6223 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6224
6225 return ret;
6226 }
6227
6228 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
6229 {
6230 struct rtl8xxxu_priv *priv = hw->priv;
6231 unsigned long flags;
6232
6233 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6234
6235 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6236 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6237
6238 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6239 priv->shutdown = true;
6240 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6241
6242 usb_kill_anchored_urbs(&priv->rx_anchor);
6243 usb_kill_anchored_urbs(&priv->tx_anchor);
6244 if (priv->usb_interrupts)
6245 usb_kill_anchored_urbs(&priv->int_anchor);
6246
6247 rtl8723a_disable_rf(priv);
6248
6249 /*
6250 * Disable interrupts
6251 */
6252 if (priv->usb_interrupts)
6253 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
6254
6255 rtl8xxxu_free_rx_resources(priv);
6256 rtl8xxxu_free_tx_resources(priv);
6257 }
6258
6259 static const struct ieee80211_ops rtl8xxxu_ops = {
6260 .tx = rtl8xxxu_tx,
6261 .add_interface = rtl8xxxu_add_interface,
6262 .remove_interface = rtl8xxxu_remove_interface,
6263 .config = rtl8xxxu_config,
6264 .conf_tx = rtl8xxxu_conf_tx,
6265 .bss_info_changed = rtl8xxxu_bss_info_changed,
6266 .configure_filter = rtl8xxxu_configure_filter,
6267 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6268 .start = rtl8xxxu_start,
6269 .stop = rtl8xxxu_stop,
6270 .sw_scan_start = rtl8xxxu_sw_scan_start,
6271 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6272 .set_key = rtl8xxxu_set_key,
6273 .ampdu_action = rtl8xxxu_ampdu_action,
6274 };
6275
6276 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6277 struct usb_interface *interface)
6278 {
6279 struct usb_interface_descriptor *interface_desc;
6280 struct usb_host_interface *host_interface;
6281 struct usb_endpoint_descriptor *endpoint;
6282 struct device *dev = &priv->udev->dev;
6283 int i, j = 0, endpoints;
6284 u8 dir, xtype, num;
6285 int ret = 0;
6286
6287 host_interface = &interface->altsetting[0];
6288 interface_desc = &host_interface->desc;
6289 endpoints = interface_desc->bNumEndpoints;
6290
6291 for (i = 0; i < endpoints; i++) {
6292 endpoint = &host_interface->endpoint[i].desc;
6293
6294 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6295 num = usb_endpoint_num(endpoint);
6296 xtype = usb_endpoint_type(endpoint);
6297 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6298 dev_dbg(dev,
6299 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6300 __func__, dir, num, xtype);
6301 if (usb_endpoint_dir_in(endpoint) &&
6302 usb_endpoint_xfer_bulk(endpoint)) {
6303 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6304 dev_dbg(dev, "%s: in endpoint num %i\n",
6305 __func__, num);
6306
6307 if (priv->pipe_in) {
6308 dev_warn(dev,
6309 "%s: Too many IN pipes\n", __func__);
6310 ret = -EINVAL;
6311 goto exit;
6312 }
6313
6314 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6315 }
6316
6317 if (usb_endpoint_dir_in(endpoint) &&
6318 usb_endpoint_xfer_int(endpoint)) {
6319 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6320 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6321 __func__, num);
6322
6323 if (priv->pipe_interrupt) {
6324 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6325 __func__);
6326 ret = -EINVAL;
6327 goto exit;
6328 }
6329
6330 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6331 }
6332
6333 if (usb_endpoint_dir_out(endpoint) &&
6334 usb_endpoint_xfer_bulk(endpoint)) {
6335 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6336 dev_dbg(dev, "%s: out endpoint num %i\n",
6337 __func__, num);
6338 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6339 dev_warn(dev,
6340 "%s: Too many OUT pipes\n", __func__);
6341 ret = -EINVAL;
6342 goto exit;
6343 }
6344 priv->out_ep[j++] = num;
6345 }
6346 }
6347 exit:
6348 priv->nr_out_eps = j;
6349 return ret;
6350 }
6351
6352 static int rtl8xxxu_probe(struct usb_interface *interface,
6353 const struct usb_device_id *id)
6354 {
6355 struct rtl8xxxu_priv *priv;
6356 struct ieee80211_hw *hw;
6357 struct usb_device *udev;
6358 struct ieee80211_supported_band *sband;
6359 int ret = 0;
6360 int untested = 1;
6361
6362 udev = usb_get_dev(interface_to_usbdev(interface));
6363
6364 switch (id->idVendor) {
6365 case USB_VENDOR_ID_REALTEK:
6366 switch(id->idProduct) {
6367 case 0x1724:
6368 case 0x8176:
6369 case 0x8178:
6370 case 0x817f:
6371 untested = 0;
6372 break;
6373 }
6374 break;
6375 case 0x7392:
6376 if (id->idProduct == 0x7811)
6377 untested = 0;
6378 break;
6379 default:
6380 break;
6381 }
6382
6383 if (untested) {
6384 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6385 dev_info(&udev->dev,
6386 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6387 id->idVendor, id->idProduct);
6388 dev_info(&udev->dev,
6389 "Please report results to Jes.Sorensen@gmail.com\n");
6390 }
6391
6392 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6393 if (!hw) {
6394 ret = -ENOMEM;
6395 goto exit;
6396 }
6397
6398 priv = hw->priv;
6399 priv->hw = hw;
6400 priv->udev = udev;
6401 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6402 mutex_init(&priv->usb_buf_mutex);
6403 mutex_init(&priv->h2c_mutex);
6404 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6405 spin_lock_init(&priv->tx_urb_lock);
6406 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6407 spin_lock_init(&priv->rx_urb_lock);
6408 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6409
6410 usb_set_intfdata(interface, hw);
6411
6412 ret = rtl8xxxu_parse_usb(priv, interface);
6413 if (ret)
6414 goto exit;
6415
6416 ret = rtl8xxxu_identify_chip(priv);
6417 if (ret) {
6418 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6419 goto exit;
6420 }
6421
6422 ret = rtl8xxxu_read_efuse(priv);
6423 if (ret) {
6424 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6425 goto exit;
6426 }
6427
6428 ret = priv->fops->parse_efuse(priv);
6429 if (ret) {
6430 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6431 goto exit;
6432 }
6433
6434 rtl8xxxu_print_chipinfo(priv);
6435
6436 ret = priv->fops->load_firmware(priv);
6437 if (ret) {
6438 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6439 goto exit;
6440 }
6441
6442 ret = rtl8xxxu_init_device(hw);
6443
6444 hw->wiphy->max_scan_ssids = 1;
6445 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6446 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6447 hw->queues = 4;
6448
6449 sband = &rtl8xxxu_supported_band;
6450 sband->ht_cap.ht_supported = true;
6451 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6452 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6453 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6454 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6455 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6456 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6457 if (priv->rf_paths > 1) {
6458 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6459 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6460 }
6461 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6462 /*
6463 * Some APs will negotiate HT20_40 in a noisy environment leading
6464 * to miserable performance. Rather than defaulting to this, only
6465 * enable it if explicitly requested at module load time.
6466 */
6467 if (rtl8xxxu_ht40_2g) {
6468 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6469 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6470 }
6471 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6472
6473 hw->wiphy->rts_threshold = 2347;
6474
6475 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6476 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6477
6478 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6479 ieee80211_hw_set(hw, SIGNAL_DBM);
6480 /*
6481 * The firmware handles rate control
6482 */
6483 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6484 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6485
6486 ret = ieee80211_register_hw(priv->hw);
6487 if (ret) {
6488 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6489 __func__, ret);
6490 goto exit;
6491 }
6492
6493 exit:
6494 if (ret < 0)
6495 usb_put_dev(udev);
6496 return ret;
6497 }
6498
6499 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6500 {
6501 struct rtl8xxxu_priv *priv;
6502 struct ieee80211_hw *hw;
6503
6504 hw = usb_get_intfdata(interface);
6505 priv = hw->priv;
6506
6507 rtl8xxxu_disable_device(hw);
6508 usb_set_intfdata(interface, NULL);
6509
6510 dev_info(&priv->udev->dev, "disconnecting\n");
6511
6512 ieee80211_unregister_hw(hw);
6513
6514 kfree(priv->fw_data);
6515 mutex_destroy(&priv->usb_buf_mutex);
6516 mutex_destroy(&priv->h2c_mutex);
6517
6518 usb_put_dev(priv->udev);
6519 ieee80211_free_hw(hw);
6520 }
6521
6522 static struct rtl8xxxu_fileops rtl8723au_fops = {
6523 .parse_efuse = rtl8723au_parse_efuse,
6524 .load_firmware = rtl8723au_load_firmware,
6525 .power_on = rtl8723au_power_on,
6526 .llt_init = rtl8xxxu_init_llt_table,
6527 .writeN_block_size = 1024,
6528 .mbox_ext_reg = REG_HMBOX_EXT_0,
6529 .mbox_ext_width = 2,
6530 };
6531
6532 static struct rtl8xxxu_fileops rtl8723bu_fops = {
6533 .parse_efuse = rtl8723bu_parse_efuse,
6534 .load_firmware = rtl8723bu_load_firmware,
6535 .power_on = rtl8723au_power_on,
6536 .llt_init = rtl8xxxu_auto_llt_table,
6537 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
6538 .writeN_block_size = 1024,
6539 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6540 .mbox_ext_width = 4,
6541 };
6542
6543 #ifdef CONFIG_RTL8XXXU_UNTESTED
6544
6545 static struct rtl8xxxu_fileops rtl8192cu_fops = {
6546 .parse_efuse = rtl8192cu_parse_efuse,
6547 .load_firmware = rtl8192cu_load_firmware,
6548 .power_on = rtl8192cu_power_on,
6549 .llt_init = rtl8xxxu_init_llt_table,
6550 .writeN_block_size = 128,
6551 .mbox_ext_reg = REG_HMBOX_EXT_0,
6552 .mbox_ext_width = 2,
6553 };
6554
6555 #endif
6556
6557 static struct rtl8xxxu_fileops rtl8192eu_fops = {
6558 .parse_efuse = rtl8192eu_parse_efuse,
6559 .load_firmware = rtl8192eu_load_firmware,
6560 .power_on = rtl8192eu_power_on,
6561 .llt_init = rtl8xxxu_auto_llt_table,
6562 .writeN_block_size = 128,
6563 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6564 .mbox_ext_width = 4,
6565 };
6566
6567 static struct usb_device_id dev_table[] = {
6568 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6569 .driver_info = (unsigned long)&rtl8723au_fops},
6570 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6571 .driver_info = (unsigned long)&rtl8723au_fops},
6572 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6573 .driver_info = (unsigned long)&rtl8723au_fops},
6574 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6575 .driver_info = (unsigned long)&rtl8192eu_fops},
6576 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6577 .driver_info = (unsigned long)&rtl8723bu_fops},
6578 #ifdef CONFIG_RTL8XXXU_UNTESTED
6579 /* Still supported by rtlwifi */
6580 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6581 .driver_info = (unsigned long)&rtl8192cu_fops},
6582 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6583 .driver_info = (unsigned long)&rtl8192cu_fops},
6584 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6585 .driver_info = (unsigned long)&rtl8192cu_fops},
6586 /* Tested by Larry Finger */
6587 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6588 .driver_info = (unsigned long)&rtl8192cu_fops},
6589 /* Currently untested 8188 series devices */
6590 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6591 .driver_info = (unsigned long)&rtl8192cu_fops},
6592 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6593 .driver_info = (unsigned long)&rtl8192cu_fops},
6594 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6595 .driver_info = (unsigned long)&rtl8192cu_fops},
6596 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6597 .driver_info = (unsigned long)&rtl8192cu_fops},
6598 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6599 .driver_info = (unsigned long)&rtl8192cu_fops},
6600 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6601 .driver_info = (unsigned long)&rtl8192cu_fops},
6602 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6603 .driver_info = (unsigned long)&rtl8192cu_fops},
6604 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6605 .driver_info = (unsigned long)&rtl8192cu_fops},
6606 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6607 .driver_info = (unsigned long)&rtl8192cu_fops},
6608 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6609 .driver_info = (unsigned long)&rtl8192cu_fops},
6610 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6611 .driver_info = (unsigned long)&rtl8192cu_fops},
6612 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6613 .driver_info = (unsigned long)&rtl8192cu_fops},
6614 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6615 .driver_info = (unsigned long)&rtl8192cu_fops},
6616 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6617 .driver_info = (unsigned long)&rtl8192cu_fops},
6618 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6619 .driver_info = (unsigned long)&rtl8192cu_fops},
6620 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6621 .driver_info = (unsigned long)&rtl8192cu_fops},
6622 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6623 .driver_info = (unsigned long)&rtl8192cu_fops},
6624 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6625 .driver_info = (unsigned long)&rtl8192cu_fops},
6626 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6627 .driver_info = (unsigned long)&rtl8192cu_fops},
6628 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6629 .driver_info = (unsigned long)&rtl8192cu_fops},
6630 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6631 .driver_info = (unsigned long)&rtl8192cu_fops},
6632 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6633 .driver_info = (unsigned long)&rtl8192cu_fops},
6634 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6635 .driver_info = (unsigned long)&rtl8192cu_fops},
6636 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6637 .driver_info = (unsigned long)&rtl8192cu_fops},
6638 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6639 .driver_info = (unsigned long)&rtl8192cu_fops},
6640 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6641 .driver_info = (unsigned long)&rtl8192cu_fops},
6642 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6643 .driver_info = (unsigned long)&rtl8192cu_fops},
6644 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6645 .driver_info = (unsigned long)&rtl8192cu_fops},
6646 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6647 .driver_info = (unsigned long)&rtl8192cu_fops},
6648 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6649 .driver_info = (unsigned long)&rtl8192cu_fops},
6650 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6651 .driver_info = (unsigned long)&rtl8192cu_fops},
6652 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6653 .driver_info = (unsigned long)&rtl8192cu_fops},
6654 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6655 .driver_info = (unsigned long)&rtl8192cu_fops},
6656 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6657 .driver_info = (unsigned long)&rtl8192cu_fops},
6658 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6659 .driver_info = (unsigned long)&rtl8192cu_fops},
6660 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6661 .driver_info = (unsigned long)&rtl8192cu_fops},
6662 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6663 .driver_info = (unsigned long)&rtl8192cu_fops},
6664 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6665 .driver_info = (unsigned long)&rtl8192cu_fops},
6666 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6667 .driver_info = (unsigned long)&rtl8192cu_fops},
6668 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6669 .driver_info = (unsigned long)&rtl8192cu_fops},
6670 /* Currently untested 8192 series devices */
6671 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6672 .driver_info = (unsigned long)&rtl8192cu_fops},
6673 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6674 .driver_info = (unsigned long)&rtl8192cu_fops},
6675 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6676 .driver_info = (unsigned long)&rtl8192cu_fops},
6677 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6678 .driver_info = (unsigned long)&rtl8192cu_fops},
6679 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6680 .driver_info = (unsigned long)&rtl8192cu_fops},
6681 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6682 .driver_info = (unsigned long)&rtl8192cu_fops},
6683 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6684 .driver_info = (unsigned long)&rtl8192cu_fops},
6685 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6686 .driver_info = (unsigned long)&rtl8192cu_fops},
6687 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6688 .driver_info = (unsigned long)&rtl8192cu_fops},
6689 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6690 .driver_info = (unsigned long)&rtl8192cu_fops},
6691 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6692 .driver_info = (unsigned long)&rtl8192cu_fops},
6693 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6694 .driver_info = (unsigned long)&rtl8192cu_fops},
6695 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6696 .driver_info = (unsigned long)&rtl8192cu_fops},
6697 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6698 .driver_info = (unsigned long)&rtl8192cu_fops},
6699 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6700 .driver_info = (unsigned long)&rtl8192cu_fops},
6701 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6702 .driver_info = (unsigned long)&rtl8192cu_fops},
6703 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6704 .driver_info = (unsigned long)&rtl8192cu_fops},
6705 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6706 .driver_info = (unsigned long)&rtl8192cu_fops},
6707 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6708 .driver_info = (unsigned long)&rtl8192cu_fops},
6709 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6710 .driver_info = (unsigned long)&rtl8192cu_fops},
6711 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6712 .driver_info = (unsigned long)&rtl8192cu_fops},
6713 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6714 .driver_info = (unsigned long)&rtl8192cu_fops},
6715 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6716 .driver_info = (unsigned long)&rtl8192cu_fops},
6717 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6718 .driver_info = (unsigned long)&rtl8192cu_fops},
6719 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6720 .driver_info = (unsigned long)&rtl8192cu_fops},
6721 #endif
6722 { }
6723 };
6724
6725 static struct usb_driver rtl8xxxu_driver = {
6726 .name = DRIVER_NAME,
6727 .probe = rtl8xxxu_probe,
6728 .disconnect = rtl8xxxu_disconnect,
6729 .id_table = dev_table,
6730 .disable_hub_initiated_lpm = 1,
6731 };
6732
6733 static int __init rtl8xxxu_module_init(void)
6734 {
6735 int res;
6736
6737 res = usb_register(&rtl8xxxu_driver);
6738 if (res < 0)
6739 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6740
6741 return res;
6742 }
6743
6744 static void __exit rtl8xxxu_module_exit(void)
6745 {
6746 usb_deregister(&rtl8xxxu_driver);
6747 }
6748
6749
6750 MODULE_DEVICE_TABLE(usb, dev_table);
6751
6752 module_init(rtl8xxxu_module_init);
6753 module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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